MC14011BDG - ON Semiconductor

June, 2011 − Rev. 8

1Publication Order Number:

MC14001B/D

MC14001B Series

B-Suffix Series CMOS Gates

MC14001B, MC14011B, MC14023B,

MC14025B, MC14071B, MC14073B,

MC14081B, MC14082B

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure

(Complementary MOS). Their primary use is where low power

dissipation and/or high noise immunity is desired.

Features

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•All Outputs Buffered

•Capable of Driving Two Low−power TTL Loads or One Low−power

Schottky TTL Load Over the Rated Temperature Range.

•Double Diode Protection on All Inputs Except: Triple Diode

Protection on MC14011B and MC14081B

•Pin−for−Pin Replacements for Corresponding CD4000 Series

B Suffix Devices

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

VESD ESD Withstand Voltage

Human Body Model

Machine Model

Charged Device Model

> 3000

> 300

N/A

V

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

Device Description

DEVICE INFORMATION

MC14001B Quad 2−Input NOR Gate

MC14011B Quad 2−Input NAND Gate

MC14023B Triple 3−Input NAND Gate

MC14025B Triple 3−Input NOR Gate

MC14071B Quad 2−Input OR Gate

MARKING

DIAGRAMS

1

14

PDIP−14

P SUFFIX

CASE 646

MC140xxBCP

AWLYYWWG

SOIC−14

D SUFFIX

CASE 751A

TSSOP−14

DT SUFFIX

CASE 948G

1

14

140xxBG

AWLYWW

14

0xxB

ALYWG

G

1

14

xx = Specific Device Code

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

SOEIAJ−14

F SUFFIX

CASE 965

1

14

MC140xxB

ALYWG

MC14073B Triple 3−Input AND Gate

MC14081B Quad 2−Input AND Gate

MC14082B Dual 4−Input AND Gate

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

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(Note: Microdot may be in either location)

MC14001B Series

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2

LOGIC DIAGRAMS

1

2

5

6

8

9

12

13

3

4

10

11

1

2

5

6

8

9

12

13

3

4

10

11

1

2

5

6

8

9

12

13

3

4

10

11

1

2

5

6

8

9

12

13

3

4

10

11

2 INPUT

1

29

3 INPUT

8

3

46

5

11

12 10

13

1

29

8

3

46

5

11

12 10

13

1

29

8

3

46

5

11

12 10

13

1

13

3

4

5

2

10

11

12

9

NC = 6, 8

VDD = PIN 14

VSS = PIN 7

FOR ALL DEVICES

NOR

MC14001B

Quad 2−Input NOR Gate

MC14025B

Triple 3−Input NOR Gate

MC14023B

Triple 3−Input NAND Gate

NAND

MC14011B

Quad 2−Input NAND Gate

OR

MC14071B

Quad 2−Input OR Gate

AND

MC14081B

Quad 2−Input AND Gate

MC14073B

Triple 3−Input AND Gate

MC14082B

Dual 4−Input AND Gate

PIN ASSIGNMENTS

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

IN 1C

IN 2C

IN 3C

VDD

IN 3A

OUTA

IN 2B

IN 1B

IN 2A

IN 1A

VSS

OUTB

IN 3B

11

12

13

14

8

9

105

4

3

2

1

7

6

OUTC

OUTD

IN 1D

IN 2D

VDD

IN 1C

IN 2C

OUTB

OUTA

IN 2A

IN 1A

VSS

IN 2B

IN 1B

11

12

13

14

8

9

105

4

3

2

1

7

6

IN 2B

IN 3B

IN 4B

OUTB

VDD

NC

IN 1B

IN 3A

IN 2A

IN 1A

OUTA

VSS

NC

IN 4A

NC = NO CONNECTION

MC14023B

Triple 3−Input NAND Gate

MC14001B

Quad 2−Input NOR Gate

MC14011B

Quad 2−Input NAND Gate

MC14082B

Dual 4−Input AND Gate

MC14081B

Quad 2−Input AND Gate

MC14025B

Triple 3−Input NOR Gate

MC14071B

Quad 2−Input OR Gate

MC14073B

Triple 3−Input AND Gate

MC14001B Series

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ (2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.25

0.5

1.0

ÎÎÎÎ

−

ÎÎÎ

0.0005

0.0010

0.0015

ÎÎÎÎ

0.25

0.5

1.0

ÎÎÎ

−

ÎÎÎ

7.5

15

30

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (3) (4)

(Dynamic plus Quiescent,

Per Gate, CL = 50 pF)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.3 mA/kHz) f + IDD/N

IT = (0.6 mA/kHz) f + IDD/N

IT = (0.9 mA/kHz) f + IDD/N

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL − 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD − VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates

per package.

MC14001B Series

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4

B−SERIES GATE SWITCHING TIMES

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ (6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise Time, All B−Series Gates

tTLH = (1.35 ns/pF) CL + 33 ns

tTLH = (0.60 ns/pF) CL + 20 ns

tTLH = (0.40 ns/PF) CL + 20 ns

ÎÎÎÎÎ

tTLH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Fall Time, All B−Series Gates

tTHL = (1.35 ns/pF) CL + 33 ns

tTHL = (0.60 ns/pF) CL + 20 ns

tTHL = (0.40 ns/pF) CL + 20 ns

ÎÎÎÎÎ

tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

MC14001B, MC14011B only

tPLH, tPHL = (0.90 ns/pF) CL + 80 ns

tPLH, tPHL = (0.36 ns/pF) CL + 32 ns

tPLH, tPHL = (0.26 ns/pF) CL + 27 ns

All Other 2, 3, and 4 Input Gates

tPLH, tPHL = (0.90 ns/pF) CL + 115 ns

tPLH, tPHL = (0.36 ns/pF) CL + 47 ns

tPLH, tPHL = (0.26 ns/pF) CL + 37 ns

8−Input Gates (MC14068B, MC14078B)

tPLH, tPHL = (0.90 ns/pF) CL + 155 ns

tPLH, tPHL = (0.36 ns/pF) CL + 62 ns

tPLH, tPHL = (0.26 ns/pF) CL + 47 ns

ÎÎÎÎÎ

tPLH, tPHL

ÎÎÎÎ

5.0

10

15

5.0

10

15

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

125

50

40

160

65

50

200

80

60

ÎÎÎÎ

250

100

80

300

130

100

350

150

110

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

VDD

14

CL

VSS

7

PULSE

GENERATOR

INPUT

OUTPUT

90%

50%

10%

50%

90%

20 ns 20 ns

tPHL tPLH

tTLH

tTHL

VOL

VOH

0 V

VDD

INPUT

OUTPUT

INVERTING

*All unused inputs of AND, NAND gates must be connected to VDD.

All unused inputs of OR, NOR gates must be connected to VSS.

90%

50%

10% VOL

VOH

OUTPUT

NON-INVERTING

tTHL

tTLH

tPLH tPHL

*

Figure 1. Switching Time Test Circuit and Waveforms

MC14001B Series

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5

CIRCUIT SCHEMATIC

NOR, OR GATES

14

*

7

VSS

3, 4, 10, 11

VDD

VSS

VDD

*Inverter omitted in MC14001B

1, 6, 8, 13

2, 5, 9, 12

14

*

7

9, 6, 10

VSS

VDD

1, 3, 11

2, 4, 12

VSS

VDD

VSS

VDD

8, 5, 13

MC14001B, MC14071B

One of Four Gates Shown

MC14025B

One of Three Gates Shown

*Inverter omitted in MC14025B

CIRCUIT SCHEMATIC

NAND, AND GATES

14

*

7

3, 4, 10, 11

VSS

VDD

*Inverter omitted in MC14011B

14

*

7

9, 6, 10

VSS

VDD

*Inverter omitted in MC14023B

2, 5, 9, 12

1, 6, 8, 13

2, 4, 12

1, 3, 11

VDD

VSS

8, 5, 13

MC14011B, MC14081B

One of Four Gates Shown

MC14023B, MC14073B

One of Three Gates Shown

MC14001B Series

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6

TYPICAL B−SERIES GATE CHARACTERISTICS

N−CHANNEL DRAIN CURRENT (SINK) P−CHANNEL DRAIN CURRENT (SOURCE)

- 40°C

+ 85°C

+ 125°C

Figure 2. VGS = 5.0 Vdc Figure 3. VGS = − 5.0 Vdc

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00

VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

- 1.0

00

TA = - 55°C

Figure 4. VGS = 10 Vdc Figure 5. VGS = − 10 Vdc

16

14

12

10

8.0

6.0

4.0

2.0

05.03.01.0 108.06.04.02.00 00

Figure 6. VGS = 15 Vdc Figure 7. VGS = − 15 Vdc

0000

- 40°C

+ 25°C

+ 85°C

+ 125°C

- 1.0 - 3.0 - 5.0- 4.0- 2.0

VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

TA = - 55°C

+ 25°C

TA = - 55°C

- 40°C

+ 25°C

+ 85°C

+ 125°C

VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc) VDS, DRAIN-TO-SOURCE VOLTAGE (Vdc)

TA = - 55°C

- 40°C

+ 25°C

+ 85°C

+ 125°C

18

20

9.07.0 - 5.0- 3.0- 1.0 - 10- 8.0- 6.0- 4.0- 2.0 - 9.0- 7.0

- 40

- 35

- 30

- 25

- 20

- 15

- 10

- 5.0

- 45

- 50

106.02.0 2016128.04.0 1814

TA = - 55°C

- 40°C

+ 25°C

+ 85°C

- 10- 6.0- 2.0 - 20- 16- 12- 8.0- 4.0 - 18- 14

- 80

- 70

- 60

- 50

- 40

- 30

- 20

- 10

- 90

- 100

40

35

30

25

20

15

10

5.0

45

50

TA = - 55°C

- 40°C

+ 25°C

+ 85°C

- 2.0

- 3.0

- 4.0

- 5.0

- 6.0

- 7.0

- 8.0

- 9.0

- 10

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

I ,

DDRAIN CURRENT (mA)

+ 125°C

These typical curves are not guarantees, but are design aids.

Caution: The maximum rating for output current is 10 mA per pin.

MC14001B Series

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7

TYPICAL B−SERIES GATE CHARACTERISTICS (cont’d)

VOLTAGE TRANSFER CHARACTERISTICS

Figure 8. VDD = 5.0 Vdc Figure 9. VDD = 10 Vdc

1.0

3.0

5.0

4.0

2.0

01.0 3.0 5.04.02.00 00

Vin, INPUT VOLTAGE (Vdc)

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0

Vin, INPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

V ,

out OUTPUT VOLTAGE (Vdc)

Figure 10. VDD = 15 Vdc

00

SINGLE INPUT NAND, AND

MULTIPLE INPUT NOR, OR

SINGLE INPUT NOR, OR

MULTIPLE INPUT NAND, AND

2.0

6.0

10

8.0

4.0

2.0 6.0 108.04.0

Vin, INPUT VOLTAGE (Vdc)

12

14

16

V ,

out OUTPUT VOLTAGE (Vdc)

DC NOISE MARGIN

The DC noise margin is defined as the input voltage range

from an ideal “1” or “0” input level which does not produce

output state change(s). The typical and guaranteed limit

values of the input values VIL and VIH for the output(s) to

be at a fixed voltage VO are given in the Electrical

Characteristics table. VIL and VIH are presented graphically

in Figure 11.

Guaranteed minimum noise margins for both the “1” and

“0” levels =

1.0 V with a 5.0 V supply

2.0 V with a 10.0 V supply

2.5 V with a 15.0 V supply

Figure 11. DC Noise Immunity

Vout

VO

VIL

0

VIH

Vin

VDD

VDD Vout

VO

VIL

0

VIH

Vin

VDD

(a) Inverting Function (b) Non−Inverting Function

VSS = 0 VOLTS DC

MC14001B Series

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8

ORDERING INFORMATION

Device Package Shipping†

MC14001BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14001BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14001BDR2G SOIC−14

(Pb−Free)

2500 Units / Tape & Reel

MC14001BDTR2G TSSOP−14*

(Pb−Free)

MC14001BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14011BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14011BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14011BDR2G SOIC−14

(Pb−Free)

2500 Units / Tape & Reel

MC14011BDTR2G TSSOP−14*

(Pb−Free)

MC14011BFG SOEIAJ−14

(Pb−Free) 50 Units / Rail

MC14011BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14023BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14023BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14023BDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC14023BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14025BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14025BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14025BDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC14025BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14071BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14071BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14071BDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC14071BDTG TSSOP−14*

(Pb−Free) 96 Units per Rail

MC14071BDTR2G TSSOP−14*

(Pb−Free) 2500 Units / Tape & Reel

MC14001B Series

http://onsemi.com

9

ORDERING INFORMATION

Device Shipping†

Package

MC14071BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14073BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14073BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14073BDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

MC14073BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14081BCPG PDIP−14

(Pb−Free) 25 Units / Rail

MC14081BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14081BDR2G SOIC−14

(Pb−Free)

2500 Units / Tape & Reel

MC14081BDTR2G TSSOP−14*

(Pb−Free)

MC14081BFELG SOEIAJ−14

(Pb−Free) 2000 Units / Tape & Reel

MC14082BCPG PDIP−14

(Pb−Free) 2000 Units / Box

MC14082BDG SOIC−14

(Pb−Free) 55 Units / Rail

MC14082BDR2G SOIC−14

(Pb−Free) 2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC14001B Series

http://onsemi.com

10

PACKAGE DIMENSIONS

PDIP−14

CASE 646−06

ISSUE P

17

14 8

B

ADIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.715 0.770 18.16 19.56

B0.240 0.260 6.10 6.60

C0.145 0.185 3.69 4.69

D0.015 0.021 0.38 0.53

F0.040 0.070 1.02 1.78

G0.100 BSC 2.54 BSC

H0.052 0.095 1.32 2.41

J0.008 0.015 0.20 0.38

K0.115 0.135 2.92 3.43

L

M−−− 10 −−− 10

N0.015 0.039 0.38 1.01

__

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

F

HG D

K

C

SEATING

PLANE

N

−T−

14 PL

M

0.13 (0.005)

L

M

J

0.290 0.310 7.37 7.87

MC14001B Series

http://onsemi.com

11

PACKAGE DIMENSIONS

SOIC−14 NB

CASE 751A−03

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

2. CONTROLLING DIMENSION: MILLIMETERS.

3. DIMENSION b DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF AT

MAXIMUM MATERIAL CONDITION.

4. DIMENSIONS D AND E DO NOT INCLUDE

MOLD PROTRUSIONS.

5. MAXIMUM MOLD PROTRUSION 0.15 PER

SIDE.

H

14 8

71

M

0.25 B M

C

h

X 45

SEATING

PLANE

A1

A

M

_

S

A

M

0.25 B S

C

b

13X

B

A

E

D

e

DETAIL A

L

A3

DETAIL A

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

D8.55 8.75 0.337 0.344

E3.80 4.00 0.150 0.157

A1.35 1.75 0.054 0.068

b0.35 0.49 0.014 0.019

L0.40 1.25 0.016 0.049

e1.27 BSC 0.050 BSC

A3 0.19 0.25 0.008 0.010

A1 0.10 0.25 0.004 0.010

M0 7 0 7

H5.80 6.20 0.228 0.244

h0.25 0.50 0.010 0.019

__ __

6.50

14X

0.58

14X

1.18

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14001B Series

http://onsemi.com

12

PACKAGE DIMENSIONS

TSSOP−14

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT*

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

MC14001B Series

http://onsemi.com

13

PACKAGE DIMENSIONS

SOEIAJ−14

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC14001B/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

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Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

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