MOTOROLA CMOS LOGIC DATA 1
MC14583B
The MC14583B is a dual Schmitt trigger constructed with complementary
P–channel and N–channel MOS devices on a monolithic silicon substrate.
Each Schmitt trigger is functionally independent except for a common
3–state input and an internally–connected Exclusive OR output for use in
line receiver applications. Trigger levels are adjustable through the positive,
negative, and common terminals with the use of external resistors.
Applications include the speed–up of a slow waveform edge in interface
receivers, level detectors, etc.
•Diode Protection on All Inputs
•Supply Voltage Range = 3.0 Vdc to 18 Vdc
•Single Supply Operation
•Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
•Resistor Adjustable Trigger Levels
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
MAXIMUM RATINGS* (Voltages Referenced to VSS)
Symbol Parameter Value Unit
VDD DC Supply Voltage – 0.5 to + 18.0 V
Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V
Iin, Iout Input or Output Current (DC or Transient),
per Pin ± 10 mA
PDPower Dissipation, per Package† 500 mW
Tstg Storage Temperature – 65 to + 150
_
C
TLLead Temperature (8–Second Soldering) 260
_
C
*Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/
_
C From 65
_
C To 125
_
C
Ceramic “L” Packages: – 12 mW/
_
C From 100
_
C To 125
_
C
LOGIC DIAGRAM
POSITIVE A
6 5
NEGATIVE A
7 COMMON A
Bout
9Ain
12
Bout
10
EXCLUSIVE OR14
Aout
11
Aout
4
13
15Bin
POSITIVE B2
2 3
NEGATIVE B
1 COMMON B
3–STATE
OUTPUT DISABLE
VDD = PIN 16
VSS = PIN 8
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 620
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 648
D SUFFIX
SOIC
CASE 751B
BLOCK DIAGRAM
TRUTH TABLE
Inputs Outputs
A B Dis Aout Aout Bout Bout
ę
0 0 0 0 Z 0 Z 0
0 0 1 0 1 0 1 0
0 1 0 0 Z 1 Z 1
0 1 1 0 1 1 0 1
1 0 0 1 Z 0 Z 1
1 0 1 1 0 0 1 1
1 1 0 1 Z 1 Z 0
1 1 1 1 0 1 0 0
Z = High impedance at output
VDD = PIN 16
VSS = PIN 8
9
13
15 12
10
14
11
4
APos ANeg ACom
BPos BNegBCom
Ain
Bin
Dis
Bout
Bout
Aout
Aout
6 5 7
2 3 1
MOTOROLA CMOS LOGIC DATAMC14583B
2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
VDD
Vdc
– 55
_
C 25
_
C 125
_
C
Unit
Characteristic
Symbol
VDD
Vdc
Min Max Min Typ # Max Min Max
Unit
Output Voltage “0” Level
Vin = VDD or 0 VOL 5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
Vin = 0 or VDD VOH 5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage “0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL 5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
Vdc
“1” Level
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
VIH 5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Vdc
Output Drive Current
(VOH = 2.5 Vdc) Source
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
IOH 5.0
5.0
10
15
– 1.2
– 0.25
– 1.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
mAdc
(VOL = 0.4 Vdc) Sink
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
IOL 5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current Iin 15 — ±0.1 — ±0.00001 ±0.1 — ±1.0 µAdc
Input Capacitance
(Vin = 0) Cin — — — — 5.0 7.5 — — pF
Quiescent Current
(Per Package) IDD 5.0
10
15
—
—
—
0.25
0.5
1.0
—
—
—
0.0005
0.0010
0.0015
0.25
0.5
1.0
—
—
—
7.5
15
30
µAdc
Total Supply Current**†
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
IT5.0
10
15
IT = (1.33 µA/kHz) f + IDD
IT = (2.65 µA/kHz) f + IDD
IT = (3.98 µA/kHz) f + IDD
µAdc
Three–State Leakage Current ITL 15 — ±0.1 — ±0.0001 ±0.1 — ±3.0 µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.
**The formulas given are for the typical characteristics only at 25
_
C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005.
This device contains protection circuitry to guard against damage
due to high static voltages or electric fields. However , precautions must
be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, Vin and
Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage
level (e.g., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Bout
DIS
Bin
VDD
Ain
Bout
Aout
Aout
BNeg
BPos
BCom
VSS
ACom
APos
ANeg
MOTOROLA CMOS LOGIC DATA 3
MC14583B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25
_
C)
Characteristic Symbol VDD Min Typ # Max Unit
Output Rise Time
tTLH = (3.0 ns/pF) CL + 30 ns
tTLH = (1.5 ns/pF) CL + 15 ns
tTLH = (1.1 ns/pF) CL + 10 ns
tTLH 5.0
10
15
—
—
—
180
90
65
360
180
130
ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 25 ns
tTHL = (0.75 ns/pF) CL + 12.5 ns
tTHL = (0.55 ns/pF) CL + 9.5 ns
tTHL 5.0
10
15
—
—
—
100
50
40
200
100
80
ns
Propagation Delay Time
Ain, Bin to Aout, Bout
tPLH, tPHL = (1.7 ns/pF) CL + 565 ns
tPLH, tPHL = (0.66 ns/pF) CL + 197 ns
tPLH, tPHL = (0.5 ns/pF) CL + 125 ns
tPLH,
tPHL 5.0
10
15
—
—
—
650
230
150
1300
460
300
ns
Ain, Bin to Aout, Bout
tPLH, tPHL = (1.7 ns/pF) CL + 1015 ns
tPLH, tPHL = (0.66 ns/pF) CL + 347 ns
tPLH, tPHL = (0.5 ns/pF) CL + 235 ns
tPLH,
tPHL 5.0
10
15
—
—
—
1100
380
260
2200
760
520
ns
Ain, Bin to Exclusive OR
tPLH, tPHL = (1.7 ns/pF) CL + 665 ns
tPLH, tPHL = (0.66 ns/pF) CL + 257 ns
tPLH, tPHL = (0.5 ns/pF) CL + 145 ns
tPLH,
tPHL 5.0
10
15
—
—
—
750
280
170
1500
560
340
ns
3–State Enable, Disable Delay Time (see figure 5)
ton, toff = (1.7 ns/pF) CL + 140 ns
ton, toff = (0.66 ns/pF) CL + 57 ns
ton, toff = (0.5 ns/pF) CL + 30 ns
ton,
toff 5.0
10
15
—
—
—
225
90
55
450
180
110
ns
Positive Threshold Voltage
(R1, R2 = 5.0 kΩ)VT+ 5.0
10
15
—
—
—
3.30
5.70
8.20
—
—
—
Vdc
Negative Threshold Voltage
(R1, R2 = 5.0 kΩ)VT– 5.0
10
15
—
—
—
1.70
4.30
6.80
—
—
—
Vdc
Hysteresis Voltage
(R1, R2 = 5.0 kΩ)VH5.0
10
15
0.85
0.70
0.70
1.70
1.40
1.40
3.40
2.80
2.80
Vdc
Threshold Voltage Variation, A to B
(R1, R2 = 5.0 kΩ)∆VT5.0
10
15
—
—
—
0.1
0.15
0.20
—
—
—
Vdc
*The formulas given are for the typical characteristics only at 25
_
C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’ s potential performance.
MOTOROLA CMOS LOGIC DATAMC14583B
4
Figure 1. Typical Output Source and Sink Characteristics Test Circuit
NJ
VDD Vout
VDD
VSS SW1
SW2 VSS
IO
EXTERNAL
POWER
SUPPLY
Ain
DIS
Bin
Aout
Aout
Bout
Bout
Output Source
Characteristics Output Sink
Characteristics
Test
Value VGS = – VDD
VDS = Vout – VDD
NJ
Test
Value VGS = VDD
VDS = Vout
Output
Under Test Switch Position Switch Position
SW1 SW2 SW1 SW2
1Aout, Bout 1 2 2
2Aout, Bout 2 1 1
1Exclusive OR 2 1 1
1
2
2
1
Figure 2. Power Dissipation Test Circuit and Waveforms
PULSE
GENERATOR 1 Ain Aout
PULSE
GENERATOR 2
DIS
Bin
Aout
Bout
Bout
VDD
VSS
0.01
µ
F
CERAMIC
500
µ
F
CLCL
CL
CL
CLfout, Ain
fout, Bin
ID
Figure 3. Typical Threshold Points
POSITIVE
COMMON
NEGATIVE
R1
R2
POSITIVE
COMMON
NEGATIVE
R1
A — Feedback scheme for independent threshold adjustment:
B — Feedback scheme for hysteresis adjustment:
80
70
60
50
40
30
20
10 1.0 M100 k10 k1.0 k10010 20 40 6 8
R1, R2, RESISTANCE (OHMS)
TYPICAL THRESHOLD POINT (%VDD)
VDD = 5.0 V
VDD = 10 V
VDD = 15 V
VSS = 0
MOTOROLA CMOS LOGIC DATA 5
MC14583B
Figure 4. Switching Time Test Circuit and Waveforms
PULSE
GENERATOR 1
PULSE
GENERATOR 3
PULSE
GENERATOR 2
Ain Aout
DIS
Bin
Aout
Bout
Bout
VDD
CL
VSS CLCLCLCL
50%
tPLH
50%
50%
50% 90%
10%
90%
10%
50%
90%
10%
50%
50%
90% 10%
tftr
tPHL
tPHL
tPLH
tPHL
tPLH tftoff ton
tPLH
tPHL
trton
toff
tftrtPHL
tPLH tPHL
tPLH
tftr
Ain
Bin
3–STATE
DISABLE
Aout
Bout
Aout
Bout
EXCLUSIVE
OR
VDD
VSS
VDD
VSS
VDD
VSS
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
VOH
VOL
NOTE: Dashed lines indicate high output resistance
INPUT = tr = tf = 20 ns
trtf
MOTOROLA CMOS LOGIC DATAMC14583B
6
Figure 5. 3–State Switching Time Test Circuit and Waveforms
VOL′ and VOH′ refer to the levels present as a result of the 1 k ohm load resistors.
*Metal film, ± 1%, 1/4 W or greater
CL = 15 pF, which includes test circuit capacitance.
Test Switch Position
ton HL 1
ton LH 2
toff HL 2
toff LH 1
PULSE
GENERATOR 1
PULSE
GENERATOR 2
VDD VDD
VSS
Ain
DIS
Bin
Aout
Aout
Bout
Bout CL1 k*
1 k*
1
2SW
Ain
Bin
3–STATE
DISABLE
Aout
Bout
VDD
VSS
VDD
VSS
VDD
VSS
VOH
VOL
VOH
VOL
50%
ton LH toff LH toff LH
10%
toff HL
VOL
ton LH
10% 90%
VOH
′
VOH
′
90% VOH
toff LH
VOL
′
10% (VOH – VOL
′
)
VOL
′
10% (VOH – VOL
′
)
90% 90%
VOH
ton HL
VOH
′
SWITCH POSITION 2 SWITCH POSITION 1
MOTOROLA CMOS LOGIC DATA 7
MC14583B
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
–A–
B
FC
S
HGD
J
L
M
16 PL
SEATING
1 8
916
K
PLANE
–T–
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
L SUFFIX
CERAMIC DIP PACKAGE
CASE 620–10
ISSUE V
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
–A–
–B–
–T–
FE
G
NK
C
SEATING
PLANE
16 PLD
S
A
M
0.25 (0.010) T
16 PLJ
S
B
M
0.25 (0.010) T
M
L
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.750 0.785 19.05 19.93
B0.240 0.295 6.10 7.49
C––– 0.200 ––– 5.08
D0.015 0.020 0.39 0.50
E0.050 BSC 1.27 BSC
F0.055 0.065 1.40 1.65
G0.100 BSC 2.54 BSC
H0.008 0.015 0.21 0.38
K0.125 0.170 3.18 4.31
L0.300 BSC 7.62 BSC
M0 15 0 15
N0.020 0.040 0.51 1.01
_ _ _ _
16 9
1 8
MOTOROLA CMOS LOGIC DATAMC14583B
8
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1 8
16 9
SEATING
PLANE
F
J
M
RX 45
_
G
8 PLP
–B–
–A–
M
0.25 (0.010) B S
–T–
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided
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MC14583B/D
*MC14583B/D*
◊
