TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
A-Suffix Versions Offer 5-mV VIO
D
B-Suffix Versions Offer 2-mV VIO
D
Wide Range of Supply Voltages
1.4 V to 16 V
D
True Single-Supply Operation
D
Common-Mode Input Voltage Includes the
Negative Rail
D
Low Noise . . . 30 nV/√Hz Typ at f = 1 kHz
(High-Bias Versions)
description
The TLC252, TLC25L2, and TLC25M2 are
low-cost, low-power dual operational amplifiers
designed to operate with single or dual supplies.
These devices utilize the Texas Instruments
silicon gate LinCMOS process, giving them stable input of fset voltages that are available in selected grades
of 2, 5, or 10 mV maximum, very high input impedances, and extremely low input offset and bias currents.
Because the input common-mode range extends to the negative rail and the power consumption is extremely
low, this series is ideally suited for battery-powered or energy-conserving applications. The series offers
operation down to a 1.4-V supply, is stable at unity gain, and has excellent noise characteristics.
These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures
at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015.1. However , care should be exercised
in handling these devices as exposure to ESD may result in a degradation of the device parametric
performance.
AVAILABLE OPTIONS
VIOmax
PACKAGED DEVICES
CHIP FORM
TA
V
IO
max
AT 25°CSMALL OUTLINE
(D) PLASTIC DIP
(P) TSSOP
(PW)
CHIP
FORM
(Y)
10 mV TLC252CD TLC252CP TLC252CPW TLC252Y
10
mV
5 mV
TLC252CD
TLC252ACD
TLC252CP
TLC252ACP
TLC252CPW
TLC252ACPW —
2 mV TLC252BCD TLC252BCP TLC252BCPW —
10 mV TLC25L2CD TLC25L2CP TLC25L2CPW TLC25L2Y
0°C to 70°C
10
mV
5 mV
TLC25L2CD
TLC25L2ACD
TLC25L2CP
TLC25L2ACP
TLC25L2CPW
TLC25L2ACPW —
2 mV TLC25L2BCD TLC25L2BCP TLC25L2BCPW —
10 mV TLC25M2CD TLC25M2CP — TLC25M2Y
5 mV TLC25M2ACD TLC25M2ACP — —
2 mV TLC25M2BCD TLC25M2BCP — —
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC252CDR). Chips are tested at 25°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2001, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
8
7
6
5
1OUT
1IN–
1IN+
VDD–/GND
VDD
2OUT
2IN–
2IN+
D
,
P
,
OR
PW
PACKAGE
(TOP VIEW)
s
ymbol (each amplifier)
+
–OUT
IN+
IN–
LinCMOS is a trademark of Texas Instruments.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Because of the extremely high input impedance and low input bias and offset currents, applications for the
TLC252/25_2 series include many areas that have previously been limited to BIFET and NFET product types.
Any circuit using high-impedance elements and requiring small offset errors is a good candidate for
cost-effective use of these devices. Many features associated with bipolar technology are available with
LinCMOS operational amplifiers without the power penalties of traditional bipolar devices. General
applications such as transducer interfacing, analog calculations, amplifier blocks, active filters, and signal
buffering are all easily designed with the TLC252/25_2 series devices. Remote and inaccessible equipment
applications are possible using their low-voltage and low-power capabilities. The TLC252/25_2 series is well
suited to solve the difficult problems associated with single-battery and solar-cell-powered applications. This
series includes devices that are characterized for the commercial temperature range and are available in 8-pin
plastic dip and the small-outline package. The device is also available in chip form.
The TLC252/25_2 series is characterized for operation from 0°C to 70°C.
equivalent schematic (each amplifier)
ESD-
Protective
Network
ESD-
Protective
Network
VDD
IN+
IN–
VDD–/GND
OUT
8
3, 5
2, 6
4
1, 7
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC252Y, TLC25L2Y, and TLC25M2Y chip information
These chips, properly assembled, display characteristics similar to the TLC252/25_2. Thermal compression
or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 × 4 MINIMUM
TJMAX = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
PIN (4) IS INTERNALLY CONNECTED
TO BACKSIDE OF CHIP.
+
–1OUT
1IN+
1IN–
VDD
VDD–/GND
(8)
(6)
(3)
(2)
(5)
(1)
–
+
(7) 2IN+
2IN–
2OUT
(4)
60
73
(2)
(1)
(8)
(7)
(6)
(5) (3)
(4)
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID (see Note 2) ±18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (any input) –0.3 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duration of short circuit at (or below) 25°C free-air temperature (see Note 3) unlimited. . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to VDD–/GND.
2. Differential voltages are at IN+, with respect to IN–.
3. The output may be shorted to either supply . T emperature and/or supply voltages must be limited to ensure the maximum dissipation
rating is not exceeded.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING
D725 mW 5.8 mW/°C464 mW
P1000 mW 8.0 mW/°C 640 mW
PW 525 mW 4.2 mW/°C336 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD 1.4 16 V
VDD = 1.4 V 0 0.2
Common mode in
p
ut voltage VIC
VDD = 5 V –0.2 4
V
Common
-
mode
input
voltage
,
V
IC VDD = 10 V –0.2 9
V
VDD = 16 V –0.2 14
Operating free-air temperature, TA0 70 °C
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 1.4 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
TLC252_C TLC25L2_C TLC25M2_C
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNIT
25°C 10 10 10
TLC25_2C 0°C to
70°C12 12 12
Input
VO=02V
25°C 5 5 5
VIO offset
voltage TLC25_2AC
V
O =
0
.
2
V
,
RS = 50 Ω0°C to
70°C6.5 6.5 6.5 mV
25°C 2 2 2
TLC25_2BC 0°C to
70°C3 3 3
αVIO Average temperature
coefficient of input
offset voltage
25°C
to
70°C1 1 1 µV/°C
25°C 1 60 1 60 1 60
IIO Input offset current VO = 0.2 V 0°C to
70°C300 300 300 pA
25°C 1 60 1 60 1 60
IIB Input bias current VO = 0.2 V 0°C to
70°C600 600 600 pA
VICR Common-mode input
voltage range 25°C0 to
0.2 0 to
0.2 0 to
0.2 V
VOM Peak output voltage
swing‡VID = 100 mV 25°C 450 700 450 700 450 700 mV
AVD Large-signal
differential voltage
amplification
VO = 100 to 300 mV,
RS = 50 Ω25°C 10 20 20 V/mV
CMRR Common-mode
rejection ratio VO = 0.2 V,
VIC = VICRmin 25°C 60 77 60 77 60 77 dB
IDD Supply current VO = 0.2 V,
No load 25°C 300 375 25 34 200 250 µA
†All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Unless otherwise
noted, an output load resistor is connected from the output to ground and has the following value: for low bias RL = 1 MΩ, for medium bias
RL = 100 kΩ, and for high bias RL = 10 kΩ.
‡The output swings to the potential of VDD–/GND.
operating characteristics, VDD = 1.4 V, TA = 25°C
TEST CONDITIONS
TLC252_C TLC25L2_C TLC25M2_C
UNIT
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNIT
B1Unity-gain bandwidth AV = 40 dB,
CL = 10 pF,
RS = 50 Ω12 12 12 kHz
SR Slew rate at unity gain See Figure 1 0.1 0.001 0.01 V/µs
Overshoot factor See Figure 1 30% 35% 35%
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
†TLC252C, TLC252AC,
TLC252BC UNIT
A
MIN TYP MAX
TLC252C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC252C
O,
RS = 50 Ω,
IC ,
RL = 10 kΩFull range 12
VIO
In
p
ut offset voltage
TLC252AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5
mV
V
IO
Input
offset
voltage
TLC252AC
O,
RS = 50 Ω,
IC ,
RL = 10 kΩFull range 6.5
mV
TLC252BC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.23 2
TLC252BC
O,
RS = 50 Ω,
IC ,
RL = 10 kΩFull range 3
αVIO Average temperature coef ficient of
input offset voltage 25°C to 70°C 1.8 µV/°C
IIO
In
p
ut offset current (see Note 4)
VO=25V
VIC =25V
25°C 0.1 60 p
A
I
IO
Input
offset
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 7 300
pA
IIB
In
p
ut bias current (see Note 4)
VO=25V
VIC =25V
25°C 0.6 60 p
A
I
IB
Input
bias
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 40 600
pA
VICR
Common-mode input volta
g
e25°C–0.2
to
4
–0.3
to
4.2 V
V
ICR
g
range (see Note 5) Full range –0.2
to
3.5 V
25°C 3.2 3.8
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ0°C3 3.8 V
70°C 3 3.8
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
70°C 0 50
L i l diff ti l lt
25°C 5 23
AVD Large-signal differential voltage
am
p
lification
VO = 0.25 V to 2 V, RL = 10 kΩ0°C4 27 V/mV
am lification
70°C 4 20
25°C 65 80
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 84 dB
70°C 60 85
S l lt j ti ti
25°C 65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VDD)
VDD = 5 V to 10 V, VO = 1.4 V 0°C60 94 dB
(∆VDD/∆VDD)
70°C 60 96
V25V
V25V
25°C 1.4 3.2
IDD Supply current (two amplifiers)
V
O =
2
.
5
V
,
No load
V
IC =
2
.
5
V
,0°C1.6 3.6 mA
No
load
70°C 1.2 2.6
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS T
A
†TLC252C, TLC252AC,
TLC252BC UNIT
A
MIN TYP MAX
TLC252C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC252C
O,
RS = 50 Ω,
IC ,
RL = 10 kΩFull range 12
VIO
In
p
ut offset voltage
TLC252AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5
mV
V
IO
Input
offset
voltage
TLC252AC
O,
RS = 50 Ω,
IC ,
RL = 10 kΩFull range 6.5
mV
TLC252BC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.29 2
TLC252BC
O,
RS = 50 Ω,
IC ,
RL = 10 kΩFull range 3
αVIO Average temperature coef ficient of input
offset voltage 25°C to 70°C 2 µV/°C
IIO
In
p
ut offset current (see Note 4)
VO=25V
VIC =25V
25°C 0.1 60 p
A
I
IO
Input
offset
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 7 300
pA
IIB
In
p
ut bias current (see Note 4)
VO=25V
VIC =25V
25°C 0.6 60 p
A
I
IB
Input
bias
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 50 600
pA
VICR
Common-mode input volta
g
e25°C–0.2
to
9
–0.3
to
9.2 V
V
ICR
g
range (see Note 5) Full range –0.2
to
8.5 V
25°C 8 8.5
VOH High-level output voltage VID = 100 mV, RL = 10 kΩ0°C8 8.5 V
70°C 7.8 8.4
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
70°C 0 50
L i l diff ti l lt
25°C 10 36
AVD Large-signal differential voltage
am
p
lification
VO = 1 V to 6 V, RL = 10 kΩ0°C7.5 42 V/mV
am lification
70°C 7.5 32
25°C 65 85
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 88 dB
70°C 60 88
S l lt j ti ti
25°C 65 95
kSVR Supply-voltage rejection ratio
(∆VDD/∆VDD)
VDD = 5 V to 10 V, VO = 1.4 V 0°C60 94 dB
(∆VDD/∆VDD)
70°C 60 96
V5V
V5V
25°C 1.9 4
IDD Supply current (two amplifiers)
V
O =
5
V
,
No load
V
IC =
5
V
,0°C2.3 4.4 mA
No
load
70°C 1.6 3.4
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VDD = 5 V
PARAMETER TEST CONDITIONS T
A
TLC252C, TLC252AC,
TLC252BC UNIT
A
MIN TYP MAX
25°C 3.6
VI
(
PP
)
= 1 V 0°C 4
SR
Slew rate at unity gain
R
L
= 10 kΩ, C
L
= 20 pF,
()
70°C 3
V/µs
SR
Slew
rate
at
unity
gain
L,
See Figure 1
L,
25°C 2.9
V/
µ
s
VI
(
PP
)
= 2.5 V 0°C 3.1
()
70°C 2.5
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25°C 25 nV/√Hz
VV
C20F
R 100 kΩ
25°C 320
BOM Maximum output-swing bandwidth VO = VOH,
See Figure
CL = 20 pF, RL = 100 kΩ,0°C340 kHz
See
Figure
70°C 260
25°C 1.7
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 0°C2MHz
70°C 1.3
V10mV
fB
C20pF
25°C 46°
φmPhase margin
V
I =
10
m
V
,
See Figure 3
f
=
B
1,
C
L =
20
p
F
,0°C47°
See
Figure
3
70°C 43°
operating characteristics, VDD = 10 V
PARAMETER TEST CONDITIONS T
A
TLC252C, TLC252AC,
TLC252BC UNIT
A
MIN TYP MAX
25°C 5.3
VI
(
PP
)
= 1 V 0°C 5.9
SR
Slew rate at unity gain
R
L
= 10 kΩ, C
L
= 20 pF,
()
70°C 4.3
V/µs
SR
Slew
rate
at
unity
gain
L,
See Figure 1
L,
25°C 4.6
V/
µ
s
VI
(
PP
)
= 5.5 V 0°C 5.1
()
70°C 3.8
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25°C 25 nV/√Hz
VV
C20F
R 100 kΩ
25°C 200
BOM Maximum output-swing bandwidth VO = VOH,
See Figure 1
CL = 20 pF, RL = 100 kΩ,0°C220 kHz
See
Figure
1
70°C 140
25°C 2.2
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 0°C2.5 MHz
70°C 1.8
V10mV
fB
C20pF
25°C 49°
φmPhase margin
V
I =
10
m
V
,
See Figure 3
f
=
B
1,
C
L =
20
p
F
,0°C50°
See
Figure
3
70°C 46°
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC25L2C
TLC25L2AC
TLC25L2BC UNIT
MIN TYP MAX
TLC252C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC252C
O,
RS = 50 Ω,
IC ,
RL = 1 MΩFull range 12
VIO
In
p
ut offset voltage
TLC252AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5
mV
V
IO
Input
offset
voltage
TLC252AC
O,
RS = 50 Ω,
IC ,
RL = 1 MΩFull range 6.5
mV
TLC252BC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.204 2
TLC252BC
O,
RS = 50 Ω,
IC ,
RL = 1 MΩFull range 3
αVIO Average temperature coef ficient of
input offset voltage 25°C to 70°C 1.1 µV/°C
IIO
In
p
ut offset current (see Note 4)
VO=25V
VIC =25V
25°C 0.1 60 p
A
I
IO
Input
offset
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 7 300
pA
IIB
In
p
ut bias current (see Note 4)
VO=25V
VIC =25V
25°C 0.6 60 p
A
I
IB
Input
bias
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 50 600
pA
VICR
Common-mode input volta
g
e25°C–0.2
to
4
–0.3
to
4.2 V
V
ICR
g
range (see Note 5) Full range –0.2
to
3.5 V
25°C 3.2 4.1
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ0°C3 4.1 V
70°C 3 4.2
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
70°C 0 50
L i l diff ti l lt
25°C 50 700
AVD Large-signal differential voltage
am
p
lification
VO = 0.25 V to 2 V, RL = 1 MΩ0°C50 700 V/mV
am lification
70°C 50 380
25°C 65 94
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 95 dB
70°C 60 95
S l lt j ti ti
25°C 70 97
kSVR Supply-voltage rejection ratio
(∆VDD/∆VDD)
VDD = 5 V to 10 V, VO = 1.4 V 0°C60 97 dB
(∆VDD/∆VDD)
70°C 60 98
V25V
V25V
25°C 20 34
IDD Supply current (two amplifiers)
V
O =
2
.
5
V
,
No load
V
IC =
2
.
5
V
,0°C24 42 µA
No
load
70°C 16 28
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC25L2C
TLC25L2AC
TLC25L2BC UNIT
MIN TYP MAX
TLC252C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC252C
O,
RS = 50 Ω,
IC ,
RL = 1 MΩFull range 12
VIO
In
p
ut offset voltage
TLC252AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5
mV
V
IO
Input
offset
voltage
TLC252AC
O,
RS = 50 Ω,
IC ,
RL = 1 MΩFull range 6.5
mV
TLC252BC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.235 2
TLC252BC
O,
RS = 50 Ω,
IC ,
RL = 1 MΩFull range 3
αVIO Average temperature coef ficient of
input offset voltage 25°C to 70°C 1 µV/°C
IIO
In
p
ut offset current (see Note 4)
VO=5V
VIC =5V
25°C 0.1 60 p
A
I
IO
Input
offset
current
(see
Note
4)
V
O =
5
V
,
V
IC =
5
V
70°C 8 300
pA
IIB
In
p
ut bias current (see Note 4)
VO=5V
VIC =5V
25°C 0.7 60 p
A
I
IB
Input
bias
current
(see
Note
4)
V
O =
5
V
,
V
IC =
5
V
70°C 50 600
pA
VICR
Common-mode input volta
g
e25°C–0.2
to
9
–0.3
to
9.2 V
V
ICR
g
range (see Note 5) Full range –0.2
to
8.5 V
25°C 8 8.9
VOH High-level output voltage VID = 100 mV, RL = 1 MΩ0°C7.8 8.9 V
70°C 7.8 8.9
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
70°C 0 50
L i l diff ti l lt
25°C 50 860
AVD Large-signal differential voltage
am
p
lification
VO = 1 V to 6 V, RL = 1 MΩ0°C50 1025 V/mV
am lification
70°C 50 660
25°C 65 97
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 97 dB
70°C 60 97
S l lt j ti ti
25°C 70 97
kSVR Supply-voltage rejection ratio
(∆VDD/∆VDD)
VDD = 5 V to 10 V, VO = 1.4 V 0°C60 97 dB
(∆VDD/∆VDD)
70°C 60 98
V5V
V5V
25°C 29 46
IDD Supply current (two amplifiers)
V
O =
5
V
,
No load
V
IC =
5
V
,0°C36 66 µA
No
load
70°C 22 40
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC25L2C
TLC25L2AC
TLC25L2BC UNIT
MIN TYP MAX
25°C 0.03
VI
(
PP
)
= 1 V 0°C 0.04
SR
Slew rate at unity gain
R
L
= 1 MΩ, C
L
= 20 pF,
()
70°C 0.03
V/µs
SR
Slew
rate
at
unity
gain
L,
See Figure 1
L,
25°C 0.03
V/
µ
s
VI
(
PP
)
= 2.5 V 0°C 0.03
()
70°C 0.02
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25°C 68 nV/√Hz
Mi tt i
VV
C20F
R1MΩ
25°C 5
BOM Maximum output-swing
bandwidth
VO = VOH,
See Figure
CL = 20 pF, RL = 1 MΩ,0°C6kHz
bandwidth
See
Figure
70°C 4.5
25°C 85
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 0°C100 MHz
70°C 65
V10mV
fB
C20pF
25°C 34°
φmPhase margin
V
I =
10
m
V
,
See Figure 3
f
=
B
1,
C
L =
20
p
F
,0°C36°
See
Figure
3
70°C 30°
operating characteristics, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC25L2C
TLC25L2AC
TLC25L2BC UNIT
MIN TYP MAX
25°C 0.05
VI
(
PP
)
= 1 V 0°C 0.05
SR
Slew rate at unity gain
R
L
= 1 MΩ, C
L
= 20 pF,
()
70°C 0.04
V/µs
SR
Slew
rate
at
unity
gain
L,
See Figure 1
L,
25°C 0.04
V/
µ
s
VI
(
PP
)
= 5.5 V 0°C 0.05
()
70°C 0.04
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25°C 68 nV/√Hz
Mi tt i
VV
C20F
R1MΩ
25°C 1
BOM Maximum output-swing
bandwidth
VO = VOH,
See Figure 1
CL = 20 pF, RL = 1 MΩ,0°C1.3 kHz
bandwidth
See
Figure
1
70°C 0.9
25°C110
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 0°C125 MHz
70°C 90
V10mV
fB
C20pF
25°C 38°
φmPhase margin
V
I =
10
m
V
,
See Figure 3
f
=
B
1,
C
L =
20
p
F
,0°C40°
See
Figure
3
70°C 34°
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC25M2C
TLC25M2AC
TLC25M2BC UNIT
MIN TYP MAX
TLC252C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC252C
O,
RS = 50 Ω,
IC ,
RL = 100 kΩFull range 12
VIO
In
p
ut offset voltage
TLC252AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5
mV
V
IO
Input
offset
voltage
TLC252AC
O,
RS = 50 Ω,
IC ,
RL = 100 kΩFull range 6.5
mV
TLC252BC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.22 2
TLC252BC
O,
RS = 50 Ω,
IC ,
RL = 100 kΩFull range 3
αVIO Average temperature coef ficient of
input offset voltage 25°C to 70°C 1.7 µV/°C
IIO
In
p
ut offset current (see Note 4)
VO=25V
VIC =25V
25°C 0.1 60 p
A
I
IO
Input
offset
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 7 300
pA
IIB
In
p
ut bias current (see Note 4)
VO=25V
VIC =25V
25°C 0.6 60 p
A
I
IB
Input
bias
current
(see
Note
4)
V
O =
2
.
5
V
,
V
IC =
2
.
5
V
70°C 40 600
pA
VICR
Common-mode input volta
g
e25°C–0.2
to
4
–0.3
to
4.2 V
V
ICR
g
range (see Note 5) Full range –0.2
to
3.5 V
25°C 3.2 3.9
VOH High-level output voltage VID = 100 mV, RL = 100 kΩ0°C3 3.9 V
70°C 3 4
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
70°C 0 50
L i l diff ti l lt
25°C 25 170
AVD Large-signal differential voltage
am
p
lification
VO = 0.25 V to 2 V, RL = 100 kΩ0°C15 200 V/mV
am lification
70°C 15 140
25°C 65 91
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 91 dB
70°C 60 92
S l lt j ti ti
25°C 70 93
kSVR Supply-voltage rejection ratio
(∆VDD/∆VDD)
VDD = 5 V to 10 V, VO = 1.4 V 0°C60 92 dB
(∆VDD/∆VDD)
70°C 60 94
V25V
V25V
25°C 210 560
IDD Supply current (two amplifiers)
V
O =
2
.
5
V
,
No load
V
IC =
2
.
5
V
,0°C250 640 µA
No
load
70°C 170 440
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics at specified free-air temperature, VDD = 10 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TA†
TLC25M2C
TLC25M2AC
TLC25M2BC UNIT
MIN TYP MAX
TLC252C
V
O
= 1.4 V, V
IC
= 0, 25°C 1.1 10
TLC252C
O,
RS = 50 Ω,
IC ,
RL = 100 kΩFull range 12
VIO
In
p
ut offset voltage
TLC252AC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.9 5
mV
V
IO
Input
offset
voltage
TLC252AC
O,
RS = 50 Ω,
IC ,
RL = 100 kΩFull range 6.5
mV
TLC252BC
V
O
= 1.4 V, V
IC
= 0, 25°C 0.224 2
TLC252BC
O,
RS = 50 Ω,
IC ,
RL = 100 kΩFull range 3
αVIO Average temperature coef ficient of
input offset voltage 25°C to 70°C 2.1 µV/°C
IIO
In
p
ut offset current (see Note 4)
VO=5V
VIC =5V
25°C 0.1 60 p
A
I
IO
Input
offset
current
(see
Note
4)
V
O =
5
V
,
V
IC =
5
V
70°C 7 300
pA
IIB
In
p
ut bias current (see Note 4)
VO=5V
VIC =5V
25°C 0.7 60 p
A
I
IB
Input
bias
current
(see
Note
4)
V
O =
5
V
,
V
IC =
5
V
70°C 50 600
pA
VICR
Common-mode input volta
g
e25°C–0.2
to
9
–0.3
to
9.2 V
V
ICR
g
range (see Note 5) Full range –0.2
to
8.5 V
25°C 8 8.7
VOH High-level output voltage VID = 100 mV, RL = 100 kΩ0°C7.8 8.7 V
70°C 7.8 8.7
25°C 0 50
VOL Low-level output voltage VID = –100 mV, IOL = 0 0°C0 50 mV
70°C 0 50
L i l diff ti l lt
25°C 25 275
AVD Large-signal differential voltage
am
p
lification
VO = 1 V to 6 V, RL = 100 kΩ0°C15 320 V/mV
am lification
70°C 15 230
25°C 65 94
CMRR Common-mode rejection ratio VIC = VICRmin 0°C 60 94 dB
70°C 60 94
S l lt j ti ti
25°C 70 93
kSVR Supply-voltage rejection ratio
(∆VDD/∆VDD)
VDD = 5 V to 10 V, VO = 1.4 V 0°C60 92 dB
(∆VDD/∆VDD)
70°C 60 94
V5V
V5V
25°C 285 600
IDD Supply current (two amplifiers)
V
O =
5
V
,
No load
V
IC =
5
V
,0°C345 800 µA
No
load
70°C 220 560
†Full range is 0°C to 70°C.
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics, VDD = 5 V
PARAMETER TEST CONDITIONS TA
TLC25M2C
TLC25M2AC
TLC25M2BC UNIT
MIN TYP MAX
25°C 0.43
VI
(
PP
)
= 1 V 0°C 0.46
SR
Slew rate at unity gain
R
L
= 100 kΩ, C
L
= 20 pF,
()
70°C 0.36
V/µs
SR
Slew
rate
at
unity
gain
L,
See Figure 1
L,
25°C 0.40
V/
µ
s
VI
(
PP
)
= 2.5 V 0°C 0.43
()
70°C 0.34
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25°C 32 nV/√Hz
VV
C20F
R 100 kΩ
25°C 55
BOM Maximum output-swing bandwidth VO = VOH,
See Figure
CL = 20 pF, RL = 100 kΩ,0°C60 kHz
See
Figure
70°C 50
25°C 525
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 0°C600 MHz
70°C 400
V10mV
fB
C20pF
25°C 40°
φmPhase margin
V
I =
10
m
V
,
See Figure 3
f
=
B
1,
C
L =
20
p
F
,0°C41°
See
Figure
3
70°C 39°
operating characteristics, VDD = 10 V
PARAMETER TEST CONDITIONS TA
TLC25M2C
TLC25M2AC
TLC25M2BC UNIT
MIN TYP MAX
25°C 0.62
VI
(
PP
)
= 1 V 0°C 0.67
SR
Slew rate at unity gain
R
L
= 100 kΩ, C
L
= 20 pF,
()
70°C 0.51
V/µs
SR
Slew
rate
at
unity
gain
L,
See Figure 1
L,
25°C 0.56
V/
µ
s
VI
(
PP
)
= 5.5 V 0°C 0.61
()
70°C 0.46
VnEquivalent input noise voltage f = 1 kHz, RS = 20 Ω,See Figure 2 25°C 32 nV/√Hz
VV
C20F
R 100 kΩ
25°C 35
BOM Maximum output-swing bandwidth VO = VOH,
See Figure 1
CL = 20 pF, RL = 100 kΩ,0°C40 kHz
See
Figure
1
70°C 30
25°C 635
B1Unity-gain bandwidth VI = 10 mV, CL = 20 pF, See Figure 3 0°C710 MHz
70°C 510
V10mV
fB
C20pF
25°C 43°
φmPhase margin
V
I =
10
m
V
,
See Figure 3
f
=
B
1,
C
L =
20
p
F
,0°C44°
See
Figure
3
70°C 42°
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC252Y TLC25L2Y TLC25M2Y
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNIT
VIO Input offset voltage VO = 1.4 V,
RS = 50 Ω,VIC = 0 V,
See Note 6 1.1 10 1.1 10 1.1 10 mV
αVIO Average temperature
coefficient of input
offset voltage 1.8 1.1 1.7 µV/°C
IIO Input offset current
(see Note 4) VO = VDD/2, VIC = VDD/2 0.1 60 0.1 60 0.1 60 pA
IIB Input bias current
(see Note 4) VO = VDD/2, VIC = VDD/2 0.6 60 0.6 60 0.6 60 pA
VICR Common-mode input
voltage range
(see Note 5)
–0.2
to
4
–0.3
to
4.2
–0.2
to
4
–0.3
to
4.2
–0.2
to
4
–0.3
to
4.2 V
VOH High-level output
voltage VID = 100 mV, See Note 6 3.2 3.8 3.2 4.1 3.2 3.9 V
VOL Low-level output
voltage VID = –100 mV, IOL = 0 0 50 0 50 0 50 mV
AVD Large-signal
differential voltage
amplification VO = 0.25 V, See Note 6 5 23 50 700 25 170 V/mV
CMRR Common-mode
rejection ratio VIC = VICRmin 65 80 65 94 65 91 dB
kSVR Supply-voltage
rejection ratio
(∆VDD/∆VIO)
VDD = 5 V to 10 V,
VO = 1.4 V 65 95 70 97 70 93 dB
IDD Supply current VO = VDD/2,
VIC = VDD/2, No load 1.4 3.2 0.02 0.034 0.21 0.56 mA
operating characteristics, VDD = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TLC252Y TLC25L2Y TLC25M2Y
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
UNIT
Slew rate at C
L
= 20 pF, V
I(PP)
= 1 V 3.6 0.03 0.43
V/µs
unity gain
L,
See Note 6
I(PP)
VI(PP) = 2.5 V 2.9 0.03 0.40
V/
µ
s
VnEquivalent input
noise voltage f = 1 kHz, RS = 20 Ω2.5 68 32 nV√/Hz
BOM Maximum output-
swing bandwidth VO = VOH,
RL = 10 kΩCL = 20 pF, 320 5 55 kHz
B1Unity-gain
bandwidth VI = 10 mV, CL = 20 pF 1.7 0.085 0.525 MHz
φmPhase margin f = B1,
CL = 20 pF VI = 10 mV, 46°34°40°
NOTES: 4. The typical values of input bias current and input offset current below 5 pA were determined mathematically.
5. This range also applies to each input individually.
6. For low-bias mode, RL = 1 MΩ; for medium-bias mode, RL = 100 kΩ, and for high-bias mode, RL = 10 kΩ.
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
single-supply versus split-supply test circuits
Because the TLC252, TLC25L2, and TLC25M2 are optimized for single-supply operation, circuit configurations
used for the various tests often present some inconvenience since the input signal, in many cases, must be
offset from ground. This inconvenience can be avoided by testing the device with split supplies and the output
load tied to the negative rail. A comparison of single-supply versus split-supply test circuits is shown below. The
use of either circuit gives the same result.
+
–
CLRL
VI
VO
VDD
+
–
CLRL
VI
VO
VDD+
VDD–
(a) SINGLE SUPPLY (b) SPLIT SUPPLY
Figure 1. Unity-Gain Amplifier
(a) SINGLE SUPPLY (a) SPLIT SUPPLY
+
–
1/2 VDD VO
VDD
2 kΩ
20 Ω
20 Ω
+
–VO
VDD
2 kΩ
20 Ω20 ΩVDD–
Figure 2. Noise-Test Circuit
(a) SINGLE SUPPLY (a) SPLIT SUPPLY
+
–
1/2 VDD
VO
VDD
10 kΩ
100 Ω
CL
VI+
–VO
VDD+
10 kΩ
100 Ω
CL
VI
VDD–
Figure 3. Gain-of-100 Inverting Amplifier
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IDD
Su
pp
ly current
vs Suppl
y
volta
g
e 4
I
DD
Supply
current
yg
vs Free-air temperature 5
Low bias vs Frequency 6
AVD Large-signal differential voltage amplification Medium bias vs Frequency 7
High bias vs Frequency 8
Low bias vs Frequency 6
Phase shift Medium bias vs Frequency 7
High bias vs Frequency 8
Figure 4
10
0024681012
100
1000
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
10000
14 16 18 20
– Supply Current –IDD Aµ
VDD – Supply Voltage – V
VO = VIC = 0.2 VDD
No Load
TA = 25°CHigh-Bias Versions
Medium-Bias Versions
Low-Bias Versions
Figure 5
10
00102030405060
100
1000
10000
70 80
– Supply Current –IDD Aµ
TA – Free-Air Temperature – °C
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
VDD = 10 V
VIC = 0 V
VO = 2 V
No Load
High-Bias Versions
Medium-Bias Versions
Low-Bias Versions
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
0.1 1 10 100 1 k 10 k 100 k
LOW-BIAS LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE SHIFT
vs
FREQUENCY
Frequency – Hz
107
106
105
104
103
102
101
1
0.1
Phase Shift
(right scale)
AVD (left scale)
VDD = 10 V
RL = 1 MΩ
TA = 25°C
Phase Shift
0°
30°
60°
90°
120°
150°
180°
AVD – Low-Bias Large-Signal Differential
ÁÁ
ÁÁ
ÁÁ
AVD V oltage Amplification
Figure 6
110 100 1 k 10 k 100 k 1 M
MEDIUM-BIAS LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE SHIFT
vs
FREQUENCY
Frequency – Hz
107
106
105
104
103
102
101
1
0.1
Phase Shift
(right scale)
AVD (left scale)
VDD = 10 V
RL = 100 kΩ
TA = 25°C
Phase Shift
0°
30°
60°
90°
120°
150°
180°
AVD – Medium-Bias Large-Signal Differential
ÁÁ
ÁÁ
AVD V oltage Amplification
Figure 7
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
10 100 1 k 10 k 100 k 1 M 10 M
Phase Shift
HIGH-BIAS LARGE-SIGNAL
DIFFERENTIAL VOLTAGE AMPLIFICATION
AND PHASE SHIFT
vs
FREQUENCY
Frequency – Hz
107
106
105
104
103
102
101
1
0.1
Phase Shift (right scale)
AVD (left scale)
0°
30°
60°
90°
120°
150°
180°
VDD = 10 V
RL = 10 kΩ
TA = 25°C
AVD – High-Bias Large-Signal Differential
ÁÁ
ÁÁ
AVD V oltage Amplification
Figure 8
TLC252, TLC252A, TLC252B, TLC252Y, TLC25L2, TLC25L2A, TLC25L2B
TLC25L2Y, TLC25M2, TLC25M2A, TLC25M2B, TLC25M2Y
LinCMOS DUAL OPERATIONAL AMPLIFIERS
SLOS002I – JUNE 1983 – REVISED MARCH 2001
20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
latch-up avoidance
Junction-isolated CMOS circuits have an inherent parasitic PNPN structure that can function as an SCR. Under
certain conditions, this SCR may be triggered into a low-impedance state, resulting in excessive supply current.
To avoid such conditions, no voltage greater than 0.3 V beyond the supply rails should be applied to any pin.
In general, the operational amplifier supplies should be applied simultaneously with, or before, application of
any input signals.
output stage considerations
The amplifier’s output stage consists of a source-follower-connected pullup transistor and an open-drain
pulldown transistor. The high-level output voltage (VOH) is virtually independent of the IDD selection and
increases with higher values of VDD and reduced output loading. The low-level output voltage (VOL) decreases
with reduced output current and higher input common-mode voltage. With no load, VOL is essentially equal to
the potential of VDD–/GND.
supply configurations
Even though the TLC252/25_2C series is characterized for single-supply operation, it can be used effectively
in a split-supply configuration if the input common-mode voltage (VICR), output swing (VOL and VOH), and supply
voltage limits are not exceeded.
circuit layout precautions
The user is cautioned that whenever extremely high circuit impedances are used, care must be exercised in
layout, construction, board cleanliness, and supply filtering to avoid hum and noise pickup, as well as excessive
dc leakages.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC252ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252ACDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252ACP OBSOLETE SOIC D 8 TBD Call TI Call TI
TLC252BCD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252BCDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252BCP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC252BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC252CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC252CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC252CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC252CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2ACDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2BCD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2BCDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC25L2BCDR PREVIEW SOIC D 8 TBD Call TI Call TI
TLC25L2BCP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25L2BCPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25L2CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25L2CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25L2CPSR ACTIVE SO PS 8 TBD Call TI Call TI
TLC25L2CPSRG4 ACTIVE SO PS 8 TBD Call TI Call TI
TLC25L2CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25L2CPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25M2ACD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25M2ACDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25M2ACP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25M2ACPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25M2BCD OBSOLETE SOIC D 8 TBD Call TI Call TI
TLC25M2BCP OBSOLETE PDIP P 8 TBD Call TI Call TI
TLC25M2CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25M2CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25M2CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLC25M2CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLC25M2CP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25M2CPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLC25M2CPWLE OBSOLETE TSSOP PW 8 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLC252CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC252CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC252CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC25L2CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLC25L2CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1
TLC25M2CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC252CDR SOIC D 8 2500 340.5 338.1 20.6
TLC252CDR SOIC D 8 2500 367.0 367.0 35.0
TLC252CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC25L2CDR SOIC D 8 2500 340.5 338.1 20.6
TLC25L2CPWR TSSOP PW 8 2000 367.0 367.0 35.0
TLC25M2CDR SOIC D 8 2500 340.5 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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