19-0172; Rev 6; 2/97 MAXUM +5V, Low-Power, Voltage-Output, General Description The MAX531/MAX538/MAX539 are low-power, voltage- output, 12-bit digital-to-analog converters (DACs) speci- fied for single +5V power-supply operation. The MAX531 can also be operated with +5V supplies. The MAX538/MAX539 draw only 140uA, and the MAX531 (with internal reference} draws only 260uA. The MAX538/MAX539 come in 8-pin DIP and SO packages, while the MAX531 comes in 14-pin DIP and SO pack- ages. All parts have been trimmed for offset voltage, gain, and linearity, so no further adjustment is necessary. The MAX538's buffer is fixed at a gain of +1 and the MAX539s buffer at a gain of +2. The MAX531s internal op amp may be configured for a gain of +1 or +2, as well as for unipolar or bipolar output voltages. The MAX531 can also be used as a four-quadrant multiplier without external resistors or op amps. For parallel data inputs, see the MAXS&30 data sheet. Applications Battery-Powered Test Instruments Digital Offset and Gain Adjustment Battery-Operated/Remote Industrial Controls Machine and Motion Control Devices Cellular Telephones Functional Diagram Serial 12-Bit DACs Features Operate from Single +45V Supply Buffered Voltage Output Internal 2.048V Reference (MAX531) 140pA Supply Current (MAX538/MAX539) INL = +1/2LSB (max) Guaranteed Monotonic over Temperature *-+-+ (e+e e+e he 6% Flexible Output Ranges: OV to Vop (MAX531/MAX539) Vss to Vop (MAX531) OV to 2.6V (MAX531/MAX538) 4 8-Pin SO/DIP (MAX538/MAX539) + Power-On Reset # Serial Data Output for Daisy-Chaining Ordering Information PART TEMP. RANGE PIN-PACKAGE rie MAXS31ACPD O0Cto+70 14PlasticDIP +12 MAXS31BCPD 0%Sto+70C 14PlasticDIP +1 MAXS31ACSD O10+70%S 1480 +1/2 MAXS31BCSD O0C10+70% 1480 + MAXS31BG/D O0%to+70C Dice* +1 Ordering Information continued at end of data sheet. *Dice are specified at TA = +25T only. (MAXB31 ONLY) (MAX531 ONLY) REFOUT = PEFIN BIPOFF : : . | Pin Configurations MAXLN 2048 MAXS31 FFB REFERENCE MAX538 (MAXS31 (MAX531 ONLY) MAX539 ONLY) TOP VIEW H VOUT ar AGND e POWER UP PY oN [4 [3] Yoo ain | LAeSEr MANES sok [2| AAAXLAA [7] your DAC REGISTER - (MAXS31 ONLY) os [a] MAX538 ont (12 BITS) Ves Maxsaa [6] FERN aH ae 4 tT (MAXS31 pout [4] s | aan CLK He} SHIFT REGISTER 4 ony) 5IP SO DIN mass) (2878) wasay[ ats OT , Pin Configurations continued at end of data sheet. MAXIMA Maxim Iniegrated Products 1 For free samples & the latest literature: hitp:/(www.maxim-ic.com, or phone 1-800-998-8800 6BESGXVW/S8SESXVIN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output Serial 12-Bit DACs ABSOLUTE MAXIMUM RATINGS Vop to DGND and Vpp to AGND........... -0.3V, +6V Continuous Power Dissipation (Ta = +70C) Vss to DGND and Vss to AGND ........ ee -6V, +0.3V 8-Pin Plastic DIP (derate 9.09mW/C above +70C)....727mW VDD tO VSG... occ cc ccc cce cece ceseececssceateeesseeasesseetasaness -0.3V, +12V 8-Pin SO (derate 5.88mMW/C above +70C) oe 471mWw AGND to DGND..0.. eee eect eetee ee teeeeeteenaees -0.3V, +0.3V 14-Pin Plastic DIP (derate 10.00mW/C above +70)...8300mW Digital Input Voltage to DGND ............ ee -0.3V, (Vpp + 0.3V) 14-Pin SO (derate 8. 33mW/C above +70C) 667mW REFIN ooo... cece cece ceseeceeeeeeeeeeeeseeeeeaees (Ves - 0.3V), (Vpp + 0.3V) Operating Temperature Ranges REFOUT to AGND oo... ccc ete eteeee -0.3V, (Vop + 0.3V) MAX53 ee cccecccceee ccc ceeteeeesneeeeetneeteee OT to +70 RFB ooo. .eeecceceeceeseeeseceeeeeees (Vgs - 0.3), (Vpp + 0.3V) MAK53 Eee -40T to +85 BIPOFF 0.0... cccceeeeeee (Vss - 0.3V), (Vpp + 0.3V) Storage Temperature Range 65 to +165 VOUT (Note 1) oo. ccccccscccsecseseresseesssecrsssceserseserseaeees Vss, Vpp Lead Temperature (soldering, 10SEC} 0... seeeiees +300 Continuous Current, Any Pin..........0..ceeeeee -20mA, +20mA Note 1: The output may be shorted to Vpp, Vss, or AGND if the package power dissipation limit is not exceeded. Siresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device ai these or any other condilions beyond those indicated in the operational sections of the specifications is not implied. Exposure lo absolute maximum raling conditions for extended pericds may affect device reliability. ELECTRICAL CHARACTERISTICSSingle +5V Supply (Vpp = +5V +10%, Veg = OV, AGND = DGND = OV, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531}, CREFoUT = 33F (MAX531), RL = 10k, CL = 100pF, Ta = Twin to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS STATIC PERFORMANCE Resolution N 12 Bits MAX53_ AC/E +0.5 Relative Accuracy (Note 2) INL LSB MAX53_BC/E +14 Differential Nonlinearity DNL Guaranteed monotonic +1 LSB Unipolar Offset Error Vos MAX53 C/E 0 8 LSB Unipolar Offset Tempco TGVos 3 ppm Gain Error (Note 2) GE MAX53_ C/E +14 LSB Gain-Error Tempco 1 ppm/*G Nowa) Rejection Ratio | pgpR | 4.5V<Vpp<5.5V 0.4 1 | LSBV VOLTAGE OUTPUT (VOUT) MAX531 (G = +1), MAX538 0 Vpp - 2 Output Voltage Range Vv MAX531 (G = +2), MAX539 0 Vop - 0.4 Output Load Regulation VOLT = 2V, RL = 2kQ 1 LSB Short-Circuit Current Isc 12 mA REFERENCE INPUT (REFIN) Voltage Range 0 Vop -2 Vv Input Resistance Code dependent, minimum at code 555 hex 40 kQ Input Capacitance Code dependent (Note 4) 10 50 pF AG Feedthrough REFIN = 1kHz, 2Vp-p -80 dB 2 MAAXLAA+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs ELECTRICAL CHARACTERISTICSSingle +5V Supply (continued) (VpD = +5V 410%, Vss = OV, AGND = DGND = OV, REFIN = 2.048V (external), RFB = BIPOFF = VOUT (MAX531}, CREFOUT = 33ynF (MAX531), RL = 10kQ, CL = 100pF, Ta = TIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS REFERENCE OUTPUT (REFOUTMAX531 only) Ta = +25 2.024 2.048 2.072 Reference Output Voltage Vpp = 5.0V MAX531BC 2.017 2.079 Vv MAX531BE 2.013 2.083 Temperature Coefficient TCREFOUT MAXSS1 AG/AB/AM/EM 30 80 ppm/*C MAX531 BG/BE 30 Resistance RREFOUT (Note 5) 0.5 2 Q Power-Supply Rejection Ratio PSRR 4.5V < Vpp <5.5V 300 pV Noise Voltage en 0.1Hz to 10kHz 400 LVp-p Capacitor External Cumin 3.3 uF DIGITAL INPUTS (DIN, SCLK, CS, CLR) Input High VIH 2.4 Vv Input Low VIL 0.8 Vv Input Current lIN VIN = OV or Vpp +1 pA Input Capacitance CIN a pF DIGITAL OUTPUT (DOUT) Output High Vou ISOURCE = 2mA Vpp- 1 V Output Low VoL ISINK = 2mA 0.4 Vv DYNAMIC PERFORMANCE Voltage-Output Slew Rate SR Ta = +25C 0.15 0.25 Vius Voltage-Output Settling Time To 1/2L8B, VOUT = 2V 25 Ls Digital Feedthrough CS = Vpp, DIN = 100kHz 5 nv-s Signal-to-Noise plus Distortion SINAD Ae (G= +1 or +2}, 68 dB POWER SUPPLY Positive Supply Voltage Vbb 45 5.5 V ; = MAX531 260 400 Power-Supply Current Ip outp eek MAX538, MAX539 140300] SWITCHING CHARACTERISTICS CS Setup Time tcss 20 ns SCLK Fall to CS Fall Hold Time toSHo 15 ns SCLK Fall to CS Rise Hold Time tCSH1 0 ns SCLK High Width tcH 35 ns SCLK Low Width teL 35 ns DIN Setup Time tos 45 ns DIN Hold Time tDH 0 ns DOUT Valid Propagation Delay tbo CL = 50pF 80 ns CS High Pulse Width tosw 20 ns CLR Pulse Width tcLR 25 ns CS Rise to SCLK Rise Setup Time tcs1 50 ns MA AXIAA 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs ELECTRICAL CHARACTERISTICSDual Supplies (MAX531 Only) (Vpp = +5V +10%, Ves = -5V +10%, AGND = DGND = OV, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, Crerout = 33HF, RL = 10kQ, CL = 100pF, Ta = TaIN to TMAx, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS Resolution N 12 Bits . Tested at Vpp = 5V, MAX531AC/E +0.5 Relative Accuracy INL Veg = -5V MAX531BC/E 4 LSB Differential Nonlinearity DNL Guaranteed monotonic +1 LSB Bipolar Offset Error Vos BIPOFF = REFIN, MAX531_C/E +8 LSB Bipolar Offset Tempco TGVos | BIPOFF = REFIN 3 ppm/G Gain Error (Unipolar or Bipolar) GEU MAX531_C/E +1 LSB Gain-Error Tempco 1 ppm Now 3) Rejection Ratio | perR | 4.5V<Vpp<5.5V, -5.5V< Ves < ~4.5V 0.4 1 | LsBv REFERENCE INPUT (REFIN) Voltage Range Vss +2 Vop -2 Vv Input Resistance Gode dependent, minimum at code 555 hex 40 kQ Input Capacitance Gode dependent (Note 4) 16 50 pF AG Feedthrough REFIN = 1kHz, 2.0Vp-p -80 dB REFERENCE OUTPUT (REFOUTMAX531 only) Ta = +25 2.024 2.048 2.072 Reference Output Voltage Vpp = 5.0V MAX531BC 2.017 2.079 V MAX531BE 2.013 2.083 .. MAX531AC/AE/AM/BM 30 50 Temperature Coefficient TCREFOUT MAX531BG/BE 30 ppm/G Resistance RREFouT | (Note 5) 0.5 2 Q Power-Supply Rejection Ratio PSRR | 4.5V<Vpp<5.5V 300 V/V Noise Voltage en 0.1Hz to 10kHz 400 uVp-p Capacitor External Cumin 33 uF DIGITAL INPUTS (DIN, SCLK, Cs) Input High VIH 24 V Input Low VIL 0.8 V Input Current lin VIN = OV or VoD +1 pA Input Capacitance CIN 8 pF DIGITAL OUTPUT (DOUT) Output High Vou ISOURCE = 2mA Vop - 1 V Output Low VoL IsSINK = 2mA 0.4 V 4 PAAXIAN+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs ELECTRICAL CHARACTERISTICSDual Supplies (MAX531 Only) (continued) (Vpp = +5V +10%, Veg = -5V +10%, AGND = DGND = OV, REFIN = 2.048V (external), RFB = BIPOFF = VOUT, CRerout = 33HF, RL = 10kQ, CL= 100pF, Ta = TIN to Tmax, unless otherwise noted.) PARAMETER | SYMBOL | CONDITIONS | MIN TYP MAX | UNITS VOLTAGE OUTPUT (VOUT) Output Voltage Range MAXSS1 (G = +1) Vas + 2 Yop -2 Vv MAX531 (G = +2) Ves + 0.4 Vpp - 0.4 Output Load Regulation VOUT = 2V, RL = 2kQ 1 LSB Short-Circuit Current Isc 12 mA DYNAMIC PERFORMANCE Voltage-Cutput Slew Rate SR 0.15 0.25 Vis Voltage-Output Settling Time To +1/2LSB, VOUT = 2V 25 us Digital Feedthrough Step 000 hex to FFF hex 5 nv-s . . . . REFIN = 1kHz, 2Vp-p, (G = +1) 68 Signal-to-Noise plus Distortion SINAD dB REFIN = 1kHz, 2Vp-p, (G = +2) 68 POWER SUPPLY Positive Supply Voltage Vpp 45 5.5 Vv Negative Supply Voltage Vss -5.5 0 Vv Positive Supply Current IDD All inputs = OV or Vpp, no load 260 400 HA Negative Supply Current Iss All inputs = OV or Vpp, no load -120 -200 LA SWITCHING CHARACTERISTICS CS Setup Time toss 20 ns SCLK Fall to CS Fall Hold Time tcsHo 15 ns SCLK Fall to CS Rise Hold Time tCSH1 0 ns SCLK High Width tcH 35 ns SCLK Low Width teL 35 ns DIN Setup Time tos 45 ns DIN Hold Time {DH 0 ns DOUT Valid Propagation Delay tbo CL = 50pF 80 ns CS High Pulse Width tcsw 20 ns CLR Pulse Width tcLR 25 ns CS Rise to SCLK Rise Setup Time test 50 ns Note 2: Insingle-supply operation, INL and GE calculated from code 11 to code 4095. Tested at Vpp = +5V. Note 3: This specification applies to both gain-error power-supply rejection ratio and offset-error power-supply rejection ratio. Note 4: Guaranteed by design. Note 5: Tested at louT= 100yA. The reference can typically source up to 5mA (see Typical Operating Characteristics). MAAXLAA 5 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs (VoD = +5V, VREFIN = 2.048V, Ta = +25, INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (FIRST 12 CODES) DUAL SUPPLIES Q SINGLE SUPPLY INTEGRAL NONLINEARITY (LSB) a on a 0 2 4 6 8 10 DIGITAL INPUT CODE (DECIMAL} OUTPUT SCURCE CAPABILITY vs. QUTPUT PULL-UP VOLTAGE OUTPUT SQUAGE CAPABILITY (mA} - Voo-4 Vpp-3 -Vpp-2 OUTPUT PULL-UP VOLTAGE (V} SUPPLY CURRENT vs. TEMPERATURE Vpp-6 Voo-1 > c z MAXS31 = 240 a = 220 3 2 200 a & 180 a wo 160 MAX538/MAX539 140 120 0 -40 -20 0 20 40 60 80 TEM PERATURE (C) 6 MAXEI1-1 12 MAYES + Vpp-9 MARES1-7 100 unless otherwise noted.) INTEGRAL NONLINEARITY vs. DIGITAL INPUT CODE (ALL CODES) 0.25 a wv a z oc ia Zz a = o a <= c fa Ee 2 0.25 O S12 1024 1536 2048 2560 3072 3584 4095 DIGITAL INPUT CODE (DECIMAL) ANALOG FEEDTHROUGH vs. FREQUENCY -110 2 -100 CODE = 000 hex i @ -30 = -80 g a 70 oc f= -60 ff -0 8 40 a -30 a = 120 10 0 1 10 100 ik 10k 100k 1M FREQUENCY (Hz) MAX531 GAIN (dB) GAIN vs. FREQUENCY REFIN = 4p-p MAKE -8 1 100 ik FREQUENCY (Hz) 10k 100k REFERENCE VOLTAGE (V} OUTPUT SINK CAPABILITY (m A) SIGNAL-TO-NOISE RATIO (dB) Typical Operating Characteristics QUTPUT SINK CAPABILITY vs. QUTPUT PULL-DOWN VOLTAGE 16 2 g 14 2 12 10 8 5 4 z 0 0 O02 o4 06 o8 1.0 OUTPUT PULL-DOWN VOLTAGE (V) MAXS531 REFERENCE VOLTAGE vs. TEM PERATURE 2.055 g 2.050 L Le Lae | 2.045 s0 -40 -20 0 #20 40 60 80 100 TEM PERATURE (C} MAX531 AMPLIFIER SIGNAL-TO-NOISE RATIO 80 2 RERIN = 4Vp-p g 70 = 80 50 40 30 20 10 0 100 tk FREQUENCY (Hz) 10k 100k MAAXIMA+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs Typical Operating Characteristics (continued) (VoD = +5V, VREFIN = 2.048V, Ta = +25 C, unless otherwise noted.) MAX531 MAX531 REFERENCE OUTPUT VOLTAGE GAIN AND PHASE vs. FREQUENCY vs. REFERENCE LOAD CURRENT 20 80 2.0520 2 FFB CONNECTED TO AGND (G=2)|] 4 N 3 RFB CONNECTED TO VOUT ( NX 3 ria 2.0515 - 10 GAIN > N\ =e 5 2.0810 N = g 2 \ a 9 > 5 NY > = Oo, M, z 0& tu 2.0505 B 49 2 Gi N\ a ih 2.0500 mS rd NJ 20 t 2.0495 J -80 180 2.0490 1 10 100 B00 0 08 1015 202530 35 4045 50 FREQUENCY (kHz) REFERENCE LOAD CURRENT (ma) DIGITAL FEEDTHROUGH 2usidiv CS = HIGH A: DIN = 4Vp-p, 100KHz B: VOUT, 10m Vidiv POSITIVE SETTLING TIME (MAX&3 1) Lanta ret Naya attatat y i A tA i 4 B i | 3 i sic ree menses a oes a nates teat Voo = +5, Vacrn = 2V, BIPOLAR CONFIGURATION Voo=+5, VaerIN = 2V, BIPOLAR CONFIGURATION A: GS RISING EDGE, SV/div A: CS RISING EDGE, 5Waiv B: VOUT, NO LOAD, 1Wadiv B: VOUT, NO LOAD, 1Wolv MA AXIAA 7 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output Serial 12-Bit DACs Pin Description Detailed Description PIN General DAC Discussion NAME FUNCTION The MAX53 1/MAX538/MAX539 use an inverted R-2R MAX538 ladder network with a single-supply CMOS op amp to con- MAX531 | waxsag vert 12-bit digital data to analog voltage levels (see ; ; Functional Diagram). The term inverted describes the { _ BIPOFF | Bipolar Offset/Gain ladder network because the REFIN pin in current-output Resistor DACs is the summing junction, or virtual ground, of an op 2 1 DIN Serial Data Input amp. However, such use would result in the output voltage being the inverse of the reference voltage. The 3 _ CIR Glear. Asynchronously sets MAX831/MAX538/MAX539s topology makes the output DAG register to 000 hex. the same polarity as the reference input. 4 2 SCLK Serial Clock Input An internal reset circuit forces the DAC register to reset to 000 hex on power-up. Additionally, a clear CLR pin, when 5 3 CS Chip Select, active low held low, sets the DAC register to 000 hex. CLR operates 5 4 pour | Serial Data Output for coon and independently from the chip-select daisy-chaining ( pin. 7 _ DGND | Digital Ground Buffer Amplifier The output buffer is a unity-gain stable, rail-to-rail output, 8 5 AGND | Analog Ground BiCMOS op amp. Input offset voltage and CMRR are ) 6 REFIN | Reference Input trimmed to achieve better than 12-bit performance. Settling time is 25us to 0.01% of final value. The settling 10 _ REFoUT | Reference Output, time is considerably longer when the DAC code is initially 2.048V set to 000 hex, because at this code the op amp is com- 1 _ V Negative Power Suool pletely debiased. Start from code 001 hex if necessary. Ss 9 PPV The output is short-circuit protected and can drive a 2kQ 12 7 VOUT | DAG Output load with more than 100pF load capacitance. 13 8 Vpb Positive Power Supply 14 _ RFB Feedback Resistor cs Nn fF NL cso me a wi s tesw | et rat toss tH at eric. test tom _ ! sax XXXXX ; \ i \ i \ / \ / Lt XX aH i tes tbs _ I ei 1Do Ma 1 DOUT a f Figure 1. Timing Diagram MAAXIAA+5V, Low-Power, Voltage-Output, REFOUT. | Rs + TOTAL REFERENCE NOISE IH lH CREFOUT w o o TTT SINGLE-POL m +a Oo = _ i s) 4 i] on o ol oe qe oz Ee a n wo to = N N ph iN} o o 5b iy So o Me, '% =" d - 0.6 Lt Le ot | ot 0.4 Li iii = ATUF LA o 0.1 1 10 100 1000 FREQUENCY (KHz) REFERENCE NOISE (uVams) 3 ee, REFERENCE NOISE (m Vp-p) on o Figure 2. Reference Noise vs. Frequency Internal Reference (MAX531 only) The on-chip reference is lesser trimmed to generate 2.048V at REFOUT. The output stage can source and sink current, so REFOUT can settle to the correct voltage quickly in response to code-dependent loading changes. Typically, source current is 5mA and sink current is 100A. REFOUT connects the internal reference to the R-2R DAC ladder at REFIN. The R-2R ladder draws 50WA maximum load current. If any other connection is made to REFOUT, ensure that the total load current is less than 100UA to avoid gain errors. For applications requiring very low-noise performance, connect a 383uUF capacitor from REFOUT to AGND. If noise is not a concern, a lower value capacitor (3 8yF min} may be used. To reduce noise further, insert a buffered RC filter between REFOUT and REFIN (Figure 2). The reference bypass capacitor, CREFOLT, is still required for reference stability. In applications not requiring the reference, con- nect REFOUT to Vpp or use the MAX538 or MAX539 (no internal reference). External Reference An external reference in the range (Vsg + 2V) to (Vpp - 2V) may be used with the MAX531 in dual-supply operation. With the MAXS38/MAX539 or the MAX531 in single-supply use, the reference must be positive and may not exceed Vpp - 2V. The reference voltage determines the DAC's full- scale output. The DAC input resistance is code dependent and is minimum (40k) at code 555 hex and virtually infi- MA AXIAA Serial 12-Bit DACs nite at code 000 hex. REFINs input capacitance is also code dependent and has a 50pF maximum value at sever- al codes. Because of the code-dependent nature of refer ence input impedances, a high-quality, low-cutput-imped- ance amplifier (such as the MAX480 low-power, precision op amp) should be used. If an upgrade to the internal reference is required, the 2.5V MAX873A is suitable: +15mV initial accuracy, TCVOUT = 7ppm/* (max). Logic Interface The MAX531 /MAX538/MAX5339 logic inputs are designed to be compatible with TTL or CMOS logic levels. However, to achieve the lowest power dissipation, drive the digital inputs with rail-to-rail CMOS logic. With TTL logic levels, the power requirement increases by a factor of approximately 2. Serial Clock and Update Rate Figure 1 shows the MAXS31/MAX538/MAX539 timing. The maximum serial clock rate is given by 1 / (tcH + tcL), approximately 14MHz. The digital update rate is limited by the chip-select period, which is 16 x (tCH + tCL) + tcsw. This equals a 1.14ps, or 877kHz, update rate. However, the DAS settling time to 12 bits is 25us, which may limit the update rate to 40kHz for full-scale step transitions. Applications Information Refer to Figures 3a and 3b for typical operating connec- tions. Serial interface The MAX531/MAX538/MAX539 use a three-wire serial interface that is compatible with SPI, QSPI (GPOL = CPHA = 0}, and Microwire standards as shown in Figures 4 and 5. The DAC is programmed by writing two 8-bit words (see Figure 1 and the Functional Diagram). Sixteen bits of serial data are clocked into the DAC MSB first with the MSB preceded by four fill (dummy) bits. The four dummy bits are not normally needed. They are required only when DACs are daisy-chained. Data is clocked in on SCLKs rising edge while CS is low. The seri- al input data is held in a 16-bit serial shift register. On CSs rising edge, the 12 least significant bits are transferred to the DAC register and update the DAC. With CS high, data cannot be clocked into the MAXS31 /MAXS38/MAX539 . The MAX531 /MAX538/MAX539 input data in 16-bit blocks. The SPI and Microwire interfaces output data in 8-bit blocks, thereby requiring two write cycles to input data to the DAG. The QSPI interface allows variable data input from eight to 16 bits, and can be loaded inte the DAC in one write cycle. SPi and QSPI are trademarks of Motorola, Inc. Microwire is a trademark of National Semiconductor Corp. 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs DIN DOUT SCLK CS CIR PEIN your INVERTED Fe2R DAC . ar oR aocay| AALAXLAA on V8 Tr MAX531 . L BIPOFE] CONNECT BIPOFF at = TO VOUT FOR G= 1, TL AGND DGND Von. Vgg TO AGND FOR G=2, = | o1uF OR TO REFIN FoR SUF o jours | +5V BIPOLAR GAIN +_ pe ov TO-5V DIN SCLK CS DOUT REAIN INVERTED OUT R-2R DAG MAXIM MAX538 aR MAX539 AGND Yop }_+_ +5 Lt O.1LF Figure 3a. MAX531 Typical Operating Circuit Daisy-Chaining Devices The serial output, DOUT, allows cascading of two or more DACs. The data at DIN appears at DOUT, delayed by 16 clock cycles plus one clock width. For low power, DOUT is a GMCS output that does not require an external pull-up resistor. DOUT does not go into a high-impedance state when CS is high. DOUT changes on SCLKs falling edge when CS is low. When CS is high, DOUT remains in the state of the last data bit. Any number of MAX531/MAX538/MAX539 DACs can be daisy-chained by connecting the DOUT of one device to the DIN of the next device in the chain. For proper timing, ensure that tcL (CS low to SCLK high) is greater than tpo + tbs. Unipolar Configuration The MAX531 is configured for a gain of +1 (OV to VREFIN unipolar output) by connecting BIPOFF and RFB to VOUT (Figure 6). The converter operates from either sin- gle or dual supplies in this configuration. See Table 1 for the DAC-latch contents (input) vs. the analog VOUT (output). In this range, 1LSB = VREFIN (2-12). The MAX538 is internally configured for unipolar gain = +1 operation. Again of +2 (OV to 2VREFIN Unipolar output) is set up by connecting BIPOFF to AGND and RFB to VOUT (Figure 7). Table 2 shows the DAC-latch contents vs. VOUT. The MAX531 operates from either single or dual 10 Figure 3b. MAX538/MAX539 Typical Operating Circuit supplies in this mode. In this range, 1LSB = (2)(VREFIN) (2-12) = (VREFIN}(211). The MAX539 is internally config- ured for unipolar gain = +2 operation. Bipolar Configuration A bipolar range is set up by connecting BIPOFF to REFIN and RFB to VOUT, and operating from dual (+5V) supplies (Figure 8). Table 3 shows the DAC-latch contents (input) vs. VOUT (output). In this range, {LSB = VREFIN (211). Four-Quadrant Multiplication The MAX531 can be used as a four-quadrant multiplier by connecting BIPOFF to REFIN and RFB to VOUT, using (1) an offset binary digital code, (2) bipolar power supplies, using dual power supplies, and (3) a bipolar analog input at REFIN within the range Vss + 2V to VoD - 2V, as shown in Figure 9. In general, a 12-bit DACs output is (D) (VREFIN} (G), where G is the gain (+1 or +2) and D is the binary representation of the digital input divided by 2! or 4096. This formula is precise for unipolar operation. However, for bipolar, offset binary operation, the MSB is really a polarity bit. No resolution is lost, as there are the same number of steps. The output voltage, howev- er, has been shifted from a range of, for example, OV to 4.096V (G = +2) to a range of -2.048V to +2.048V. Keep in mind that when using the DAC as a four-quad- rant multiplier, the scale is skewed. Negative full scale is -VREAN, while positive full scale is +VREFIN - 1LSB. MAAXIAA+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs SCLK SK MA AXILSVI MAXS3t DIN [be 50 MIGROWIRE MAX538 PORT MAXS39 | o DOUT sl THEDOUT-S] CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER . AAAXLAA MAX538 MAXS31 DIN MAX539 GS DOUT SCLK [At SCK * mos, SPI PORT vo * MISO CPOL =0, CPHA=0 THE DOUT- MISO CONNECTION IS NOT REQUIRED FOR WRITING TO THE DEVICE, BUT MAY BE USED FOR VERIFYING DATA TRANSFER . Figure 4. Microwire Connection Figure 5. SPVQSPI Connection B aie +5V AF REFN AGND Vop REFOUT MA AXL/VI MAX531 DGND Vss BIPOFF VOUT] Vout OV TO -5Y +5 a 33u Vop REAN REFQUT SVLAXLAA pipope ~ MAX531 AFB AGND DGND VOUT Vout G=+2 Ves OV TO -5V Figure 6. Unipolar Cenfiquration (OV to +2.048V Output) Table 1. Unipolar Binary Code Table (OV to VREFIN Output), Gain = +1 INPUT OUTPUT 14104411411 (VresIN) see 1000 0000 0001 (Veer) Soe 1000 0000 0000 (Veer) poe +WREAN/ 2 od tt 1414 (Veer) So 0000 =0000 = n001 (VPEFIN) am 0000 0000 000 Ov MA AXIAA Figure 7. Unipolar Configuration (OV to +4.096V Ouiput) Table 2. Unipolar Binary Code Table (OV to 2VREFIN Output), Gain = +2 INPUT OUTPUT 4095 410 44441411 +2 (VPEFIN) dogg 2049 4000 0000 9001 +2 (VREFIN) 3595 2048 1000 0000 000 +2 (VREFIN) 4ogg = *VREFIN 01444444414 +2 (VaeRIN) See 0000 0000 9001 +2 (VREAN) ips 0000 0000) 000 ov 11 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs Table 3. Bipolar (Offset Binary) Code Table (-VREFIN to +VREFIN Output) +5V | PEFIN BIPOFF| [To REFOUT MAAXLAA SH MANG3I FFB - AGND 1 DGND Vout -5 Figure 8. Bipolar Configuration (-2.048V to +2.048V Output) Single-Supply Linearity As with any amplifier, the MAX531/MAX538/MAX539's output buffer can be positive or negative. When the off- set is positive, it is easily accounted for (Figure 10). However, when the offset is negative, the buffer output cannot follow linearly when there is no negative supply. In that case, the amplifier output (VOUT) remains at ground until the DAC voltage is sufficient to overcome the offset and the output becomes positive. Normally, linearity is measured after accounting for zero error and gain error. Since, in single-supply opera- tion, the actual value of a negative offset is unknown, it cannot be accounted for during test. Additionally, the output buffer amplifier exhibits a nonlinearity near-zero output when operating with a single supply. To account for this nonlinearity in the MAX531/MAX538/MAX5339, linearity and gain error are measured from code 11 to code 4095. The output buffers offset and nonlinear behavior do not affect monotonicity, and these DACs are guaranteed monotonic starting with code zero. In dual-supply operation, linearity and gain error are mea- sured from code 0 to 4095. Power-Supply Bypassing and Ground Management Best system performance is obtained with printed cir- cuit boards that use separate analog and digital ground planes. Wire-wrap boards are not recommend- ed. The two ground planes should be connected together at the low-impedance power-supply source. 12 INPUT OUTPUT W144 4414 (-Vrern) Se 1000 0000 = 0001 (+VREFIN) wa 1000 9000 0000 ov Of 141101111 (VRE) sous 0000 0000 0001 (-VRERN) a 0000 cn00 0000 (-VRERIN) a = -VRERN DGND and AGND should be connected together at the chip. For the MAX531 in single-supply applications, connect Vss to AGND at the chip. The best ground connection may be achieved by connecting the DACs DGND and AGND pins together and connecting that point to the system analog ground plane. If the DACs DGND is connected to the system digital ground, digi- tal noise may get through to the DACs analog portion. Bypass VDD (and Vss in dual-supply mode} with a 0.1uF ceramic capacitor, connected between Vpp and AGND (and between Vss and AGND). Mount with short leads close to the device. Ferrite beads may also be used to further isolate the analog and digital power supplies. Figures 11a and 11b illustrate the grounding and bypassing scheme described. Saving Power When the DAC is not being used by the system, mini- mize power consumption by setting the appropriate code to minimize load current. For example, in bipolar mode, with a resistive load to ground, set the DAC code to mid-scale (Table 3). If there is no output load, minimize internal loading on the reference by setting the DAC to all Os (on the MAX531, use CLR). Under this condition, REFIN is high impedance and the op amp operates at its minimum quiescent current. Due to these low current levels, the output settling time for an input code close to 0 typically increases to 60us (no more than 100Qus). MAAXIAA+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs | | PEFOUT Vpp) sss CS |CLRIDIN |DOUT 2048V SIGNAL [REIN 7% = IN PQ your INVERTED Pe2R DAC _ 2R REB maxian | On y MAX531 AA A___BIPOFF * f POSITIVEOFFSET e OUTPUT (LSB) o- NM oO 123 4567 8 DAC CODE (LSB) Figure 9. MAX531 Connected as Four-Quadrant Multiplier. The unused REFOUT is connected to Vop. AC Considerations Digital Feedthrough High-speed serial data at any of the digital input or output pins may couple through the DAG package and cause internal stray capacitance to appear at the DAC output as noise, even though CS is held high (see Typical Operating Characteristics). This digital feedthrough is tested by hold- ing CS high, transmitting 555 hex from DIN to DOUT. Analog Feedihrough Because of internal stray capacitance, higher frequency analog input signals may couple to the output as shown in the Analog Feedthrough vs. Frequency graph in the Typical Operating Characteristics. |t is tested by holding CS high, setting the DAC code to all Os, and sweeping REFIN. MA AXIAA Figure 10. Single-Suppiy Offset ANALOG-GROUND PLANE Janae FTE EEE O.1uF (2) MAXS31 BYPASSING Le LI a [| rl ft H a] | t a OF (b) MAXS38/MAX539 BYPASSING Figure 17. Power-Supply Bypassing 13 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs __Ordering Information (continued) Pin Configurations (continued) PART TEMP. RANGE PIN-PACKAGE rise) MAXS31AEPD -40Cto+85C 14Plastic DIP -+1/2 MAX531BEPD -40C to +85C 14 Plastic DIP 1 MAXS531AESD -40C t0+85% 8691480 1/2 MAX5S31BESD -40C to +85C) = 14 80 1 MAX538AGPA OCto+70% = Plastic DIP 1/2 MAXS38BCPA O to+70C = 8 Plastic DIP 1 MAX5S38ACSA =O to +70 = 8 SO 1/2 MAX538BCSA = Ot0+70T &30 1 MAX538BC/D oCtie+70S = Dice 1 MAX538AEPA -40C to+85%C ~ & Plastic DIP 1/2 MAXS38BEPA -40C to+85C = 8 Plastic DIP 1 MAX538AESA -40C to+85% 8 &30 MAX538BESA -40C to+85% 880 =~ TOP VIEW VW BIPOFF [1 | 14] FFB DN [2 | AAAXIAA [73] vp GR [a MAX531 re our souk [Fy it] vs 3s a] aour pout [a [9 | RERN DGND [7 Al AGND DIP/SO MAX539ACPA O to+70C = 8 Plastic DIP 1/2 MAX539BCPA O to+70% = 8 Plastic DIP 1 MAX539ACSA =O to +70 = 8 SO 1/2 MAX539BCSA OC to+70T &80 1 MAX539BC/D OC tie +70S ~ Dice 1 MAXS539AEPA -40C to+85C = 8 Plastic DIP 1/2 MAXS539BEPA -40C to+85C = & Plastic DIP 1 =~, ho MAXS539AESA -40C to+85% 8880 It} He] ee Ee] | ee] ~~ ho MAX539BESA -40C to+85% 880 "Dice are specified at TA = +25'T only. 14 Chip Topography DIN (BIPOFF){RFB) Vpp DOUT ; EL Be (DGND} AGND 0,080" (2.032mm)} () ARE FOR MAX531 ONLY. TRANSISTOR COUNT: 922 SUBSTRATE CONNECTED TO Vop MAAXIAA+5V, Low-Power, Voltage-Output, Serial 12-Bit DACs Package Information PDIFY EPS E rr f caf | | qt a. TED AM CAI, OP SMAIVALE CA SUBS PAY dm) TH TG PROPRIETARY INFORMATION 4 INC HE = MILLIME TEP: IMLHES MILLIMETER. MIM | MA | MIM | MA MIM [| MA | MIM | MAS | [M800 A | -- [neon | --- [soe] [pb ins4s(nscn | ses] aor [es [ag Al LOLS [--- --- I lee? [Lo 2 [14 Ar Ac[h les [W175 445 U late [lads fle |AA AS WOSS [LOO es I ee de} es24 {le [A BUM Mee |) O56 I 2S, 7o[cn, 54) 20 | AE Bl OO45 [hoes fil 165 DU 26,95] se.13 | cd Ar CWO te Peo fo a0 I 34.54) 35,05 | ost TH OS LOWS LES PE. OS E [i s0n [tls =e [Ect 1 Wee LO NOT INCLUDE MOLD FLASH El eso sl fed [Ae 2, MOLD FLASH OF PPOTPUSIONS MOT v7yan | -_ l2s4)__ TO ExCEED JSmm :006" = LUI cot 3, CONTROLLING DIMENTIOM, MILLIMETER AL SON | -7 P7be | W-= 4, MEETS JETEC MOGUI#% AT SHOWE -E! - In4on | - finds IN ABOVE TABLE Lois [oiso [232 [3.1 6M HIMBEP OF PINS MA AXIAMA | Paci ce FAMILY QUTLINE: PLIP 200" | 1; [2l-t043 4 DOCUPEWT CONTPOL_HUNBER FEV. MA AXIAA 15 6BESGXVW/BESXVIAN/LESXVWNMAX531/MAX538/MAX539 +5V, Low-Power, Voltage-Output, Serial 12-Bit DACs Package Information (continued) "SOEN EPS Te | EH irr Poe) pel fPooL. = |. f IMC HES MILLIMETERS IMECHE | MILLIMETEP*. MIbd MA | MIM | MAS MAS MA |i [MSole A O05 3 [OMe So L759 D Wa Oo? SO) S00 fe | A Al aud | o.oo eo U MAU as4] B55) 6.75 [14] B Blade [ool So] o43 U 286} OU ao4 SO} LOU} te po FE] oo07 [ool 25 & US NOTES: E/oiso0 [0.157 oy] 2.00 L Dee DO NOT INCLUDE MOLD FLAzH aan = 2. MOLD FLASH OP PROTRUSIONS MOT A | eee] Oct ecu TO EstEED Simm '.006"! hf Gale | oeeo 7,50 3 LEAD: 10 BE COPLANAR WITHIN Sf = AN2rarm 1 Abe Lj OOS | oO Lev 4. CONTPOLLING DIMENSION MILLIMETER 5, MEET. JEDEC Mlule-s* Al CHOWN IM ABOVE TAELE & Mo= HUMBERP OF PIMC MAAXIMA |pece nce FAMILY OUTLINE: SOIC 150 [iy fe {2 4 GAURIEL (GURWYOWLE Ch ABR FAG 198) TE 7K PROPFIETAR | INFOPHA TOON. -UUA4L A JOCUREHT CONTPOL_HUNEER FE Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 @ 1997 Maxim Integrated Products Printed USA MAXIMA js 4 registered trademark of Maxim Integrated Products.