IRFZ14S/L
HEXFET® Power MOSFET
PD - 9.890A
lAdvanced Process Technology
lSurface Mount (IRFZ14S)
lLow-profile through-hole (IRFZ14L)
l175°C Operating Temperature
lFast Switching
Parameter Typ. Max. Units
RθJC Junction-to-Case –– 3.5
RθJA Junction-to-Ambient ( PCB Mounted,steady-state)** 4 0
Thermal Resistance
°C/W
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 10
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V7.2 A
IDM Pulsed Drain Current  40
PD @TA = 25°C Power Dissipation 3.7 W
PD @TC = 25°C Power Dissipation 43 W
Linear Derating Factor 0.29 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy 47 mJ
dv/dt Peak Diode Recovery dv/dt  4.5 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Absolute Maximum Ratings
VDSS = 60V
RDS(on) = 0.20
ID = 10A
2
D P a k
TO-262
S
D
G
8/25/97
Description
Third Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This
benefit, combined with the fast switching speed and
ruggedized device design that HEXFET Power MOSFETs
are well known for, provides the designer with an extremely
efficient and reliable device for use in a wide variety of
applications.
The D2Pak is a surface mount power package capable of
accommodating die sizes up to HEX-4. It provides the
highest power capability and the lowest possible on-
resistance in any existing surface mount package. The
D2Pak is suitable for high current applications because of
its low internal connection resistance and can dissipate
up to 2.0W in a typical surface mount application.
The through-hole version (IRFZ14L) is available for low-
profile applications.
°C
IRFZ14S/L
VDD = 25V, starting TJ = 25°C, L = 548µH
RG = 25, IAS = 10A. (See Figure 12)
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
Notes:
** When mounted on 1" square PCB (FR-4 or G-10 Material ).
For recommended footprint and soldering techniques refer to application note #AN-994.
ISD 10A, di/dt 90A/µs, VDD V(BR)DSS,
TJ 175°C
Pulse width 300µs; duty cycle 2%.
Uses IRFZ14 data and test conditions
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode)
––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– ––– 1.6 V TJ = 25°C, IS = 10A, VGS = 0V
trr Reverse Recovery Time ––– 70 140 ns TJ = 25°C, IF = 10A
Qrr Reverse Recovery Charge ––– 200 400 nC di/dt = 100A/µs 
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
A
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 –– V V GS = 0V, ID = 250µA
V(BR)DSS/TJBreakdown Voltage Temp. Coefficient ––– 0.063 ––– V/°C Reference to 25°C, ID =1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.20 VGS =10V, ID = 6.0A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 2.4 ––– ––– S VDS = 25V, ID = 6.0A
––– ––– 25 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 48V, VGS = 0V, T J = 150°C
Gate-to-Source Forward Leakage ––– ––– 10 0 V GS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge –– –– 11 I D = 10A
Qgs Gate-to-Source Charge –– –– 3.1 nC V DS = 48V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 5.8 VGS = 10V, See Fig. 6 and 13 
td(on) Turn-On Delay Time ––– 10 ––– V DD = 30V
trRise Time ––– 50 ––– I D = 10A
td(off) Turn-Off Delay Time ––– 13 ––– RG = 24
tfFall Time ––– 19 ––– RD = 2.7Ω, See Fig. 10
Between lead,
––– ––– and center of die contact
Ciss Input Capacitance ––– 300 ––– VGS = 0V
Coss Output Capacitance ––– 160 ––– pF VDS = 25V
Crss Reverse Transfer Capacitance ––– 29 ––– ƒ = 1.0MHz, See Fig. 5
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
IGSS
ns
IDSS Drain-to-Source Leakage Current
nH
7.5
LSInternal Source Inductance
10
40
S
D
G
IRFZ14S/L
TJTJ
Fig 2. Typical Output Characteristics
Fig 1. Typical Output Characteristics
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 3. Typical Transfer Characteristics
IRFZ14S/L
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
IRFZ14S/L
Fig 9. Maximum Drain Current Vs.
Case Temperature
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
+
-
VDS
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
VDD
RGD.U.T.
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
Fig 10a. Switching Time Test Circuit
IRFZ14S/L
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01
R
G
+
-
t
p
V
DS
I
AS
V
DD
V
(BR)DSS
10 V
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50K
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
IRFZ14S/L
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
*
Fig 14. For N-Channel HEXFETS
IRFZ14S/L
D2Pak Package Outline
D2Pak
Part Marking Information
10.16 (.400)
REF.
6.47 (.255)
6.18 (.243)
2.61 (.103)
2.32 (.091)
8.89 (.350)
REF.
- B -
1.32 (.052)
1.22 (.048)
2.79 (.110)
2.29 (.090)
1.39 (.055)
1.14 (.045)
5.28 (.208)
4.78 (.188)
4.69 (.185)
4.20 (.165)
10.54 (.415)
10.29 (.405)
- A -
2
1 3 15.49 (.610)
14.73 (.580)
3X 0.93 (.037)
0.69 (.027)
5.08 (.200)
3X 1.40 (.055)
1.14 (.045)
1.78 (.070)
1.27 (.050)
1.40 (.055)
MAX.
NOTES:
1 DIMENSIONS AFTER SOLDER DIP.
2 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982.
3 CONTROLLING DIMENSION : INCH.
4 HEATSINK & L EAD DIMENSIONS DO NOT INCLUDE BURRS.
0.55 (.022)
0.46 (.018)
0.25 (.010) M B A M MINIMUM RECO MM ENDED FOOTP RINT
11.43 (.450)
8.89 (.350)
17.78 (.700)
3.81 (.150)
2.08 (.082)
2X
LE AD ASS IG NMEN TS
1 - GATE
2 - DRAIN
3 - SOU RC E
2.54 ( .100)
2X
PART NUM BER
INTERNATIONAL
REC TIFIER
L OGO DATE CODE
(YYWW)
YY = YEAR
WW = WEEK
AS SEMBLY
LOT CODE
F530S
9B 1M
9246
A
IRFZ14S/L
Package Outline
TO-262 Outline
TO-262
Part Marking Information
IRFZ14S/L
Tape & Reel Information
D2Pak
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
EUROPEAN HEADQUARTERS: Hurst Green, Oxted, Surrey RH8 9BB, UK Tel: ++ 44 1883 732020
IR CANADA: 7321 Victoria Park Ave., Suite 201, Markham, Ontario L3R 2Z8, Tel: (905) 475 1897
IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 6172 96590
IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 11 451 0111
IR FAR EAST: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo Japan 171 Tel: 81 3 3983 0086
IR SOUTHEAST ASIA: 315 Outram Road, #10-02 Tan Boon Liat Building, Singapore 0316 Tel: 65 221 8371
http://www.irf.com/ Data and specifications subject to change without notice. 8/97
3
4
4
TRR
FE ED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (.161)
3.90 (.153)
TRL
FEED DIRECTION
10.90 (.429)
10.70 (.421) 16.10 (.634)
15.90 (.626)
1. 75 (.069)
1. 25 (.049)
11.6 0 (.457)
11.4 0 (.449) 15.4 2 (.609)
15.2 2 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (.0145)
0.342 (.0135)
1.60 (.063)
1.50 (.059)
13.50 (. 532)
12.80 (. 504)
330.00
(14.173)
M A X.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
M IN.
30.40 (1.197)
M AX.
26.40 (1. 039)
24.40 (.961)
NO TES :
1. C O M F ORM S T O EIA -418.
2. CONTROLLING DIMENSIO N: MILLIME TER .
3. DIME NS ION M EAS URE D @ HUB .
4. INCLU DES FLAN GE DISTORTION @ OUTER ED GE.