SGL08G72B1BE2MT-CCRT - Swissbit

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 1

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

Figure: mechanical dimensions1

8GB DDR3 – SDRAM unbuffered ECC Mini-UDIMM

244 Pin ECC Mini-UDIMM

SGL08G72B1BE2MT-CCRT

8GB in FBGA Technology

RoHS compliant

Environmental Requirements:

 Operating temperature (ambient)

Standard Grade 0°C to 70°C

-40°C to 85°C

 Operating Humidity

10% to 90% relative humidity, noncondensing

 Operating Pressure

105 to 69 kPa (up to 10000 ft.)

 Storage Temperature

-55°C to 100°C

 Storage Humidity

5% to 95% relative humidity, noncondensing

 Storage Pressure

1682 PSI (up to 5000 ft.) at 50°C

Options:

 Data Rate / Latency Marking

DDR3 1333 MT/s CL9 -CC

DDR3 1066 MT/s CL7 -BB

 Module density

8GB with 18 dies and 2 ranks

 Standard Grade (TA) 0°C to 70°C

(TC) 0°C to 85°C

Features:

 244-pin 72-bit DDR3 ECC Mini-UDIMM module

 Module organization: dual rank 1024M x 72

 VDD = 1.5V ±0.075V, VDDQ 1.5V ±0.075V

 1.5V I/O ( SSTL_15 compatible)

 Fly-by-bus with termination for C/A & CLK bus

 On-board I2C temperature sensor with integrated serial

presence-detect (SPD) EEPROM

 Gold-contact pad

 This module is fully pin and functional compatible to the

JEDEC PC3-10600 DDR3 SDRAM Mini-UDIMM design spec.

and JEDEC- Standard MO-244 R/C B. (see www.jedec.org)

 The pcb and all components are manufactured according to

the RoHS compliance specification

[EU Directive 2002/95/EC Restriction of Hazardous

Substances (RoHS)]

DDR3 - SDRAM component Micron MT41K512M8RH-125:E

 512Mx8 DDR3 SDRAM in PG-TFBGA-78 package

 8-bit prefetch architecture

 Programmable CAS Latency, CAS Write Latency, Additive

Latency, Burst Length and Burst Type.

 On-Die-Termination (ODT) and Dynamic ODT for improved

signal integrity.

 Refresh, Self Refresh and Power Down Modes.

 ZQ Calibration for output driver and ODT.

 System Level Timing Calibration Support via Write Leveling

and Multi Purpose Register (MPR) Read Pattern.

1if no tolerances specified ± 0.15mm

82.00

20.00

30.00

10.00

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 2

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

This Swissbit module is an industry standard 244-pin DDR3 SDRAM ECC Mini-DIMM which is organized as x72

high speed CMOS memory arrays. The module uses internally configured octal-bank DDR3 SDRAM devices. The

module uses double data rate architecture to achieve high-speed operation. DDR3 SDRAM modules operate

from a differential clock (CK and CK#). READ and WRITE accesses to a DDR3 SDRAM module is burst-oriented;

accesses start at a selected location and continue for a programmed number of locations in a programmed

sequence. The burst length is either four or eight locations. An auto precharge function can be enabled to provide

a self-timed row precharge that is initiated at the end of a burst access. The DDR3 SDRAM devices have a

multibank architecture which allows a concurrent operation that is providing a high effective bandwidth. A self

refresh mode is provided and a power-saving “power-down” mode. All inputs and all full drive-strength outputs are

SSTL_15 compatible.

The DDR3 SDRAM module uses the serial presence detect (SPD) function implemented via serial EEPROM

using the standard I2C protocol. This nonvolatile storage device contains 256 bytes. The first 128 bytes are

utilized by the SO-UDIMM manufacturer (Swissbit) to identify the module type, the module’s organization and

several timing parameters. The second 128 bytes are available to the end user.

Module Configuration

Organization

DDR3 SDRAMs used

Row

Addr.

Device Bank

Select

Column

Addr.

Refresh

Module

Bank Select

1G x 72bit

18 x 512M x 8bit (4Gbit)

16

BA0, BA1, BA2

10

8k

S0#, S1#

Module Dimensions

in mm

82.00 (long) x 30.00 (high) x 5.30 [max] (thickness with heat spreader)

Timing Parameters

Part Number

Module Density

Transfer Rate

Memory clock/Data bit

rate

Latency

SGL08G72B1BE2MT-CCRT

8 GB

10.6 GB/s

1.5ns / 1333MT/s

9-9-9

Label Info

Part Number

JEDEC Module Label

SGL08G72B1BE2MT-CCRT

8GB 2Rx8 PC3-10600W-9-11-B0

Figure 1: Mechanical Dimensions

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 3

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

Pin Name

A0-9, A11 – A15

Address Inputs

A10/AP

Address Input / Autoprecharge Bit

BA0 – BA2

Bank Address Inputs

DQ0 – DQ63

Data Input / Output

CB0 – CB07

ECC check bits

DM0-DM8

Input Data Mask

DQS0 – DQS8

Data Strobe, positive line

DQS0# - DQS8#

Data Strobe, negative line (only used when differential data strobe mode is enabled)

RAS#

Row Address Strobe

CAS#

Column Address Strobe

WE#

Write Enable

CKE0 – CKE1

Clock Enable

S0#, S1#

Chip Select

CK0 – CK1

Clock Inputs, positive line

CK0# - CK1#

Clock Inputs, negative line

Event#

Temperature event: The EVENT# pin is asserted by the temperature sensor when critical

Reset#

Reset signal for DDR3 SDRAMs

VDD

Supply Voltage (1.5V± 0.075V)

VREFDQ

Reference voltage: DQ, DM (VDD/2)

VREFCA

Reference voltage: Control, command, and address (VDD/2)

VSS

Ground

VTT

Termination voltage: Used for control, command, and address (VDD/2).

VDDSPD

Serial EEPROM Positive Power Supply

SCL

Serial Clock for Presence Detect

SDA

Serial Data Out for Presence Detect

SA0 – SA1

Presence Detect Address Inputs

ODT0, ODT1

On-Die Termination

NC

No Connection

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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Pin Configuration

Frontside

Symbol

1

VTT

31

DQ24

61

VDD

92

DQ40

2

VREFDQ

32

DQ25

62

A2

93

DQ41

3

VSS

33

VSS

63

VDD

94

VSS

4

DQ0

34

DQS3#

64

CK1

95

DQS5#

5

DQ1

35

DQS3

65

CK1#

96

DQS5

6

VSS

36

VSS

66

VDD

97

VSS

7

DQS0#

37

DQ26

67

VREFCA

98

DQ42

8

DQS0

38

DQ27

68

VDD

99

DQ43

9

VSS

39

VSS

69

NC

100

VSS

10

DQ2

40

CB0

70

VDD

101

DQ48

11

DQ3

41

CB1

71

A10

102

DQ49

12

VSS

42

VSS

72

BA0

103

VSS

13

DQ8

43

DQS8#

73

VDD

104

DQS6#

14

DQ9

44

DQS8

74

WE#

105

DQS6

15

VSS

45

VSS

75

CAS#

106

VSS

16

DQS1#

46

CB2

76

VDD

107

DQ50

17

DQS1

47

CB3

77

NC

108

DQ51

18

VSS

48

VSS

78

NC

109

VSS

19

DQ10

49

NC

79

VDD

110

DQ56

20

DQ11

50

Reset#

80

NC

111

DQ57

21

VSS

51

CKE0

81

NC

112

VSS

22

DQ16

52

VDD

82

VSS

113

DQS7#

23

DQ17

53

BA2

83

DQ32

114

DQS7

24

VSS

54

NC

84

DQ33

115

VSS

25

DQS2#

55

VDD

85

VSS

116

DQ58

26

DQS2

56

A11

86

DQS4#

117

DQ59

27

VSS

57

A7

87

DQS4

118

VSS

28

DQ18

58

VDD

88

VSS

119

SA0

29

DQ19

59

A5

89

DQ34

120

SCL

30

VSS

60

A4

90

DQ35

121

SA2

91

VSS

122

VTT

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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Backside

Symbol

123

VTT

153

DQ29

183

A3

214

DQ45

124

VSS

154

VSS

184

A1

215

VSS

125

DQ4

155

DM3

185

VDD

216

DM5

126

DQ5

156

NC

186

CK0

217

NC

127

VSS

157

VSS

187

CK0#

218

VSS

128

DM0

158

DQ30

188

VDD

219

DQ46

129

NC

159

DQ31

189

VDD

220

DQ47

130

VSS

160

VSS

190

Event#

221

VSS

131

DQ6

161

CB4

191

A0

222

DQ52

132

DQ7

162

CB5

192

VDD

223

DQ53

133

VSS

163

VSS

193

BA1

224

VSS

134

DQ12

164

DM8

194

VDD

225

DM6

135

DQ13

165

NC

195

RAS#

226

NC

136

VSS

166

VSS

196

CS0#

227

VSS

137

DM1

167

CB6

197

VDD

228

DQ54

138

NC

168

CB7

198

ODT0

229

DQ55

139

VSS

169

VSS

199

A13

230

VSS

140

DQ14

170

NC

200

VDD

231

DQ60

141

DQ15

171

NC

201

NC

232

DQ61

142

VSS

172

NC

202

NC

233

VSS

143

DQ20

173

VDD

203

VSS

234

DM7

144

DQ21

174

A15

204

DQ36

235

NC

145

VSS

175

A14

205

DQ37

236

VSS

146

DM2

176

VDD

206

VSS

237

DQ62

147

NC

177

A12

207

DM4

238

DQ63

148

VSS

178

A9

208

NC

239

VSS

149

DQ22

179

VDD

209

VSS

240

VDDSPD

150

DQ23

180

A8

210

DQ38

241

SA1

151

VSS

181

A6

211

DQ39

242

SDA

152

DQ28

182

VDD

212

VSS

243

VSS

213

DQ44

244

VTT

(Sig): Signal in brackets may be routed to the socket connector, but is not used on the module

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 6

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

FUNCTIONAL BLOCK DIAGRAMM 8GB DDR3 SDRAM Mini-DIMM,

2 RANK AND 18 COMPONENTS

DQ0

DQ1

DQ2

DQ3

DQ5

DQ4

DQ6

DQ7

S0

DQS0

DM0

DQS1

DM1

DQ8

DQ9

DQ10

DQ11

DQ13

DQ12

DQ14

DQ15

DQS2

DM2

DQ16

DQ17

DQ18

DQ19

DQ21

DQ20

DQ22

DQ23

DQS3

DM3

DQ24

DQ25

DQ26

DQ27

DQ29

DQ28

DQ30

DQ31

DQ32

DQ33

DQ34

DQ35

DQ37

DQ36

DQ38

DQ39

DQS4

DM4

DQS5

DM5

DQ40

DQ41

DQ42

DQ43

DQ45

DQ44

DQ46

DQ47

DQS6

DM6

DQ48

DQ49

DQ50

DQ51

DQ53

DQ52

DQ54

DQ55

DQS7

DM7

DQ56

DQ57

DQ58

DQ59

DQ61

DQ60

DQ62

DQ63

VDDSPD SPD

VDD/VDDQ D0-D17

VREFDQ

VREFCA

D0-D17

VSS

CK0,CK1

Notes:

1. DQ-to-I/O wiring is shown as recommended but may

be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relationship must be

maintained as shown.

3. DQ, DM, DQS/DQS resistors: Refer to associated

topology diagram.

4. Refer to the appropriate clock wiring topology under

the DIMM wiring details section of the JEDED document.

5. For each DRAM, a unique ZQ resistor is connected to

GND. The ZQ resistor is 240O±1%.

6. Refer to associated figure for SPD details.

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D0

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D9

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D1

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D10

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D2

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D11

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D3

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D12

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D4

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D13

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D5

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D14

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D6

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D15

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D7

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D16

DQSCS

S1

CB0

CB1

CB2

CB3

CB5

CB4

CB6

CB7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D8

DQSCS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 5

I/O 4

I/O 6

I/O 7

DM DQS

ZQ

D17

DQSCS

BA0-BA2BA0-BA2: SDRAM D0-D17

A0-A15 A0-A15: SDRAM D0-D17

RAS RAS: SDRAM D0-D17

CAS CAS: SDRAM D0-D17

WE WE: SDRAM D0-D17

ODT0 ODT: SDRAM D0-D8

CKE1 CKE: SDRAM D9-D17

CK: SDRAM D0-D17

CK0,CK1CK: SDRAM D0-D17

RESET RESET: SDRAM D0-D17

CKE0 CKE: SDRAM D0-D8

ODT1 ODT: SDRAM D9-D17

DQS8

DM8

DQS8

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 7

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

MAXIMUM ELECTRICAL DC CHARACTERISTICS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Supply Voltage

VDD

-0.4

1.975

V

I/O Supply Voltage

VDDQ

-0.4

1.975

V

VDDL Supply Voltage

VDDL

-0.4

1.975

V

Voltage on any pin relative to VSS

VIN, VOUT

-0.4

1.975

V

INPUT LEAKAGE CURRENT

Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 0.95V

(All other pins not under test = 0V)

II

µA

Command/Address

RAS#, CAS#, WE#, S#, CKE

-16

16

CK, CK#

-16

16

DM

-2

2

OUTPUT LEAKAGE CURRENT

(DQ’s and ODT are disabled; 0V ≤ VOUT ≤ VDDQ)

IOZ

-5

5

µA

DQ, DQS, DQS#

VREF LEAKAGE CURRENT ; VREF is on a valid level

IVREF

-8

8

µA

DC OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

NOM

MAX

UNITS

Supply Voltage

VDD

1.425

1.5

1.575

V

I/O Supply Voltage

VDDQ

1.425

1.5

1.575

V

VDDL Supply Voltage

VDDL

1.425

1.5

1.575

V

I/O Reference Voltage

VREF

0.49 x VDDQ

0.50 x VDDQ

0.51x VDDQ

V

I/O Termination Voltage (system)

VTT

0.49 x VDDQ-20mV

0.50 x VDDQ

0.51x VDDQ+20mV

V

Input High (Logic 1) Voltage

VIH (DC)

VREF + 0.1

VDDQ + 0.3

V

Input Low (Logic 0) Voltage

VIL (DC)

-0.3

VREF – 0.1

V

AC INPUT OPERATING CONDITIONS

PARAMETER/ CONDITION

SYMBOL

MIN

MAX

UNITS

Input High (Logic 1) Voltage

VIH (AC)

VREF + 0.175

-

V

Input Low (Logic 0) Voltage

VIL (AC)

-

VREF - 0.175

V

CAPACITANCE

At DDR3 data rates, it is recommended to simulate the performance of the module to achieve optimum values.

When inductance and delay parameters associated with trace lengths are used in simulations, they are

significantly more accurate and realistic than a gross estimation of module capacitance. Simulations can then

render a considerably more accurate result. JEDEC modules are now designed by using simulations to close

timing budgets.

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 8

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

IDD Specifications and Conditions

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

Parameter

& Test Condition

Symbol

max.

Unit

10600-999

8500-777

OPERATING CURRENT *) :

One device bank Active-Precharge;

tRC= tRC (IDD); tCK = tCK (IDD); CKE is HIGH, CS# is HIGH

between valid commands;

DQ inputs changing once per clock cycle; Address and

control inputs changing once every two clock cycles

IDD0

567

540

mA

OPERATING CURRENT *) :

One device bank; Active-Read-Precharge;

IOUT = 0mA; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRC= tRC (IDD), tRAS = tRAS MIN (IDD),

tRCD = tRCD (IDD); CKE is HIGH, CS# is HIGH between

valid commands; Address inputs changing once every

two clock cycles; Data Pattern is same as IDD4W

IDD1

702

675

mA

PRECHARGE POWER-DOWN

CURRENT:

All device banks idle; Power-down mode;

tCK = tCK (IDD); CKE is LOW; All Control and

Address bus inputs are not changing; DQ’s

are floating at VREF

Fast Exit

IDD2P

468

mA

Slow Exit

288

PRECHARGE QUIET STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All Control and Address bus inputs are not changing;

DQ’s are floating at VREF

IDD2Q

450

396

mA

PRECHARGE STANDBY CURRENT:

All device banks idle;

tCK = tCK (IDD); CKE is HIGH, CS# is HIGH;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD2N

450

396

mA

ACTIVE POWER-DOWN CURRENT:

All device banks open; tCK = tCK (IDD); CKE is LOW; All

Control and Address bus inputs are not changing; DQ’s

are floating at VREF (always fast exit)

IDD3P

630

576

mA

ACTIVE STANDBY CURRENT:

All device banks open; tCK = tCK (IDD),

tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

All other Control and Address bus inputs are changing

once every two clock cycles; DQ inputs changing once

per clock cycle

IDD3N

630

576

mA

OPERATING READ CURRENT:

All device banks open, Continuous burst reads; One

module rank active; IOUT = 0mA; BL = 4, CL = CL (IDD),

AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP

(IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are changing once

every two clock cycles; DQ inputs changing once per

clock cycle

IDD4R

1404

1251

mA

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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Parameter

& Test Condition

Symbol

max.

Unit

10600-999

8500-777

OPERATING WRITE CURRENT:

All device banks open, Continuous burst writes; One

module rank active; BL = 4, CL = CL (IDD), AL = 0;

tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are changing once every two clock

cycles; DQ inputs changing once per clock cycle

IDD4W

1134

999

mA

BURST REFRESH CURRENT:

tCK = tCK (IDD); refresh command at every tRFC (IDD)

interval, CKE is HIGH, CS# is HIGH between valid

commands; All other Control and Address bus inputs

are changing once every two clock cycles; DQ inputs

changing once per clock cycle

IDD5

1476

1440

mA

SELF REFRESH CURRENT:

CK and CK# at 0V; CKE ≤ 0.2V; All other Control and

Address bus inputs are floating at VREF; DQ’s are

floating at VREF

IDD6

360

mA

OPERATING CURRENT*) :

Four device bank interleaving READs, IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = tRCD (IDD) – 1 x tCK (IDD); tCK = tCK

(IDD), tRC = tRC (IDD), tRRD = tRRD (IDD), tRCD = tRCD (IDD);

CKE is HIGH, CS# is HIGH between valid commands;

Address bus inputs are not changing during

DESELECT; DQ inputs changing once per clock cycle

IDD7

1854

1584

mA

*) Value calculated as one module rank in this operating condition, and all other module ranks in IDD2P (CKE LOW)

mode.

TIMING VALUES USED FOR IDD MEASUREMENT

IDD MEASUREMENT CONDITIONS

SYMBOL

10600-999

8500-777

Unit

CL (IDD)

9

7

tCK

tRCD (IDD)

13.5

13.125

ns

tRC (IDD)

49.5

50.625

ns

tRRD (IDD)

6

7.5

ns

tCK (IDD)

1.5

1.87

ns

tRAS MIN (IDD)

36

37.5

ns

tRAS MAX (IDD)

70’200

ns

tRP (IDD)

13.5

13.125

ns

tRFC (IDD)

260

ns

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 10

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

10600-999

8500-777

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

Clock cycle time

CL = 10

tCK (10)

1.5

<1.875

-

ns

CL = 9

tCK (9)

1.5

<1.875

-

ns

CL = 8

tCK (8)

1.875

<2.5

-

ns

CL = 7

tCK (7)

1.875

<2.5

1.875

<2.5

ns

CL = 6

tCK (6)

2.5

3.3

2.5

3.3

ns

CL = 5

tCK (5)

3.0

3.3

3.0

3.3

ns

CK high-level width

tCH (avg)

0.47

0.53

0.47

0.53

tCK

CK low-level width

tCL (avg)

0.47

0.53

0.47

0.53

tCK

Data-out high-impedance

window from CK/CK#

tHZ

250

300

ps

Data-out low-impedance window

from CK/CK#

tLZ

-500

250

-600

300

ps

DQ and DM input pulse width

( for each input )

tDIPW

400

490

ps

DQS input high pulse width

tDQSH

0.45

0.55

0.45

0.55

tCK

DQS input low pulse width

tDQSL

0.45

0.55

0.45

0.55

tCK

DQS read preamble

tRPRE

0.9

Note1

0.9

Note1

tCK

DQS read postamble

tRPST

0.3

Note2

0.3

Note2

tCK

DQS write preamble

tWPRE

0.9

tCK

DQS write postamble

tWPST

0.3

tCK

Address and control input pulse

width ( for each input )

tIPW

620

780

ps

1 The maximum preamble is bound by tLZDQS (MAX)

2 The maximum postamble is bound by tHZDQS (MAX)

DQ, DQS and C/A signal setup and hold times tDS, tDH, tDQSQ, tDSS, tDQSS, tDQSCK, tIS, tIH need to be calculated with the

respective DRAM derating tables and the driver slew rate or determined by simulation

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 11

CH – 9552 Bronschhofen Fax: +41 (0) 71 913 03 15 eMail: info@swissbit.com of 18

DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

10600-999

8500-777

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

CAS# to CAS# command delay

tCCD

4

tCK

ACTIVE to ACTIVE (same bank)

command period

tRC

49.5

50.625

ns

ACTIVE bank a to ACTIVE bank

b command

tRRD

max

4nCK,10ns

max

4nCK,7.5ns

ns

ACTIVE to READ or WRITE

delay

tRCD

13.5

13.125

ns

Four bank

Activate period

1K Page size

tFAW

30

37.5

ns

2K Page size

45

50

ACTIVE to PRECHARGE

command

tRAS

36

70’200

37.5

70’200

ns

Internal READ to precharge

command delay

tRTP

max

4nCK,7.5ns

max

4nCK,7.5ns

ns

Write recovery time

tWR

15

ns

Auto precharge write recovery +

precharge time

tDAL

tWR + tRP/tCK

ns

Internal WRITE to READ

command delay

tWTR

max

4nCK,7.5ns

max

4nCK,7.5ns

ns

PRECHARGE command period

tRP

15

13.125

ns

LOAD MODE command cycle

time

tMRD

4

tCK

REFRESH to ACTIVE or

REFRESH to REFRESH

command interval

tRFC

260

70’200

260

70’200

ns

Average periodic refresh interval

0 °C ≤ TCASE ≤ 85°C

tREFI

7.8

µs

85 °C < TCASE ≤ 95°C

tREFI IT

3.9

RTT turn-on from ODTL on

reference

tAON

-250

250

-300

300

ps

RTT turn-on from ODTL off

reference

tAOF

0.3

0.7

0.3

0.7

tCK

Asynchronous RTT turn-on

delay (power Down with DLL off)

tAONPD

2

8,5

2

8,5

ns

Asynchronous RTT turn-off

delay (power Down with DLL off)

tAOFPD

2

8,5

2

8,5

ns

RTT dynamic change skew

tADC

0.3

0.7

0.3

0.7

tCK

Exit self refresh to commands

not requiring a locked DLL

tXS

max

5nCK,tR

FC + 10ns

max

5nCK,tR

FC + 10ns

ns

Write levelling setup from rising

CK, CK# crossing to rising DQS,

DQS# crossing

tWLS

195

245

ps

Write levelling setup from rising

DQS, DQS# crossing to rising

CK, CK# crossing

tWLH

195

245

ps

First DQS, DQS# rising edge

tWLMRD

40

tCK

DQS, DQS# delay

tWLDQSEN

25

tCK

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 12

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DDR3 SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED

AC OPERATING CONDITIONS (Continued)

(0°C ≤ TCASE ≤ + 85°C; VDDQ = +1.5V ± 0.075V, VDD = +1.5V ± 0.075V)

AC CHARACTERISTICS

10600-999

8500-777

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Unit

Exit reset from CKE HIGH to a

valid command

tXPR

max

5nCK,

tRFC + 10ns

max

5nCK,

tRFC + 10ns

Begin power supply ramp to

power supplies stable

tVDDPR

200

ms

RESET# LOW to power supplies

stable

tRPS

200

ms

RESET# LOW to I/O and RTT

High-Z

tIOz

20

ns

Exit precharge power-down to

any non-READ command

tXP

max

3nCK,6ns

max

3nCK,7.5ns

CKE minimum high/low time

tCKE

max

3nCK,

5.625ns

max

3nCK,

5.625ns

Temperature Sensor with Serial Presence-Detect EEPROM

Temperature Sensor with Serial Presence-Detect EEPROM Operating Conditions

Parameter / Condition

Symbol

MIN

MAX

Unit

Supply voltage

VDDSPD

+3

+3.6

V

Supply current: VDD = 3.3V

IDD

+2.0

mA

Input high voltage: Logic 1; SCL, SDA

VIH

+1.45

VDDSPD +1

V

Input low voltage: Logic 0; SCL, SDA

VIL

-

550

mV

Output low voltage: IOUT = 2.1mA

VOL

-

400

mV

Input current

IIN

-5.0

5.0

µA

Temperature sensing range

TBD

°C

Temperature sensor accuracy

TBD

°C

SCL SDA

EVENT

SA2

SA1

SA0

EVENT

WP/

R1

0O

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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A.C. Characteristics of Temperature Sensor

VCC = 3.3 V ± 10%, TA = −40°C to +125°C

Symbol

Parameter / Condition

MIN

MAX

Unit

fSCL

SCL clock frequency

10

400

kHz

tBUF

Bus Free Time Between STOP and START

1300

ns

tF

SDA fall time

300

ns

tR

SDA rise time

300

ns

tHD:DAT

Data hold time (accepted for Input Data)

0

ns

Data Hold Time (guaranteed for Output Data)

300

900

ns

tH:STA

Start condition hold time

600

ns

tHIGH

High Period of SCL

600

ns

tLOW

Low Period of SCL

1300

ns

tSU:DAT

Data setup time

100

ns

tSU:STA

Start condition setup time

600

ns

tSU:STO

Stop condition setup time

600

ns

tTIMEOUT

SMBus SCL Clock Low Timeout

25

35

ms

tI

Noise Pulse Filtered at SCL and SDA Inputs

100

ns

tWR

Write Cycle Time

5

ms

tPU

Power-up Delay to Valid Temperature Recording

100

ms

Temperature Characteristics of Temperature Sensor

VCC = 3.3 V ± 10%, TA = −40°C to +125°C

Parameter

Test Conditions/Comments

MAX

Unit

Temperature Reading Error

Class B, JC42.4 compliant

+75°C ≤ TA ≤ +95°C, active range

±1.0

°C

+40°C ≤ TA ≤ +125°C, monitor range

±2.0

°C

-40°C ≤ TA ≤ +125°C, sensing range

±3.0

°C

ADC Resolution

12

Bits

Temperature Resolution

0.0625

°C

Conversion Time

100

Ms

Thermal Resistance1 θJA

Junction-to-Ambient (Still Air)

92

°C/W

1 Power Dissipation is defined as PJ = (TJ − TA)/θJA, where TJ is the junction temperature and TA is the ambient temperature. The thermal

resistance value refers to the case of a package being used on a standard 2-layer PCB.

Slave Address Bits of Temperature Sensor

Device

Device Type Identifier

Select Address Signals

R/W#

b71

b6

b5

b4

b3

b2

b1

b0

EEPROM

1

0

1

0

A2

A1

A0

R/W#

Temp. Sensor

0

1

A2

A1

A0

R/W#

1 The most significant bit, b7, is sent first.

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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SERIAL PRESENCE-DETECT MATRIX

Byte

Byte Description

10600-999

0

CRC RANGE, EEPROM BYTES, BYTES USED

0x92

1

SPD REVISON

0x11

2

DRAM DEVICE TYPE

0x0B

3

MODULE TYPE (FORM FACTOR)

0x06

4

SDRAM DEVICE DENSITY & BANKS

0x04

5

SDRAM DEVICE ROW & COLUMN COUNT

0x21

6

BYTE 6 RESERVED

0x00

7

MODULE RANKS & DEVICE DQ COUNT

0x09

8

ECC TAG & MODULE MEMORY BUS WIDTH

0x0B

9

FINE TIMEBASE DIVIDEND/DIVISOR

0x11

10

MEDIUM TIMEBASE DIVIDEND

0x01

11

MEDIUM TIMEBASE DIVISOR

0x08

12

MIN SDRAM CYCLE TIME (tCK MIN)

0x0C

13

BYTE 13 RESERVED

0x00

14

CAS LATENCIES SUPPORTED (CL4 => CL11)

0x7E

15

CAS LATENCIES SUPPORTED (CL12 => CL18)

0x00

16

MIN CAS LATENCY TIME (tAA MIN)

0x69

17

MIN WRITE RECOVERY TIME (tWR MIN)

0x78

18

MIN RAS# TO CAS# DELAY (tRCD MIN)

0x69

19

MIN ROW ACTIVE TO ROW ACTIVE DELAY (tRRD MIN)

0x30

20

MIN ROW PRECHARGE DELAY (tRP MIN)

0x69

21

UPPER NIBBLE FOR tRAS & tRC

0x11

22

MIN ACTIVE TO PRECHARGE DELAY (tRAS MIN)

0x20

23

MIN ACTIVE TO ACTIVE/REFRESH DELAY (tRC MIN)

0x89

24

MIN REFRESH RECOVERY DELAY (tRFC MIN) LSB

0x20

25

MIN REFRESH RECOVERY DELAY (tRFC MIN) MSB

0x08

26

MIN INTERNAL WRITE TO READ CMD DELAY (tWTR MIN)

0x3C

27

MIN INTERNAL READ TO PRECHARGE CMD DELAY

(tRTP MIN)

0x3C

28

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) MSB

0x00

29

MIN FOUR ACTIVE WINDOW DELAY (tFAW MIN) LSB

0xF0

30

SDRAM DEVICE OUTPUT DRIVERS SUPPORTED

0x83

31

SDRAM DEVICE THERMAL & REFRESH OPTIONS

0x05

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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Byte

Byte Description

10600-999

32

DDR3-MODULE THERMAL SENSOR

0x80

33

DDR3-SDRAM DEVICE TYPE

0x00

34

DDR3-FINE OFFSET FOR tCKMIN

0x00

35-59

BYTES 33-59 RESERVED

0x00

60

MODULE HEIGHT (NOMINAL)

0x0F

61

MODULE THICKNESS (MAX)

0x11

62

REFERENCE RAW CARD ID

0x01

63

ADDRESS MAPPING EDGE CONECTOR TO DRAM

0x00

64

DDR3-HEATSPREADER SOLUTION

0x00

65-116

BYTES 64-116 RESEVED

0x00

117

MODULE MFR ID (LSB)

0x83

118

MODULE MFR ID (MSB)

0xDA

119

MODULE MFR LOCATION ID

0x01 (Switzerland)

0x02 (Germany)

0x03 (USA)

120

MODULE MFR YEAR

X

121

MODULE MFR WEEK

X

122-125

MODULE SERIAL NUMBER

X

126-127

CRC

tbd

128-145

MODULE PART NUMBER

"SGL08G72B1BE2MT-xx"

146

MODULE DIE REV

n.a.

147

MODULE PCB REV

n.a.

148

DRAM DEVICE MFR ID (LSB)

0x80

149

DRAM DEVICE MFR (MSB)

0x2C

150-175

MFR RESERVED BYTES 150-175

0x00

176-255

CUSTOMER RESERVED BYTES 176-255

0xFF

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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Part Number Code

S

G

L

08G

72

B1

B

E

2

MT

-

CC

*

R

T

1

2

3

4

5

6

7

8

9

10

11

12

13

14

*RoHs compl.

Swissbit AG

DDR3-1333 MT/s

1.5V DDR3

244 Pin Mini-UDIMM

Chip Vendor (Micron)

Depth (8GB)

2 Module Ranks

Width

Chip Rev. E

PCB-Type (BA3S782 1.00)

Chip organisation x8

* optional / additional information

T= Thermal Sensor

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

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Revision History

Revision

Changes

Date

1.0

First release version

25.07.2012

Data Sheet Rev.1.0 25.07.2012

Swissbit AG

Industriestrasse 4 Fon: +41 (0) 71 913 03 03 www.swissbit.com Page 18

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Locations

Swissbit AG

Industriestrasse 4

CH – 9552 Bronschhofen

Switzerland

Phone: +41 (0)71 913 03 03

Fax: +41 (0)71 913 03 15

_____________________________

Swissbit Germany GmbH

Wolfener Strasse 36

D – 12681 Berlin

Germany

Phone: +49 (0)30 93 69 54 – 0

Fax: +49 (0)30 93 69 54 – 55

_____________________________

Swissbit NA, Inc.

1202 E Winding Creek

Eagle, Idaho 83616

USA

Phone: +1 208 938 4525

Fax: +1 914 935 9865

_____________________________

Swissbit Japan, Inc.

3F Core Koenji,

2-1-24 Koenji-Kita, Suginami-Ku,

Tokyo 166-0002

Japan

Phone: +81 3 5356 3511

Fax: +81 3 5356 3512

Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Swissbit:

SGL08G72B1BE2MT-CCRT