Quad Channel, 128-/256-Position, I2C,
Nonvolatile Digital Potentiometer
Data Sheet AD5123/AD5143
Rev. A Document Feedback
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FEATURES
10 kΩ and 100 kΩ resistance options
Resistor tolerance: 8% maximum
Wiper current: ±6 mA
Low temperature coefficient: 35 ppm/°C
Wide bandwidth: 3 MHz
Fast start-up time < 75 μs
Linear gain setting mode
Single- and dual-supply operation
Wide operating temperature: −40°C to +125°C
3 mm × 3 mm package
4 kV ESD protection
APPLICATIONS
Portable electronics level adjustment
LCD panel brightness and contrast controls
Programmable filters, delays, and time constants
Programmable power supplies
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
SS
GND
7/8
SERIAL
INTERFACE
POWER-ON
RESET RDAC1
INPUT
REGISTER 1
RDAC2
INPUT
REGISTER 2
RDAC3
INPUT
REGISTER 3
RDAC4
INPUT
REGISTER 4
EEPROM
MEMORY
A1
W1
B1
A2
W2
B2
W3
B3
W4
B4
AD5123/AD5143
SCL
SDA
A
DDR
10878-001
Figure 1.
GENERAL DESCRIPTION
The AD5123/AD5143 potentiometers provide a nonvolatile
solution for 128-/256-position adjustment applications, offering
guaranteed low resistor tolerance errors of ±8% and up to ±6 mA
current density in the Ax, Bx, and Wx pins.
The low resistor tolerance and low nominal temperature coefficient
simplify open-loop applications as well as applications requiring
tolerance matching.
The linear gain setting mode allows independent programming
of the resistance between the digital potentiometer terminals,
through the RAW and RWB string resistors, allowing very accurate
resistor matching.
The high bandwidth and low total harmonic distortion (THD)
ensure optimal performance for ac signals, making the devices
suitable for filter design.
The low wiper resistance of only 40 Ω at the ends of the resistor
array allows for pin-to-pin connection.
The wiper values can be set through an I2C-compatible digital
interface that is also used to read back the wiper register and
EEPROM contents.
The AD5123/AD5143 are available in a compact, 16-lead, 3 mm ×
3 mm LFCSP. The parts are guaranteed to operate over the extended
industrial temperature range of −40°C to +125°C.
Table 1. Family Models
Model Channel Position Interface Package
AD51231 Quad 128 I2C LFCSP
AD5124 Quad 128 SPI/I2C LFCSP
AD5124 Quad 128 SPI TSSOP
AD5143 Quad 256 I2C LFCSP
AD5144 Quad 256 SPI/I2C LFCSP
AD5144 Quad 256 SPI TSSOP
AD5144A Quad 256 I2C TSSOP
AD5122 Dual 128 SPI LFCSP/TSSOP
AD5122A Dual 128 I2C LFCSP/TSSOP
AD5142 Dual 256 SPI LFCSP/TSSOP
AD5142A Dual 256 I2C LFCSP/TSSOP
AD5121 Single 128 SPI/I2C LFCSP
AD5141 Single 256 SPI/I2C LFCSP
1 Two potentiometers and two rheostats.
AD5123/AD5143 Data Sheet
Rev. A | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—AD5123 .......................................... 3
Electrical Characteristics—AD5143 .......................................... 6
Interface Timing Specifications .................................................. 9
Shift Register and Timing Diagrams ....................................... 10
Absolute Maximum Ratings .......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 13
Test Circuits ..................................................................................... 18
Theory of Operation ...................................................................... 19
RDAC Register and EEPROM .................................................. 19
Input Shift Register .................................................................... 19
I2C Serial Data Interface ............................................................ 19
I2C Address .................................................................................. 19
Advanced Control Modes ......................................................... 21
EEPROM or RDAC Register Protection ................................. 22
RDAC Architecture .................................................................... 25
Programming the Variable Resistor ......................................... 25
Programming the Potentiometer Divider ............................... 26
Terminal Voltage Operating Range ......................................... 26
Power-Up Sequence ................................................................... 26
Layout and Power Supply Biasing ............................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
3/13—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
10/12—Revision 0: Initial Version
Data Sheet AD5123/AD5143
Rev. A | Page 3 of 28
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—AD5123
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution N 7 Bits
Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ
VDD ≥ 2.7 V −1 ±0.1 +1 LSB
VDD < 2.7 V −2.5 ±1 +2.5 LSB
RAB = 100 kΩ
VDD ≥ 2.7 V −0.5 ±0.1 +0.5 LSB
V
DD
< 2.7 V
−1
±0.25
+1
LSB
Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.1 +0.5 LSB
Nominal Resistor Tolerance ΔRAB/RAB −8 ±1 +8 %
Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance3 RW Code = zero scale
R
AB
= 10 kΩ
55
125
Ω
R
AB
= 100 kΩ
130
400
Ω
Bottom Scale or Top Scale RBS or RTS
RAB = 10 kΩ 40 80 Ω
RAB = 100 kΩ 60 230 Ω
Nominal Resistance Match RAB1/RAB2 Code = 0xFF −1 ±0.2 +1 %
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4 INL
R
AB
= 10 kΩ
−0.5
±0.1
+0.5
LSB
RAB = 100 kΩ −0.25 ±0.1 +0.25 LSB
Differential Nonlinearity4 DNL −0.25 ±0.1 +0.25 LSB
Full-Scale Error VWFSE
RAB = 10 kΩ −1.5 −0.1 LSB
RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB
Zero-Scale Error VWZSE
RAB = 10 kΩ 1 1.5 LSB
RAB = 100 kΩ 0.25 0.5 LSB
Voltage Divider Temperature
Coefficient3
(ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C
AD5123/AD5143 Data Sheet
Rev. A | Page 4 of 28
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
RESISTOR TERMINALS
Maximum Continuous Current IA, IB, and IW
RAB = 10 kΩ −6 +6 mA
RAB = 100 kΩ −1.5 +1.5 mA
Terminal Voltage Range
5
V
SS
V
DD
V
Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ 25 pF
RAB = 100 kΩ 12 pF
Capacitance W3 CW f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ 12 pF
RAB = 100 kΩ 5 pF
Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA
DIGITAL INPUTS
Input Logic3
High VINH 0.7 × VDD V
Low VINL 0.2 × VDD V
Input Hysteresis
3
V
HYST
0.1 × V
DD
V
Input Current3 IIN ±1 µA
Input Capacitance3 CIN 5 pF
DIGITAL OUTPUTS
Output High Voltage3 VOH RPULL-UP = 2.2 kΩ to VDD VDD V
Output Low Voltage3 VOL ISINK = 3 mA 0.4 V
ISINK = 6 mA 0.6 V
Three-State Leakage Current −1 +1 µA
Three-State Output Capacitance 2 pF
POWER SUPPLIES
Single-Supply Power Range VSS = GND 2.3 5.5 V
Dual-Supply Power Range ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND
VDD = 5.5 V 0.7 5.5 µA
VDD = 2.3 V 400 nA
Negative Supply Current ISS VIH = VDD or VIL = GND −5.5 −0.7 µA
EEPROM Store Current
3, 6
I
DD_EEPROM_STORE
V
IH
= V
DD
or V
IL
= GND
2
mA
EEPROM Read Current3, 7 IDD_EEPROM_READ VIH = VDD or VIL = GND 320 µA
Power Dissipation8 PDISS VIH = VDD or VIL = GND 3.5 µW
Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = VDD ± 10%,
code = full scale
−66 −60 dB
Data Sheet AD5123/AD5143
Rev. A | Page 5 of 28
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
DYNAMIC CHARACTERISTICS9
Bandwidth BW −3 dB
RAB = 10 kΩ 3 MHz
RAB = 100 kΩ 0.43 MHz
Total Harmonic Distortion
THD
V
DD
/V
SS
= ±2.5 V, V
A
= 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ −80 dB
RAB = 100 kΩ −90 dB
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ 7 nV/√Hz
RAB = 100 kΩ 20 nV/√Hz
VW Settling Time tS VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
R
AB
= 10 kΩ
2
µs
RAB = 100 kΩ 12 µs
Crosstalk (CW1/CW2) CT RAB = 10 kΩ 10 nV-sec
RAB = 100 kΩ 25 nV-sec
Analog Crosstalk CTA −90 dB
Endurance10 TA = 25°C 1 Mcycles
100 kcycles
Data Retention11 50 Years
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD).
9 All dynamic characteristics use VDD/VSS = ±2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
AD5123/AD5143 Data Sheet
Rev. A | Page 6 of 28
ELECTRICAL CHARACTERISTICS—AD5143
VDD = 2.3 V to 5.5 V, VSS = 0 V; VDD = 2.25 V to 2.75 V, VSS = −2.25 V to −2.75 V; −40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
DC CHARACTERISTICS—RHEOSTAT
MODE (ALL RDACs)
Resolution N 8 Bits
Resistor Integral Nonlinearity2 R-INL RAB = 10 kΩ
VDD ≥ 2.7 V −2 ±0.2 +2 LSB
V
DD
< 2.7 V
−5
±1.5
+5
LSB
RAB = 100 kΩ
VDD ≥ 2.7 V −1 ±0.1 +1 LSB
VDD < 2.7 V −2 ±0.5 +2 LSB
Resistor Differential Nonlinearity2 R-DNL −0.5 ±0.2 +0.5 LSB
Nominal Resistor Tolerance
ΔR
AB
/R
AB
−8
±1
+8
%
Resistance Temperature Coefficient3 (ΔRAB/RAB)/ΔT × 106 Code = full scale 35 ppm/°C
Wiper Resistance3 RW Code = zero scale
RAB = 10 kΩ 55 125 Ω
RAB = 100 kΩ 130 400 Ω
Bottom Scale or Top Scale RBS or RTS
RAB = 10 kΩ 40 80 Ω
RAB = 100 kΩ 60 230 Ω
Nominal Resistance Match RAB1/RAB2 Code = 0xFF −1 ±0.2 +1 %
DC CHARACTERISTICS—POTENTIOMETER
DIVIDER MODE (ALL RDACs)
Integral Nonlinearity4 INL
RAB = 10 kΩ −1 ±0.2 +1 LSB
RAB = 100 kΩ −0.5 ±0.1 +0.5 LSB
Differential Nonlinearity4 DNL −0.5 ±0.2 +0.5 LSB
Full-Scale Error VWFSE
RAB = 10 kΩ −2.5 −0.1 LSB
RAB = 100 kΩ −1 ±0.2 +1 LSB
Zero-Scale Error VWZSE
RAB = 10 kΩ 1.2 3 LSB
R
AB
= 100 kΩ
0.5
1
LSB
Voltage Divider Temperature
Coefficient3
(ΔVW/VW)/ΔT × 106 Code = half scale ±5 ppm/°C
Data Sheet AD5123/AD5143
Rev. A | Page 7 of 28
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
RESISTOR TERMINALS
Maximum Continuous Current IA, IB, and IW
RAB = 10 kΩ −6 +6 mA
RAB = 100 kΩ −1.5 +1.5 mA
Terminal Voltage Range
5
V
SS
V
DD
V
Capacitance A, Capacitance B3 CA, CB f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ 25 pF
RAB = 100 kΩ 12 pF
Capacitance W3 CW f = 1 MHz, measured to GND,
code = half scale
RAB = 10 kΩ 12 pF
RAB = 100 kΩ 5 pF
Common-Mode Leakage Current3 VA = VW = VB −500 ±15 +500 nA
DIGITAL INPUTS
Input Logic3
High VINH 0.7 × VDD V
Low VINL 0.2 × VDD V
Input Hysteresis
3
V
HYST
0.1 × V
DD
V
Input Current3 IIN ±1 µA
Input Capacitance3 CIN 5 pF
DIGITAL OUTPUTS
Output High Voltage3 VOH RPULL-UP = 2.2 kΩ to VDD VDD V
Output Low Voltage3 VOL ISINK = 3 mA 0.4 V
ISINK = 6 mA 0.6 V
Three-State Leakage Current −1 +1 µA
Three-State Output Capacitance 2 pF
POWER SUPPLIES
Single-Supply Power Range VSS = GND 2.3 5.5 V
Dual-Supply Power Range ±2.25 ±2.75 V
Positive Supply Current IDD VIH = VDD or VIL = GND
VDD = 5.5 V 0.7 5.5 µA
VDD = 2.3 V 400 nA
Negative Supply Current ISS VIH = VDD or VIL = GND −5.5 −0.7 µA
EEPROM Store Current
3, 6
I
DD_EEPROM_STORE
V
IH
= V
DD
or V
IL
= GND
2
mA
EEPROM Read Current3, 7 IDD_EEPROM_READ VIH = VDD or VIL = GND 320 µA
Power Dissipation8 PDISS VIH = VDD or VIL = GND 3.5 µW
Power Supply Rejection Ratio PSRR ∆VDD/∆VSS = VDD ± 10%,
code = full scale
−66 −60 dB
AD5123/AD5143 Data Sheet
Rev. A | Page 8 of 28
Parameter Symbol Test Conditions/Comments Min Typ 1 Max Unit
DYNAMIC CHARACTERISTICS9
Bandwidth BW −3 dB
RAB = 10 kΩ 3 MHz
RAB = 100 kΩ 0.43 MHz
Total Harmonic Distortion
THD
V
DD
/V
SS
= ±2.5 V, V
A
= 1 V rms,
VB = 0 V, f = 1 kHz
RAB = 10 kΩ −80 dB
RAB = 100 kΩ −90 dB
Resistor Noise Density eN_WB Code = half scale, TA = 25°C,
f = 10 kHz
RAB = 10 kΩ 7 nV/√Hz
RAB = 100 kΩ 20 nV/√Hz
VW Settling Time tS VA = 5 V, VB = 0 V, from
zero scale to full scale,
±0.5 LSB error band
R
AB
= 10 kΩ
2
µs
RAB = 100 kΩ 12 µs
Crosstalk (CW1/CW2) CT RAB = 10 kΩ 10 nV-sec
RAB = 100 kΩ 25 nV-sec
Analog Crosstalk CTA −90 dB
Endurance10 TA = 25°C 1 Mcycles
100 kcycles
Data Retention11 50 Years
1 Typical values represent average readings at 25°C, VDD = 5 V, and VSS = 0 V.
2 Resistor integral nonlinearity (R-INL) error is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to (0.7 × VDD)/RAB.
3 Guaranteed by design and characterization, not subject to production test.
4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. Dual-supply operation enables ground
referenced bipolar signal adjustment.
6 Different from operating current; supply current for EEPROM program lasts approximately 30 ms.
7 Different from operating current; supply current for EEPROM read lasts approximately 20 µs.
8 PDISS is calculated from (IDD × VDD).
9 All dynamic characteristics use VDD/VSS = ±2.5 V.
10 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C to +125°C.
11 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime, based on an activation energy of 1 eV,
derates with junction temperature in the Flash/EE memory.
Data Sheet AD5123/AD5143
Rev. A | Page 9 of 28
INTERFACE TIMING SPECIFICATIONS
VDD = 2.3 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 4. I2C Interface
Parameter1 Test Conditions/Comments Min Typ Max Unit Description
fSCL2 Standard mode 100 kHz Serial clock frequency
Fast mode 400 kHz
t1 Standard mode 4.0 µs SCL high time, tHIGH
Fast mode 0.6 µs
t2 Standard mode 4.7 µs SCL low time, tLOW
Fast mode 1.3 µs
t3 Standard mode 250 ns Data setup time, tSU; DAT
Fast mode 100 ns
t4 Standard mode 0 3.45 µs Data hold time, tHD; DAT
Fast mode 0 0.9 µs
t5 Standard mode 4.7 µs Setup time for a repeated start condition, tSU; STA
Fast mode 0.6 µs
t6 Standard mode 4 µs Hold time (repeated) for a start condition, tHD; STA
Fast mode 0.6 µs
t7 Standard mode 4.7 µs Bus free time between a stop and a start condition, tBUF
Fast mode
1.3
µs
t8 Standard mode 4 µs Setup time for a stop condition, tSU; STO
Fast mode 0.6 µs
t9 Standard mode 1000 ns Rise time of SDA signal, tRDA
Fast mode 20 + 0.1 CL 300 ns
t10 Standard mode 300 ns Fall time of SDA signal, tFDA
Fast mode 20 + 0.1 CL 300 ns
t11 Standard mode 1000 ns Rise time of SCL signal, tRCL
Fast mode 20 + 0.1 CL 300 ns
t11A Standard mode 1000 ns Rise time of SCL signal after a repeated start condition
and after an acknowledge bit, tRCL1 (not shown in Figure 3)
Fast mode 20 + 0.1 CL 300 ns
t
12
Standard mode
300
ns
Fall time of SCL signal, t
FCL
Fast mode 20 + 0.1 CL 300 ns
tSP3 Fast mode 0 50 ns Pulse width of suppressed spike (not shown in Figure 3)
tEEPROM_PROGRAM4 15 50 ms Memory program time (not shown in Figure 3)
tEEPROM_READBACK 7 30 µs Memory readback time (not shown in Figure 3)
tPOWER_UP5 75 µs Power-on EEPROM restore time (not shown in Figure 3)
tRESET 30 µs Reset EEPROM restore time (not shown in Figure 3)
1 Maximum bus capacitance is limited to 400 pF.
2 The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate; however, it has a negative effect on the
EMC behavior of the part.
3 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode.
4 EEPROM program time depends on the temperature and EEPROM write cycles. Higher timing is expected at lower temperatures and higher write cycles.
5 Maximum time after VDD − VSS is equal to 2.3 V.
AD5123/AD5143 Data Sheet
Rev. A | Page 10 of 28
SHIFT REGISTER AND TIMING DIAGRAMS
DATA BI TS
DB8DB15 (MSB) DB0 (L SB)
D7 D6 D5 D4 D3 D2 D1 D0
ADDRESS BITS
A0A1
A2C2 C1 C0 A3C3
CONTRO L BI TS
DB7
10878-002
Figure 2. Input Shift Register Contents
t
7
t
6
t
2
t
4
t
11
t
12
t
6
t
5
t
10
t
1
SCL
SD
A
PS S P
t
3
t
8
t
9
10878-003
Figure 3. I2C Serial Interface Timing Diagram (Typical Write Sequence)
Data Sheet AD5123/AD5143
Rev. A | Page 11 of 28
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter Rating
VDD to GND −0.3 V to +7.0 V
VSS to GND +0.3 V to −7.0 V
VDD to VSS 7 V
VA, VW, VB to GND VSS − 0.3 V, VDD + 0.3 V or
+7.0 V (whichever is less)
IA, IW, IB
Pulsed1
Frequency > 10 kHz
RAW = 10 kΩ ±6 mA/d2
RAW = 100 kΩ ±1.5 mA/d2
Frequency ≤ 10 kHz
RAW = 10 kΩ ±6 mA/√d2
R
AW
= 100 kΩ
±1.5 mA/√d
2
Digital Inputs −0.3 V to VDD + 0.3 V or
+7 V (whichever is less)
Operating Temperature Range, TA3 −40°C to +125°C
Maximum Junction Temperature,
TJ Maximum
150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Package Power Dissipation
(T
J
max − T
A
)/θ
JA
ESD
4
4 kV
FICDM 1.5 kV
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 d = pulse duty factor.
3 Includes programming of EEPROM memory.
4 Human body model (HBM) classification.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Table 6. Thermal Resistance
Package Type θJA θJC Unit
16-Lead LFCSP 89.51 3 °C/W
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
ESD CAUTION
AD5123/AD5143 Data Sheet
Rev. A | Page 12 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NOTES
1. INTE RNALL Y CONNECT THE
EXPOSED PAD TO VSS.
AD5123/
AD5143
TOP VI EW
(No t t o Scal e)
PIN 1
INDICATOR
1A1
2
W1 3
B1 4
W3
11 B4
12 VDD
10 W4
9B2
ADDR
GND
SDA
SCL
5
B3
6
VSS 7
A2 8
W2
15
16
14
13
10878-004
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
A1
Terminal A of RDAC1. V
SS
≤ V
A
≤ V
DD
.
2
W1
Wiper Terminal of RDAC1. V
SS
≤ V
W
≤ V
DD
.
3 B1 Terminal B of RDAC1. VSS ≤ VB ≤ VDD.
4 W3 Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.
5 B3 Terminal B of RDAC3. VSS ≤ VB ≤ VDD.
6 VSS Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
7 A2 Terminal A of RDAC2. VSS ≤ VA ≤ VDD.
8 W2 Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.
9 B2 Terminal B of RDAC2. VSS ≤ VB ≤ VDD.
10 W4 Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.
11 B4 Terminal B of RDAC4. VSS ≤ VB ≤ VDD.
12 VDD Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.
13
SCL
Serial Clock Line. Data is clocked in at the logic low transition.
14 SDA Serial Data Input/Output.
15 ADDR Programmable Address for Multiple Package Decoding.
16 GND Ground Pin, Logic Ground Reference.
EPAD Internally Connect the Exposed Paddle to VSS.
Data Sheet AD5123/AD5143
Rev. A | Page 13 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0100 200
R-INL (LSB)
CODE ( Decimal)
10kΩ, +125°C
10kΩ, + 25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10878-005
Figure 5. R-INL vs. Code (AD5143)
R-INL (LSB)
CODE ( Decimal)
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
0.20
050 100
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10878-006
Figure 6. R-INL vs. Code (AD5123)
0100 200
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
INL (LSB)
CODE ( Decimal)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10878-007
Figure 7. INL vs. Code (AD5143)
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0100 200
R-DNL (LSB)
CODE ( Decimal)
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10878-008
Figure 8. R-DNL vs. Code (AD5143)
CODE ( Decimal)
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
050 100
R-DNL (LSB)
10kΩ, +125°C
10kΩ, +25°C
10kΩ, –40°C
100kΩ, +125°C
100kΩ, +25°C
100kΩ, –40°C
10878-009
Figure 9. R-DNL vs. Code (AD5123)
–0.30
–0.25
–0.20
–0.15
–0.10
–0.05
0
0.05
0.10
DNL (LSB)
CODE ( Decimal)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10878-010
0100 200
Figure 10. DNL vs. Code (AD5143)
AD5123/AD5143 Data Sheet
Rev. A | Page 14 of 28
–0.15
–0.10
–0.05
0
0.05
0.10
0.15
050 100
INL (LSB)
CODE ( Decimal)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10878-011
Figure 11. INL vs. Code (AD5123)
–50
0
50
100
150
200
250
300
350
400
450
POTENTI O MET ER MODE TEMPERATURE
COEFFICIENT (ppm/°C)
100kΩ
10kΩ
10878-012
AD5123
AD5143
CODE ( Decimal)
0 50 100150200255
0 25 50 75 100127
Figure 12. Potentiometer Mode Temperature Coefficient ((ΔVW/VW)/ΔT × 106) vs.
Code
0
100
200
300
400
500
600
700
800
CURRENT (nA)
TEMPERATURE(°C
)
10878-013
I
DD
, V
DD
= 2.3V
I
DD
, V
DD
= 3.3V
I
DD
, V
DD
= 5V
–40 10 60 125110
VSS = GND
Figure 13. Supply Current vs. Temperature
–0.14
–0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
050 100
DNL (LSB)
CODE (Deci mal)
10kΩ, –40°C
10kΩ, +25°C
10kΩ, +125°C
100kΩ, –40°C
100kΩ, +25°C
100kΩ, +125°C
10878-014
Figure 14. DNL vs. Code (AD5123)
–50
0
50
100
150
200
250
300
350
400
450
RHEOSTAT MODE TEMPERATURE
COEFFICIENT (ppm/°C)
10kΩ
100kΩ
10878-015
AD5122A
AD5142A
CODE ( Decimal)
0 50 100150200255
0 25 50 75 100127
Figure 15. Rheostat Mode Temperature Coefficient ((ΔRWB/RWB)/ΔT × 106)
vs. Code
0
200
400
600
800
1000
1200
012345
I
DD
CURRENT (µA)
INPUT VOLTAGE (V)
V
DD
= 2.3V
V
DD
= 3.3V
V
DD
= 5V
V
DD
= 5.5V
10878-016
Figure 16. IDD Current vs. Digital Input Voltage
Data Sheet AD5123/AD5143
Rev. A | Page 15 of 28
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
GAIN (d B)
FREQUENCY (Hz)
AD5143 (AD5123)
0x80 (0x40)
0x40 (0x20)
0x20 (0x10)
0x10 (0x08)
0x8 (0x04)
0x4 (0x02)
0x2 (0x01)
0x1 (0x00)
0x00
10878-017
Figure 17. 10 kΩ Gain vs. Frequency and Code
–100
–90
–80
–70
–60
–50
–40
20 200 2k 20k200k
THD + N (dB)
FREQUENCY (Hz)
10kΩ
100kΩ
V
DD
/V
SS
= ±2.5V
V
A
= 1V rms
V
B
= GND
CODE = HALF SCALE
NOISE FILTER = 22kHz
10878-018
Figure 18. Total Harmonic Distortion Plus Noise (THD + N) vs. Frequency
–100
–80
–60
–40
–20
0
20
10 100 1k 10k 100k 1M 10M
PHASE (Degrees)
FREQUENCY (Hz)
QUARTER SCALE
MIDSCALE
FULL-SCALE
VDD/VSS = ± 2.5V
RAB = 10kΩ
10878-019
Figure 19. Normalized Phase Flatness vs. Frequency, RAB = 10 kΩ
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
GAIN (d B)
FREQUENCY (Hz)
10 100 1k 10k 100k 1M 10M
0x80 (0x40)
0x40 (0x20)
0x20 (0x10)
0x10 (0x08)
0x8 (0x04)
0x4 (0x02)
0x2 (0x01)
0x1 (0x00)
0x00
AD5143 (AD5123)
10878-020
Figure 20. 100 kΩ Gain vs. Frequency and Code
10kΩ
100kΩ
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.001 0.01 0.1 1
THD + N (dB)
VOLTAGE (V rms)
V
DD
/V
SS
= ±2.5V
f
IN
=1kHz
CODE = HALF SCALE
NOISE FILTER = 22kHz
10878-021
Figure 21. Total Harmonic Distortion Plus Noise (THD + N) vs. Amplitude
–80
–90
–70
–60
–50
–40
–30
–20
–10
0
10
10 100 1k 10k 100k 1M
PHASE (Degrees)
FREQUENCY (Hz)
QUARTER SCALE
MIDSCALE
FULL-SCALE V
DD
/V
SS
= ±2. 5V
R
AB
= 100kΩ
10878-022
Figure 22. Normalized Phase Flatness vs. Frequency, RAB = 100 kΩ
AD5123/AD5143 Data Sheet
Rev. A | Page 16 of 28
0
100
200
300
400
500
600
01234 5
WIPER ON RESISTANCE (Ω)
VOLTAGE (V)
100kΩ, V
DD
= 2.3V
100kΩ, V
DD
= 2.7V
100kΩ, V
DD
= 3V
100kΩ, V
DD
= 3.6V
100kΩ, V
DD
= 5V
100kΩ, V
DD
= 5.5V
10kΩ, V
DD
= 2.3V
10kΩ, V
DD
= 2.7V
10kΩ, V
DD
= 3V
10kΩ, V
DD
= 3.6V
10kΩ, V
DD
= 5V
10kΩ, V
DD
= 5.5V
10878-023
Figure 23. Incremental Wiper On Resistance vs. Positive Power Supply (VDD)
0
1
2
3
4
5
6
7
8
9
10
020 40 60 80 100 120
010 20 30 40 50 60
BANDWIDTH ( M Hz )
CODE ( Decimal)
AD5143
AD5123
10kΩ + 0pF
10kΩ + 75pF
10kΩ + 150pF
10kΩ + 250pF
100kΩ + 0p F
100kΩ + 75p F
100kΩ + 150p F
100kΩ + 250p F
10878-024
Figure 24. Maximum Bandwidth vs. Code and Net Capacitance
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0 5 10 15
RELAT I VE VOLTAGE (V)
TIME (µs)
0x80 TO 0x7F 100kΩ
0x80 TO 0x7F 10kΩ
10878-025
Figure 25. Maximum Transition Glitch
0
0.2
0.4
0.6
0.8
1.0
1.2
0
0.0005
0.0010
0.0015
0.0020
0.0025
–400–500–600–300–200–1000100200300400500600
CUMULATIVE PROBABILITY
PROBABILITY DENSITY
RESISTOR DRIFT (ppm)
10878-026
Figure 26. Resistor Lifetime Drift
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10 100 1k 10k 100k 1M 10M
PSRR ( dB)
FREQUENCY (Hz)
10kΩ, RDAC1
100kΩ, RDAC1
10878-027
V
DD
=5V ±10% AC
V
SS
= GND,V
A
=4V, V
B
= GND
CODE =MIDSCALE
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
–0.020
–0.015
–0.010
–0.005
0
0.005
0.010
0.015
0.020
0500 1000 1500 2000
RELAT I VE VOLTAGE (V)
TIME (n s)
10878-028
Figure 28. Digital Feedthrough
Data Sheet AD5123/AD5143
Rev. A | Page 17 of 28
–120
–100
–80
–60
–40
–20
0
10 100 1k 10k 100k 1M 10M
GAIN (d B)
FREQUENCY (Hz)
10kΩ
100kΩ
10878-029
SHUTDOWN MODE ENABLED
Figure 29. Shutdown Isolation vs. Frequency
0
1
2
3
4
5
6
7
050 100 150 200 250
025 50 75 100 125
AD5123
THEORETICAL I
MAX
(mA)
AD5143
100kΩ
10kΩ
CODE ( Decimal)
10878-030
Figure 30. Theoretical Maximum Current vs. Code
AD5123/AD5143 Data Sheet
Rev. A | Page 18 of 28
TEST CIRCUITS
Figure 31 to Figure 35 define the test conditions used in the Specifications section.
AW
B
NC
IW
DUT
VMS
NC = NO CONNECT
10878-031
Figure 31. Resistor Integral Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)
AW
B
DUT
V
MS
V+
V+ = V
DD
1LSB = V + /2
N
10878-032
Figure 32. Potentiometer Divider Nonlinearity Error (INL, DNL)
10878-033
AW
B
DUTIW= VDD/RNOMINAL
V
MS1
V
W
R
W
=V
MS1
/I
W
NC =NO CONNECT
Figure 33. Wiper Resistance
AW
BV
MS
V+ = V
DD
±10%
PSRR (dB) = 20 LO G V
MS
ΔVDD
()
~
VA
VDD
Δ
VMS%
ΔVDD%
PSS (%/%) =
V+
Δ
10878-034
Figure 34. Power Supply Sensitivity and
Power Supply Rejection Ratio (PSS, PSRR)
+
–
DUT CODE = 0x00
0.1V
V
SS
TO V
DD
R
SW
=0.1V
I
SW
I
SW
W
B
A = NC
10878-035
Figure 35. Incremental On Resistance
Data Sheet AD5123/AD5143
Rev. A | Page 19 of 28
THEORY OF OPERATION
The AD5123/AD5143 digital programmable potentiometers are
designed to operate as true variable resistors for analog signals
within the terminal voltage range of VSS < VTERM < VDD. The resistor
wiper position is determined by the RDAC register contents. The
RDAC register acts as a scratchpad register that allows unlimited
changes of resistance settings. A secondary register (the input
register) can be used to preload the RDAC register data.
The RDAC register can be programmed with any position setting
using the I2C interface (depending on the model). When a desirable
wiper position is found, this value can be stored in the EEPROM
memory. Thereafter, the wiper position is always restored to
that position for subsequent power-ups. The storing of EEPROM
data takes approximately 15 ms; during this time, the device is
locked and does not acknowledge any new command, preventing
any changes from taking place.
RDAC REGISTER AND EEPROM
The RDAC register directly controls the position of the digital
potentiometer wiper. For example, when the RDAC register is
loaded with 0x80 (AD5143, 256 taps), the wiper is connected to
half scale of the variable resistor. The RDAC register is a standard
logic register; there is no restriction on the number of changes
allowed.
It is possible to both write to and read from the RDAC register
using the digital interface (see Table 9).
The contents of the RDAC register can be stored to the EEPROM
using Command 9 (see Table 9). Thereafter, the RDAC register
always sets at that position for any future on-off-on power supply
sequence. It is possible to read back data saved into the EEPROM
with Command 3 (see Table 9).
Alternatively, the EEPROM can be written to independently
using Command 11 (see Table 15).
INPUT SHIFT REGISTER
For the AD5123/AD5143, the input shift register is 16 bits wide,
as shown in Figure 2. The 16-bit word consists of four control
bits, followed by four address bits and by eight data bits.
If the AD5143 RDAC or EEPROM registers are read from or
written to, the lowest data bit (Bit 0) is ignored.
Data is loaded MSB first (Bit 15). The four control bits determine
the function of the software command, as listed in Table 9 and
Table 15.
I2C SERIAL DATA INTERFACE
The AD5123/AD5143 has 2-wire, I2C-compatible serial interfaces.
These devices can be connected to an I2C bus as a slave device,
under the control of a master device. See Figure 3 for a timing
diagram of a typical write sequence.
The AD5123/AD5143 supports standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
The 2-wire serial bus protocol operates as follows:
1. The master initiates a data transfer by establishing a start
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high. The following byte is
the address byte, which consists of the 7-bit slave address
and an R/W bit. The slave device corresponding to the
transmitted address responds by pulling SDA low during
the ninth clock pulse (this is called the acknowledge bit).
At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its shift register.
If the R/W bit is set high, the master reads from the slave
device. However, if the R/W bit is set low, the master writes
to the slave device.
2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL.
3. When all data bits have been read from or written to, a stop
condition is established. In write mode, the master pulls the
SDA line high during the tenth clock pulse to establish a stop
condition. In read mode, the master issues a no acknowledge
for the ninth clock pulse (that is, the SDA line remains high).
The master then brings the SDA line low before the tenth
clock pulse, and then high again during the tenth clock pulse
to establish a stop condition.
I2C ADDRESS
The facility to make hardwired changes to ADDR allows the
user to incorporate up to three of these devices on one bus as
outlined in Table 8.
Table 8. I2C Address Selection
ADDR Pin 7-Bit I2C Device Address
VDD 0101000
No connect
1
0101010
GND 0101011
1 Not available in bipolar mode ( VSS < 0 V).
AD5123/AD5143 Data Sheet
Rev. A | Page 20 of 28
Table 9. Reduced Commands Operation Truth Table
Command
Number
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1 Data Bits[DB7:DB0]1
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing
1 0 0 0 1 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to RDAC
2 0 0 1 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial register
data to input register
3
0
0
1
1
0
0
A1
A0
X
X
X
X
X
X
D1
D0
Read back contents
D1 D0 Data
0 1 EEPROM
1 1 RDAC
9 0 1 1 1 0 0 A1 A0 X X X X X X X 1 Copy RDAC register to EEPROM
10
0
1
1
1
0
0
A1
A0
X
X
X
X
X
X
X
0
Copy EEPROM into RDAC
14 1 0 1 1 X X X X X X X X X X X X Software reset
15 1 1 0 0 A3 0 A1 A0 X X X X X X X D0 Software shutdown
D0
Condition
0 Normal mode
1
Shutdown mode
1 X = don’t care.
Table 10. Reduced Address Bits Table
A3 A2 A1 A0 Channel Stored Channel Memory
1 X1 X1 X1 All channels Not applicable
0
0
0
0
RDAC1
RDAC1
0 0 0 1 RDAC2 RDAC2
0 0 1 0 RDAC3 RDAC3
0 0 1 1 RDAC4 RDAC4
1 X = don’t care.
Data Sheet AD5123/AD5143
Rev. A | Page 21 of 28
ADVANCED CONTROL MODES
The AD5123/AD5143 digital potentiometers include a set of user
programming features to address the wide number of applications
for these universal adjustment devices (see Table 15 and Table 17).
Key programming features include the following:
• Input register
• Linear gain setting mode
• Low wiper resistance feature
• Linear increment and decrement instructions
• ±6 dB increment and decrement instructions
• Burst mode (I2C only)
• Reset
• Shutdown mode
Input Register
The AD5123/AD5143 include one input register per RDAC
register. These registers allow preloading of the value for the
associated RDAC register. These registers can be written to using
Command 2 and read back using Command 3 (see Table 15).
This feature allows a synchronous and asynchronous update of
one or all of the RDAC registers at the same time.
The transfer from the input register to the RDAC register is
done synchronously by Command 8 (see Table 15).
If new data is loaded in an RDAC register, this RDAC register
automatically overwrites the associated input register.
Linear Gain Setting Mode
The patented architecture of the AD5123/AD5143 allows the
independent control of each string resistor, RAW, and RWB. To enable
linear gain setting mode, use Command 16 (see Table 15) to set
Bit D2 of the control register (see Table 17).
This mode of operation can control the potentiometer as two
independent rheostats connected at a single point, W terminal,
as opposed to potentiometer mode where each resistor is
complementary, RAW = RAB − RWB.
This mode enables a second input and an RDAC register per
channel, as shown in Table 16; however, the actual RDAC
contents remain unchanged. The same operations are valid
for potentiometer and linear setting gain modes. The parts
restore in potentiometer mode after a reset or power-up.
Low Wiper Resistance Feature
The AD5123/AD5143 include two commands to reduce the wiper
resistance between the terminals when the devices achieve full scale
or zero scale. These extra positions are called bottom scale, BS, and
top scale, TS. The resistance between Terminal A and Terminal W
at top scale is specified as RTS. Similarly, the bottom scale resistance
between Terminal B and Terminal W is specified as RBS.
The contents of the RDAC registers are unchanged by entering
in these positions. There are three ways to exit from top scale
and bottom scale: by using Command 12 or Command 13
(see Table 15); by loading new data in an RDAC register, which
includes increment/decrement operations; or by entering
shutdown mode, Command 15 (see Table 15).
Table 11 and Table 12 show the truth tables for the top scale
position and the bottom scale position, respectively, when the
potentiometer or linear gain setting mode is enabled.
Table 11. Top Scale Truth Table
Linear Gain Setting Mode Potentiometer Mode
RAW RWB RAW RWB
RAB RAB RTS RAB
Table 12. Bottom Scale Truth Table
Linear Gain Setting Mode Potentiometer Mode
RAW RWB RAW RWB
RTS RBS RAB RBS
Linear Increment and Decrement Instructions
The increment and decrement commands (Command 4 and
Command 5 in Table 15) are useful for linear step adjustment
applications. These commands simplify microcontroller
software coding by allowing the controller to send an increment
or decrement command to the device. The adjustment can be
individual or in a ganged potentiometer arrangement, where all
wiper positions are changed at the same time.
For an increment command, executing Command 4 automatically
moves the wiper to the next resistance RDAC position. This
command can be executed in a single channel or multiple channels.
AD5123/AD5143 Data Sheet
Rev. A | Page 22 of 28
±6 dB Increment and Decrement Instructions
Two programming instructions produce logarithmic taper
increment or decrement of the wiper position control by
an individual potentiometer or by a ganged potentiometer
arrangement where all RDAC register positions are changed
simultaneously. The +6 dB increment is activated by Command 6,
and the −6 dB decrement is activated by Command 7 (see Table 15).
For example, starting with the zero-scale position and executing
Command 6 ten times moves the wiper in 6 dB steps to the full-
scale position. When the wiper position is near the maximum
setting, the last 6 dB increment instruction causes the wiper to
go to the full-scale position (see Table 13).
Incrementing the wiper position by +6 dB essentially doubles
the RDAC register value, whereas decrementing the wiper
position by −6 dB halves the register value. Internally, the
AD5123/AD5143 use shift registers to shift the bits left and
right to achieve a ±6 dB increment or decrement. These
functions are useful for various audio/video level adjustments,
especially for white LED brightness settings in which human
visual responses are more sensitive to large adjustments than to
small adjustments.
Table 13. Detailed Left Shift and Right Shift Functions for
the ±6 dB Step Increment and Decrement
Left Shift (+6 dB/Step) Right Shift (−6 dB/Step)
0000 0000 1111 1111
0000 0001 0111 1111
0000 0010 0011 1111
0000 0100 0001 1111
0000 1000 0000 1111
0001 0000 0000 0111
0010 0000 0000 0011
0100 0000 0000 0001
1000 0000 0000 0000
1111 1111 0000 0000
Burst Mode
By enabling the burst mode, multiple data bytes can be sent to
the part consecutively. After the command byte, the part
interprets the consecutive bytes as data bytes for the command.
A new command can be sent by generating a repeat start or by a
stop and start condition.
The burst mode is activated by setting Bit D3 of the control
register (see Table 17).
Reset
The AD5123/AD5143 can be reset through software by executing
Command 14 (see Table 15). The reset command loads the
RDAC registers with the contents of the EEPROM and takes
approximately 30 µs. The EEPROM is preloaded to midscale at
the factory, and initial power-up is, accordingly, at midscale.
Shutdown Mode
The AD5123/AD5143 can be placed in shutdown mode by
executing the software shutdown command, Command 15
(see Table 15), and setting the LSB (D0) to 1. This feature places
the RDAC in a zero power consumption state where the device
operates in potentiometer mode, Terminal A is open-circuited,
and the wiper, Te rm in al W, is connected to Terminal B; however, a
finite wiper resistance of 40 Ω is present. When the device is
configured in linear gain setting mode, the resistor addressed,
RAW or RWB, is internally place at high impedance. Table 14
shows the truth table depending on the device operating mode.
The contents of the RDAC register are unchanged by entering
shutdown mode. However, all commands listed in Table 15 are
supported while in shutdown mode. Execute Command 15 (see
Table 15) and set the LSB (D0) to 0 to exit shutdown mode.
Table 14. Truth Table for Shutdown Mode
Linear Gain Setting Mode Potentiometer Mode
RAW RWB RAW RWB
High impedance High impedance High impedance RBS
EEPROM OR RDAC REGISTER PROTECTION
The EEPROM and RDAC registers can be protected by disabling
any update to these registers. This can be done by using software or
by using hardware. If these registers are protected by software,
set Bit D0 and/or Bit D1 (see Table 17 ), which protects the RDAC
and EEPROM registers independently.
When RDAC is protected, the only operation allowed is to copy
the EEPROM into the RDAC register.
Data Sheet AD5123/AD5143
Rev. A | Page 23 of 28
Table 15. Advance Commands Operation Truth Table
Command
Number
Control
Bits[DB15:DB12]
Address
Bits[DB11:DB8]1 Data Bits[DB7:DB0] 1
C3 C2 C1 C0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Operation
0 0 0 0 0 X X X X X X X X X X X X NOP: do nothing
1 0 0 0 1 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to RDAC
2 0 0 1 0 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to input register
3
0
0
1
1
X
A2
A1
A0
X
X
X
X
X
X
D1
D0
Read back contents
D1 D0 Data
0 0 Input register
0 1 EEPROM
1 0 Control
register
1 1 RDAC
4 0 1 0 0 A3 A2 A1 A0 X X X X X X X 1 Linear RDAC increment
5
0
1
0
0
A3
A2
A1
A0
X
X
X
X
X
X
X
0
Linear RDAC decrement
6 0 1 0 1 A3 A2 A1 A0 X X X X X X X 1 +6 dB RDAC increment
7 0 1 0 1 A3 A2 A1 A0 X X X X X X X 0 −6 dB RDAC decrement
8
0
1
1
0
A3
A2
A1
A0
X
X
X
X
X
X
X
X
Copy input register to RDAC
(software LRDAC)
9 0 1 1 1 0 0 A1 A0 X X X X X X X 1 Copy RDAC register to
EEPROM
10 0 1 1 1 0 0 A1 A0 X X X X X X X 0 Copy EEPROM into RDAC
11 1 0 0 0 0 0 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 Write contents of serial
register data to EEPROM
12 1 0 0 1 A3 A2 A1 A0 1 X X X X X X D0 Top scale
D0 = 0; normal mode
D0 = 1; shutdown mode
13 1 0 0 1 A3 A2 A1 A0 0 X X X X X X D0 Bottom scale
D0 = 1; enter
D0 = 0; exit
14 1 0 1 1 X X X X X X X X X X X X Software reset
15
1
1
0
0
A3
A2
A1
A0
X
X
X
X
X
X
X
D0
Software shutdown
D0 = 0; normal mode
D0 = 1; device placed in
shutdown mode
16 1 1 0 1 X X X X X X X X D3 D2 D1 D0 Copy serial register data to
control register
1 X = don’t care.
Table 16. Address Bits
A3 A2 A1 A0
Potentiometer Mode Linear Gain Setting Mode Stored RDAC
Memory
Input Register
RDAC Register
Input Register
RDAC Register
1 X1 X1 X1 All channels All channels All channels All channels Not applicable
0 0 0 0 RDAC1 RDAC1 RWB1 RWB1 RDAC1
0 1 0 0 Not applicable Not applicable RAW1 RAW1 Not applicable
0 0 0 1 RDAC2 RDAC2 RWB2 RWB2 RDAC2
0 1 0 1 Not applicable Not applicable RAW2 RAW2 Not applicable
0 0 1 0 RDAC3 RDAC3 RWB3 RWB3 RDAC3
0 1 1 0 Not applicable Not applicable RAW3 RAW3 Not applicable
0 0 1 1 RDAC4 RDAC4 RWB4 RWB4 RDAC4
0 1 1 1 Not applicable Not applicable RAW4 RAW4 Not applicable
1 X = don’t care.
AD5123/AD5143 Data Sheet
Rev. A | Page 24 of 28
Table 17. Control Register Bit Descriptions
Bit Name Description
D0 RDAC register write protect
0 = wiper position frozen to value in EEPROM memory
1 = allows update of wiper position through digital interface (default)
D1 EEPROM program enable
0 = EEPROM program disabled
1 = enables device for EEPROM program (default)
D2 Linear setting mode/potentiometer mode
0 = potentiometer mode (default)
1 = linear gain setting mode
D3 Burst mode
0 = disabled (default)
1 = enabled (no disable after stop or repeat start condition)
Data Sheet AD5123/AD5143
Rev. A | Page 25 of 28
RDAC ARCHITECTURE
To achieve optimum performance, Analog Devices, Inc., has
patented the RDAC segmentation architecture for all the digital
potentiometers. In particular, the AD5123/AD5143 employ a
three-stage segmentation approach, as shown in Figure 36. The
AD5123/AD5143 wiper switch is designed with the transmission
gate CMOS topology and with the gate voltage derived from
VDD and VSS.
7-BIT/8-BIT
ADDRESS
DECODER
R
L
W
R
L
A
R
H
R
H
R
M
R
M
B
R
M
R
M
R
H
R
H
S
TS
S
BS
10878-036
Figure 36. AD5123/AD5143 Simplified RDAC Circuit
Top Scale/Bottom Scale Architecture
In addition, the AD5123/AD5143 include new positions to
reduce the resistance between terminals. These positions are
called bottom scale and top scale. At bottom scale, the typical
wiper resistance decreases from 130 Ω to 60 Ω (RAB = 100 kΩ).
At top scale, the resistance between Terminal A and Terminal W is
decreased by 1 LSB, and the total resistance is reduced to 60 Ω
(RAB = 100 kΩ).
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation—±8% Resistor Tolerance
The AD5123/AD5143 operate in rheostat mode when only two
terminals are used as a variable resistor. The unused terminal can
be floating, or it can be tied to Terminal W, as shown in Figure 37.
A
W
B
A
W
B
A
W
B
10878-037
Figure 37. Rheostat Mode Configuration
The nominal resistance between Terminal A and Terminal B,
RAB, is 10 k or 100 k, and has 128/256 tap points accessed by
the wiper terminal. The 7-bit/8-bit data in the RDAC latch is
decoded to select one of the 128/256 possible wiper settings. The
general equations for determining the digitally programmed
output resistance between Terminal W and Terminal B are
AD5123:
W
AB
WB RR
D
DR
128
)( From 0x00 to 0x7F (1)
AD5143:
W
AB
WB RR
D
DR
256
)( From 0x00 to 0xFF (2)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
In potentiometer mode, similar to the mechanical potentiometer,
the resistance between Terminal W and Terminal A also produces
a digitally controlled complementary resistance, RWA . RWA also
gives a maximum of 8% absolute. RWA starts at the maximum
resistance value and decreases as the data loaded into the latch
increases. The general equations for this operation are
AD5123:
W
ABAW RR
D
DR
128
128
)( From 0x00 to 0x7F (3)
AD5143:
W
ABAW RR
D
DR
256
256
)( From 0x00 to 0xFF (4)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
If the part is configured in linear gain setting mode, the resistance
between Terminal W and Terminal A is directly proportional
to the code loaded in the associate RDAC register. The general
equations for this operation are
AD5123:
W
ABAW RR
D
DR
128
)( From 0x00 to 0x7F (5)
AD5143:
W
ABAW RR
D
DR
256
)( From 0x00 to 0xFF (6)
where:
D is the decimal equivalent of the binary code in the 7-bit/8-bit
RDAC register.
RAB is the end-to-end resistance.
RW is the wiper resistance.
AD5123/AD5143 Data Sheet
Rev. A | Page 26 of 28
In the bottom scale condition or top scale condition, a finite
total wiper resistance of 40 Ω is present. Regardless of which
setting the part is operating in, limit the current between
Terminal A to Terminal B, Terminal W to Terminal A, and
Terminal W to Terminal B, to the maximum continuous
current of ±6 mA or to the pulse current specified in Table 5.
Otherwise, degradation or possible destruction of the internal
switch contact can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A that is proportional to the input voltage
at A to B, as shown in Figure 38.
W
A
B
V
A
V
OUT
V
B
10878-038
Figure 38. Potentiometer Mode Configuration
Connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the Wiper W to Terminal B
ranging from 0 V to 5 V. The general equation defining the
output voltage at VW with respect to ground for any valid
input voltage applied to Terminal A and Terminal B is
B
AB
AW
A
AB
WB
WV
R
DR
V
R
DR
DV )(
)(
)( (7)
where:
RWB(D) can be obtained from Equation 1 and Equation 2.
RAW(D) can be obtained from Equation 3 and Equation 4.
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors, RAW and RWB, and not the
absolute values. Therefore, the temperature drift reduces to
5 ppm/°C.
TERMINAL VOLTAGE OPERATING RANGE
The AD5123/AD5143 are designed with internal ESD diodes
for protection. These diodes also set the voltage boundary of
the terminal operating voltages. Positive signals present on
Terminal A, Terminal B, or Terminal W that exceed VDD are
clamped by the forward-biased diode. There is no polarity
constraint between VA, VW, and VB, but they cannot be higher
than VDD or lower than VSS.
V
DD
A
W
B
V
SS
10878-039
Figure 39. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Because there are diodes to limit the voltage compliance at
Terminal A, Terminal B, and Terminal W (see Figure 39), it is
important to power up VDD first before applying any voltage to
Terminal A, Terminal B, and Terminal W. Otherwise, the diode
is forward-biased such that VDD is powered unintentionally. The
ideal power-up sequence is VSS, VDD, digital inputs, and VA, VB,
and VW. The order of powering VA, VB, VW, and digital inputs is
not important as long as they are powered after VSS and VDD.
Regardless of the power-up sequence and the ramp rates of the
power supplies, once VDD is powered, the power-on preset
activates, which restores EEPROM values to the RDAC registers.
LAYOUT AND POWER SUPPLY BIASING
It is always a good practice to use a compact, minimum lead
length layout design. Ensure that the leads to the input are as
direct as possible with a minimum conductor length. Ground
paths should have low resistance and low inductance. It is also
good practice to bypass the power supplies with quality capacitors.
Apply low equivalent series resistance (ESR) 1 μF to 10 μF
tantalum or electrolytic capacitors at the supplies to minimize
any transient disturbance and to filter low frequency ripple.
Figure 40 illustrates the basic supply bypassing configuration
for the AD5123/AD5143.
VSS
VDD +VDD
C1
0.1µF
C3
10µF
+C2
0.1µF
C4
10µF
VSS
AD5123/
AD5143
GND
10878-040
Figure 40. Power Supply Bypassing
Data Sheet AD5123/AD5143
Rev. A | Page 27 of 28
OUTLINE DIMENSIONS
3.10
3.00 SQ
2.90
0.30
0.23
0.18
1.75
1.60 S Q
1.45
08-16-2010-E
1
0.50
BSC
BOTTOM VIEWTOP VIEW
16
5
8
9
1213
4
EXPOSED
PAD
PIN 1
INDICATOR
0.50
0.40
0.30
SEATING
PLANE
0.05 MAX
0.02 NOM
0.20 RE F
0.25 MI N
COPLANARITY
0.08
PIN 1
INDI
C
ATOR
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NF IG URATI O N AND
FUNCTION DESCRIPTIONS
SECTION OF T HIS DATA SHEET.
0.80
0.75
0.70
COMPLIANT
TO
JEDEC S TANDARDS MO - 2 20-WEED- 6.
Figure 41. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 R
AB (kΩ) Resolution Interface Temperature Range Package Description Package Option Branding
AD5123BCPZ10-RL7 10 128 I2C −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DGZ
AD5123BCPZ100-RL7 100 128 I2C −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH0
AD5143BCPZ10-RL7 10 256 I2C −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH1
AD5143BCPZ100-RL7 100 256 I2C −40°C to +125°C 16-Lead LFCSP_WQ CP-16-22 DH2
EVAL-AD5143DBZ Evaluation Board
1 Z = RoHS Compliant Part.
2 The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all of the available resistor value options.
AD5123/AD5143 Data Sheet
Rev. A | Page 28 of 28
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10878-0-3/13(A)
