W24258/LL 4 Winbond s eEchoe Electronics Carp. ore 32K x 8 CMOS STATIC RAM GENERAL DESCRIPTION The W24258/LL is a normal speed, very low power CMOS static RAM organized as 32768 x 8 bits that operates on a single 5-volt power supply. This device is manufactured using Winbonc's high pertormance CMOS technology. FEATURES Low power consumption: Three-state outputs Active: 350 mW (max.) Battery back-up operation capability Standby: 25 pW (max.) Data retention voltage: 2V (min.) Access time: 55/70 nS (max.) + Packaged in 28-pin 600 mil DIP, 330 mil SOP Single 5V power supply and standard type one TSOP (8 mm ~x 13.4 * Fully static operation mm) * All inputs and outputs directly TTL compatible PIN CONFIGURATIONS BLOCK DIAGRAM Ale A R AP Go aa Clio L_ 2 Oy aac w CORE CELL ARRAY Az C] 2 a = Ad E S12ROWS ar [3 26 [] aia AS 3 64 X 8 COLUMNS AB C4 25 [|] As AB E 4s Cl 5 24 [] ag A4 Cle ; 23 [J] Ali as OC)? oI ae [OE [__vocKT. _| a2 Che a1 ate Al La 2 7] cs 4 ADC] io ia [-] vos vor [] 44 is [1 vor vo2 [] t2 17 [] vos vos [| i3 is [] vos Vgs (| 14 is [1 voa PIN DESCRIPTION a fie zB SYMBOL DESCRIPTION Ag | 3 pg fo O08 aa os a5 198 AO-A14 Address Inputs WE C7) 6 . ps 5 aie oa 58S ae ee 01-08 | Data Inputs/Outputs acia zo | vO3 . M | i i Es! cs Chip Select Input as i 13 2 al WE Write Enable Input OE Output Enable Input VDD Power Supply Vss Ground Publication Release Date: November 1998 -I- Revision ASW24258/LL Atty & Winbond TRUTH TABLE cs OE WE MODE /01- /O8 Vpp CURRENT H x x Not Selected High 2 ISB, ISB1 L H H Output Disable High 7 IDD L L H Read Data Out IDD L x L Write Data In IDD DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER RATING UNIT Supply Voltage to Vss Potential -0.5 to +7.0 Vv Input/Output to Vss Potential -0.5 to VDD +0.5 V Allowable Power Dissipation 1.0 W Storage Temperature -65 to +150 C Operating Temperature 0 to 70 C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. Operating Characteristics (VDD = 5V 410%; Vss = OV; TA = 0 C to 70 C) PARAMETER SYM. TEST CONDITIONS MIN. | TYP.* MAX. UNIT Input Low Voltage VIL - -0.5 - +0.8 V Input High Voltage VIH - +2.2 - Vob +0.5 V Input Leakage Current IL VIN = Vss to VDD -1 - +1 pA Output Leakage Current | ILO | yyo=Vssto Vop, CS = VIH -1 - +1 LA (min.) or OE = Vin (min.) or WE = VIL (max.) Output Low Voltage VoL | loL=+2.1 mA - - 0.4 V Output High Voltage VOH | lOH=-1.0 mA 2.4 - - Vv Operating Power IDD |GS=vIL (max.), /O =0 55 - - 70 mA Supply Current /O =O mA, Cycle = 70 - - 60 mA min. Duty =100% Standby Power Supply IsBB | GS=VH (min.), Cycle = min. - - 3 mA Current Duty = 100% IsB1_ | CS 2 VoD -0.2V - | 07 5 A Note : Typical parameter is measured under ambient temperature TA = 25 C and Vbp = 5V. _2-an G Winbond NE Flectronics Corn. W24258/LL SRR TITIES CAPACITANCE (VoD = 5V, TA = 25 C, f= 1 MHz) PARAMETER SYM. CONDITIONS MAX. UNIT Input Capacitance CIN VIN = OV 6 pF Input/Output Capacitance Cio VOUT = OV 8 pF Note: These parameters are sampled but not 100% tested. AC CHARACTERISTICS AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels OV to 3.0V Input Rise and Fall Times 5n8 Input and Output Timing Reference Level 1.5V Output Load See the drawing below AC TEST LOADS AND WAVEFORM 1 7TL 1 TTL OUTPUT OUTPUT I 100 pF l 5 pF 1 Including | Including ~ Jig and ~ Jig and Scope Scope (For Tetz, ToLz, TcHz, Touz, TwHz, Tow) 304. 1+ 90% 90% a ov _| 10% 2 6 5nS 5nS Publication Release Date: November 1998 Revision ASW24258/LL Athy @ Winbond SOR Electronics Corn, SIRES I SIDS IIIS IIIS II IIIS AC Characteristics, continued (VDD = 5V 410%; Vss = OV; TA = 0 C to 70 C) Read Cycle PARAMETER SYM. W24258-55LL W24258-70LL UNIT MIN. MAX. MIN. MAX. Read Cycle Time TRC 55 - 70 - ns Address Access Time TAA - 55 - 70 ns Chip Select Access Time TACS - 55 - 70 ns Qutput Enable to Output Valid TAOE - af - 35 ns Chip Selection to Output in Low 2 TcLz* 10 - 10 - ns Output Enable to Output in Low 7 ToOLz* 5 - 5 - ns Chip Deselection te Output in High 2 TCHZ* - 20 - 30 ns Output Disable to Output in High 2 TOHzZ* - 20 - 30 ns Output Hold from Address Change TOH 10 - 10 - ns + These parameters are sampled but nat 100% tested Write Cycle PARAMETER SYM. W24258-55LL W24258-70LL UNIT MIN. MAX. MIN. MAX. Write Cycle Time Twec 55 - 70 - ns Chip Selection to End of Write Tow 40 - 50 - ns Address Valid to End of Write TAW 40 - 50 - ns Address Setup Time TAS 0 - 0 - ns Write Pulse Width TWP 40 - 50 - ns Write Recovery Time CS, WE | TWR 0 - 0 - ns Data Valid to End of Write TDW 25 - 30 - ns Data Hold from End of Write TDH 0 - 0 - ns Write to Output in High 4 TWHzZ* - 20 - 25 ns Output Disable to Output in High 7 TOHzZ* - 20 - 25 ns Output Active from End of Write TOW 5 - 5 - ns * These parameters are sampled but not 100% testedW24258/LL Winbond fetthey, SIP III IIIT TIMING WAVEFORMS Read Cycle 1 (Address Controlled) TAC Address a TAA al TOH TOH Read Cycle 2 (Chip Select Controlled) s \\ANY LLLLLLL LLL TACS _* m TCLZ TeHz * : XXXX s Read Cycle 3 (Output Enable Controlled) Address DOUT Publication Release Date: November 1998 -5- Revision ASW24258/LL Winbond fetthey, SIP III IIIT Timing Waveforms, continued Write Cycle 1 = LLL 1/ MWAAAAAAL B NNAANAASS OSS LLL LLL TAW WE oN N \ x +f wt TOHZ ~Tw~ywT NSS (1, 4) Dout 44 44 f/ i ete TDH 7 << xXXXXX Write Cycle 2 (OE = Vit Fixed) ~ = WWW WZ Do TNS NN SS Z2L2L2LLLL ;