AD8143ACPZ-REEL - Analog Devices

High Speed, Triple Differential

Receiver with Comparators

AD8143

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

High speed

160 MHz large signal bandwidth

1000 V/μs slew rate @ G = 1, VO = 2 V p-p

High CMRR: 65 dB @ 10 MHz

High differential input impedance: 5 MΩ

Input common-mode range: ±10.5 V (±12 V supplies)

User-adjustable gain

Wide power supply range: +5 V to ±12 V

Fast settling: 8 ns to 1%

Disable feature

Low offset: ±3.4 mV on 5 V supply

2 on-chip comparators

Small packaging: 32-lead, 5 mm × 5 mm LFCSP

APPLICATIONS

RGB video receivers

KVM (keyboard-video-mouse)

UTP (unshielded twisted pair) receivers

PIN CONFIGURATION

REF_G

GND

IN+_G

FB_G

REF_R

IN–_G

GND

FB_R

OUT_B

GND

OUT_R

OUT_G

COMPB_IN+

S+

GND

COMPB_IN–

IN–_B

GND

FB_B

IN+_B

DIS/PD

REF_B

GND

S–

IN+_R

GND

COMPA_IN+

IN–_R

COMPA_OUT

COMPA_IN–

GND

COMPB_OUT

AD8143

05538-001

32 31 30 29 28 27 26 25

9 10111213141516

Figure 1.

GENERAL DESCRIPTION

The AD8143 is a triple, low cost, differential-to-

single-ended receiver specifically designed for

receiving red-green-blue (RGB) signals over twisted

pair cable. It can also be used for receiving any type of

analog signal or high speed data transmission. Two

auxiliary comparators are provided to receive digital

or sync signals. The AD8143 can be used in conjunction

with the AD8133 and AD8134 triple, differential

drivers to provide a complete low cost solution for

RGB over Category-5 UTP cable applications,

including KVM.

The excellent common-mode rejection (65 dB @

10 MHz) of the AD8143 allows for the use of low cost

unshielded twisted pair cables in noisy environments.

The AD8143 has a wide power supply range from single +5 V

supply to ±12 V, which allows for a wide common-mode range.

The wide common-mode input range of the AD8143 maintains

signal integrity in systems where the ground potential is a few

volts different between the drive and receive ends without the

use of isolation transformers.

The AD8143 is stable at a gain of 1. Closed-loop gain is easily

set using external resistors.

The AD8143 is available in a 5 mm × 5 mm, 32-lead LFCSP and

is rated to work over the extended industrial temperature range

of −40°C to +85°C.

AD8143

Rev. 0 | Page 2 of 24

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Pin Configuration............................................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 9

Thermal Resistance ...................................................................... 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Theory of Operation ...................................................................... 17

Applications..................................................................................... 18

Overview ..................................................................................... 18

Basic Closed-Loop Gain Configurations ................................ 18

Terminating the Input................................................................ 19

Input Clamping........................................................................... 19

Printed Circuit Board Layout Considerations ....................... 20

Driving a Capacitive Load......................................................... 22

Power-Down ............................................................................... 22

Comparators ............................................................................... 22

Sync Pulse Extraction Using Comparators............................. 22

Outline Dimensions ....................................................................... 24

Ordering Guide .......................................................................... 24

REVISION HISTORY

10/05—Revision 0: Initial Version

AD8143

Rev. 0 | Page 3 of 24

SPECIFICATIONS

VS = ±12 V, TA = 25°C, REF = 0 V, RL = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth VOUT = 0.2 V p-p 260 MHz

OUT = 2 V p-p 160 MHz

Bandwidth for 0.1dB Flatness VOUT = 0.2 V p-p 45 MHz

Slew Rate VOUT = 2 V p-p, RL = 1 kΩ 1000 V/μs

Settling Time VOUT = 2 V p-p, 1% 8 ns

OUT = 2 V p-p, 0.1% 31 ns

Output Overdrive Recovery 50 ns

NOISE/DISTORTION

Second Harmonic VOUT = 2 V p-p, 1 MHz −70 dBc

Third Harmonic VOUT = 2 V p-p, 1 MHz −80 dBc

Crosstalk VOUT = 1 V p-p, 10 MHz −70 dB

Input Voltage Noise (RTI) f ≥ 10 kHz 14 nV/√Hz

Differential Gain Error NTSC, 200 IRE, RL ≥ 150 Ω 0.03 %

Differential Phase Error NTSC, 200 IRE, RL ≥ 150 Ω 0.06 Degrees

INPUT CHARACTERISTICS

Common-Mode Rejection DC, VCM = −3.5 V to +3.5 V 86 90 dB

CM = 1 V p-p, f = 10 MHz 65 dB

CM = 1 V p-p, f = 100 MHz 28 dB

Common-Mode Voltage Range V+IN − V−IN = 0 V ±10.5 V

Differential Operating Range ±2.5 V

Resistance Differential 5 MΩ

Common-mode 3 MΩ

Capacitance Differential 2 pF

Common-mode 3 pF

DC PERFORMANCE

Open-Loop Gain VOUT = ±1 V 70 dB

Closed-Loop Gain Error DC 0.25 %

Input Offset Voltage −4.3 +4.3 mV

MIN to TMAX 15 μV/°C

Input Bias Current (+IN, −IN) −3.0 +3.0 μA

Input Bias Current (REF, FB) −4.6 +3.7 μA

Input Bias Current Drift TMIN to TMAX (+IN, −IN) 16 nA/°C

Input Offset Current (+IN, −IN, REF, FB) −2.55 +1.45 μA

Input Offset Current Drift TMIN to TMAX ±3 nA/°C

OUTPUT PERFORMANCE

Voltage Swing RLOAD = 1 kΩ −10.80 +10.82 V

Output Current 40 mA

Short Circuit Current Short to GND, source/sink 107/147 mA

COMPARATOR PERFORMANCE

VOH 3.135 3.3 V

VOL 0.2 0.255 V

Hysteresis Width 41 mV

Input Bias Current Input driven low 3.5 μA

Propagation Delay, tPLH RL = 10 kΩ 20 ns

Propagation Delay, tPHL RL = 10 kΩ 15 ns

Output Rise Time 25% to 75%, RL = 10 kΩ 15 ns

Output Fall Time 25% to 75%, RL = 10 kΩ 11 ns

AD8143

Rev. 0 | Page 4 of 24

Parameter Conditions Min Typ Max Unit

POWER-DOWN PERFORMANCE

Power-Down VIH V

S+ − 1.5 V

Power-Down VIL V

S+ − 2.5 V

Power-Down IIH PD = VCC 1.0 μA

Power-Down IIL PD = GND 800 μA

Power-Down Assert Time 0.5 μs

POWER SUPPLY

Operating Range 4.5 24 V

Quiescent Current, Positive Supply 44.0 57.5 mA

Quiescent Current, Negative Supply 37.0 51.0 mA

PSRR, Positive Supply DC −75 −71 dB

PSRR, Negative Supply DC −82 −81 dB

AD8143

Rev. 0 | Page 5 of 24

VS = ±5 V, TA = 25°C, REF = 0 V, RL = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 2.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth VOUT = 0.2 V p-p 230 MHz

OUT = 2 V p-p 130 MHz

Bandwidth for 0.1dB Flatness VOUT = 0.2 V p-p 45 MHz

Slew Rate VOUT = 2 V p-p, RL = 1 kΩ 1000 V/μs

Settling Time VOUT = 2 V p-p, 1% 10 ns

OUT = 2 V p-p, 0.1% 23 ns

Output Overdrive Recovery 50 ns

NOISE/DISTORTION

Second Harmonic VOUT = 1 V p-p, 1 MHz −68 dBc

Third Harmonic VOUT = 1 V p-p, 1 MHz −82 dBc

Crosstalk VOUT = 1 V p-p, 10 MHz −70 dB

Input Voltage Noise (RTI) f ≥ 10 kHz 14 nV/√Hz

Differential Gain Error NTSC, 200 IRE, RL ≥ 150 Ω 0.3 %

Differential Phase Error NTSC, 200 IRE, RL ≥ 150 Ω 0.6 Degrees

INPUT CHARACTERISTICS

Common-Mode Rejection DC, VCM = −3.5 V to +3.5 V 84 90 dB

CM = 1 V p-p, f = 10 MHz 65 dB

CM = 1 V p-p, f = 100 MHz 28 dB

Common-Mode Voltage Range V+IN − V−IN = 0 V ±3.8 V

Differential Operating Range ±2.5 V

Resistance Differential 5 MΩ

Common-mode 3 MΩ

Capacitance Differential 2 pF

Common-mode 3 pF

DC PERFORMANCE

Open-Loop Gain VOUT = ±1 V 70 dB

Closed-Loop Gain Error DC 0.25 %

Input Offset Voltage −3.7 +3.7 mV

MIN to TMAX 15 μV/°C

Input Bias Current (+IN, −IN) −3.0 +2.7 μA

Input Bias Current (REF, FB) −4.3 +3.0 μA

Input Bias Current Drift TMIN to TMAX (+IN, −IN, REF, FB) 16 nA/°C

Input Offset Current (+IN, −IN, REF, FB) −2.9 1.9 μA

Input Offset Current Drift TMIN to TMAX ±3 nA/°C

OUTPUT PERFORMANCE

Voltage Swing RLOAD = 150 Ω −3.53 +3.53 V

Output Current 40 mA

Short Circuit Current Short to GND, source/sink 107/147 mA

COMPARATOR PERFORMANCE

VOH RL = 10 kΩ 3.02 3.14 V

VOL RL = 10 kΩ 0.19 0.25 V

Hysteresis Width 32 mV

Input Bias Current Input driven low 3.5 μA

Propagation Delay, tPLH 20 ns

Propagation Delay, tPHL 15 ns

Output Rise Time 10% to 90% 15 ns

Output Fall Time 10% to 90% 11 ns

AD8143

Rev. 0 | Page 6 of 24

Parameter Conditions Min Typ Max Unit

POWER-DOWN PERFORMANCE

Power-Down VIH V

S+ − 1.5 V

Power-Down VIL V

S+ − 2.5 V

Power-Down IIH PD = VCC 1 μA

Power-Down IIL PD = GND 230 μA

Power-Down Assert Time 0.5 μs

POWER SUPPLY

Operating Range 4.5 24 V

Quiescent Current, Positive Supply 39.0 49.5 mA

Quiescent Current, Negative Supply 34.5 43.5 mA

PSRR, Positive Supply DC −80 −74 dB

PSRR, Negative Supply DC −80 −75 dB

AD8143

Rev. 0 | Page 7 of 24

VS = 5 V, TA = 25°C, REF = +2.5 V, RL = 150 Ω, CL = 2 pF, G = 1, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.

Table 3.

Parameter Conditions Min Typ Max Unit

DYNAMIC PERFORMANCE

−3 dB Bandwidth VOUT = 0.2 V p-p 220 MHz

OUT = 2 V p-p 125 MHz

Bandwidth for 0.1dB Flatness VOUT = 0.2 V p-p 45 MHz

Slew Rate VOUT = 2 V p-p, RL = 1 kΩ 1000 V/μs

Settling Time VOUT = 2 V p-p, 1% 10 ns

OUT = 2 V p-p, 0.1% 23 ns

Output Overdrive Recovery 50 ns

NOISE

Crosstalk VOUT = 1 V p-p, 10 MHz −70 dB

Input Voltage Noise (RTI) f ≥ 10 kHz 14 nV/√Hz

INPUT CHARACTERISTICS

Common-Mode Rejection DC, VCM = −3.5 V to +3.5 V 76 90 dB

CM = 1 V p-p, f = 10 MHz 65 dB

CM = 1 V p-p, f = 100 MHz 32 dB

Common-Mode Voltage Range V+IN − V−IN = 0 V 1.3 to 3.7 V

Differential Operating Range ±2.5 V

Resistance Differential 5 MΩ

Common-mode 3 MΩ

Capacitance Differential 2 pF

Common-mode 3 pF

DC PERFORMANCE

Open-Loop Gain VOUT = ±1 V 70 dB

Closed-Loop Gain Error DC, measured at G = 11 0.25 %

Input Offset Voltage −3.4 +3.4 mV

MIN to TMAX 15 μV/°C

Input Bias Current (+IN, −IN) −3 +2.7 μA

Input Bias Current (REF, FB) −4.5 +3 μA

Input Bias Current Drift TMIN to TMAX (+IN, −IN, REF, FB) 16 nA/°C

Input Offset Current (+IN, −IN, REF, FB) −2.3 +1.3 μA

Input Offset Current Drift TMIN to TMAX ±3 nA/°C

OUTPUT PERFORMANCE

Voltage Swing RLOAD = 150 Ω 0.88 3.58 V

Output Current 40 mA

Short Circuit Current Short to GND 150 mA

COMPARATOR PERFORMANCE

VOH RL = 10 kΩ 3.02 V

VOL RL = 10 kΩ 0.25 V

Hysteresis Width 32 mV

Input Bias Current Input driven low 3.5 μA

Propagation Delay, tPLH 20 ns

Propagation Delay, tPHL 15 ns

Output Rise Time 10% to 90% 15 ns

Output Fall Time 10% to 90% 11 ns

POWER-DOWN PERFORMANCE

Power-Down VIH V

S+ − 1.5 V

Power-Down VIL V

S+ − 2.5 V

Power-Down IIH PD = VCC 1 μA

Power-Down IIL PD = GND 230 μA

Power-Down Assert Time 0.5 μs

AD8143

Rev. 0 | Page 8 of 24

Parameter Conditions Min Typ Max Unit

POWER SUPPLY

Operating Range 4.5 24 V

Quiescent Current, Positive Supply 31.5 38.8 mA

PSRR, Positive Supply DC −86 −76 dB

AD8143

Rev. 0 | Page 9 of 24

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

Supply Voltage 24 V

Power Dissipation See Figure 2

Storage Temperature Range –65°C to +125°C

Operating Temperature Range –40°C to +85°C

Lead Temperature Range (Soldering 10 sec) 300°C

Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, θJA is

specified for a device soldered in the circuit board with its

exposed paddle soldered to a pad on the PCB surface which is

thermally connected to a copper plane.

Table 5. Thermal Resistance

Package Type θJA θJC Unit

5 mm × 5 mm, 32-Lead LFCSP 45 7 °C/W

Maximum Power Dissipation

The maximum safe power dissipation in the AD8143 package is

limited by the associated rise in junction temperature (TJ) on

the die. At approximately 150°C, which is the glass transition

temperature, the plastic changes its properties. Even temporarily

exceeding this temperature limit can change the stresses that the

package exerts on the die, permanently shifting the parametric

performance of the AD8143. Exceeding a junction temperature

of 150°C for an extended period can result in changes in the

silicon devices potentially causing failure.

The power dissipated in the package (PD) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive for all outputs. The quiescent

power is the voltage between the supply pins (VS) times the

quiescent current (IS). The power dissipated due to the load

drive depends upon the particular application. For each output,

the power due to load drive is calculated by multiplying the load

current by the associated voltage drop across the device. The

power dissipated due to all of the loads is equal to the sum of

the power dissipation due to each individual load. RMS voltages

and currents must be used in these calculations.

Airflow increases heat dissipation, effectively reducing θJA. In

addition, more metal directly in contact with the package leads

from metal traces, through-holes, ground, and power planes

reduces the θJA. The exposed paddle on the underside of the

package must be soldered to a pad on the PCB surface which is

thermally connected to a copper plane to achieve the specified θJA.

Figure 2 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the 32-lead LFCSP

(45°C/W) on a JEDEC standard 4-layer board with the underside

paddle soldered to a pad which is thermally connected to a PCB

plane. Extra thermal relief is required for operation at high

supply voltages. See the Applications section for details. θJA

values are approximations.

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

–40–200 20406080

AMBIENT TEMPERATURE (°C)

MAXIMUM POWER DISSIPATION (W)

05538-056

Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

AD8143

Rev. 0 | Page 10 of 24

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REF_G

GND

IN+_G

FB_G

REF_R

IN–_G

GND

FB_R

OUT_B

GND

OUT_R

OUT_G

COMPB_IN+

S+

GND

COMPB_IN–

IN–_B

GND

FB_B

IN+_B

DIS/PD

REF_B

GND

S–

IN+_R

GND

COMPA_IN+

IN–_R

COMPA_OUT

COMPA_IN–

GND

COMPB_OUT

AD8143

TOP VIEW

(Not to Scale)

05538-050

32 31 30 29 28 27 26 25

9 10111213141516

Figure 3. 32-Lead LFCSP Pin Configuration

Note exposed pad on underside of device must be connected to ground.

Table 6. 32-Lead LFCSP Pin Function Descriptions

Pin No. Mnemonic Description

1, 8, 9,16, 17, 24, 25, 32 GND Signal Ground and Thermal Plane Connection (See the Applications Section)

2 REF_G Reference Input, Green Channel

3 FB_G Feedback Input, Green Channel

4 IN+_G Noninverting Input, Green Channel

5 IN−_G Inverting Input, Green Channel

6 REF_R Reference Input, Red Channel

7 FB_R Feedback Input, Red Channel

10 IN+_R Noninverting Input, Red Channel

11 IN−_R Inverting Input, Red Channel

12 COMPA_IN+ Positive Input, Comparator A

13 COMPA_IN− Negative Input, Comparator A

14 COMPA_OUT Output, Comparator A

15 COMPB_OUT Output, Comparator B

18 COMPB_IN− Negative Input, Comparator B

19 COMPB_IN+ Positive Input, Comparator B

20 VS+ Positive Power Supply

21 OUT_R Output, Red Channel

22 OUT_G Output, Green Channel

23 OUT_B Output, Blue Channel

26 VS− Negative Power Supply

27 DIS/PD Disable/Power Down

28 REF_B Reference Input, Blue Channel

29 FB_B Feedback Input, Blue Channel

30 IN+_B Noninverting Input, Blue Channel

31 IN−_B Inverting Input, Blue Channel

Exposed Underside Pad GND Signal Ground and Thermal Plane Connection (See the Applications Section)

AD8143

Rev. 0 | Page 11 of 24

TYPICAL PERFORMANCE CHARACTERISTICS

Unless otherwise noted, G = 1, RL = 150 Ω, CL = 2 pF, VS = ±5 V, TA = 25°C. Refer to the circuit in Figure 38.

–71 10 100

05538-002

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–5

–6 VOUT = 0.2V p-p

VS =±5

VS = ±12

VS = +5

Figure 4. Small Signal Frequency Response at Various Power Supplies, G = 1

–11 10 100

05538-003

FREQUENCY (MHz)

GAIN (dB)

0VOUT = 0.2V p-p

VS =±5

VS = ±12

VS = +5

Figure 5. Small Signal Frequency Response at Various Power Supplies, G = 2

–7110100

05538-004

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–5

–6 V

OUT

=0.2Vp-p

=1kΩ

= 150Ω

Figure 6. Small Signal Frequency Response at Various Loads

–71 10 100

05538-005

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–5

–6

=±5

= ±12

= +5

OUT

= 2V p-p

Figure 7. Large Signal Frequency Response at Various Power Supplies, G = 1

–11 10 100

05538-006

FREQUENCY (MHz)

GAIN (dB)

=±5

= ±12

= +5

OUT

= 2V p-p

Figure 8. Large Signal Frequency Response at Various Power Supplies, G = 2

1 10 100

05538-007

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–5

–6

–7

= 1kΩ

= 150Ω

OUT

= 2V p-p

Figure 9. Large Signal Frequency Response at Various Loads

AD8143

Rev. 0 | Page 12 of 24

–511000

05538-013

FREQUENCY (MHz)

GAIN (dB)

10 100

–1

–2

–3

–4 R

= 1kΩ

OUT

= 0.2V p-p

G = 1, C

= 2pF

G = 1, C

= 10pF, R

SNUB

= 40Ω

G = 2, C

= 2pF

G = 2, C

= 10pF, R

SNUB

= 40Ω

Figure 10. Small Signal Frequency Response at Various Gains and 10 pF

Capacitive Load Buffered by 40 Ω Resistor

–71 10 100

05538-009

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–5

–6 V

OUT

= 0.2V p-p

G = 1

G = 2

Figure 11. Small Signal Frequency Response at Various Gains

0.5

–0.51 100

05538-010

FREQUENCY (MHz)

GAIN (dB)

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

= 150Ω, V

OUT

= 0.2V p-p

= 150Ω, V

OUT

= 2V p-p

= 1kΩ, V

OUT

= 0.2V p-p

= 1kΩ, V

OUT

= 2V p-p

Figure 12. 0.1 dB Flatness for Various Loads and Output Amplitudes

–511000

05538-014

FREQUENCY (MHz)

GAIN (dB)

10 100

–1

–2

–3

–4

G = 1, C

= 2pF

G = 1, C

= 10pF, R

SNUB

= 40Ω

G = 2, C

= 2pF

G = 2, C

= 10pF, R

SNUB

= 40Ω

= 1kΩ

OUT

= 2V p-p

Figure 13. Large Signal Frequency Response at Various Gains and 10 pF

Capacitive Load Buffered by 40 Ω Resistor

–71 10 100

05538-012

FREQUENCY (MHz)

GAIN (dB)

–1

–2

–3

–4

–5

–6

G = 1

G = 2

OUT

= 2V p-p

Figure 14. Large Signal Frequency Response at Various Gains

–10

0.001 1000

05538-016

FREQUENCY (MHz)

OPEN LOOP-GAIN (dB)

0.01 0.1 1 10 100

–180

OPEN LOOP-PHASE (Degrees)

–20

–60

–40

–80

–100

–120

–140

–160

MAGNITUDE

PHASE

Figure 15. Open-Loop Gain and Phase Responses

AD8143

Rev. 0 | Page 13 of 24

100

0.1 1000

05538-020

FREQUENCY (MHz)

COMMON-MODE REJECTION (dB)

1 10 100

±5V

±12V

+5V

Figure 16. Common-Mode Rejection Ratio vs. Frequency at Various Supplies

200

–2000 100

05538-015

TIME (ns)

VOLTAGE (mV)

150

100

–50

–100

–150

10 20 30 40 50 60 70 80 90

OUT

= 0.2V p-p

G = 1, R

= 150

G = 1, R

= 1k

G = 2, R

= 150

G = 2, R

= 1k

Figure 17. Small Signal Transient Response at Various Gains and Loads

200

–2000100

05538-017

TIME (ns)

OUTPUT VOLTAGE (mV)

150

100

–50

–100

–150

10 20 30 40 50 60 70 80 90

= 1k

OUT

= 0.2V p-p

G = 2, C

= 2pF

G = 2, C

= 10pF, R

SNUB

= 40

G = 1, C

= 2pF

G = 1, C

= 10pF, R

SNUB

= 40

Figure 18. Small Signal Transient Response at Various Gains and 10 pF

Capacitive Load Buffered by 40 Ω Resistor

100

0.00001 10

05538-021

FREQUENCY (MHz)

INPUT VOLTAGE NOISE (nV/

√

Hz)

0.0001 0.001 0.01 0.1 1

= ±12V

Figure 19. Input Referred Voltage Noise vs. Frequency

1.5

–1.50 100

05538-018

TIME (ns)

VOLTAGE (V)

1.0

0.5

–0.5

–1.0

10 20 30 40 50 60 70 80 90

OUT

= 2V p-p

G = 1, R

= 150

G = 1, R

= 1k

G = 2, R

= 150

G = 2, R

= 1k

Figure 20. Large Signal Transient Response at Various Gains and Loads

1.5

–1.50100

05538-019

TIME (ns)

OUTPUT VOLTAGE (dB)

1.0

0.5

–0.5

–1.0

10 20 30 40 50 60 70 80 90

G = 2, C

= 2pF

G = 2, C

= 10pF, R

SNUB

= 40

G = 1, C

= 2pF

G=1,C

= 10pF, R

SNUB

=40

= 1k

OUT

= 2V p-p

Figure 21. Large Signal Transient Response at Various Gains and 10 pF

Capacitive Load Buffered by 40 Ω Resistor

AD8143

Rev. 0 | Page 14 of 24

1.25

–1.250 100

05538-027

TIME (ns)

VOLTAGE (V)

1.00

0.75

0.50

0.25

–0.25

–0.50

–0.75

–1.00

0.5

–0.5

ERROR (%)

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

10 20 30 40 50 60 70 80 90

INPUT

OUTPUT

ERROR

Figure 22. Settling Time (0.1%) at Various Loads

–

–80

0.1 100

05538-047

FREQUENCY (MHz)

DISTORTION (dBc)

110

–55

–60

–65

–70

–75

= ±5V

= ±12V

Figure 23. Second Harmonic Distortion vs. Frequency and Power Supplies,

VO = 2 V p-p, G = 2

–50

–75

0.1 100

05538-048

FREQUENCY (MHz)

DISTORTION (dBc)

110

–55

–60

–65

–70 V

= ±5V

= ±12V

Figure 24. Second Harmonic Distortion vs. Frequency and Power Supplies,

VO = 2 V p-p

1400

00 4.5

05538-023

OUTPUT VOLTAGE (V p-p)

SLEW RATE (V/

1200

1000

800

600

400

200

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

+SR, R

= 150

–SR, R

= 150

+SR, R

= 1k

–SR, R

= 1k

Figure 25. Slew Rate vs. Input Voltage Swing at Various Loads

–30

–100

0.1 100

05538-055

FREQUENCY (MHz)

DISTORTION (dBc)

110

–40

–50

–60

–70

–80

–90

Vs = ±12V Vs = ±5V

Figure 26. Third Harmonic Distortion vs. Frequency and Power Supplies,

VO = 2 V p-p, G = 2

–

–90

0.1 100

05538-049

FREQUENCY (MHz)

DISTORTION (dBc)

110

–40

–50

–60

–70

–80 V

=±5V

= ±12V

Figure 27. Third Harmonic Distortion vs. Frequency and Power Supplies,

VO = 2 V p-p

AD8143

Rev. 0 | Page 15 of 24

38–5 5

05538-022

DIFFERENTIAL INPUT VOLTAGE (V)

SUPPLY CURRENT (mA)

–4–3–2–101234

= ±12V

∞

–

Figure 28. Power Supply Current vs. Differential Input Voltage at ±12 V Supplies

–50 100

05538-031

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

–40–30–20–100 102030405060708090

= ∞I

+, V

= ±12V

–, V

= ±12V

+, V

= ±5V

–, V

= ±5V

Figure 29. Power Supply Current vs. Temperature

–100

0.01 1000

05538-046

FREQUENCY (MHz)

PSRR (dB)

0.1 1 10 100

–10

–20

–30

–40

–50

–60

–70

–80

–90

= ±5V

= ±12V

= +5V

Figure 30. Positive Power Supply Rejection Ratio vs. Frequency

–4

–3

–2

–1

–5 5

05538-026

DIFFERENTIAL INPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

–4–3–2–1 01234

Figure 31. Differential Input Operating Range

25512

05538-024

SUPPLY VOLTAGE (±V

)

SUPPLY CURRENT (mA)

67891011

–

= ∞

Figure 32. Power Supply Current vs. Power Supply Voltage

–100

0.01 1000

05538-045

FREQUENCY (MHz)

PSRR (dB)

0.1 1 10 100

–90

–80

–70

–60

–50

–40

–20

–30

–10 V

= ±5V

= ±12V

Figure 33. Negative Power Supply Rejection Ratio vs. Frequency

AD8143

Rev. 0 | Page 16 of 24

–150 1000

05538-025

OUTPUT LOAD (

)

OUTPUT VOLTAGE (V)

–5

–10

100 200 300 400 500 600 700 800 900

SAT

_±5V

–V

SAT

_±5V

–V

SAT

_±12V

SAT

_±12V

G = +2 (R

= R

= 499

) AND V

=±5V

G = +5 (R

= 8.06k

= 2k

) AND V

= ±12V

Figure 34. Output Saturation Voltage vs. Output Load

–60 1000

05538-029

TIME (ns)

VOLTAGE (V)

–1

–2

–3

–4

–5

100 200 300 400 500 600 700 800 900

2× V

OUTPUT

G = 2

Figure 35. Output Overdrive Recovery

4.0

–25 25

05538-032

(mV)

OUT

(V)

–20 –10 –5 0 5 10 15 20

3.5

3.0

2.5

2.0

1.5

1.0

0.5

–15

= ±12V

= ±5V

Figure 36. Comparator Hysteresis

AD8143

Rev. 0 | Page 17 of 24

THEORY OF OPERATION

The AD8143 amplifiers use an architecture called active

feedback, which differs from that of conventional op amps. The

most obvious differentiating feature is the presence of two

separate pairs of differential inputs compared to a conventional

op amp’s single pair. Typically, for the active-feedback architecture,

one of these input pairs is driven by a differential input signal,

while the other is used for the feedback. This active stage in the

feedback path is where the term active feedback is derived.

The active feedback architecture offers several advantages over a

conventional op amp in several types of applications. Among

these are excellent common-mode rejection, wide input common-

mode range, and a pair of inputs that are high impedance and

completely balanced in a typical application. In addition, while

an external feedback network establishes the gain response as in

a conventional op amp, its separate path makes it entirely

independent of the signal input. This eliminates any interaction

between the feedback and input circuits, which traditionally

causes problems with CMRR in conventional differential-input

op amp circuits.

Another advantage of active feedback is the ability to change the

polarity of the gain merely by switching the differential inputs.

A high input impedance inverting amplifier can therefore be

made. Besides high input impedance, a unity-gain inverter with

the AD8143 has noise gain of unity, producing lower output

noise and higher bandwidth than op amps that have noise gain

equal to 2 for a unity-gain inverter.

The two differential input stages of the AD8143 are each

transconductance stages that are well-matched. These stages

convert the respective differential input voltages to internal

currents. The currents are then summed and converted to a

voltage, which is buffered to drive the output. The compensation

capacitor is included in the summing circuit. When the

feedback path is closed around the part, the output drives

the feedback input to that voltage which causes the internal

currents to sum to zero. This occurs when the two differential

inputs are equal and opposite; that is, their algebraic sum is zero.

In a closed-loop application, a conventional op amp has its

differential input voltage driven to near zero under non-

transient conditions. The AD8143 generally has differential

input voltages at each of its input pairs, even under equilibrium

conditions. As a practical consideration, it is necessary to

internally limit the differential input voltage with a clamp

circuit. Thus, the input dynamic ranges are limited to about

2.5 V for the AD8143 (see Specifications section for more

detail). For this and other reasons, it is not recommended to

reverse the input and feedback stages of the AD8143, even

though some apparently normal functionality may be observed

under some conditions.

AD8143

Rev. 0 | Page 18 of 24

APPLICATIONS

OVERVIEW

The AD8143 contains three independent active-feedback

amplifiers that can be effectively applied as differential line

receivers for red-green-blue (RGB) signals or component video,

such as YPbPr, signals transmitted over unshielded-twisted-pair

(UTP) cable. The AD8143 also contains two general-purpose

comparators with hysteresis that can be used to receive digital

signals or to extract video synchronization pulses from received

common-mode signals that contain encoded synchronization

signals.

An internal linear voltage regulator derives power for the

comparators from the positive supply; therefore, the AD8143

must always have a minimum positive supply voltage of 4.5 V.

The AD8143 includes a power-down feature that can be

asserted to reduce the supply current when a particular device

is not in use.

BASIC CLOSED-LOOP GAIN CONFIGURATIONS

As described in the Theory of Operation section, placing a

resistive feedback network between an amplifier output and its

respective feedback amplifier input creates a stable negative

feedback amplifier. It is important to note that the closed-loop

gain of the amplifier used in the signal path is defined as the

amplifier’s single-ended output voltage divided by its differential

input voltage. Therefore, each amplifier in the AD8143 provides

differential-to-single-ended gain. Additionally, the amplifier

used for feedback has two high impedance inputs—the FB

input, where the negative feedback is applied, and the REF

input, which can be used as an independent single-ended

input to apply a dc offset to the output signal. Some basic

gain configurations implemented with an AD8143 amplifier

are shown in Figure 37 through Figure 39.

–

+5V

–5V

REF

0.01μF

OUT

05538-038

Figure 37. Basic Gain Circuit: VOUT = (VIN + VREF)(1 + RF/RG)

The gain equation for the circuit in Figure 37 is

VOUT = (VIN + VREF)(1 + RF/RG) (1)

In this configuration, the voltage applied to the REF pin appears

at the output with a gain of 1 + RF/RG.

To achieve unity gain from V REF to VOUT in this configuration,

divide VREF by the same factor used in the feedback loop; the

same RF and RG values can be used. Figure 38 illustrates this

approach.

–

+5V

–5V

REF

0.01μF

OUT

05538-039

Figure 38. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) + VREF

The gain equation for the circuit in Figure 38 is

VOUT = VIN (1 + RF/RG) + VREF (2)

Another configuration that provides the same gain equation as

Equation 2 is shown in Figure 39. In this configuration, it is

important to keep the source resistance of VREF much smaller

than RG to avoid gain errors.

–

+5V

–5V

REF

0.01μF

OUT

05538-040

REF

Figure 39. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) + VREF

For stability reasons, the inductance of the trace connected to

the REF pin must be kept to less than 10 nH. The typical

inductance of 50 Ω traces on the outer layers of the FR-4 boards

is 7 nH/in, and on the inner layers, it is typically 9 nH/in. Vias

must be accounted for as well. The inductance of a typical via in

a 0.062-inch board is on the order of 1.5 nH. If longer traces are

required, a 200 Ω resistor should be placed in series with the

trace to reduce the Q-factor of the inductance.

AD8143

Rev. 0 | Page 19 of 24

In many dual-supply applications, VREF can be directly

connected to ground right at the device.

TERMINATING THE INPUT

One of the key benefits of the active-feedback architecture is the

separation that exists between the differential input signal and

the feedback network. Because of this separation, the differential

input maintains its high CMRR and provides high differential

and common-mode input impedances, making line termination

a simple task.

Most applications that use the AD8143 involve transmitting

broadband video signals over 100 Ω UTP cable and use

dc-coupled terminations. The two most common types of

dc-coupled terminations are differential and common-mode.

Differential termination of 100 Ω UTP is implemented by

simply connecting a 100 Ω resistor across the amplifier input,

as shown in Figure 40.

–

+5V

–5V

REF

RGRF

0.01μF

–VIN

VOUT

05538-041

100Ω

UTP 100Ω

Figure 40. Differential-Mode Termination

Some applications require common-mode terminations for

common-mode currents generated at the transmitter. In these

cases, the 100 Ω termination resistor is split into two 50 Ω

resistors. The required common-mode termination voltage is

applied at the tap between the two resistors. In many of these

applications, the common-mode tap is connected to ground

(VTERM (CM) = 0). This scheme is illustrated in Figure 41.

–

+5V

–5V

REF

0.01μF

–V

OUT

TERM

(CM)

05538-042

100Ω

UTP 50Ω

50Ω

Figure 41. Common-Mode Termination

INPUT CLAMPING

The differential input that is assigned to receive the input signal

includes clamping diodes that limit the differential input swing

to approximately 5.5 V p-p at 25°C. Because of this, the input

and feedback stages should never be interchanged. Figure 31

illustrates the clamping action at the signal input stage.

The supply current drawn by the AD8143 has a strong

dependence on input signal magnitude because the input

transconductance stages operate with differential input signals

that can be up to a few volts peak-to-peak. This behavior is

distinctly different from that of traditional op-amps, where the

differential input signal is driven to essentially 0 V by negative

feedback. Figure 28 illustrates the supply current dependence on

input voltage.

For most applications, including receiving RGB video signals,

the input signal magnitudes encountered are well within the

safe operating limits of the AD8143 over its full power supply

and operating temperature ranges. In some extreme applications

where large differential and/or common-mode voltages can be

encountered, external clamping may be necessary. Another

application where external common-mode clamping is

sometimes required is when an unpowered AD8143 receives a

signal from an active driver. In this case, external diodes are

required when the current drawn by the internal ESD diodes

cannot be kept to less than 5 mA.

When using ±12 V supplies, the differential input signal must

be kept to less than 4 V p-p. In applications that use ±12 V

supplies where the input signals are expected to reach or exceed

4 V p-p, external differential clamping at a maximum of 4 V p-p

is required.

Figure 42 shows a general approach to external differential-

mode clamping.

POSITIVE CLAMP NEGATIVE CLAM

OUT

–

05538-051

Figure 42. Differential-Mode Clamping

The positive and negative clamps are nonlinear devices that

exhibit very low impedance when the voltage across them

reaches a critical threshold (clamping voltage), thereby limiting

the voltage across the AD8143 input. The positive clamp has a

positive threshold, and the negative clamp has a negative

threshold.

AD8143

Rev. 0 | Page 20 of 24

A diode is a simple example of such a clamp. Schottky diodes

generally have lower clamping voltages than typical signal

diodes. The clamping voltage should be larger than the largest

expected signal amplitude, with enough margin to ensure that

the received signal passes without being distorted.

A simple way to implement a clamp is to use a number of

diodes in series. The resultant clamping voltage is then the sum

of the clamping voltages of individual diodes.

A 1N4448 diode has a forward voltage of approximately 0.70 V

to 0.75 V at typical current levels that are seen when it is being

used as a clamp, and 2 pF maximum capacitance at 0 V bias.

(The capacitance of a diode decreases as its reverse bias voltage

is increased.) The series connection of two 1N4448 diodes,

therefore, has a clamping voltage of 1.4 V to 1.5 V. Figure 43

shows how to limit the differential input voltage applied to an

AD8143 amplifier to ±1.4 V to ±1.5 V (2.8 V p-p to 3.0 V p-p).

Note that the resulting capacitance of the two series diodes is

half that of one diode. Different numbers of series diodes can be

used to obtain different clamping voltages.

RT is the differential termination resistor and the series

resistances, RS, limit the current into the diodes. The series

resistors should be highly matched in value to preserve high

frequency CMRR.

POSITIVE CLAMP NEGATIVE CLAMP

–

05538-052

OUT

–

Figure 43. Using Two 1N4448 Diodes in Series as a Clamp

There are many other nonlinear devices that can be used as

clamps. The best choice for a particular application depends

upon the desired clamping voltage, response time, parasitic

capacitance, and other factors.

When using external differential-mode clamping, it is

important to ensure that the series resistors (RS), the sum of

the parasitic capacitance of the clamping devices, and the input

capacitance of the AD8143 are small enough to preserve the

desired signal bandwidth.

Figure 44 shows a specific example of external common-mode

clamping.

05538-044

–V

OUT

V+

V–

–

HBAT-540C

Figure 44. External Common-Mode Clamping

The series resistances, RS, limit the current in each leg,

and the Schottky diodes limit the voltages on each input to

approximately 0.3 V to 0.4 V over the positive power supply,

V+ and to 0.3 V to 0.4 V below the negative power supply, V−.

The maximum value of RS is determined by the required signal

bandwidth, the line impedance, and the effective differential

capacitance due to the AD8143 inputs and the diodes.

As with the differential clamp, the series resistors should be

highly matched in value to preserve high frequency CMRR.

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

The two most important issues with regard to printed circuit

board (PCB) layout are minimizing parasitic signal trace

reactances in the feedback network and providing sufficient

thermal relief.

Excessive parasitic reactances in the feedback network cause

excessive peaking in the amplifier’s frequency response and

excessive overshoot in its step response due to a reduction in

phase margin. Oscillation occurs when these parasitic

reactances are increased to a critical point where the phase

margin is reduced to zero. Minimizing these reactances is

important to obtain optimal performance from the AD8143.

When operating at ±12 V power, it is important to pay special

attention to removing heat from the AD8143.

Besides the special layout considerations previously mentioned

and expounded upon in the following sections, general high

speed layout practices must be adhered to when applying the

AD8143. Controlled impedance transmission lines are required

for incoming and outgoing signals, referenced to a ground plane.

AD8143

Rev. 0 | Page 21 of 24

Typically, the input signals are received over 100 Ω differential

transmission lines. A 100 Ω differential transmission line is

readily realized on the printed circuit board using two well-

matched, closely-spaced 50 Ω single-ended traces that are

coupled through the ground plane. The traces that carry the

single-ended output signals are most often 75 Ω for video

signals. Output signal connections should include series

termination resistors that are matched to the impedance

of the line they are driving.

Broadband power supply decoupling networks should be placed

as close as possible to the supply pins. Small surface-mount

ceramic capacitors are recommended for these networks, and

tantalum capacitors are recommended for bulk supply

decoupling.

Minimizing Parasitic Reactances in the Feedback Network

Parasitic trace capacitance and inductance are both reduced

when the traces that connect the feedback network together are

reduced in length. Removing the copper from all planes below

the traces reduces trace capacitance, but increases trace inductance

because the loop area formed by the trace and ground plane is

increased. A reasonable compromise that works well is to void

all copper directly under the feedback loop traces and component

pads with margins on each side approximately equal to one

trace width. Combining this technique with minimizing trace

lengths is effective in keeping parasitic trace reactances in the

feedback loop to a minimum. Additionally, all components used

in the feedback network should be in 0402 surface-mount

packages. Figure 45 illustrates the magnified view of a proven

feedback network layout that provides excellent performance. Note

that the internal layers are not shown.

It is strongly recommended that the layout shown in Figure 45,

or something very similar, be used for the three AD8143

feedback networks.

A conservative estimate for feedback-loop trace capacitance in

each loop of the layout shown in Figure 45 is 2 pF. This value is

viewed as the minimum load capacitance and is reflected in the

frequency response and transient response plots.

Maximizing Heat Removal

The AD8143 pinout includes ground connections on its corner

pins to facilitate heat removal. These pins should be connected

to the exposed paddle on the underside of the AD8143 and to a

ground plane on the component side of the board. Additionally,

a 5 × 5 array of thermal vias connecting the exposed paddle to

internal ground planes should be placed inside the PCB pad

that is soldered to the exposed paddle. Using these techniques

is highly recommended in all applications, and is required in

±12 V applications where power dissipation is the greatest.

Figure 45 illustrates how to optimize the circuit board layout

for heat removal.

Designs must often conform to design-for-manufacturing

(DFM) rules that stipulate how to lay out PCBs in such a way

as to facilitate the manufacturing process. Some of these rules

require thermal relief on pads that connect to planes, and the

rules may preclude the use of the technique illustrated in Figure 45.

In these cases, the ground pins should be connected to the exposed

paddle and component-side ground plane using techniques that

conform to the DFM requirements.

GND

GND C

= CIRCUIT SIDE

= COMPONENT SIDE

05538-043

Figure 45. Recommended Layout for Feedback Loops and Grounding

AD8143

Rev. 0 | Page 22 of 24

DRIVING A CAPACITIVE LOAD

The AD8143 typically drives either high impedance loads,

such as crosspoint switch inputs, or doubly terminated coaxial

cables. A gain of 1 is commonly used in the high impedance

case because the 6 dB transmission line termination loss is not

incurred. A gain of 2 is required when driving cables to

compensate for the 6 dB termination loss.

In all cases, the output must drive the parasitic capacitance

of the feedback loop, conservatively estimated to be 2 pF, in

addition to the capacitance presented by the actual load. When

driving a high impedance input, it is recommended that a small

series resistor be used to buffer the input capacitance of the

device being driven. Clearly, the resistor value must be small

enough to preserve the required bandwidth. In the ideal doubly

terminated cable case, the AD8143 output sees a purely resistive

load. In reality, there is some residual capacitance, and this is

buffered by the series termination resistor. Figure 46 illustrates

the high impedance case, and Figure 47 illustrates the cable-

driving case.

05538-053

–

0.01μF

+5V

–5V

REF

Figure 46. Buffering the Input Capacitance of a High-Z Load

05538-054

RGRF

–

0.01μF

+5V

–5V

REF

VIN

Figure 47. Driving a Doubly Terminated Cable

Small and large signal frequency responses for the High-Z case

with a 40 Ω series resistor and 10 pF load capacitance are shown

in Figure 10 and Figure 13; transient responses for the same

conditions are shown in Figure 18 and Figure 21. In the cable

driving case shown in Figure 47, CS << 2 pF for a well-designed

circuit; therefore, the feedback loop capacitance is the dominant

capacitive load. The feedback loop capacitance is present for all

cases, and its effect is included in the data presented in the

Typical Performance Characteristics and Specifications tables.

POWER-DOWN

The power-down feature is intended to be used to reduce power

consumption when a particular device is not in use, and does

not place the output in a High-Z state when asserted. The

power-down feature is asserted when the voltage applied to the

power-down pin drops to approximately 2 V below the positive

supply. The AD8143 is enabled by pulling the power-down pin

to the positive supply.

COMPARATORS

In addition to general-purpose applications, the two on-chip

comparators can be used to receive differential digital information

or to decode video sync pulses from received common-mode

voltages. Built-in hysteresis helps to eliminate false triggers

from noise.

The comparator outputs are not designed to drive transmission

lines. When the signals detected by the comparators are driven

over cables or controlled impedance printed circuit board

traces, the comparator outputs must be fed to a spare logic gate,

FPGA, or other device that is capable of driving signals over

transmission lines.

An internal linear voltage regulator derives power for the

comparators from the positive supply; therefore, the AD8143

must always have a minimum positive supply voltage of 4.5 V.

SYNC PULSE EXTRACTION USING COMPARATORS

The AD8143 is particularly useful in keyboard video mouse

(KVM) applications. KVM networks transmit and receive

computer video signals, which are typically comprised of red,

green, and blue (RGB) video signals and separate horizontal

and vertical sync signals. Because the sync signals are separate

and not embedded in the color signals, it is advantageous to

transmit them using a simple scheme that encodes them among

the three common-mode voltages of the RGB signals. The

AD8134 triple differential driver is a natural complement to the

AD8143 and performs the sync pulse encoding with the

necessary circuitry on-chip.

AD8143

Rev. 0 | Page 23 of 24

where:

The AD8134 encoding equations are given in Equation 3,

Equation 4, and Equation 5.

[]

(3)

Red VCM, Green VCM, and Blue VCM are the transmitted common-

mode voltages of the respective color signals.

VRed CM −= 2

[

2−= K

VGreen CM

]

(4)

K is a an adjustable gain constant that is set by the AD8134.

[

VBlue CM += 2

]

(5)

V and H are the vertical and horizontal sync pulses, defined

with a weight of −1 when the pulses are in their low states, and a

weight of +1 when they are in their high states.

The AD8134 data sheet contains further details regarding the

encoding scheme.

Figure 48 illustrates how the AD8143 comparators can be used

to extract the horizontal and vertical sync pulses that are

encoded on the RGB common-mode voltages by the AD8134.

05538-057

RECEIVED RED VIDEO HSYNC

RED CMV

GREEN CMV

BLUE CMV

50Ω

1kΩ

VSYNC

RECEIVED GREEN VIDEO

50Ω

RECEIVED BLUE VIDEO

50Ω

Figure 48. Extracting Sync Signals from Received Common-Mode Signals

AD8143

Rev. 0 | Page 24 of 24

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

0.30

0.23

0.18

0.20 REF

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

12° MAX

1.00

0.85

0.80 SEATING

PLANE

COPLANARITY

0.08

0.50

0.40

0.30

3.50 REF

0.50

BSC

PIN 1

INDICATOR TOP

VIEW

5.00

BSC SQ

4.75

BSC SQ 3.45

3.30 SQ

3.15

PIN 1

INDICATOR

0.60 MAX

0.25 MIN

EXPOSED

PAD

(BOTTOM VIEW)

Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad

(CP-32-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD8143ACPZ-R21–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-3

AD8143ACPZ-REEL1–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-3

AD8143ACPZ-REEL71–40°C to +85°C 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-32-3

1 Z = Pb-free part.

registered trademarks are the property of their respective owners.

D05538–0–10/05(0)