MAX21002 Ultra-Accurate, Low Power,
Dual-Axis Digital Output Gyroscope
www.maximintegrated.com Maxim Integrated
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The slave address of the IC is b101100X, which is 7 bits
long. The LSb of the 7-bit address is determined by the
logic level on pin SA0. This allows two MAX21002s to be
connected on the same I2C bus. When used in this con-
figuration, the address of one of the two devices should
beb1011000(pinSA0_SD0is settologic-low)andthe
addressoftheothershouldbeb1011001(pinSA0_SD0
is set to logic-high).
SPI Interface
TheIC’sSPIcanoperateupto20MHz,inboth3-wires
(half duplex) and 4-wires mode (full duplex).
ItisrecommendedtosettheI2C_DISABLEbitataddress
0x15 if the IC is used together with other SPI devices to
avoid the possibility to switch inadvertently into I2C mode
when traffic is detected with the CS unasserted.
The IC operates as an SPI slave device. Both the read
register and write register commands are completed in 16
clock pulses, or in multiples of 8 in case of multiple read/
write bytes. Bit duration is the time between two falling
edgesofCLK.
Thefirstbit(bit0)startsatthefirstfallingedgeofCLK
after the falling edge of CS while the last bit (bit 15, bit 23,
etc.)startsatthelastfallingedgeofCLKjustbeforethe
rising edge of CS.
Bit 0: RWbit.When0,thedataDI[7:0]iswrittentothe
IC.When1,thedataDO[7:0]fromthedeviceisread.In
the latter case, the chip drives SDO at the start of bit 8.
Bit 1: MS bit. Depending on the configuration of
IF_PARITY,this bit can eitherbe used to operate in
multi-addressing standard mode or to check the parity
with the register address.
If used as MS bit, when 1, the address remains
unchanged in multiple read/write commands. When 0,
the address is autoincremented in multiple read/write
commands.
Bits 2–7:AddressAD[5:0].Thisistheaddressfieldof
the indexed register.
Bits 8–15:DataDI[7:0](writemode).Thisisthedata
that is written to the device (MSb first).
Bits 8–15:DataDO[7:0](readmode).Thisisthedata
that is read from the device (MSb first).
SPI Half- and Full-Duplex Operation
The IC can be programmed to operate in half-duplex (a
bidirectional data pin) or full-duplex (one data-in and one
data-out pin) mode. The SPI master sets a register bit called
SPI_3_WIRE into ITF_OTP to 0 for full-duplex, and 1 for
half-duplex operation. Full duplex is the power-on default.
Full-Duplex Operation
The IC is put into full-duplex mode at power-up, or when
the SPI master clears the SPI_3_WIRE bit, the SPI
interface uses separate data pins, MOSI and MISO to
transfer data. Because of the separate data pins, bits can
be simultaneously clocked into and out of the IC. The IC
makes use of this feature by clocking out 8 output data
bits as the command byte is clocked in.
Reading from the SPI Slave Interface (MOSI)
The SPI master reads data from the IC slave interface
using the following steps:
1) When CS is high, the IC is unselected and three-states
the MISO output.
2)After driving SCL_CLK to its inactive state, the SPI
master selects the IC by driving CS low.
3) The SPI master simultaneously clocks the command
byte into the IC. The SPI Read command is performed
with 16 clock pulses. Multiple byte read command is
performed adding blocks of 8 clock pulses at the previ-
ous one.
Bit 0: READbit.Thevalueis1.
Bit 1: MS bit. When 1, do not increment address.
When 0, increment address in multiple reading.
Bits 2–7:AddressAD[5:0].Thisistheaddressfieldof
the indexed register.
Bits 8–15:DataDO[7:0](readmode).Thisisthedata
that is read from the device (MSb first).
Bits 16–... : Data DO[...–8]. Further data in multiple
byte reading.
4) After 16 clock cycles, the master can drive CS high to
deselect the IC, causing it to three-state its MISO out-
put. The falling edge of the clock puts the MSB of the
next data byte in the sequence on the MISO output.
5) By keeping CS low, the master clocks register data
bytesoutoftheICbycontinuingtosupplySCL_CLK
pulses (burst mode). The master terminates the trans-
fer by driving CS high. The master must ensure that
SCL_CLKisinitsinactivestateatthebeginningofthe
next access (when it drives CS low).
Writing to the SPI Slave Interface (MOSI)
The SPI master writes data to the IC slave interface
through the following steps:
1) The SPI master sets the clock to its inactive state.
When CS is high, the master can drive the MOSI input.
2) The SPI master selects the IC by driving CS low.