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FEATURES
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
GND
VCC
SDA
SCL
INT
P7
P6
P5
P4
DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
INT
SCL
NC
SDA
VCC
A0
A1
NC
A2
P0
P7
P6
NC
P5
P4
GND
P3
NC
P2
P1
DGV OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
RGY PACKAGE
(TOP VIEW)
1 20
10 11
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
P6
NC
P5
P4
GND
P3
NC
P2
SCL
NC
SDA
VCC
A0
A1
NC
A2
INT
P1 P7
P0
NC − No internal connection
DESCRIPTION/ORDERING INFORMATION
PCF8574AREMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
•Low Standby-Current Consumption of •Compatible With Most Microcontrollers10 µA Max
•Latched Outputs With High-Current Drive•I
2
C to Parallel-Port Expander Capability for Directly Driving LEDs•Open-Drain Interrupt Output •Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
This 8-bit input/output (I/O) expander for the two-line bidirectional bus (I
2
C) is designed for 2.5-V to 6-V V
CCoperation.
The PCF8574A provides general-purpose remote I/O expansion for most microcontroller families via the I
2
Cinterface [serial clock (SCL), serial data (SDA)].
The device features an 8-bit quasi-bidirectional I/O port (P0–P7), including latched outputs with high-current drivecapability for directly driving LEDs. Each quasi-bidirectional I/O can be used as an input or output without the useof a data-direction control signal. At power on, the I/Os are high. In this mode, only a current source to V
CC
isactive. An additional strong pullup to V
CC
allows fast rising edges into heavily loaded outputs. This device turnson when an output is written high and is switched off by the negative edge of SCL. The I/Os should be highbefore being used as inputs.
ORDERING INFORMATION
T
A
PACKAGE
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
QFN – RGY Tape and reel PCF8574ARGYR PF574APDIP – N Tube PCF8574AN PCF8574ANTube PCF8574ADW–40 °C to 85 °C SOIC – DW PCF8574ATape and reel PCF8574ADWRTSSOP – PW Tape and reel PCF8574APWR PF574ATVSOP – DGV Tape and reel PCF8574ADGVR PF574A
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available atwww.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2005, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DESCRIPTION/ORDERING INFORMATION (CONTINUED)
14
I/O
Port
4
5
6
7
9
10
11
12
P0
P1
P2
P3
P4
P5
P6
P7
Shift
Register 8 Bit
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset
Read Pulse
Write Pulse
PCF8574A
3
2
1
13
16
8
GND
VCC
SDA
SCL
A2
A1
A0
INT
Pin numbers shown are for the DW and N packages.
I2C Bus
Control
PCF8574A
REMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
The PCF8574A provides an open-drain output ( INT) that can be connected to the interrupt input of amicrocontroller. An interrupt is generated by any rising or falling edge of the port inputs in the input mode. Aftertime, t
iv
, INT is valid. Resetting and reactivating the interrupt circuit is achieved when data on the port is changedto the original setting or data is read from, or written to, the port that generated the interrupt. Resetting occurs inthe read mode at the acknowledge bit after the rising edge of the SCL signal, or in the write mode at theacknowledge bit after the high-to-low transition of the SCL signal. Interrupts that occur during the acknowledgeclock pulse can be lost (or be very short) due to the resetting of the interrupt during this pulse. Each change ofthe I/Os after resetting is detected and, after the next rising clock edge, is transmitted as INT. Reading from, orwriting to, another device does not affect the interrupt circuit.
By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming dataon its ports without having to communicate via the I
2
C bus. Therefore, the PCF8574A can remain a simple slavedevice.
LOGIC DIAGRAM (POSITIVE LOGIC)
2
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To Interrupt
Logic
P0 to P7
VCC
GND
CIS
D Q
FF
CIS
D Q
FF
Write Pulse
Data From
Shift Register
Power-On
Reset
Read Pulse
Data To
Shift Register
100 µA
I
2
C Interface
PCF8574AREMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
SIMPLIFIED SCHEMATIC DIAGRAM OF EACH P-PORT INPUT/OUTPUT
I
2
C communication with this device is initiated by a master sending a start condition, a high-to-low transition onthe SDA I/O while the SCL input is high. After the start condition, the device address byte is sent,most-significant bit (MSB) first, including the data direction bit (R/ W). This device does not respond to the generalcall address. After receiving the valid address byte, this device responds with an acknowledge, a low on the SDAI/O during the high of the acknowledge-related clock pulse. The address inputs (A0–A2) of the slave device mustnot be changed between the start and the stop conditions.
The data byte follows the address acknowledge. If the R/ W bit is high, the data from this device are the valuesread from the P port. If the R/ W bit is low, the data are from the master, to be output to the P port. The data byteis followed by an acknowledge sent from this device. If other data bytes are sent from the master, following theacknowledge, they are ignored by this device. Data are output only if complete bytes are received andacknowledged. The output data will be valid at time, t
pv
, after the low-to-high transition of SCL and during theclock cycle for the acknowledge.
A stop condition, a low-to-high transition on the SDA I/O while the SCL input is high, is sent by the master.
Interface Definition
BITBYTE
7 (MSB) 6 5 4 3 2 1 0 (LSB)
I
2
C slave address L H H H A2 A1 AO R/ WI/O data bus P7 P6 P5 P4 P3 P2 P1 P0
3
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Absolute Maximum Ratings
(1)
Recommended Operating Conditions
PCF8574A
REMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
Address Reference
INPUTS
I
2
C BUS SLAVE ADDRESSA2 A1 A0
L L L 56 (decimal), 38 (hexadecimal)L L H 57 (decimal), 39 (hexadecimal)L H L 58 (decimal), 3A (hexadecimal)L H H 59 (decimal), 3B (hexadecimal)H L L 60 (decimal), 3C (hexadecimal)H L H 61 (decimal), 3D (hexadecimal)H H L 62 (decimal), 3E (hexadecimal)H H H 63 (decimal), 3F (hexadecimal)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
V
CC
Supply voltage range –0.5 7 VV
I
Input voltage range
(2)
–0.5 V
CC
+ 0.5 VV
O
Output voltage range
(2)
–0.5 V
CC
+ 0.5 VI
IK
Input clamp current V
I
< 0 –20 mAI
OK
Output clamp current V
O
< 0 –20 mAI
OK
Input/output clamp current V
O
< 0 or V
O
> V
CC
±400 µAI
OL
Continuous output low current V
O
= 0 to V
CC
50 mAI
OH
Continuous output high current V
O
= 0 to V
CC
–4 mAContinuous current through V
CC
or GND ±100 mADGV package
(3)
92DW package
(3)
57θ
JA
Package thermal impedance N package
(3)
67 °C/WPW package
(3)
83RGY package
(4)
37T
stg
Storage temperature range –65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operatingconditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.(3) The package thermal impedance is calculated in accordance with JESD 51-7.(4) The package thermal impedance is calculated in accordance with JESD 51-5.
MIN MAX UNIT
V
CC
Supply voltage 2.5 6 VV
IH
High-level input voltage 0.7 ×V
CC
V
CC
+ 0.5 VV
IL
Low-level input voltage –0.5 0.3 ×V
CC
VI
OH
High-level output current –1 mAI
OL
Low-level output current 25 mAT
A
Operating free-air temperature –40 85 °C
4
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Electrical Characteristics
I
2
C Interface Timing Requirements
PCF8574AREMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP
(1)
MAX UNIT
V
IK
Input diode clamp voltage I
I
= –18 mA 2.5 V to 6 V –1.2 VV
POR
Power-on reset voltage
(2)
V
I
= V
CC
or GND, I
O
= 0 6 V 1.3 2.4 VI
OH
P port V
O
= GND 2.5 V to 6 V 30 300 µAI
OHT
P-port transient pullup current High during acknowledge, V
OH
= GND 2.5 V –1 mASDA V
O
= 0.4 V 2.5 V to 6 V 3I
OL
P port V
O
= 1 V 5 V 10 25 mAINT V
O
= 0.4 V 2.5 V to 6 V 1.6SCL, SDA ±5I
I
INT V
I
= V
CC
or GND 2.5 V to 6 V ±5µAA0, A1, A2 ±5I
IHL
P port V
I
≥V
CC
or V
I
≤GND 2.5 V to 6 V ±400 µAOperating mode V
I
= V
CC
or GND, I
O
= 0, f
SCL
= 100 kHz 40 100I
CC
6 V µAStandby mode V
I
= V
CC
or GND, I
O
= 0 2.5 10C
i
SCL V
I
= V
CC
or GND 2.5 V to 6 V 1.5 7 pFSDA 3 7C
io
V
IO
= V
CC
or GND 2.5 V to 6 V pFP port 4 10
(1) All typical values are at V
CC
= 5 V, T
A
= 25 °C.(2) The power-on reset circuit resets the I
2
C-bus logic with V
CC
< V
POR
and sets all I/Os to logic high (with current source to V
CC
).
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 )
MIN MAX UNIT
f
scl
I
2
C clock frequency 100 kHzt
sch
I
2
C clock high time 4 µst
scl
I
2
C clock low time 4.7 µst
sp
I
2
C spike time 100 nst
sds
I
2
C serial-data setup time 250 nst
sdh
I
2
C serial-data hold time 0 nst
icr
I
2
C input rise time 1 µst
icf
I
2
C input fall time 0.3 µst
ocf
I
2
C output fall time (10-pF to 400-pF bus) 300 nst
buf
I
2
C bus free time between stop and start 4.7 µst
sts
I
2
C start or repeated start condition setup 4.7 µst
sth
I
2
C start or repeated start condition hold 4 µst
sps
I
2
C stop-condition setup 4 µst
vd
Valid-data time SCL low to SDA output valid 3.4 µsC
b
I
2
C bus capacitive load 400 pF
5
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Switching Characteristics
PCF8574A
REMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
over recommended operating free-air temperature range, C
L
≤100 pF (unless otherwise noted) (see Figure 2 )
FROM TOPARAMETER MIN MAX UNIT(INPUT) (OUTPUT)
t
pv
Output data valid SCL P port 4 µst
su
Input data setup time P port SCL 0 µst
h
Input data hold time P port SCL 4 µst
iv
Interrupt valid time P port INT 4 µst
ir
Interrupt reset delay time SCL INT 4 µs
6
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PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
VCC
CL = 10 pF to = 400 pF
tbuf
ticr
tsth tsds
tsdh
ticf
ticr
tscl tsch
tsts
tPHL
tPLH
0.3 × VCC
Stop
Condition
tsps
Repeat
Start
Condition
Start or
Repeat
Start
Condition
SCL
SDA
Start
Condition
(S) Bit 7
(MSB) Bit 6 Bit 0
LSB
(R/W) Acknowledge
(A)
Stop
Condition
(P)
2 Bytes for Complete Device
Programming
LOAD CIRCUIT
VOLTAGE WA VEFORMS
ticf
Stop
Condition
(P)
tsp
DUT Pn
0.7 × VCC
0.3 × VCC
0.7 × VCC
PCF8574AREMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
Figure 1. I
2
C Interface Load Circuit and Voltage Waveforms
7
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A
A
A
A
S 0 1 1 1 A1A2 A0 1 Data 1 1 PData 3
Start
Condition
Acknowledge
From Slave Acknowledge
From Slave
Data From Port Data From PortSlave Address
R/W
87654321
tir
tir
tsps
tiv
Data 1 Data 2 Data 3
INT
Data
Into
Port
B
B
A
A
PnINT
R/W A
tir
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC
0.7 × VCC
0.3 × VCC SCL
View B−BView A−A
tiv
INT
W A 0.7 × VCC
0.3 × VCC
SCL D



tpv
Slave
Acknowledge
Unstable
Data
Last Stable Bit
SDA
Pn
PCF8574A
REMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 2. Interrupt Voltage Waveforms
Figure 3. I
2
C Write Voltage Waveforms
8
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PCF8574AREMOTE 8-BIT I/O EXPANDER FOR I
2
C BUS
SCPS069D – JULY 2001 – REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 4. Load Circuits
9
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PCF8574ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADWE4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ADWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
PCF8574ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
PCF8574APW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574APWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PCF8574ARGYR ACTIVE VQFN RGY 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PCF8574ARGYRG4 ACTIVE VQFN RGY 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 1
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 21-Dec-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
PCF8574ADGVR TVSOP DGV 20 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PCF8574ADWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
PCF8574APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PCF8574ARGYR VQFN RGY 20 3000 330.0 12.4 3.8 4.8 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PCF8574ADGVR TVSOP DGV 20 2000 367.0 367.0 35.0
PCF8574ADWR SOIC DW 16 2000 366.0 364.0 50.0
PCF8574APWR TSSOP PW 20 2000 367.0 367.0 38.0
PCF8574ARGYR VQFN RGY 20 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194