1
TM
File Number 4755.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil and Design is a trademark of Intersil Corporation. |Copyright © Intersil Corporation 2000
FSTYC9055D, FSTYC9055R
Radiation Hardened, SEGR Resistant
P-Channel Power MOSFETs
The Discrete Products Operation of Intersil has developed a
series of Radiation Hardened MOSFETs specifically
designed for commercial and military space applications.
Immunity to Single Event Effects (SEE) is combined with
100K RADs of total dose hardness to provide devices which
are ideally suited to harsh space environments. The dose
rate and neutron tolerance necessary for military
applications have not been sacrificed.
The Intersil portfolio of SEGR resistant radiation hardened
MOSFETs includes N-Channel and P-Channel devices in a
variety of voltage, current and on-resistance ratings.
Numerous packaging options are also available.
This MOSFET is an enhancement-mode silicon-gate power
field-effect transistor of the vertical DMOS (VDMOS)
structure. It is specially designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, motor drives,
relay drivers and drivers for high-power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Reliability screening is available as either commercial, TXV
equivalent of MIL-S-19500, or Space equivalent of
MIL-S-19500. Contact Intersil for any desired deviations
from the data sheet.
Formerly available as type TA17750T.
Features
• 64A, -60V, rDS(ON) = 0.023Ω
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
• Typical SEE Immunity
- LET of 36MeV/mg/cm2 with VDS up to 80% of Rated
Breakdown and VGS of 0V
- LET of 26MeV/mg/cm2with VDS up to 100% of Rated
Breakdown and VGS of 5V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BVDSS
- Typically Survives 2E12 if Current Limited to IDM
• Photo Current
- 6nA Per-RAD (Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 3E13 Neutrons/cm2
- Usable to 3E14 Neutrons/cm2
Symbol
Packaging SMD2
Ordering Information
RAD LEVEL SCREENING LEVEL PART NUMBER/BRAND
10K Commercial FSTYC9055D1
10K TXV FSTYC9055D3
100K Commercial FSTYC9055R1
100K TXV FSTYC9055R3
100K Space FSTYC9055R4
G
D
S
Data Sheet June 2000
2
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified FSTYC9055D, FSTYC9055R UNITS
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDS -60 V
Drain to Gate Voltage (RGS = 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -60 V
Continuous Drain Current
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID64 A
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D41 A
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM 192 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS ±20 V
Maximum Power Dissipation
TC = 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PT162 W
TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PT65 W
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.30 W/oC
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . . . IAS 192 A
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IS64 A
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM 192 A
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
(Distance >0.063in (1.6mm) from Case, 10s Max) 300 oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 1mA, VGS = 0V -60 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS,
ID = 1mA TC = -55oC - - -7.0 V
TC = 25oC -2.0 - -6.0 V
TC = 125oC -1.0 - - V
Zero Gate Voltage Drain Current IDSS VDS = -48V,
VGS = 0V TC = 25oC--25µA
TC = 125oC - - 250 µA
Gate to Source Leakage Current IGSS VGS = ±20V TC = 25oC - - 100 nA
TC = 125oC - 200 nA
Drain to Source On-State Voltage VDS(ON) VGS = -12V, ID = 64A - - -1.60 V
Drain to Source On Resistance rDS(ON)12 ID = 41A,
VGS = -12V TC = 25oC - 0.016 0.023 Ω
TC = 125oC - - 0.037 Ω
Turn-On Delay Time td(ON) VDD = -30V, ID = 64A,
RL = 0.47Ω, VGS = -12V,
RGS = 2.35Ω
- - 60 ns
Rise Time tr- - 45 ns
Turn-Off Delay Time td(OFF) - - 90 ns
Fall Time tf- - 35 ns
Total Gate Charge Qg(TOT) VGS = 0V to -20V VDD = -30V,
ID = 64A - - 330 nC
Gate Charge at 12V Qg(12) VGS = 0V to -12V - 160 190 nC
Threshold Gate Charge Qg(TH) VGS = 0V to -2V - - 18 nC
Gate Charge Source Qgs -5171nC
Gate Charge Drain Qgd -3146nC
Plateau Voltage V(PLATEAU) ID = 64A, VDS = -15V - -7 - V
Input Capacitance CISS VDS = -25V, VGS = 0V,
f = 1MHz - 7100 - pF
Output Capacitance COSS - 2130 - pF
Reverse Transfer Capacitance CRSS - 370 - pF
Thermal Resistance Junction to Case RθJC - - 0.77 oC/W
FSTYC9055D, FSTYC9055R
3
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Forward Voltage VSD ISD = 64A -0.6 - -1.8 V
Reverse Recovery Time trr ISD = 64A, dISD/dt = 100A/µs - - 120 ns
Electrical Specifications up to 100K RAD TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS
Drain to Source Breakdown Volts (Note 3) BVDSS VGS = 0, ID = 1mA -60 - V
Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA -2.0 -6.0 V
Gate to Body Leakage (Notes 2, 3) IGSS VGS = ±20V, VDS = 0V - 100 nA
Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = -48V - 25 µA
Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = -12V, ID = 64A - -1.60 V
Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = -12V, ID = 41A - 0.023 Ω
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS.
Single Event Effects (SEB, SEGR) Note 4
TEST SYMBOL
ENVIRONMENT (NOTE 5) APPLIED
VGS BIAS
(V)
(NOTE 6)
MAXIMUM
VDS BIAS (V)
ION
SPECIES TYPICAL LET
(MeV/mg/cm) TYPICAL
RANGE (µ)
Single Event Effects Safe Operating Area SEESOA Ni 26 43 20 -60
Br 37 36 10 -60
Br 37 36 15 -36
Br 37 36 20 -24
NOTES:
4. Testing conducted at Brookhaven National Labs; witnessed by Naval Surface Warfare Center (NSWC), Crane, IN.
5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
Performance Curves Unless Otherwise Specified
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT
GAMMA DOT CURRENT TO IAS
-40
0010
15 20 25
5
VGS (V)
VDS (V)
-10
-20
-30
-50
-60
-70
LET = 37MeV/mg/cm2, RANGE = 36µ
LET = 26MeV/mg/cm2, RANGE = 43µ
FLUENCE = 1E5 IONS/cm2 (TYPICAL)
TEMP = 25oC
-300-100-10
LIMITING INDUCTANCE (HENRY)
DRAIN SUPPLY (V)
-1000
ILM = 10A
300A
1E-4
1E-5
1E-6
-30
100A
30A
1E-7
1E-3
FSTYC9055D, FSTYC9055R
4
FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE
FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
Performance Curves Unless Otherwise Specified (Continued)
ID, DRAIN (A)
TC, CASE TEMPERATURE (oC) 150100500-50
0
20
40
30
10
70
60
50 100
10
1-1
ID, DRAIN CURRENT (A)
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
-10 -100
500
100µs
1ms
10ms
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
-200
TC = 25oC
CHARGE
QGD
QG
VG
QGS
-12V
2.5
2.0
1.5
1.0
0.5
0.0
-80 -40 0 40 80 120 160
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED rDS(ON)
PULSE DURATION = 250ms, VGS = -12V, ID = 41A
1
10-5 10-4 10-3 10-2 10-1 100101
THERMAL RESPONSE (ZθJC)
0.001
0.01
0.1
NORMALIZED
PDM
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
SINGLE PULSE
0.01
0.02
0.2
0.1
0.05
0.5
10
t, RECTANGULAR PULSE DURATION (s)
FSTYC9055D, FSTYC9055R
5
FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING
Performance Curves Unless Otherwise Specified (Continued)
100
100.1 1
tAV, TIME IN AVALANCHE (ms)
IAS, AVALANCHE CURRENT (A)
10
STARTING TJ = 150oC
STARTING TJ = 25oC
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
IF R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
IF R ≠ 0
500
Test Circuits and Waveforms
FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS
FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT FIGURE 12. RESISTIVE SWITCHING WAVEFORMS
tP
VGS ≤ 20V
L
+
-
VDS
VDD
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
50Ω
50W
50V-150V
IAS
+
-
ELECTRONIC SWITCH OPENS
WHEN IAS IS REACHED
CURRENT
TRANSFORMER
VDD
VDS
BVDSS
tP
IAS
tAV
VDD
RL
VDS
DUT
RGS
0V
VGS = -12V
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%50%
10% PULSE WIDTH
VGS
tON
FSTYC9055D, FSTYC9055R
6
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table).
Delta Tests and Limits (JANTXV Equivalent, JANS Equivalent) TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Gate to Source Leakage Current IGSS VGS = ±20V ±20 (Note 7) nA
Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value ±25 (Note 7) µA
Drain to Source On Resistance rDS(ON) TC = 125oC at Rated ID±20% (Note 8) Ω
Gate Threshold Voltage VGS(TH) ID = 1.0mA ±20% (Note 8) V
NOTES:
7. Or 100% of Initial Reading (whichever is greater).
8. Of Initial Reading.
Screening Information
TEST JANTXV EQUIVALENT JANS EQUIVALENT
Gate Stress VGS = -30V, t = 250µsV
GS = -30V, t = 250µs
Pind Optional Required
Pre Burn-In Tests (Note 9) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC) MIL-S-19500 Group A,
Subgroup 2 (All Static Tests at 25oC)
Steady State Gate
Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests
and Limits Table All Delta Parameters Listed in the Delta Tests
and Limits Table
Steady State Reverse
Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 160 hours
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 240 hours
PDA 10% 5%
Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroup 2 MIL-S-19500, Group A,
Subgroups 2 and 3
NOTE:
9. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER SYMBOL TEST CONDITIONS MAX UNITS
Safe Operating Area SOA VDS = -48V, t = 10ms 9.0 A
Unclamped Inductive Switching IAS VGS(PEAK) = -15V, L = 0.1mH 192 A
Thermal Response ∆VSD tH = 10ms; VH = -25V; IH = 4A 65 mV
Thermal Impedance ∆VSD tH = 500ms; VH = -20V; IH = 4A 135 mV
FSTYC9055D, FSTYC9055R
7
Rad Hard Data Packages - Intersil Power Transistors
TXV Equivalent
1. RAD HARD TXV EQUIVALENT - STANDARD DATA
PACKAGE
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
D. Group A - Attributes Data Sheet
E. Group B - Attributes Data Sheet
F. Group C - Attributes Data Sheet
G. Group D - Attributes Data Sheet
2. RAD HARD TXV EQUIVALENT - OPTIONAL DATA
PACKAGE
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
- Pre and Post Burn-In Read and Record
Data
D. Group A - Attributes Data Sheet
E. Group B - Attributes Data Sheet
- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High Temperature Operating
Life Read and Record Data (Subgroup B6)
F. Group C - Attributes Data Sheet
- Pre and Post Read and Record Data for
Intermittent Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
G. Group D - Attributes Data Sheet
- Pre and Post RAD Read and Record Data
Class S - Equivalents
1. RAD HARD “S” EQUIVALENT - STANDARD DATA
PACKAGE
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
F. Group A - Attributes Data Sheet
G. Group B - Attributes Data Sheet
H. Group C - Attributes Data Sheet
I. Group D - Attributes Data Sheet
2. RAD HARD MAX. “S” EQUIVALENT - OPTIONAL
DATA PACKAGE
A. Certificate of Compliance
B. Serialization Records
C. Assembly Flow Chart
D. SEM Photos and Report
E. Preconditioning - Attributes Data Sheet
- HTRB - Hi Temp Gate Stress Post
Reverse Bias Data and Delta Data
- HTRB - Hi Temp Drain Stress Post
Reverse Bias Delta Data
- X-Ray and X-Ray Report
F. Group A - Attributes Data Sheet
- Subgroups A2, A3, A4, A5 and A7 Data
G. Group B - Attributes Data Sheet
- Subgroups B1, B3, B4, B5 and B6 Data
H. Group C - Attributes Data Sheet
- Subgroups C1, C2, C3 and C6 Data
I. Group D - Attributes Data Sheet
- Pre and Post Radiation Data
FSTYC9055D, FSTYC9055R
8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil Ltd.
8F-2, 96, Sec. 1, Chien-kuo North,
Taipei, Taiwan 104
Republic of China
TEL: 886-2-2515-8508
FAX: 886-2-2515-8369
FSTYC9055D, FSTYC9055R
SMD2
3 PAD CERAMIC LEADLESS CHIP CARRIER
D
A
D1
E1E2
b
D2
E
1
2
3
1 - GATE
2 - SOURCE
3 - DRAIN
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.130 0.142 3.30 3.60 3
b 0.135 0.145 3.43 3.68 -
D 0.520 0.530 13.20 13.46 -
D10.435 0.445 11.05 11.30 -
D20.115 0.125 2.92 3.17 -
E 0.685 0.695 17.40 17.65 -
E10.470 0.480 11.94 12.19 -
E20.152 0.162 3.86 4.11 -
NOTES:
1. No current JEDEC outline for this package.
2. Controlling dimension: INCH.
3. Measurement prior to pre-solder coating the mounting pads.
4. Revision 3 dated 5-00.
