High Performance,
Narrow-Band Transceiver IC
Data Sheet ADF7021-V
Rev. B Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2010–2014 Analog Devices, Inc. All rights reserved.
Technical Support www.analog.com
FEATURES
High performance, low power, narrow-band transceiver
Enhanced performance ADF7021-N with external VCO
Frequency bands using external VCO: 80 MHz to 960 MHz
Improved adjacent channel power (ACP) and adjacent
channel rejection (ACR) compared with the ADF7021-N
Programmable IF filter bandwidths: 9 kHz, 13.5 kHz,
and 18.5 kHz
Modulation schemes: 2FSK, 3FSK, 4FSK, MSK
Spectral shaping: Gaussian and raised cosine filtering
Data rates: 0.05 kbps to 24 kbps
Power supply: 2.3 V to 3.6 V
Programmable output power: −16 dBm to +13 dBm
in 63 steps
Automatic power amplifier (PA) ramp control
Receiver sensitivity
−125 dBm at 250 bps, 2FSK
−122 dBm at 1 kbps, 2FSK
Patent pending, on-chip image rejection calibration
On-chip fractional-N PLL
On-chip, 7-bit ADC and temperature sensor
Fully automatic frequency control (AFC) loop
Digital received signal strength indication (RSSI)
Integrated Tx/Rx switch
Leakage current in power-down mode: 0.1 μA
APPLICATIONS
Narrow-band, short-range device (SRD) standards
ETSI EN 300 220
500 mW output power capability in 869 MHz g3 subband
with external PA
High performance receiver rejection, blocking, and
adjacent channel power (ACP)
FCC Part 90 (meets Emission Mask D requirements)
FCC Part 95
ARIB STD-T67
Wireless metering
Narrow-band wireless telemetry
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
2FSK
3FSK
4FSK
DEMODULATOR
CLOCK
AND DATA
RECOVERY
7-BIT ADC
GAIN
DIV R
RFOUT
LNA
PFD
CP
BUFFER
OSC1 OSC2
N/N + 1
DIV P
OSC
CLKOUT
TEST MUX
CPOUT
LDO[1:4]
MUXOUT
RSET C
R
EG[1:4]CE
ADF7021-V
TxRxCLK
SWD
TxRxDATA
SLE
SDATA
SREAD
SCLK
IF FILTER
PA RAMP
L2
MUX
2FSK
3FSK
4FSK
MOD CONTROL
GAUSSIAN/
RAISED COSINE
FILTER
3FSK
ENCODING
÷1/÷2
÷2
0
8635-001
CLK
DIV
Σ-∆
MODULATOR
SERIAL
PORT
Tx/Rx
CONTROL
AGC
CONTROL
AFC
CONTROL
TEMP
SENSOR
RSSI/
LOG AMP
R
LNA
RFIN
RFIN
Data Sheet ADF7021-V
REVISION HISTORY
9/14—Rev. A to Rev. B
Changes to Table 8 .......................................................................... 16
Change to RSSI Formula (Converting to dBm) Section ............ 30
Change to Postdemodulator Filter Setup Section ....................... 33
Change to When to Use Fine Calibration Section ...................... 38
Change to Battery Voltage/ADCIN/Temperature Sensor
Readback Section ............................................................................ 44
Change to Register 4—Demodulator Setup Register Section ....... 50
Change to Register 7—Readback Setup Register Section .............. 53
Change to Register 4—AFC Register Section ................................ 56
8/12—Rev. 0 to Rev. A
Changes to Figure 6 ........................................................................ 15
Updated Outline Dimensions........................................................ 60
Changes to Ordering Guide ........................................................... 60
4/10—Revision 0: Initial Version
Rev. B | Page 3 of 66
08635-011
NOTES
1. THE EXPOSED PADDLE MUST BE CONNECTED
TO THE GROUND PLANE.
MIX_I
MIX_Q
FILT_I
GND4
FILT_Q
GND4
TEST_A
CE
CLKOUT
TxRxDATA
TxRxCLK
SWD
VDD2
CREG2
ADCIN
GND2
SCLK
SREAD
SDATA
SLE
CVCO
GND1
L1
GND
L2
VDD
CPOUT
CREG3
VDD3
OSC1
OSC2
MUXOUT
MIX_I
MIX_Q
FILT_I
FILT_Q
VCOIN
CREG1
VDD1
RFOUT
RFGND
RFIN
RLNA
VDD4
RSET
CREG4
GND4
RFIN
1
2
3
4
5
6
7
24
23
22
21
20
19
18
17
16
15
14
13
44
45
46
47
48
43
42
41
40
39
38
37
25
26
27
28
29
30
31
32
33
34
35
36
8
9
10
11
12
ADF7021-V
TOP VIEW
(Not to Scale)
–80
–90
–100
–110
–120
–130
–140
–150
–160 110 100 1k 10k 100k
FREQUENCY OFFSET (kHz)
PHASE NOISE (dBc/Hz)
08635-077
RF FREQ = 460MHz
TCXO = 19.2MHz
ICP = 0.3mA
ICP = 0.9mA
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
–160 110 100 1k 10k
FREQUENCY OFFSET (kHz)
PHASE NOISE (dBc/Hz)
08635-078
ICP = 0.3mA
ICP = 0.9mA
ICP = 1.5mA
ICP = 2.1mA
RF FREQ = 868MHz
TCXO = 19.2MHz
20
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–25,000
–20,000
–15,000
–10,000
–5000
0
5000
10,000
15,000
20,000
25,000
FREQUENCY OFFSET FROM CARRIER (Hz)
OUTPUT POWER (dBm)
08635-079
FCC PART 90
EMISSION MASK D
DEMODULATION = GFSK
DATA RATE = 2.4kbps
fDEV = 1.2kHz
RF FREQ = 470MHz
IFBW = 4kHz
–40
–36
–32
–28
–24
–20
–16
–12
–8
–4
0
4
8
12
16
0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60
PA SETTING
RF OUTPUT POWER (dBm)
PA_BIAS = 5µA
PA_BIAS = 11µA
PA_BIAS = 9µA
PA_BIAS = 7µA
08635-012
20
0
–20
–40
–60
–80
–100
300 800 1300 1800 2300 2800
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-013
10
0
–10
–20
–30
–40
–50
–60
–70
–80
867.97 867.98 867.99 868.00 868.01 868.02 868.03
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-014
2FSK
GFSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
10
0
–10
–20
–30
–40
–50
–60
–70
–80
867.97 867.98 867.99 868.00 868.01 868.02 868.03
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-015
2FSK
RC2FSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
10
0
–10
–20
–30
–40
–50
–60
–70
–80
867.97 867.98 867.99 868.00 868.01 868.02 868.03
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-016
3FSK
RC3FSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
10
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
867.94 867.96 867.98 868.00 868.02 868.04 868.06
FREQUENCY (MHz)
OUTPUT POWER (dBm)
08635-017
4FSK
RC4FSK
DATA RATE = 9.6kbps
DATA = PRBS9
fDEV = 2.4kHz
RF FREQ = 868MHz
FREQUENCY OFFSET (kHz)
OUTPUT POWER (dBm)
0
–10
10
–20
–30
–40
–100 –50 500100
–50
–60
RAMP RATE:
CW ONLY
256 CODES/BIT
128 CODES/BIT
64 CODES/BIT
32 CODES/BIT
TRACE = MAX HOLD
PA ON/OFF RATE = 3Hz
PA ON/OFF CYCLES = 10,000
VDD = 3.0V
08635-018
0.6
0.5
0.4
0.3
0.2
0.1
0
–130 –125 –120 –115 –110 –105
RF INPUT POWER (dBm)
BIT ERROR RATE
08635-021
–40°C, 2.3V
–40°C, 3V
–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
+25°C, 3.6V
+85°C, 2.3V
+85°C, 3V
+85°C, 3.6V
DATA RATE = 1.2kbps
fDEV = 2.4Hz
RF FREQ = 868MHz
IFBW = 9kHz
0.6
0.5
0.4
0.3
0.2
0.1
0
–130 –125 –120 –115 –110 –105
RF INPUT POWER (dBm)
BIT ERROR RATE
08635-022
–40°C, 2.3V
–40°C, 3V
–40°C, 3.6V
+25°C, 2.3V
+25°C, 3V
+25°C, 3.6V
+85°C, 2.3V
+85°C, 3V
+85°C, 3.6V
DATA RATE = 1.2kbps
fDEV = 2.4Hz
RF FREQ = 460MHz
IFBW = 9kHz
90
100
70
50
30
10
80
60
40
20
0
–10
–20 –15 –10 –5 0 5 10 15 20
FREQUENCY OFFSET (MHz)
BLOCKING (dB)
08635-024
–140
–120
–100
–80
–60
–40
–20
–122.5 –112.5 –102.5 –92.5 –82.5 –72.5 –62.5 –52.5 –42.5
ACTUAL RF INPUT LEVEL
RF INPUT POWER (dBm)
RSSI LEVEL (dBm)
RSSI
READBACK LEVEL
08635-023
80
70
60
50
40
30
20
10
0
–10
459.75
459.70
459.80
459.85
459.90
459.95
460.00
460.05
460.10
460.15
BLOCKER FREQUENCY (MHz)
BLOCKING (dB)
08635-080
CALIBRATED
UNCALIBRATED
08635-025
2.5
0
–2.5
–5.0
–7.5
–10.0
–12.5
–15.0
–17.5
–20.0
–22.5
–25.0
–27.5
–30.0
–32.5
–35.0
–37.590 92 94 96 98 100 102 104 106 108 110
ATTENUATION (dB)
IF FREQUENCY (kHz)
–40°C
+90°C
MODULATION INDEX
SENSITIVITY POINT (dBm)
–118
–116
–114
–112
–110
–108
–106
–104
–102
–100
0 0.2 0.4 0.6 0.8 1.0 1.2
RF FREQ = 860MHz
2FSK MODULATION
DATA RATE = 9.6kbps
IFBW = 25kHz
VDD = 3.0V
TEMPERATURE = 25°C
DISCRIMINATOR BANDWIDTH =
1× FSK FREQUENCY DEVIATION
DISCRIMINATOR BANDWIDTH =
2× FSK FREQUENCY DEVIATION
08635-026
–120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100
3FSK MODULATION
VDD = 3.0V, TEMP = 25°C
DATA RATE = 9.6kbps
fDEV = 2.4kHz
RF FREQ = 868MHz
IFBW = 18.75kHz
INPUT POWER (dBm)
LOG BER
–7
–6
–5
–4
–3
–2
–1
0
VITERBI DETECTION
THRESHOLD DETECTION
08635-027
LNA GAIN, FILTER GAIN
SENSITIVITY (dBm)
–130
–120
–110
–100
–90
–80
–70
3, 72
(LOW GAIN MODE) 10, 72
(MEDIUM GAIN MODE) 30, 72
(HIGH GAIN MODE)
HIGH MIXER
LINEARITY
DEFAULT
MIXER
LINEARITY
2FSK MODULATION
DATA RATE = 9.6kbps
fDEV = 4kHz
IFBW = 12.5kHz
DEMOD = CORRELATOR
SENSITIVITY @ BER = 10–3
IP3 = –3dBm
IP3 = –5dBm
IP3 = –9dBm
IP3 = –13.5dBm
IP3 = –24dBm
IP3 = –20dBm
08635-028
Data Sheet ADF7021-V
Rev. B | Page 25 of 61
TRANSMITTER
RF OUTPUT STAGE
The power amplifier (PA) of the ADF7021-V is based on a
single-ended, controlled current, open-drain amplifier that has
been designed to deliver up to 13 dBm into a 50 Ω load at a
maximum frequency of 960 MHz.
The PA output current and, consequently, the output power
are programmable over a wide range. The PA configuration is
shown in Figure 38. The output power is set using Register 2,
Bits[DB18:DB13].
Figure 38. PA Configuration
The PA is equipped with overvoltage protection, which makes it
robust in severe mismatch conditions. Depending on the applica-
tion, users can design a matching network for the PA to exhibit
optimum efficiency at the desired radiated output power level for
a wide range of antennas, such as loop or monopole antennas.
See the LNA/PA Matching section for more information.
PA Ramping
When the PA is switched on or off quickly, its changing input
impedance momentarily disturbs the VCO output frequency.
This process is called VCO pulling, and it manifests as spectral
splatter or spurs in the output spectrum around the desired
carrier frequency. Some radio emissions regulations place
limits on these PA transient-induced spurs (for example, the
ETSI EN 300 220 regulations). By gradually ramping the PA
on and off, PA transient spurs are minimized.
The ADF7021-V has built-in PA ramping configurability. As
Figure 39 illustrates, there are eight ramp rate settings, defined
as a certain number of PA setting codes per one data bit period.
The PA steps through each of its 64 code levels but at different
speeds for each setting. The ramp rate is set by configuring
Bits[DB10:DB8] in Register 2.
If the PA is enabled/disabled by the PA_ENABLE bit (Register 2,
Bit DB7), it ramps up and down. If it is enabled/disabled by the
Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off.
Figure 39. PA Ramping Settings
PA Bias Currents
The PA_BIAS bits (Register 2, Bits[DB12:DB11]) facilitate an
adjustment of the PA bias current to further extend the output
power control range, if necessary. If this feature is not required,
the default value of 9 μA is recommended. If output power
greater than 10 dBm is required, a PA bias setting of 11 μA is
recommended. The output stage is powered down by resetting
Register 2, Bit DB7 to 0.
MODULATION SCHEMES
The ADF7021-V supports 2FSK, 3FSK, and 4FSK modulation.
The implementation of these modulation schemes is shown in
Figure 40.
Figure 40. Transmit Modulation Implementation
IDAC
2
6REGISTER 2,
BITS[DB18:DB13]
REGISTER 2, BIT DB7
REGISTER 2,
BITS[DB12:DB11]
+
RFGND
RFOUT
FROM VCO
REGISTER 0, BIT DB27
08635-037
DATA BITS
PA RAMP 0
(NO RAMP)
PA RAMP 1
(256 CODES PER BIT)
PA RAMP 2
(128 CODES PER BIT)
PA RAMP 3
(64 CODES PER BIT)
PA RAMP 4
(32 CODES PER BIT)
PA RAMP 5
(16 CODES PER BIT)
PA RAMP 6
(8 CODES PER BIT)
PA RAMP 7
(4 CODES PER BIT)
1 2 3 4 ... 8 ... 1
6
08635-038
VCO
÷N
THIRD-ORDER
Σ-∆ MODULATOR
PFD/
CHARGE
PUMP
REF
INTEGER_N
Tx_FREQUENCY_
DEVIATION
TO
PA STAGE
1 – D
2
PR
SHAPING
4FSK
BIT SYMBOL
MAPPER
MUX
TxRxDATA
2FSK
4FSK
GAUSSIAN
OR
RAISED COSINE
FILTERING
PRE-
CODER
3FSK
÷2
LOOP FILTER
FRACTIONAL_N
08635-039
INTERNAL
SIGNAL
SOURCE
MUX
RFIN LNA
ADF7021-V
POLYPHASE
IF FILTER
PHASE ADJUST
GAIN ADJUST
IQ
FROM LO
GAIN ADJUST
REGISTER 5
PHASE ADJUST
REGISTER 5
SERIAL
INTERFACE
4
MICROCONTROLLER
4
RSSI/
LOG AMP
7-BIT
ADC
RSSI READBACK
I/Q GAIN/PHASE ADJUST AND
RSSI MEASUREMENT
ALGORITHM
08635-050
RFIN
0
10
20
30
40
50
60
–60 –40 –20 020 40 60 80 100
VDD = 3.0V
IFBW = 25kHz
WANTED SIGNAL:
RF FREQ = 430MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
DATA = PRBS9
fDEV = 4kHz
LEVEL= –100dBm
INTERFERER SIGNAL:
RF FREQ = 429.8MHz
MODULATION = 2FSK
DATA RATE = 9.6kbps,
DATA = PRBS11
fDEV = 4kHz
TEMPERATURE (°C)
IMAGE REJECTION (dB)
CAL AT +25°C
CAL AT +85°C CAL AT –40°C
08635-051
PREAMBLE SYNC
WORD ID
FIELD DATA FIELD CRC
08635-052
READBACK MODE
AFC READBACK
DB15
RV16
X
X
RV16
0
RSSI READBACK
BATTERY VOLTAGE/ADCIN/
TEMP. SENSOR READBACK
SILICON REVISION
FILTER CAL READBACK
READBACK VALUE
DB14
RV15
X
X
RV15
0
DB13
RV14
X
X
RV14
0
DB12
RV13
X
X
RV13
0
DB11
RV12
X
X
RV12
0
DB10
RV11
LG2
X
RV11
0
DB9
RV10
LG1
X
RV10
0
DB8
RV9
FG2
X
RV9
0
DB7
RV8
FG1
X
RV8
RV8
DB6
RV7
RV7
RV7
RV7
RV7
DB5
RV6
RV6
RV6
RV6
RV6
DB4
RV5
RV5
RV5
RV5
RV5
DB3
RV4
RV4
RV4
RV4
RV4
DB2
RV3
RV3
RV3
RV3
RV3
DB1
RV2
RV2
RV2
RV2
RV2
DB0
RV1
RV1
RV1
RV1
RV1
08635-056
MISO
ADuC84x ADF7021-V
MOSI
SCLOCK
SS
P3.7
P3.2/INT0
P2.4
P2.5
TxRxDATA
TxRxCLK
CE
SWD
SREAD
SLE
P2.6
P2.7 SDATA
SCLK
GPIO
08635-057
UART
ADF7021-V
TxRxCLK
TxRxDATA
TxDATA
RxDATA
CE
SWD
SREAD
SLE
SDATA
SCLK
GPIO
MICROCONTROLLER
08635-058
SPI
ADF7021-V
TxRxCLK
TxRxDATA
MISO
MOSI
CE
SWD
SREAD
SLE
SDATA
SCLK
GPIO
MICROCONTROLLER
SCLK CLKOUT
08635-059
MOSI
ADSP-BF533 ADF7021-V
MISO
PF5
RSCLK1
DT1PRI
DR1PRI
RFS1
PF6
SDATA
SLE
TxRxDATA
SWD
CE
SCK SCLK
SREAD
TxRxCLK
08635-060
TR1 Tx/Rx
0 TRANSMIT
RECEIVE
1
M3 M2 M1 MUXOUT
0 REGULATOR_READY (DEFAULT)
FILTER_CAL_COMPLETE
0
0 DIGITAL_LOCK_DETECT
0 RSSI_READY
1 Tx_Rx
1 LOGIC_ZERO
1 TRISTATE
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1 LOGIC_ONE
U1 UART_MODE
0 DISABLED
1 ENABLED
N8 N7 N6 N5 N4 N3 N2 N1
023
024
.
.
.
1253
1254
1
0
0
.
.
.
1
1
1
0
0
.
.
.
.
.
.
1
1
1
1
1
1
1
1
.
.
.
0
1
1
1
1
.
.
.
1
0
1
1
1
.
.
.
1
0
0
1
1
.
.
.
.
.
.
1
0
1
0
1255
FRACTIONAL_NINTEGER_N
Tx/Rx
UART_MODE
MUXOUT ADDRESS
BITS
N5
N4
N8
M5
M6
M7
M8
M12
M13
M15
N1
N2
N3
M14
M9
M10
M11
M4
M3
TR1
U1
M1
M3
M2
C2 (0)
C1 (0)
C3 (0)
C4 (0)
M1
M2
N7
N6
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
FRACTIONAL_N
DIVIDE RATIO
0
1
2
.
.
.
32,764
32,765
32,766
32,767
M15
0
0
0
.
.
.
1
1
1
1
M14
0
0
0
.
.
.
1
1
1
1
M13
0
0
0
.
.
.
1
1
1
1
...
...
...
...
...
...
...
...
...
...
...
M3
0
0
0
.
.
.
1
1
1
1
M2
0
0
1
.
.
.
0
0
1
1
M1
0
1
0
.
.
.
0
1
0
1
08635-061
INTEGER_N
DIVIDE RATIO
R3 R2 R1
0
0
.
.
.
1
1
2
.
.
.
7
1
0
.
.
.
1
0
1
.
.
.
1
X1 XOSC_ENABLE
0 OFF
1 ON
D1 XTAL_
DOUBLER
0ENABLED
1
CP2
0 0 0.3
0 1 0.9
1 0 1.5
1 1 2.1
CL4 CL3 CL2 CL1 CLKOUT_
DIVIDE RATIO
0OFF
0
0
.
.
.
1
0
1
0
.
.
.
1
2
4
.
.
.
0
0
1
.
.
.
1
0
0
0
.
.
.
130
CP_
CURRENT
RF_DIVIDE_
BY_2
XOSC_
ENABLE
ADDRESS
BITS
XTAL_
DOUBLER
XTAL_
BIAS
RE5
RE4
CL1
CL2
CL3
CL4
CP1
CP2
RFD1
RE1
RE2
RE3
VE1
X1
XB1
XB2
D1
R3
C2 (0)
C1 (1)
C3 (0)
C4 (0)
R1
R2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
RE6 DB24
DB1
DB0
DB2
DB3
XB2 XB1
0 20µA
0 25µA
1 30µA
1
0
1
0
1 35µA
RFD1 RF_DIVIDE_BY_2
0OFF
ON
1
VE1
0
1
DB25
RE7
R_COUNTER
CLKOUT_
DIVIDE
08635-062
RF R_COUNTER
DIVIDE RATIO
RESERVED
BUFFER_
IMPEDANCE
50Ω
HIGH IMPEDANCE
XTAL_BIAS
DISABLED
BUFFER_
IMPEDANCE
CP1 ICP (mA)
RSET = 3.6kΩ
P6
0
0
0
0
.
.
1
...
...
...
...
...
...
...
...
P5
0
0
0
0
.
.
1
P2
0
0
1
1
.
.
1
P1
0
1
0
1
.
.
1
0 (PA OFF)
1 (–16.0dBm)
2
3
.
.
63 (+13dBm)
TFD9
0
0
0
0
.
1
TFD3
0
0
0
0
.
1
...
...
...
...
...
...
...
TFD2
0
0
1
1
.
1
TFD1
0
1
0
1
.
1
0
1
2
3
.
511
Tx_FREQUENCY_DEVIATION POWER_AMPLIFIER
TxDATA_
INVERT PA_BIAS PA_RAMP MODULATION_
SCHEME ADDRESS
BITS
PA_
ENABLE
PE1
0
1
PA_ENABLE
OFF
ON
PA2
0
0
1
1
PA1
0
1
0
1
PA_BIAS
5µA
7µA
9µA
11µA
DI2
0
0
1
1
DI1
0
1
0
1
TxDATA_INVERT
NORMAL
INVERT CLK
INVERT DATA
INV CLK AND DATA
S3
0
0
0
0
1
1
1
1
S2
0
0
1
1
0
0
1
1
MODULATION_SCHEME
2FSK
GAUSSIAN 2FSK
3FSK
4FSK
OVERSAMPLED 2FSK
RAISED COSINE2FSK
RAISED COSINE 3FSK
RAISED COSINE 4FSK
S1
0
1
0
1
0
1
0
1
PR3
0
0
0
0
1
1
1
1
PR2
0
0
1
1
0
0
1
1
NO RAMP
256 CODES/BIT
128 CODES/BIT
64 CODES/BIT
32 CODES/BIT
16 CODES/BIT
8 CODES/BIT
4 CODES/BIT
PR1 PA_RAMP RATE
0
1
0
1
0
1
0
1
TFD5
TFD4
TFD8
PR1
PR2
PR3
PA1
P3
P4
P6
TFD1
TFD2
TFD3
P5
PA2
P1
P2
PE1
S3
TFD9
DI1
DI2
C2 (1)
C1 (0)
C3 (0)
C4 (0)
S1
S2
TFD7
TFD6
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
R-COSINE_
ALPHA
DB30
NRC1
NRC1
0
1
R-COSINE_ALPHA
0.7
0.5 (DEFAULT)
fDEV
POWER_
AMPLIFIER
08635-063
FS8
0
0
.
1
1
FS7
0
0
.
1
1
FS3
0
0
.
1
1
...
...
...
...
...
...
FS2
0
1
.
1
1
FS1
1
0
.
0
1
CDR_CLK_ DIVIDE
1
2
.
254
255
BK2
0
0
1
1
BK1
0
1
0
1
BBOS_CLK_DIVIDE
4
8
16
32
SK8
0
0
.
1
1
SK7
0
0
.
1
1
SK3
0
0
.
1
1
...
...
...
...
...
...
SK2
0
1
.
1
1
SK1
1
0
.
0
1
SEQ_CLK_DIVIDE
1
2
.
254
255
OK2
0
0
...
1
OK1
0
1
...
1
DEMOD_CLK_DIVIDE
INVALID
1
...
15
SEQ_CLK_DIVIDEAGC_CLK_DIVIDE CDR_CLK_DIVIDE
BBOS_CLK_
DIVIDE
DEMOD_CLK_
DIVIDE ADDRESS
BITS
GD6
0
0
...
1
GD5
0
0
...
1
GD3
0
0
...
1
GD4
0
0
...
1
GD2
0
0
...
1
GD1
0
1
...
1
AGC_CLK_DIVIDE
INVALID
1
...
63
SK8
SK7
FS1
FS2
FS3
FS4
FS8
SK1
SK3
SK4
SK5
SK6
SK2
FS5
FS6
FS7
OK2
OK1
OK4
OK3
C2 (1)
C1 (1)
C3 (0)
C4 (0)
BK1
BK2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
GD6
GD5
GD1
GD2
GD3
GD4
DB24
DB25
DB28
DB27
DB26
DB29
DB30
DB31
DB1
DB0
DB2
DB3
OK3
0
0
...
1
0
0
...
1
OK4
08635-064
DISCRIMINATOR_BW
DOT_PRODUCT
POST_DEMOD_BW Rx_
INVERT
IF_FILTER_BW
ADDRESS
BITS
TD4
TD3
RI1
RI2
DW1
DW2
DW6
DW7
DW9
DW10
TD1
TD2
DW8
DW3
DW4
DW5
DP1
DS3
C2 (0)
C1 (0)
C3 (1)
C4 (0)
DS1
DS2
TD6
TD5
TD10
TD9
TD7
TD8
IFB2
IFB1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
DS1
0
1
0
1
0
1
0
1
DEMOD_SCHEME
2FSK LINEAR DEMODULATOR
2FSK CORRELATOR DEMODULATOR
3FSK DEMODULATOR
4FSK DEMODULATOR
RESERVED
RESERVED
RESERVED
RESERVED
DP1
0
1
DOT_PRODUCT
CROSS_PRODUCT
DOT_PRODUCT
RI1
0
1
0
1
Rx_INVERT
NORMAL
INVERT CLK
INVERT DATA
INVERT CLK/DATA
IFB1
0
1
0
1
IF_FILTER _
BW
DS2DS3
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
RI2
IFB2
0
0
1
1
DW3
0
0
.
.
.
.
1
DW1
1
0
.
.
.
.
1
POST_DEMOD_BW
1
2
.
.
.
.
1023
DW2
0
1
.
.
.
.
1
DW10
0
0
.
.
.
.
1
DW6
0
0
.
.
.
.
1
.
.
.
.
.
.
.
.
DW5
0
0
.
.
.
.
1
DW4
0
0
.
.
.
.
1
TD3
0
0
.
.
.
.
1
TD1
1
0
.
.
.
.
0
DISCRIMINATOR_BW
1
2
.
.
.
.
660
TD2
0
1
.
.
.
.
0
TD10
0
0
.
.
.
.
1
TD6
0
0
.
.
.
.
0
.
.
.
.
.
.
.
.
TD5
0
0
.
.
.
.
1
TD4
0
0
.
.
.
.
0
DEMOD_
SCHEME
08635-065
9kHz
13.5kHz
18.5kHz
INVALID
IR_PHASE_
ADJUST_MAG
IR_PHASE_
ADJUST_DIRECTION
IR_GAIN_
ADJUST_I/Q
IR_GAIN_
ADJUST_UP/DN
IR_GAIN_
ADJUST_MAG IF_FILTER_DIVIDER
IF_CAL_COARSE
IF_FILTER_ADJUST ADDRESS
BITS
IFA1
IFD9
IFD5
IFD6
PM2
PM3
GM1
GM2
GM4
GM5
IFD7
IFD8
GM3
PM4
PD1
IFD4
IFD3
C2 (0)
C1 (1)
C3 (1)
C4 (0)
IFD1
CC1
IFD2
IFA3
IFA2
PM1
IFA6
IFA4
IFA5
GA1
GQ1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
CC1 IF_CAL_COARSE
0
1DISABLED
ENABLED
PD1
0
1
IR_PHASE_ADJUST_DIRECTION
ADJUST I CH
ADJUST Q CH
GA1
0
1
IR_GAIN_ADJUST_UP/DN
GAIN
ATTENUATE
GQ1
0
1
IR_GAIN_ADJUST_I/Q
ADJUST I CH
ADJUST Q CH
IFD3
0
0
.
.
.
.
1
IFD1 IF_FILTER_
DIVIDER
1
0
.
.
.
.
1
1
2
.
.
.
.
511
IFD2
0
1
.
.
.
.
1
IFA2
0
0
1
..
1
0
0
1
.
1
IFA6
0
0
0
..
0
1
1
1
1
1
GM3 IR_GAIN_
ADJUST_MAG
GM5
0
0
0
.
1
IFD9
0
0
.
.
.
.
1
IFD6
0
0
.
.
.
.
1
.
.
.
.
.
.
.
.
IFD5
0
0
.
.
.
.
1
IFD4
0
0
.
.
.
.
1
0
1
0
..
1
0
1
0
.
1
IFA1 IF_FILTER_ADJUST
...
...
...
...
...
...
...
...
...
...
...
0
+1
+2
...
+31
0
–1
–2
...
–31
GM4 GM2 GM1
0
0
0
.
1
0
0
0
.
1
0
0
1
.
1
0
1
0
.
1
0
1
2
...
31
PM3 IR_PHASE_
ADJUST_MAG
PM4 PM2 PM1
0
0
0
.
1
0
0
0
.
1
0
0
1
.
1
0
1
0
.
1
0
1
2
...
15
IFA5
0
0
0
..
1
0
0
0
.
1
08635-066
IF_CAL_LOWER_TONE_DIVIDEIF_CAL_UPPER_TONE_DIVIDEIF_CAL_DWELL_TIME
IF_FINE_
CAL
ADDRESS
BITS
CD3
CD2
CD6
LT4
LT5
LT6
LT7
UT3
UT4
UT6
UT7
UT8
CD1
UT5
LT8
UT1
UT2
LT3
LT2
CD7
C2 (1)
C1 (0)
C3 (1)
C4 (0)
FC1
LT1
CD5
CD4
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB25
DB1
DB0
DB2
DB3
FC1
0
1
IF_FINE_CAL
DISABLED
ENABLED
UT3
0
0
0
.
.
1
UT1
1
0
1
.
.
1
IF_CAL_UPPER_
TONE_DIVIDE
1
2
3
.
.
UT2
0
1
1
.
.
1
UT8
0
0
0
.
.
0
...
...
...
...
...
...
... 127
LT3
0
0
0
.
.
1
LT1
1
0
1
.
.
1
1
2
3
.
.
LT2
0
1
1
.
.
1
LT8
0
0
0
.
.
1
...
...
...
...
...
...
... 255
IF_CAL_LOWER_
TONE_DIVIDE
CD3
0
0
0
.
.
1
CD1
1
0
1
.
.
1
IF_CAL_
DWELL_TIME
1
2
3
.
.
CD2
0
1
1
.
.
1
CD7
0
0
0
.
.
1
...
...
...
...
...
...
... 127
DB28
IRC1
DB29
DB30
IRC2
IRD1
IR_CAL_
SOURCE_
DRIVE_LEVEL
IR_CAL_
SOURCE ÷2
IRC1
0
1
0
1
IR_CAL_SOURCE_
DRIVE_LEVEL
IRC2
0
0
1
1
OFF
LOW
MED
HIGH
IRD1
0
1
IR_CAL_SOURCE ÷2
SOURCE ÷2 OFF
SOURCE ÷2 ON
0
0
0
.
.
1
LT7
0
0
0
.
.
1
UT7
08635-067
AD1AD2RB1RB2
RB3
DB8 DB7 DB6 DB5 DB4 DB3 DB2
C2 (1) C1 (1)
CONTROL
BITS
DB1 DB0
C3 (1)C4 (0)
READBACK_
SELECT ADC_
MODE
AD2
0
0
1
1
AD1
0
1
0
1
ADC_MODE
MEASURE RSSI
BATTERY VOLTAGE
TEMP SENSOR
TO EXTERNAL PIN
RB2
0
0
1
1
RB1
0
1
0
1
READBACK MODE
AFC WORD
ADC OUTPUT
FILTER CAL
SILICON REV
RB3
0
1
READBACK_SELECT
DISABLED
ENABLED
08635-068
PD1PD3 RESPD4
PD5
DB8 DB7 DB6 DB5 DB4 DB3 DB2
C2 (0) C1 (0)
CONTROL
BITS
DB1 DB0
C3 (0)C4 (1)
LOG_AMP_
ENABLE
SYNTH_
ENABLE
RESERVED
LNA/MIXER_
ENABLE
FILTER_
ENABLE
ADC_
ENABLE
DEMOD_
ENABLE
Tx/Rx_SWITCH_
ENABLE
PA_ENABLE_
Rx_MODE
COUNTER_
RESET
Rx_RESET
CR1 RR2 RR1
DB15 DB14 DB13 DB12 DB11
LE1 PD6
DB10 DB9
SW1PD7
PD7
0
1
PA_ENABLE_Rx_MODE
PA OFF
PA ON
CR1
0
1
COUNTER_RESET
NORMAL
RESET
SW1
0
1
Tx/Rx_SWITCH_ENABLE
DEFAULT (ON)
OFF
PD6
0
1
DEMOD_ENABLE
DEMOD OFF
DEMOD ON
PD5
0
1
ADC_ENABLE
ADC OFF
ADC ON
RR2
0
1
CDR_RESET
NORMAL
RESET
RR1
0
1
DEMOD_RESET
NORMAL
RESET
LE1
0
1
LOG_AMP_ENABLE
LOG AMP OFF
LOG AMP ON
PD4
0
1
FILTER_ENABLE
FILTER OFF
FILTER ON
PD3
0
1
LNA/MIXER_ENABLE
LNA/MIXER OFF
LNA/MIXER ON
PD1
0
1
SYNTH_ENABLE
SYNTH OFF
SYNTH ON
08635-069
AGC_HIGH_THRESHOLD
LNA_
GAIN AGC_
MODE
FILTER_
GAIN
LNA_
BIAS
FILTER_
CURRENT
MIXER_
LINEARITY
LNA_MODE
AGC_LOW_THRESHOLD ADDRESS
BITS
FG2
FG1
GL5
GL6
GL7
GH1
GH5
GH6
GM1
GM2
LG1
LG2
GH7
GH2
GH3
GH4
GL4
GL3
C2 (0)
C1 (1)
C3 (0)
C4 (1)
GL1
GL2
FI1
LM1
ML1
LI1
LI2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
FI1
0
1
FILTER_CURRENT
LOW
HIGH
AGC_MODE
GM2
0
0
1
1
0
1
0
1
GM1
AUTO AGC
MANUAL AGC
FREEZE AGC
RESERVED
FG2
0
0
1
1
FG1 FILTER_GAIN
0
1
0
1
8
24
72
INVALID
LG2
0
0
1
1
LG1
0
1
0
1
LNA_GAIN
3
10
30
INVALID
GL3
0
0
0
1
.
.
.
1
1
1
GL1
1
0
1
0
.
.
.
1
0
1
AGC_LOW_
THRESHOLD
1
2
3
4
.
.
.
61
62
63
GL2
0
1
1
0
.
.
.
0
1
1
GL7
0
0
0
0
.
.
.
1
1
1
GL6
0
0
0
0
.
.
.
1
1
1
GL5
0
0
0
0
.
.
.
1
1
1
GL4
0
0
0
0
.
.
.
1
1
1
GH3
0
0
0
1
.
.
.
1
1
0
GH1
1
0
1
0
.
.
.
0
1
0
AGC_HIGH_
THRESHOLD
1
2
3
4
.
.
.
78
79
80
GH2
0
1
1
0
.
.
.
1
1
0
GH7
0
0
0
0
.
.
.
1
1
1
GH6
0
0
0
0
.
.
.
0
0
0
GH5
0
0
0
0
.
.
.
0
0
1
GH4
0
0
0
0
.
.
.
1
1
0
LI2
0
LI1
0
LNA_BIAS
800µA (DEFAULT)
LM1
0
1
LNA_MODE
DEFAULT
REDUCED GAIN
ML1
0
1
MIXER_LINEARITY
DEFAULT
HIGH
08635-070
KIKP AFC_SCALING_FACTORMAX_AFC_RANGE
AFC_EN
ADDRESS
BITS
KP3
KP2
MA3
M4
M5
M6
M7
M11
M12
KI2
KI3
KI4
KP1
KI1
M8
M9
M10
M3
M2
MA4
MA5
C2 (1)
C1 (0)
C3 (0)
C4 (1)
AE1
M1
MA2
MA6
MA7
MA8
MA1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
KP1
0
1
.
1
2^0
2^1
...
2^7
AE1
0
1
AFC_EN
AFC OFF
AFC ON
MA3
0
0
0
1
.
.
.
1
1
1
MA1
1
0
1
0
.
.
.
1
0
1
MAX_AFC_RANGE
1
2
3
4
.
.
.
253
254
255
MA2
0
1
1
0
.
.
.
0
1
1
MA8
0
0
0
0
.
.
.
1
1
1
...
...
...
...
...
...
...
...
...
...
...
0
0
.
1
0
0
.
1
KP2KP3 KP KI1
0
1
.
1
2^0
2^1
...
2^15
0
0
.
1
0
0
.
1
KI2
KI3 KIKI4
0
0
.
1
M3
0
0
0
1
.
.
.
1
1
1
M1
1
0
1
0
.
.
.
1
0
1
AFC_SCALING_
FACTOR
1
2
3
4
.
.
.
4093
4094
4095
M2
0
1
1
0
.
.
.
0
1
1
M12
0
0
0
0
.
.
.
1
1
1
...
...
...
...
...
...
...
...
...
...
...
08635-071
PL2
0
0
1
1
PL1
0
1
0
1
SYNC_BYTE_
LENGTH
12 BITS
16 BITS
20 BITS
24 BITS
MT2
0
0
1
1
MT1
0
1
0
1
MATCHING_
TOLERANCE
ACCEPT 0 ERRORS
ACCEPT 1 ERROR
ACCEPT 2 ERRORS
ACCEPT 3 ERRORS
SYNC_BYTE_SEQUENCE CONTROL
BITS
SYNC_BYTE_
LENGTH
MATCHING_
TOLERANCE
MT2
SB1
SB2
SB3
SB4
SB5
SB6
SB7
SB8
SB9
SB10
SB11
SB12
SB13
SB14
SB15
SB16
SB17
SB18
SB19
SB20
SB21
SB22
SB23
SB24
MT1
C2 (1)
C1 (1)
C3 (0)
C4 (1)
PL1
PL2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
08635-072
DATA_PACKET_LENGTH CONTROL
BITS
LOCK_
THRESHOLD_
MODE
SWD_MODE
IL2
IL1
C2 (0)
C1 (0)
C3 (1)
C4 (1)
LM1
LM2
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DP8
DP7
DP6
DP5
DP4
DP3
DP2
DP1
DB7
DB6
DB5
DB4
DB1
DB0
DB2
DB3
LMx LOCK_THRESHOLD_MODE
0 THRESHOLD FREE RUNNING
1 LOCK THRESHOLD AFTER NEXT SYNC WORD
2 LOCK THRESHOLD AFTER NEXT SYNC WORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 LOCK THRESHOLD
DPx DATA_PACKET_LENGTH
0 INVALID
1 1 BYTE
... ...
255 255 BYTES
ILx SWD_MODE
0 SWD PIN LOW
1 SWD PIN HIGH AFTER NEXT SYNC WORD
2 SWD PIN HIGH AFTER NEXT SYNC WORD
FOR DATA PACKET LENGTH NUMBER OF BYTES
3 SWD PIN HIGH
08635-073
3FSK_CDR_THRESHOLD
VITERBI_
PATH_
MEMORY
3FSK/4FSK_
SLICER_THRESHOLD CONTROL
BITS
3FSK_VITERBI_
DETECTOR
PHASE_
CORRECTION
ST4
ST5
ST6
ST7
VD1
PC1
VM1
VM2
VT1
VT2
VT3
VT4
VT5
VT6
VT7
ST3
C2 (0)
C1 (1)
C3 (1)
C4 (1)
ST1
ST2
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB1
DB0
DB2
DB3
3FSK_PREAMBLE_
TIME_VALIDATE
PTV1
PTV2
PTV3
PTV4
DB24
DB23
DB22
DB25
4 BITS
0
0
1
1
VM2 VITERBI_PATH _
MEMORY
VM1
0
1
0
1
6 BITS
8 BITS
32 BITS
PHASE_
CORRECTION
0 DISABLED
1 ENABLED
PC1
3FSK_VITERBI_
DETECTOR
0 DISABLED
1 ENABLED
VD1
ST3
0
0
0
.
.
1
ST1
1
0
1
.
.
1
3FSK/4FSK_SLICER_
THRESHOLD
1
2
3
.
.
ST2
0
1
1
.
.
1
ST7
0
0
0
.
.
1
...
...
...
...
...
...
... 127
0 0
0... 0OFF
VT3
0
0
0
.
.
1
VT1
1
0
1
.
.
1
3FSK_CDR_
THRESHOLD
1
2
3
.
.
VT2
0
1
1
.
.
1
VT7
0
0
0
.
.
1
...
...
...
...
...
...
... 127
0 0
0... 0OFF
PTV3
0
0
0
.
.
1
PTV1
1
0
1
.
.
1
3FSK_PREMABLE_
TIME_VALIDATE
1
2
3
.
.
PTV2
0
1
1
.
.
1
PTV4
0
0
0
.
.
115
0 0
000
08635-074
TEST_DAC_GAIN TEST_DAC_OFFSET
TEST_
TDAC_EN
ED_PEAK_
RESPONSE
ED_LEAK_
FACTOR
PULSE_
EXTENSION
ADDRESS
BITS
TG3
TG2
ER2
TO4
TO5
TO6
TO7
TO11
TO12
TO14
TO15
TO16
TG1
TO13
TO8
TO9
TO10
TO3
TO2
EF1
EF2
C2 (1)
C1 (0)
C3 (1)
C4 (1)
TE1
TO1
ER1
EF3
PE1
PE2
TG4
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
PEx ED_PEAK_RESPONSE
0
1
2
3
FULL RESPONSE TO PEAK
0.5 RESPONSE TO PEAK
0.25 RESPONSE TO PEAK
0.125 RESPONSE TO PEAK
TGx TEST_DAC_GAIN
0
1
...
15
NO GAIN
× 2^1
...
× 2^15
TEST_TDAC_EN
TEST DAC DISABLED
TEST DAC ENABLED
TE1
0
1
EFx ED_LEAK_FACTOR
0
1
2
3
4
5
6
7
LEAKAGE =
2^–8
2^–9
2^–10
2^–11
2^–12
2^–13
2^–14
2^–15
08635-075
ERx PULSE_EXTENSION
0
1
2
3
NO PULSE EXTENSION
EXTENDED BY 1
EXTENDED BY 2
EXTENDED BY 3
Rx_TEST_
MODES
Tx_TEST_
MODES
Σ-Δ_TEST_
MODES
PFD/CP_
TEST_MODES
PLL_TEST_
MODES
ANALOG_TEST_
MODES CLK_MUX
FORCE_LD_
HIGH
REG1_PD
CAL_
OVERRIDE
ADDRESS
BITS
PM4
PM3
AM3
TM1
TM2
TM3
SD1
PC2
PC3
CM2
CM3
PM1
PM2
CM1
SD2
SD3
PC1
RT4
RT3
AM4
FH1
RD1
CO2
CO1
C2 (1)
C1 (1)
C3 (1)
C4 (1)
RT1
RT2
AM2
AM1
DB16
DB15
DB14
DB17
DB20
DB19
DB18
DB21
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB22
DB23
DB24
DB26
DB27
DB28
DB25
DB1
DB0
DB2
DB3
DB29
DB30
DB31
ANALOG_TEST_MODES
0
AMx
BAND GAP VOLTAGE
1 40µA CURRENT FROM REG4
2 FILTER I CHANNEL: STAGE 1
3 FILTER I CHANNEL: STAGE 2
4 FILTER I CHANNEL: STAGE 1
5 FILTER Q CHANNEL: STAGE 1
6 FILTER Q CHANNEL: STAGE 2
7 FILTER Q CHANNEL: STAGE 1
8 ADC REFERENCE VOLTAGE
9 BIAS CURRENT FROM RSSI 5µA
10 FILTER COARSE CAL OSCILLATOR OUTPUT
11 ANALOG RSSI I CHANNEL
12
13
14
15 BIAS CURRENT FROM BB FILTER
Tx_TEST_MODES
0
TMx
Tx CARRIER ONLY
1Tx +fDEV TONE ONLY
2
Tx –fDEV TONE ONLY
3Tx "1010" PATTERN
4Tx PN9 DATA SEQUENCE
5Tx SWD PATTERN REPEATEDLY
6
Σ-Δ_TEST_MODES
0
SDx
DEFAULT, 3RD-ORDER Σ-Δ, NO DITHER
11ST-ORDER Σ-Δ
22ND-ORDER Σ-Δ
3 DITHER TO FIRST STAGE
4 DITHER TO SECOND STAGE
5 DITHERTO THIRD STAGE
6 DITHER × 8
7 DITHER × 32
0
PMx
NORMAL OPERATION
PLL_TEST_MODES
1 R DIV
2 N DIV
3 RCNTR/2 ON MUXOUT
4 NCNTR/2 ON MUXOUT
5 ACNTR TO MUXOUT
6 PFD PUMP UP TO MUXOUT
7 PFD PUMP DNTO MUXOUT
8 S DATA TO MUXOUT (OR SREAD)
9 ANALOG LOCK DETECT ON MUXOUT
10 END OF COARSE CAL ON MUXOUT
11 END OF FINE CAL ON MUXOUT
12
13 TEST MUX SELECTS DATA
14 LOCK DETECT PRECISION
15 RESERVED
PFD/CP_TEST_MODES
0
PCx
DEFAULT, NO BLEED
1 (+VE) CONSTANT BLEED
2(–VE) CONSTANT BLEED
3(–VE) PULSED BLEED
4(–VE) PULSE BLD, DELAY UP
5 CP PUMP UP
6 CP TRISTATE
7 CP PUMP DN
CLK_MUX ON CLKOUT PIN
0
CMx
1
2
3
4
5
6
7
CAL_OVERRIDE
0
COx
AUTO CAL
1 OVERRIDE GAIN
2 OVERRIDE BW
3 OVERRIDE BW AND GAIN
FORCE_LD_HIGH
0
FH1
NORMAL
1 FORCE
REG1_PD
0
RD1
NORMAL
1 POWER-DOWN
FORCE NEW PRESCALER CONFIG
FOR ALL N
NORMAL OPERATION
NORMAL, NO OUTPUT
DEMOD CLK
CDR CLK
SEQ CLK
BB OFFSET CLK
Σ-Δ CLK
ADC CLK
TxRxCLK
Rx_TEST_MODES
0
RTx
NORMAL
1 SCLK, SDATA I,Q
2 REVERSE I,Q
3
LINEAR SLICER ON TxRxDATA
4CORRELATOR SLICER ON TxRxDATA
ADDITIONAL FILTERING ON I,Q
ENVELOPE DETECTOR WATCHDOG DISABLED
RESERVED
ENABLE REG 14 DEMOD PARAMETERS
PROHIBIT CAL ACTIVE
ENABLE DEMOD DURING CAL
FORCE CAL ACTIVE
5
6
I,Q TO TxRxCLK, TxRxDATA
7
8
9
10
11
12
POWER DOWN DDT AND ED IN T/4 MODE
13
14
15
SDATA TO CDR
3FSK SLICER ON TxRxDATA
08635-076
OFFSET LOOP +VE FBACK V (I CH)
SUMMED OUTPUT OF RSSI RECTIFIER+
SUMMED OUTPUT OF RSSI RECTIFIER–
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
1
0.50
BSC
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
7.00
BSC SQ
48
13
24
25
36
37
12
EXPOSED
PAD
PIN1
INDICATO
R
4.25
4.10 SQ
3.95
0.45
0.40
0.35
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 MIN
0.20 REF
COPLANARITY
0.08
0.30
0.23
0.18
08-16-2010-B
