Siliconix A Member of the TEMIC Group DG401/403/405 Low-Power, High-Speed CMOS Analog Switches Features Benefits Applications 44-V Supply Max Rating @ Wide Dynamic Range @ Audio and Video Switching @ +15-V Analog Signal Range @ Low Signal Errors and Distortion Sample-and-Hold Circuits @ On-Resistancerpsg(on): 20 & @ Break-Before-Make Switching Action Battery Operation @ Low LeakageIpjony: 40 pA Simple Interfacing Test Equipment Fast Switchington: 100 ns @ Hi-Rel Systems @ Ultra Low Power RequirementsPp: 0.35 u.W @ PBX, PABX TTL, CMOS Compatible @ Single Supply Capability Description The DG401/403/405 monolithic analog switches were designed to provide precision, high performance switching of analog signals. Combining low power (0.35 .W, typ) with high speed (ton: 100 ns, typ), the DG401 series is ideally suited for portable and battery powered industrial and military applications. Built on the Siliconix proprietary high-voltage silicon-gate process to achieve high voltage rating and superior switch on/off performance, break-before-make is guaranteed for the SPDT configurations. An epitaxial layer prevents latchup. Each switch conducts equally well in both directions when on, and blocks up to 30 V peak-to-peak when off. On-resistance is very flat over the full + 15-V analog range, rivaling JFET performance without the inherent dynamic range limitations. The three devices in this series are differentiated by the type of switch action as shown in the functional block diagrams. Functional Block Diagrams and Pin Configurations Dual-In-Line and SOIC DG401 > = re] NC EI] Lig-T5] IN; NC [3 4] v- NC [| fl GND NC [5 wl Ve NC [5] nl Yt Ne [7 p< Ho] Dz fe | al 9] S) Top View Ordering Information DG401 NC D) DG401 key NC v- NC GND NC NC NC Vi NC V+ NC Dz Top View NC 8, INg Two SPST Switches per Package 40 to 85C 16-Pin Plastic DIP DG401DJ DG401AK 16-Pin CerDIP -55 t0 125C P-32167Rev. C (11/1593) DG401AZ/883 Truth Table Logic Switch 0 OFF 1 ON Logic 0 < 0.8V Logic 1 = 2.4V Switches Shown for Logic 1 Input 1-127DG401/403/405 Siliconix Functional Block Diagrams and Pin Configurations (Cont'd) Dual-In-Line and SOIC Lee DG403 jk DG403 NC Di NC Si INi Di 1 +> 416] Si Nc [, +~<tfis] IN { v- D v- ; BI 4] cn S3 [a] Fe] GND NC GL, i * Ce fal V+ se GG) tho} [bf] NC Dy NC S INg Top View Top View Ordering Information DG403 Two SPDT Switches per Package Temp Range _ Package | Part Number Truth Table 4010 88C 16-Pin Plastic DIP | DG403DJ Logic | SWi,SW2 | SWs, SW4 16-Pin Narrow SOIC | DG403DY 0 OFF ON DG403AK 1 ON OFF 16-PinCerDIP (= - _ DG403AK/883 Logic 0 s 0.8 V 55 to 125C Logic 1 = 2.4V LCC-20 DG403AZ/883 Switches Shown for Logic 1 Input Dual-In-Line and SOIC Lee ual-In-Line an DG405 CJ DG405 NC Dy; NC S; INy G/pp] GL bf) . >Gh jf Y os Ss Tj 3] GND s. v NC fo Be Vi oC] iy V+ Ne fy r~<H] D2 8 |}sloT 9] Sa NC Dz NC S2 IN2 Top View Top View Ordering Information DG405 Two DPST Switches per Package : Truth Table 16-Pin Plasti P 1G. : 40 to 85C in Plastic DI DG405DJ Logic Switch SOIC 0 OFF . DG405AK 1 ON 16-Pin CerDIP __ 55 to 125C DG405AK/883 Logic 0 < 0.8V Logic 1 2 2.4V Switches Shown for Logic 1 Input LCC-20 1-128 P-32167Rev. C (11/15/93)Siliconix A Member of the TEMIC Group Absolute Maximum Ratings DG401/403/405 I 0 a 44V Notes: GND 00 Va ooo cece cece e eee ten en nenes 28V a Signals on Sx, Dx, or INx exceeding V+ or V will be clamped by Vi cccveeeseee. ee (GND - 03 V) to (V+) +03V inven diodes. Limit forward diode current to maximum current Digital Inputs? Vg, Vp .....-...066- (V~-) -2 V to (V+ plus 2 V) b. All leads welded or soldered to PC Board. or 30 mA, whichever occurs first c. Derate 6 mW/C above 75C Current (Any Terminal) Continuous ...............6.-4. 30 mA a. Derate 12 mW/C above ee Cc Current, S or D (Pulsed 1 ms 10% duty) ........ 02.0000 100 mA ee Derate 76a Cae Is Storage Temperature (AK, AZ Suffix)......... -65 to 150C (DJ, DY Suffix) ......... 65 to 125C Power Dissipation (Package) 16-Pin Plastic DIP* 16-Pin CerDIP4 . 00... cece cece e eet e eens 16-Pin SOIC ..... LOC-20F occ cece teen eee teens Specifications* Test Conditions A Suffix D Suffix Unless Otherwise Specified ~55t0 125C | ~40 to 85C V+ =15V,V-=-15V Parameter Symbol | VL=5V;Vin=24V,08V! | Temp? Typ | Min | Max | Min? | Max4 | Unit Analog Switch - Analog Signal Range* VANALOG Full . ~15 15 ~15 15 Vv : . Is = -10 mA, Vp = +10 V Room 20 35 45 Drain-Source On-Resistance TDs(on) V+ =15V,V- = ~13.5V Full 45 55 Q A Drain-Source A Is = -10 mA, Vp = 5 V,0V Room 3 3 3 On-Resistance TDS(on) V+ = 16.5 V,V- = ~-16.5V Full 5 5 Iscott Room ~0.01 -0.25 | 0.25 -0.5 0.5 = a Hot -20 20 -5 5 Switch Off Leakage Current we siney Vv. _ ee y I D> ey Ys= . Room -0.01 -0.25 | 0.25 -0.5 as D(eoff) Hot ~20] 2 | -s | 5 | 24 Channel On I V+ =16.5V,V- = -16.5V Room ~0.04 -0.4 0.4 -1 1 Leakage Current Dion) Vs = Vp = +15.5V Hot ~40 | 40 -10 | 10 Digital Control oo VIN under test = 0.8 V Input Current Vpy Low In mu Other = 24V pA . Vin under test = 2.4 V Input Current Vpy High Inn ar Other = sv Full 0.005 -1 1 -1 1 Dynamic Characterist oe Turn-On Time ton Ry = 3002, Cy = 35 pF Room 100 150 150 Turn-Off Time loFF See Figure 2 Room 60 100 100 ns Break-Before-Make Time Delay (DG403) tp Rr = 3008, Cy = 35 pF Room 12 5 5 7 Cy = 10,000 pF Charge Injection Q Veen = 0 V, Rgen = 08 Room 60 pc Off Isolation Reject Ratio OIRR Ry = 1002, Cy = 5 pF Room 72 4B Channel-to-Channel Crosstalk | Xrarx f= 1MHz Room 90 P-32167Rev. C (11/15/93) 1-129DG401/403/405 Siliconix e e Specifications? Test Conditions A Suffix D Suffix Unless Otherwise Specified 5510125C | -40 10 85C Vt =15V,V-=-15V Parameter Symbol | VL=5V. Vin =24V,08V! | Temp? Typ | Min | Max? | Min? | Max | Unit Dynamic Characteristics (Cont'd) oe - Source Off Capacitance Csoft) Room 12 Drain Off Capacitance Cpvotty f = 1 MHz, Vs =0V Room 12 pF Channel On Capacitance Cp, Csyon) Room 39 Power Supplies ae Positive Supply Current I+ Room 9.01 5 5 . Room -0.01 -1 -1 Negative Supply Current I- ative SupP'y V+ =165V,V-=-165V | Full =5 -5 WA Vin = Oor SV Room | 0.01 1 1 Logic Supply Current IL Full 5 5 Ground Current Ionp Root -0.01 7 1 7 Notes: a. Refer to PROCESS OPTION FLOWCHART (Section 5 of the 1994 Data Book or FaxBack number 7103). Room = 25C, Full = as determined by the operating temperature suffix. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. Guaranteed by design, not subject to production test. Vin = input voltage to perform proper function. mopes Typical Characteristics Input Switching Threshold vs. Logic Supply Voltage Input Switching Threshold vs. Supply Voltages 10 | | j 3.5 V+=15V g WK V-=-15V 3.0 Ta = 25C 2.5 5 5 20 rm s fs 4 DG403 | SW3, 4 10 2 oF 05 0 0 Oo 2 4 6 8 10 12 14 16 18 20 (V+) 5 10 15 20 25 30 35 40 Vi. Logic Supply (V) (V-) -5 -10 -15 -10 -5 0 0 0 1-130 P-32167Rev. C (11/15/93)Siliconix A Member of the TEMIC Group Typical Characteristics (Cont'd) Tps(on) VS: Vp and Temperature Tpscon) Drain-Source On-Resistance ( 82) -15 -10 -5 V+ =15V,V-=-15V VL=5V -55C 0 5 Vp ~ Drain Voltage (V) 10 15 Tps(on) VS. Vp and Power Supply Voltage (V= = 0) 70 60 I Ta = 25C /~\ 75V 50 r 40 N| 10V oN , 12V 30 om, | 15V Tps(on) Drain-Source On-Resistance ( Q) 20V Pnecen 20 22V 10 0 5 10 15 20 25 Vp Drain Voltage (V) Leakage Current vs. Temperature 100nA ETT] V+ =15V V-=-15V 10 nA vies Vp = 414V oH" inA Z| A Ipgotf) ZA A 100pA ZF - 00 10 pA F 1 pa a 0.1 pA -55 -35 -15 5 25 45 65 85 105 125 P-32167Rev. C (11/15/93) Temperature (C) Q (pC) rpson) ~ Drain-Source On-Resistance (2) Is, fp (pA) 150 DG401/403/405 Tps(on) VS- Vp and Power Supply Voltage 40 T Ta = 25C +6 YV, 30 4N\ +10V YN \\ +12V Ss 0 SEO, AN +20V +422V 10 -25 ~15 ~ 5 15 26 Vp Drain Voltage (V) Charge Injection vs. Analog Voltage 200 V+ =15V,V~ = ~i5V 180 Vyesv 160 140 CL = 10k pF 120 100 80 60 100 pF 40 20 1k pF -15 -10 -5 0 5 10 15 Vs ~ Source Voltage (V) Leakage Current vs. Analog Voltage 90 60 30 Tp(ony V+ =15V,V-=-15V Vi =5V,Ta = 25C -120 For Ipcoff Vs = OV For Iscorf, Vp = OV -15 -10 -5 0 5 10 15 Vp or Vs Drain or Source Voltage (V) 1-131DG401/403/405 Typical Characteristics (Cont'd) Supply Current vs. Temperature 100n T Pit tl I+ V+ =15V,V-=-15V 100 VL=5SV Y | " in 100 p I+, I-, Ty, (A) I 16.0 p I- 1p -5-35 -15 5 25 45 65 85 105 125 Ta Temperature (C) Switching Time vs. Power Supply Voltage* 180 160 Vs =5V 140 120 100 80 60 40 Vg=-5V o ton, torr (ns) VL=5V 20 mm ton = lOFF 0 +5 +10 +15 +20 25 V+, V Positive and Negative Supplies (V) *Refer to Figure 2 for test conditions. Schematic Diagram (Typical Channel) ton, torr (ns) ton, torr (ns) Siliconix AMember of the TEMIC Group Switching Time vs. Temperature* 240 rT JT | t tt 210 [| v4 515V,V-=-15V,VL=5V | | ton == torr | 180 | _ 150 orn Vs =10V Leonean 120 TL aan en 90 bom Vs=-10V ~~ [ Vs=-10V -_ -_ an go ele -| 60 | ato=ao Vs =10V 30 0 -55-35 -15 5 25 45 65 85 105 125 Ta Temperature (C) Switching Time vs. Positive Supply Voltage* 270 OV Vg =5V 240 L _sv s=5 210 | -15V 180 150 | -15v 120 -VLN 90 ov a 60 30 ton torr 0 0 5 10 15 20 25 V+ Positive Supply (V) V+ oO a 64 a Os a Vi OWA i t ! rm v- TE | Shit i i ow i Vin Drive ly ie i = 7) vs _ re e 9 GND o me a oD a v- 90 Figure 1. 1-132 P-32167Rev. C (11/15/93)Siliconix AMember of the Tamic Group Test Circuits Vo is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. +5V +15V i L Logic VL V+ Input +10V o-+5 ab o Vo Switch ! | Input* IN J pm _f>- RL cq GND ve 1k 35 pF q = = Switch Output = = -15V Switch Input* Cy (includes fixture and stray capacitance) Vo = Vs _ Rp Ri + rpscon) Figure 2. Switching Time +5V +15 V ? Logic Input VL V+ s Vsi o-+ ~ofaP1 tO Voi | D Vo2 Vs. ot & OLe* O Switch IN | Output LIN Ru | cus GND v- Ro | a2 > > Switch | b Output = = -15V =_- = C, (includes fixture and stray capacitance) Figure 3. Break-Before-Make +5V +15V VL V+ R s D Vv ce ofa Vo o roy a IN _J CL IN 3V 10nF GND v- = L -15V P-32167Rev. C (11/15/93) Figure 4. Charge Injection 3V Ov Vsi Voi OV 02 ov On *Vs = 10 V for ton, Vs = 10 V for torr t, <20 ns ty <20 ns Note: Logic input waveform is inverted for switches that have the opposite logic sense control 90% oft Q=AVoXxC, tp On DG401/403/405 1-133DG401/403/405 Siliconix Test Circuits (Cont'd) +5V +15 V c oot bw boi = VL V+ = V+ = ~ S D ~ D Vs a ofs CD Vo ___o, <_ Vo R, = 50Q ad | LL = = Iw = Ry = Ri ov.24V J 100 Q 1002 = GND v- Jc = v- c 7 = -15V = -~15V _ Vs Off Isolation = 20 log |] Vo C = RF bypass C = RF bypass Figure 5. Off Isolation Figure 6. Insertion Loss +5V +15V 9 9 go et Py / Meter 502 i IN HP4192A. OV,2.4V o_ > | "Ahelyzcr alyzer D \ [ or Equivalent GND V- c f=1MHz = GND v-]oc 4 | f A = -15V = -15V = Vs | Xrax Isolation = 20log | Vo C = RF bypass Figure 7. Crosstalk Figure 8. Capacitances Applications Stereo Source Selector: Dual] Slope Integrators: A single logic signal controls the status of all four switches of The DG403 is well suited to configure a selectable slope the device, simplifying stereo source switching. integrator. One control signal selects the timing capacitor The low on-resistance (<35 ) minimizes total harmonic C, or Cz. Another one selects ej, or discharges the distortion. 1-134 capacitor in preparation for the next integration cycle. P-32167Rev. C (11/15/93)Siliconix A Member of the TaMic Group Applications (Contd) DG401/403/405 +3V +15V +5V +15V Vi V+ Vi V+ o-Left Si [a Di O ein Sout Left Source 1 Right 33 Da Left Ni S2 a D2 Integrate/ Source 2 of Reset o-Right S4 ots D4 Right TTL | IN2 J TIL P 1 DG403 ann Select GND V- +t 6 - -15V Figure 9. Stereo Source Selector Figure 10. Dual Slope Integrator Band-Pass Switched Capacitor Filter: Single-pole double-throw switches are a common element for switched capacitor networks and filters. The fast switching times and low leakage of the DG403 allow for higher clock rates and consequently higher filter operating frequencies. +5V +15V Vi V+ S14 Dy 3 Ip IN, LPN: 2 abe Se ole Ds | IN2 J DG403 GND V- TT 7 - -15V (HE Lt IHF SLU o Clock Figure 11. Band-Pass Switched Capacitor Filter P-32167Rev. C (11/15/93) 1-135DG401/403/405 Siliconix Applications (Contd) Peak Detector: A3 acting as a comparator provides the logic drive for goes negative, turning SW off. The system will therefore operating SW,. The output of Ag is fed back to Az and store the most positive analog input experienced. compared to the analog input ejp. If ej, > eoy the output of A; is high keeping SW, closed. This allows C, to charge up to the analog input voltage. When ejn goes below egy: A3 Reset ot 7 os 2 sw p~ sw, |p ett P DG401 L 1 Ag = Figure 12. Positive Peak Detector 1-136 P-32167Rev. C (11/1593)