Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
1
Rev. 00B
11/15/04
IS24C01B IS24C02B
ISSI®
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
1K-bit/2K-bit
2-WIRE SERIAL CMOS EEPROM ADVANCED INFORMATION
NOVEMBER 2004
DESCRIPTION
The IS24C01B and IS24C02B are electrically
erasable PROM devices that use the standard 2-
wire interface for communications. The IS24C01B
and IS24C02B contain a memory array of 1K-bits
(128 x 8) and 2K-bits (256 x 8), respectively. Each
device is organized into 8 byte pages for page
write mode.
This EEPROM is offered in wide operating volt-
ages of 1.8V to 5.5V and 2.5V to 5.5V to be
compatible with most application voltages. ISSI
designed this device family to be a practical, low-
power 2-wire EEPROM solution. The devices are
available in 8-pin PDIP, 8-pin SOIC, and 8-pin
TSSOP packages.
The IS24C01B/02B maintains compatibility with
the popular 2-wire bus protocol, so it is easy to
use in applications implementing this bus type.
The simple bus consists of the Serial Clock wire
(SCL) and the Serial Data wire (SDA). Using the
bus, a Master device such as a microcontroller is
usually connected to one or more Slave devices
such as this device. The bit stream over the SDA
line includes a series of bytes, which identifies a
particular Slave device, an instruction, an address
within that Slave device, and a series of data, if
appropriate. The IS24C01B/02B has a
Write Protect pin (WP) to allow blocking of any
write instruction transmitted over the bus.
FEATURES
• Two-Wire Serial Interface, I2CTM compatible
–Bi-directional data transfer protocol
• 400 KHz (2.5V) and 1 MHz (5.0V) compatibility
• Low Power CMOS Technology
–Standby Current less than 6 µA (5.0V)
–Read Current less than 2 mA (5.0V)
–Write Current less than 3 mA (5.0V)
• Wide Voltage Operation
–Vcc = 1.8V to 5.5V for -2 version
–Vcc = 2.5V to 5.5V for -3 version
• Hardware Data Protection
–Write Protect Pin
• Sequential Read Feature
• Filtered Inputs for Noise Suppression
• Self time write cycle with auto clear
5 ms @ 2.5V
• Organization:
–IS24C01B128x8 (128 bytes)
–IS24C02B256x8 (256 bytes)
• 8 Byte Page Write Buffer
• High Reliability
–Endurance: 1,000,000 Cycles
–Data Retention: 100 Years
• Industrial and Automotive temperature ranges
• 8-pin PDIP, 8-pin SOIC, and 8-pin TSSOP
packages
• Lead-free available
2
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IS24C01B IS24C02B ISSI
®
>
CONTROL
LOGIC
X
DECODER
SLAVE ADDRESS
REGISTER &
COMPARATOR
WORD ADDRESS
COUNTER
HIGH VOLTAGE
GENERATOR,
TIMING & CONTROL
EEPROM
ARRAY
Y
DECODER
DATA
REGISTER
Clock
DI/O
ACK
8
5
6
7
4
GND
WP
SCL
SDA
Vcc
nMOS
1
2
3
A2
A1
A0
FUNCTIONAL BLOCK DIAGRAM
SCL
This input clock pin is used to synchronize the data transfer
to and from the device.
SDA
The SDA is a Bi-directional pin used to transfer addresses and
data into and out of the device. The SDA pin is an open drain
output and can be wire-Or'ed with other open drain or open
collector outputs. The SDA bus
requires
a pullup resistor to
Vcc.
PIN CONFIGURATION
8-Pin DIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
A0
A1
A2
GND
VCC
WP
SCL
SDA
PIN DESCRIPTIONS
A0-A2 Address Inputs
SDA Serial Address/Data I/O
SCL Serial Clock Input
WP Write Protect Input
Vcc Power Supply
GND Ground
A0, A1, A2
The A0, A1 and A2 are the device address inputs. The
IS24C01B/02B uses the A0, A1, and A2 for hardware addressing
and a total of 8 devices may be used on a single bus system.
When the A0, A1, or A2 inputs are left floating, the input
internally defaults to zero.
WP
WP is the Write Protect pin. If the WP pin is tied to VCC on the
EEPROM, the entire array becomes Write Protected (Read
only). When WP is tied to GND or left floating normal read/
write operations are allowed to the device.
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IS24C01B IS24C02B ISSI
®
DEVICE OPERATION
IS24C01B/02B features serial communication and supports
a bi-directional 2-wire bus transmission protocol called I2CTM.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line (SDA), and
a Serial Clock line (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Stop and Start conditions. The
IS24C01B/02B is the Slave device on the bus.
The Bus Protocol:
– Data transfer may be initiated only when the bus is not busy
– During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA
line while the SCL line is high will be interpreted as a Start
or Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of the
High period of the clock signal. The data on the SDA line may
be changed during the Low period of the clock signal. There
is one clock pulse per bit of data. Each data transfer is
initiated with a Start condition and terminated with a Stop
condition.
Start Condition
The Start condition precedes all commands to the device and
is defined as a High to Low transition of SDA when SCL is High.
The EEPROM monitors the SDA and SCL lines and will not
respond until the Start condition is met.
Stop Condition
The Stop condition is defined as a Low to High transition
of SDA when SCL is High. All operations must end with
a Stop condition.
Acknowledge (ACK)
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
Reset
The IS24C01B/02B contains a reset function in case
the 2-wire bus transmission is accidentally interrupted
(eg. a power loss), or needs to be terminated mid-
stream. The reset is caused when the Master device
creates a Start condition. To do this, it may be
necessary for the Master device to monitor the SDA
line while cycling the SCL up to nine times. (For each
clock signal transition to High, the Master checks for a
High level on SDA.)
Standby Mode
Power consumption is reduced in standby mode. The
IS24C01B/02B will enter standby mode: a) At Power-up,
and remain in it until SCL or SDA toggles; b) Following
the Stop signal if a no write operation is initiated; or c)
Following any internal write operation.
4
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IS24C01B IS24C02B ISSI
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Page Write
The IS24C01B/02B is capable of 8-byte Page-Write
operation. A Page-Write is initiated in the same manner as
a Byte W rite, but instead of terminating the internal Write
cycle after the first data word is transferred, the Master
device can transmit up to 7 more bytes. After the receipt of
each data word, the EEPROM responds immediately with an
ACK on SDA line, and the three lower order data word
address bits are internally incremented by one, while the
higher order bits of the data word address remain constant.
If a byte address is incremented from the last byte of a
page, it returns to the first byte of that page. If the Master
device should transmit more than 8 bytes prior to issuing the
Stop condition, the address counter will “roll over,” and the
previously written data will be overwritten. Once all 8 bytes
are received and the Stop condition has been sent by the
Master, the internal programming cycle begins. At this point,
all received data is written to the IS24C01B/02B in a single
Write cycle. All inputs are disabled until completion of the
internal Write cycle.
Acknowledge (ACK) Polling
The disabling of the inputs can be used to take advantage of
the typical Write cycle time. Once the Stop condition is
issued to indicate the end of the host's Write operation, the
IS24C01B/02B initiates the internal Write cycle. ACK polling
can be initiated immediately. This involves issuing the
Start condition followed by the Slave address for a Write
operation. If the EEPROM is still busy with the Write
operation, no ACK will be returned. If the IS24C01B/02B
has completed the Write operation, an ACK will be returned
and the host can then proceed with the next Read or Write
operation.
WRITE OPERATION
Byte Write
In the Byte Write mode, the Master device sends the Start
condition and the Slave address information (with the R/W
set to Zero) to the Slave device. After the Slave generates
an ACK, the Master sends the byte address that is to be
written into the address pointer of the IS24C01B/02B. After
receiving another ACK from the Slave, the Master device
transmits the data byte to be written into the address
memory location. The IS24C01B/02B acknowledges once
more and the Master generates the Stop condition, at
which time the device begins its internal programming
cycle. While this internal cycle is in progress, the device
will not respond to any request from the Master device.
DEVICE ADDRESSING
The Master begins a transmission by sending a Start
condition. The Master then sends the address of the
particular Slave devices it is requesting. The Slave device
(Fig. 5) address is 8 bits.
The four most significant bits of the Slave device address
are fixed as 1010 for the IS24C01B/02B.
The next three bits of the Slave address are specific for
each of the EEPROM. The bit values enable access to
multiple memory blocks or multiple devices.
The IS24C01B/02B uses the three bits A0, A1, and A2 in
a comparison with the hard-wired input values on the A0,
A1, and A2 pins. Up to eight units may share the 2-wire
bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte (Fig. 5), the appropriate 2-wire Slave
(eg.IS24C02B) will respond with ACK on the SDA line. The
Slave will pull down the SDA on the ninth clock cycle,
signaling that it received the eight bits of data. The selected
EEPROM then prepares for a Read or Write operation by
monitoring the bus.
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IS24C01B IS24C02B ISSI
®
READ OPERATION
Read operations are initiated in the same manner as Write
operations, except that the (R/W) bit of the Slave address
is set to “1”. There are three Read operation options:
current address read, random address read and sequential
read.
Current Address Read
The IS24C01B/02B contains an internal address counter
which maintains the address of the last byte accessed,
incremented by one. For example, if the previous operation
is either a Read or Write operation addressed to the
address location n, the internal address counter would
increment to address location n+1. When the EEPROM
receives the Slave Addressing Byte with a Read operation
(R/W bit set to “1”), it will respond an ACK and transmit the
8-bit data byte stored at address location n+1. The Master
should not acknowledge the transfer but should generate
a Stop condition so the IS24C01B/02B discontinues
transmission. If 'n' is the last byte of the memory, the data
from location '0' will be transmitted. (Refer to Figure 8.
Current Address Read Diagram.)
Random Address Read
Selective Read operations allow the Master device to
select at random any memory location for a Read
operation. The Master device first performs a 'dummy'
Write operation by sending the Start condition, Slave
address and byte address of the location it wishes to read.
After the IS24C01B/02B acknowledges the byte address,
the Master device resends the Start condition and the
Slave address, this time with the R/W bit set to one. The
EEPROM then responds with its ACK and sends the data
requested. The Master device does not send an ACK but
will generate a Stop condition. (Refer to Figure 9. Random
Address Read Diagram.)
Sequential Read
Sequential Reads can be initiated as either a Current
Address Read or Random Address Read. After the
IS24C01B/02B sends the initial byte sequence, the Master
device now responds with an ACK, indicating it requires
additional data from the IS24C01B/02B. The EEPROM
continues to output data for each ACK received. The
Master device terminates the sequential Read operation
by pulling SDA High (no ACK) indicating the last data word
to be read, followed by a Stop condition.
The data output is sequential, with the data from address
n followed by the data from address n+1,n+2 ... etc. The
address counter increments by one automatically, allowing
the entire memory contents to be serially read during
sequential Read operation. When the memory address
boundary of 127 or 255 (depending on the device) is
reached, the address counter “rolls over” to address 0, and
the device continues to output data. (Refer to Figure 10.
Sequential Read Diagram).
6
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IS24C01B IS24C02B ISSI
®
STOP
Condition
SCL
SDA
START
Condition
FIGURE 3. START AND STOP CONDITIONS
SCL SDA
Master
Transmitter/
Receiver IS24Cxx
Vcc
FIGURE 1. TYPICAL SYSTEM BUS CONFIGURATION
t
AA
Data Output
from
Transmitter
SCL from
Master
Data Output
from
Receiver
189
ACK
t
AA
FIGURE 2. OUTPUT ACKNOWLEDGE
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Rev. 00B
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IS24C01B IS24C02B ISSI
®
FIGURE 5. SLAVE ADDRESS
FIGURE 4. DATA VALIDITY PROTOCOL
SCL
SDA
Data Stable Data Stable
Data Change
FIGURE 6. BYTE WRITE
SDA
Bus
Activity
S
T
A
R
T
M
S
B
L
S
BM
S
B
W
R
I
T
E
S
T
O
P
R/W
A
C
K
A
C
K
A
C
K
Data
Device
Address Byte Address
*
7BIT 43 12560
R/W
A0A1A2
0101
* = Don't care bit for IS24C01B
8
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IS24C01B IS24C02B ISSI
®
FIGURE 9. RANDOM ADDRESS READ
SDA
Bus
Activity
A
C
K
A
C
K
A
C
K
Data n
Byte
Address (n)
Device
Address
DUMMY WRITE
Device
Address
S
T
A
R
T
W
R
I
T
E
R
E
A
D
S
T
A
R
T
S
T
O
P
M
S
B
L
S
B
N
O
A
C
K
R/W
*
FIGURE 7. PAGE WRITE
SDA
Bus
Activity
S
T
A
R
T
M
S
B
L
S
B
W
R
I
T
E
A
C
K
A
C
K
A
C
K
A
C
K
Data (n+1) Data (n)
Byte Address (n)
Device
Address
S
T
O
P
A
C
K
Data (n+7)
R/W
*
FIGURE 8. CURRENT ADDRESS READ
SDA
Bus
Activity
S
T
A
R
T
M
S
B
L
S
B
N
O
A
C
K
R
E
A
D
S
T
O
P
A
C
K
Data
Device
Address
R/W
* = Don't care bit for IS24C01B
* = Don't care bit for IS24C01B
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IS24C01B IS24C02B ISSI
®
FIGURE 10. SEQUENTIAL READ
S
T
O
P
N
O
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data Byte n+XData Byte n+1Data Byte n Data Byte n+2
R/W
SDA
Bus
Activity
Device
Address
R
E
A
D
10
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IS24C01B IS24C02B ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VSSupply Voltage –0.5 to +6.5 V
VPVoltage on Any Pin –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 ° C
IOUT Output Current 5 mA
Notes:
1 . Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
OPERATING RANGE
(IS24C01B-2 & IS24C02B-2)
Range Ambient Temperature VCC
Industrial –40°C to +85°C 1.8V to 5.5V
OPERATING RANGE
(IS24C01B-3 & IS24C02B-3)
Range Ambient Temperature VCC
Automotive –40°C to +125°C 2.5V to 5.5V
Note: A utomotive data is preliminary.
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
COUT Output Capacitance VOUT = 0V 8 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
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IS24C01B IS24C02B ISSI
®
AC WAVEFORMS
Figure 11. Bus Timing
t
SU:STA
t
F
t
HIGH
t
LOW
t
R
t
SU:STO
t
BUF
t
DH
t
AA
t
HD:STA
t
HD:DAT
t
SU:DAT
SCL
SDA
IN
SDA
OUT
tSU:WP
t
HD:WP
WP
8th BIT ACK
WORD n STOP
Condition START
Condition
tWR
SCL
SDA
Figure 12. Write Cycle Timing
12
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IS24C01B IS24C02B ISSI
®
DC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol Parameter Test Conditions Min. Max. Unit
VOL1 Output Low Voltage VCC = 1.8V, IOL = 0.15 mA — 0.2 V
VOL2 Output Low Voltage VCC = 2.5V, IOL = 3 mA — 0.4 V
VIH Input High Voltage VCC X 0.7 VCC + 0.5 V
VIL Input Low Voltage –1.0 VCC X 0.3 V
ILI Input Leakage Current VIN = VCC max. — 3 µA
ILO Output Leakage Current — 3 µA
POWER SUPPLY CHARACTERISTICS
Industrial (TA = -40oC to +85oC), Automotive (TA = -40oC to +125oC)
Symbol Parameter Test Conditions Min. Max. Unit
ICC1 Vcc Operating Current Read at 400 KHz (Vcc = 5V) — 2.0 mA
ICC2 Vcc Operating Current Write at 400 KHz (Vcc = 5V) — 3.0 mA
ISB1 Standby Current Vcc = 1.8V — 1 µA
ISB2 Standby Current Vcc = 2.5V — 2 µA
ISB3 Standby Current Vcc = 5.0V — 6 µA
Notes: VIL min and VIH max are reference only and are not tested.
AC ELECTRICAL CHARACTERISTICS
Industrial (TA = -40oC to +85oC)
1.8V-5.5V 2.5V-5.5V 4.5V-5.5V
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fSCL SCL Clock Frequency 0 100 0 400 0 1000 KHz
T Noise Suppression Time(1) — 100 — 50 — 50 ns
tLow Clock Low Period 4.7 — 1.2 — 0.6 — µs
tHigh Clock High Period 4 — 0.6 — 0.4 — µs
tBUF
Bus Free Time Before New Transmission
(1)
4.7 — 1.2 — 0.5 — µs
tSU:STA Start Condition Setup Time 4 — 0.6 — 0.25 — µs
tSU:STO Stop Condition Setup Time 4 — 0.6 — 0.25 — µs
tHD:STA Start Condition Hold Time 4 — 0.6 — 0.25 — µs
tHD:STO Stop Condition Hold Time 4 — 0.6 — 0.25 — µs
tSU:DAT Data In Setup Time 100 — 100 — 100 — n s
tHD:DAT Data In Hold Time 0 — 0 — 0 — ns
tSU:WP WP pin Setup Time 4 — 0.6 — 0.6 — µs
tHD:WP WP pin Hold Time 4.7 — 1.2 — 1.2 — µs
tDH Data Out Hold Time
(SCL Low to SDA Data Out Change)
100 — 50 — 50 — ns
tAA Clock to Output (
SCL Low to SDA Data Out Valid)
100 3500 50 900 50 400 ns
tRSCL and SDA Rise Time(1) — 1000 — 300 — 300 ns
tFSCL and SDA Fall Time(1) — 300 — 300 — 100 ns
tWR Write Cycle Time — 10 — 5 — 5 ms
Note:
1. This parameter is characterized but not 100% tested.
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IS24C01B IS24C02B ISSI
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AC ELECTRICAL CHARACTERISTICS
Automotive (TA = -40oC to +125oC)
2.5V-5.5V 4.5V-5.5V
Symbol Parameter Min. Max. Min. Max. Unit
fSCL SCL Clock Frequency 0 400 0 1000 KHz
T Noise Suppression Time(1) —50 —50 ns
tLow Clock Low Period 1.2 — 0.6 — µs
tHigh Clock High Period 0.6 — 0.4 — µs
tBUF
Bus Free Time Before New Transmission
(1)
1.2 — 0.5 — µs
tSU:STA Start Condition Setup Time 0.6 — 0. 25 — µs
tSU:STO Stop Condition Setup Time 0.6 — 0.25 — µs
tHD:STA Start Condition Hold Time 0.6 — 0.25 — µs
tHD:STO Stop Condition Hold Time 0.6 — 0.25 — µs
tSU:DAT Data In Setup Time 100 — 100 — ns
tHD:DAT Data In Hold Time 0 — 0 — ns
tSU:WP WP pin Setup Time 0.6 — 0.6 — µs
tHD:WP WP pin Hold Time 1.2 — 1.2 — µs
tDH Data Out Hold Time
(SCL Low to SDA Data Out Change)
50 — 50 — ns
tAA Clock to Output (
SCL Low to SDA Data Out Valid)
50 900 50 550 ns
tRSCL and SDA Rise Time(1) — 300 — 300 ns
tFSCL and SDA Fall Time(1) — 300 — 100 ns
tWR Write Cycle Time — 10 — 5 ms
Note:
1. This parameter is characterized but not 100% tested.
14
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IS24C01B IS24C02B ISSI
®
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Voltage
Frequency Range Part Number Package
100 KHz 1.8V IS24C01B-2PI 300-mil Plastic DIP
to 5.5V IS24C01B-2GI Small Outline (JEDEC STD)
IS24C01B-2ZI TSSOP
100 KHz 1.8V IS24C02B-2PI 300-mil Plastic DIP
to 5.5V IS24C02B-2GI Small Outline (JEDEC STD)
IS24C02B-2ZI TSSOP
Note: The specification allows for higher speed. Please see AC Characteristics (2.5V-5.5V
or 4.5V-5.5V)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C, Lead-free
Voltage
Frequency Range Part Number Package
100 KHz 1.8V IS24C01B-2PLI 300-mil Plastic DIP
to 5.5V IS24C01B-2GLI Small Outline (JEDEC STD)
IS24C01B-2ZLI TSSOP
100 KHz 1.8V IS24C02B-2PLI 300-mil Plastic DIP
to 5.5V IS24C02B-2GLI Small Outline (JEDEC STD)
IS24C02B-2ZLI TSSOP
Note: The specification allows for higher speed. Please see AC Characteristics (2.5V-5.5V
or 4.5V-5.5V)
