1/18
AN1606
APPLICATION NOTE
November 2002
L4981 PFC Controller
This appl ication features the L4981 PFC c ontroller . It is a high perfor mance dev ice operating i n average cur rent
mod e with many on-ch ip functi ons. The driver output stage can deliver 1.5A , which is very important for this type
of application.
A detailed device description can be found in AN628. A functional block diagram is shown in Figure 1.
Figu re 1. Fu nct i on a l Di agram
by Ugo Moriconi
A "BRIDGELESS P.F.C. CONFIGURATION"
BASED ON L4981 P.F.C. CONTROLLER.
This technical document describes an innovative topology dedicated to a medium to high power PFC
stage. The originality of this topology is the absence of the bridge that usually is placed between the
EMC filter and the PFC stage. The advantages of this topology can be found in terms of increased ef-
ficiency and improved thermal management.
AN1606 APP LICATION NO TE
2/18
Description of "Bridgeless PFC Configuration" Topology
The conventional boost topology is the most efficient for PFC applications. It uses a dedicated diode bridge to
rectify the AC input voltage to DC, which is then followed by the boost section. See Figure 2.
This approach is good for a low to medium power range. As the power level increas es, the diode bridge begins
to become an important part of the application and it is necessary for the designer to deal with the problem of
how to dissipate the heat in limited surface area. The dissipated power is important from an efficiency point of
view.
Figure 2.
The bridgeless configuration topology presented in this paper avoids the need for the rectifier input bridge yet
maintains the classic boost topology.
This i s easily done by m aking use of the intr insic b ody diode c onnected between drain and s ource of PowerMOS
switches.
A simplified schematic of the bridgeless PFC configuration is shown in Figure 3.
Figure 3.
Load
L
A
controller
Rs
V_Rs
Mains
M
D
Inductor
Controller
Mains
Load
L
O
A
D
Inductor
M1 M2
D1 D2
3/18
AN1606 APPLICATION NOTE
The circ uit shown from a functional point of view is similar to the common boost converter. In the traditional to-
pology current flows through two of the bridge diodes in series. In the bridgeless PFC configuration, current
flows through only one diode with the PowerMOS providing the return path.
To analyze the circuit operation, it is necessa ry to separate it into two sections. The first section operates as the
boost stage and the second section operates as the return path for the AC input signal.
Referr ing to Figure 4, the left side ( Figure 4a) shows curr ent flow during the po sitive half cycle an d the right s ide
(Figure 4b) shows current flow during the negative half cycle
Figure 4.
Positive "HALF Cycle."
When the AC input voltage goes positiv e, the gate of M1 is driven high and c urrent flows f rom the input through
the inductor , storing energy. When M1 turns off, energy in the inductor is released as current flows through D1,
through the load and returns through the body diode of M2 back to the input mains. See Figure 4A
During the-off time, the current throw the inductor L (that during this time discharges its energy), flows in to the
boost diode D1 and close the circuit through the load.
Negative "HALF Cycle".
During the negative half cycle circuit operation is mirrored as shown in Figure 4B . M2 turns on, current flows
through the inductor, storing energy. When M2 turns off, energy is released as current flows through D2, through
the load and back to the mains through the body diode of M1.
Note that the two PowerMOSFE Ts are dr iven synchronously. It doesn't matter whether the sections are per-
forming as an active boost or as a path for the current to return. In either case there is benefit of lower power
dissipation when current flows through the PowerMOSFETs during the return phase.
Current Sensing.
The PFC function requires controlling the current drawn from the mains and shaping it like the input voltage
waveform. To accomplish this it is necessary to sense the current and feed its signal to the control circuit.
In aver age current conventional boost topology, we s ense the rectifi ed cur rent rather than the AC input current.
This can be achieved by a simple sensing resistor in the return of the current to the bridge, as shown in Figure5a.
in
vL
O
A
D
controller
L
0
v
1
M2
M
1
D2
D
Positive half cycle
Fig4a C
H
O
P
P
E
R
return
L
O
A
D
in
v
controller
L
0
v
1
M2
M
1
D2
D
Negative half cycle
Fig4b C
H
O
P
P
E
R
return
AN1606 APP LICATION NO TE
4/18
The L4981A/B current loop is designed to handle this negative signal. This type of resistor current sense can
easily be achieve in medium power applications. For high power PFC circuits it is necessary to use a magnetic
current transformer for improved efficiency as shown in Figure 5b.
In the bridgeles s PFC configuration since an input r ectifier bridge is not used, the current is continuous ly chang-
ing its direction and the complexity of current sensing with a simple resistor can increase. Also in high power
applications, resistor sensing may dissipate too much power. In these cases, current sensing with a current
transformer is the preferred approach.
A current sense transformer core is typically high permeability ferrite (toroidal or a small core set). The primary
of the transformer is a single turn of wire through the core. The secondary typically consists of 50 to 100 turns.
Figure 5. .
This type of s ense tr ansformer c annot operate at low frequency and for this reas on it must be connected w here
the current is switched at high frequency. The magnetic core must be allowed reset.
This is normally accomplished by using a diode. In order to reproduce the inductor's current in boost topology,
two of magnetic sense sections are needed and the simplified schematic is shown in figure 5b.
When the sense transformer solution is applied in the bridgeless topology, the simple sense as in fig5b, is no
longer valid.
vs
Rs
IL
Iret.
Fig.5a Standard Sensing
Inductor
Ma gnetic sensing for high power
Fig.5b
vs
Rs
Iret.
IL Inductor
Lm_p Rs
1:n
Typical sense transformers
5/18
AN1606 APPLICATION NOTE
The circuitry is more complex than in the boost case because here we have two pair of PowerMOS (M1, M2)
and diodes (D1, D2) alternating.
It is necessary to sense the chopping current of the (PowerMOS + diode) section and to sum the signals to be
applied to Rs.
The sensing of the diode's current can be simply done by placing a magnetic sensor at the common cathode
(L2 in fig.6.). Only one of the two diodes operates each half input cycle.
Figure 6.
For the PowerMOSFET portion of the cir cuit, the complexity increases because dur ing the half cycle when one
of the PowerMOSFETs is chopping, the other one has to handle the current flowing back to the mains.
Using the configuration of sensors as shown in Figure 6 it is possible to solve the problem without undue com-
plexity. The unneces sar y high frequency portion of the cur rent signal is cancell ed because of the method M1 is
connected to L1A as shown in Figure 6b. The problem due to the change of polarity during each half cycle is
solved by using a center tapped secondary and two rectifiers.
Since the coupling of the two windings must not permit the demagnetization of L1, an auxiliary transistor Q1 is
used that opens the circuit dur ing the off-time. For the L4981 c ontroller, the off- time is guaranteed no t to be less
than 5% of the period. Q1 can be a small signal transistor because its switched current is low due to the fact
that the transformer secondary will have a large number of turns.
To realize the current sensing transformer, a high permeability toroidal core ( ur=>5000) has been used. The
secondary has 50 turns as a compromise to reduce secondary current yet not require a large number of turns.
L2
vs
iin
L
O
A
D
Rs
M1M2
controller
Q1
D1D2
L1
Structure of sense transformers
L2 L1
AN1606 APP LICATION NO TE
6/18
Fig 6b
Other control circuits
Input voltage sensi ng: in the standard boost topology the rectified in put voltage wavefor m is sensed using a re-
sistor that, by one internal cir cuit, delivers the mirrored signal to one of the multiplier's inputs (Iac-pin4).
For the bridgeless configuration see the circuit shown in fig.7.
L2
L
O
A
D
Rs
vs
L1a L1b
controller
M1M2
Q1
D1D2
Da Db
Dc
Φ
iin
Inductor
L1a L1b L1=L1a+L1b
L2L1 TOT
Φ
vsvsvRs
ΦΦ
M2_D2 Chopping Phase
L1a L1b L1=L1a+L1b
L2
L1 TOT
vsa vsb vRs
ΦΦ Φ
M1_D1 Chopping Phase
7/18
AN1606 APPLICATION NOTE
Figure 7.
It is based on the follow ing consideration: the frequency of the si gnal of interest (tens of H z), is much lower than
the switching frequency (tens of kHz). The boost inductor, for the low frequency, behaves like a short cir cuit.
Since the Powermos's drains are, in turns, close to ground (via the body diode), the resulting equivalent circuit
is shown in fig7b.
The relation between the voltage (from the inductor) and the current that flows in to Iac pin is:
a)
Where: and
The net introduces one pole at:
The pole must be located at a frequency high enough not to distor t the input waveform and at the same time,
low enough to filter the switching frequency.
In this application the equivalent resistance has been choosen
Req.=324-k
Ω
that fits well with the current amplifier design.
The resulting R1 is 300k
Ω
and R2 is 12k
Ω
The pole has been placed a decade before the switching frequency:
Fp = 5kHz that gives:
b)
In practice, in our test, a standard value of 2.7 nF as ben used.
Input voltage sensing (A), and equivalent circuit (B).
A
CURRENT
MIRROR
R1R1
R2
C1
iac(t)
vL(t)
iac(t)
R1
R1R2
C1
+
B
vL(t)
Coupled
Inductor
Ys() 1
Req
----------- 1
1st+
--------------
⋅=
Req R1 2 R2⋅+= tR1
2
-------- //R2 C1⋅=
fp 1
2πt⋅⋅
-----------------=
C1 1
2πfp R1
2
-------- //R2
⋅⋅ ⋅
-------------------------------------------------- 2.87nF==
AN1606 APP LICATION NO TE
8/18
Voltage feed-forward.
Voltage feed-forward, a useful function in wide range applications, requires a DC voltage proportional to the rms.
value of the input mains. For the L4981, this value must be between 1.5V to 5.5V so that it can mirror over a
wide range.
Sinc e the rectified mains frequency is 100 -120Hz, we need a large rejec tion for this frequency and be cause the
feed-forward reaction time is pr oportional to the bandwidth, we introduce a second order filter that allows good
compromise between attenuation of the fundamental frequency and response time.
The circ uit (Fig.8) is similar to the fig.7 described earlier.
Figure 8.
Defining H
LP
(s) the transfer functions between the vol tage from the inductor and the v oltage at the output o f the
filter v
LP
(Fig.8B), we have the following relation:
c)
The time constants cannot be ex pr essed i n sim ple w ay and so that th e positi on of pol es can be numer ic ally cal-
culated.
The constant K
LP
is defined taking in to account the wide-range that is, V_mains is between 88V and 264V:
d)
Choosing to calculate this value at the midpoint of the allow ed values:
e)
Voltage feed -fo r war d Ci r cu i t (A) an d eq u i valent circu it (B ).
A
Ra
Rb
Rc
Ca
vLP(t)
Ra
Cb
B
Ra
Rc
Ca
+
vLP(t)
Rb
RaCb
Coupled
Inductor
HLP KLP 1
1st
1
+()1st
2
+()⋅
-------------------------------------------------
=
KLP Rc
Ra 2Rb 2Rc
++
()
-------------------------------------------------=
VLP VRMS22
π
----------- KLP
⋅=
22
π
----------- 88 264+
2
----------------------- KLP 1.5 5.5+
2
-----------------------=⋅⋅
9/18
AN1606 APPLICATION NOTE
To fit this, it has been choosen
For the capacitors, we set 80 dB of attenuation on the fundamental frequency using the commercial values: -
The design places two poles at 3Hz and 14Hz and 80 dB of attenuation at 100Hz.
Practical exam ples.
The preceeding points of this note have described the topology peculiarity. Remainder of the topics, for PFC
design, are similar to standard P.F.C. boost applications based on L4981A/B (see the related references and
application notes).
Starting from now, we can refer to real design examples.
In fact, in order to verify the efficacy of the described configur ation, it have been checked a pair of application's
size. For evaluation porpoise, it has been realiz ed a printed circuit.
Let us beginnes wi th and 800W P.F.C application.
800W Targ et:
1 - Wide range input voltage variation 110Vrms to 220Vrms.
2 - Output power 800W.
2 - Output voltage 400Vdc.
A switching frequency of 50 kHz has been chosen as a good compromise between the coil-size and the pow -
erMOS switching losses.
Boost Inductor design.
To design the boost inductor, the parameters under consideration are the percentage current ripple (as low as
possible) and the cost of the bobbin. This portion of the design is the same as for the standard topology.
In this application, in place of a single inductor connected to one of the phases, it has been chosen to split the
inductor into two sections (two windings on the same core) as shown in the connection diagram at fig.9.
Ra 998kΩ2499⋅()≡=
Rb 150kΩ=
Rc 30kΩ=
Ca 390nF=
Cb 470nF=
AN1606 APP LICATION NO TE
10/18
Figu re 9. Con ne ction Dia g ra m f or the Coupl ed I nduc tor
Realizing the inductor in this manner improves comm on mode rejection and avoids the effect of the difference
between drain c apacitance of the PowerMOSFETs. In order to simplify the model , assume a near unity coupl ing
factor and the equivalent circuit is shown in Figure 9b.
The inductance is proportional to the square of the number of turns. For the two windings it will be:
f)
and
The required number of turns for a given inductance on the same core is the same as it is for one winding or
two windings. The only differ ence is that the two windings are separated into two section s. For simplicity we can
design the coupled inductor using the same criteria as for a standard inductor - core size, number of turns, and
size of copper wire.
For the core, the preferred design is a gapped ferrite core set.
The size of the core can be chosen c onsidering the maxi mum current Ipk . that, for the 800W target's parameters
can exceed 14A (placing Ipk. = 15A).
g)
Where:
For the 800W application, the nominal current ripple has been chosen around 25%. This fixes the boost induc-
tance value L=450
µ
H.
L
i
Mains
Inductor
Zin
is(t)
vs(t)
Zin
is(t)
vs(t)
Leq.
Equivalent circuit.
Mains
N′N
2
----=
N′ total N
2
---- N
2
----+=
Vcore Vcore ""min
,
≥KLI
2
peck (mm3)⋅⋅=
K1.410
4
lcore
lgap
--------------
⋅⋅=
11/18
AN1606 APPLICATION NOTE
The coil r equi rements can b e met usi ng a gapped c ore set type E66/33/27, character ized with the following k ey
parameters:
Ae = 550mm^3; lcore = 146mm; m_core = >1600;
Vcore = 80.4*10^3mm^3
The air gap needed to avoid saturation and optimize the coil size is equal to lap = 3mm.
Using the parameters in the form ula g).
Vcore>67.5mm^3
This result confirms the core is well above the minimum size.
The used form ula for the number of turnes, needed to design the total required inductance L, is:
h)
The resulting N=38, in our solution, has been realized with 19 turns +19 turns.
In order to minimize the high frequency losses, the winding has been made using the "multiple wire" approach.
It is possible to estimate the losses for a low frequency current.
Imposing a maximum power value to be dissipated in the copper (Pcu = 5W)
i)
Using the formula for multiple wires: -
l)
Were:
In practice 20 wires were used, each having a diameter d=0.4 mm.
Output Capacitor filter.
For the bulk capacitor selection, we consider a reasonable 100Hz voltage ripple.
NL
µ0
------ l core,
µrcore A⋅,
----------------------------- 1gap
Aπ
4
--- 1gap⋅+
2
---------------------------------------------+⋅=
Pwire RDC IRMS max
,
25W <⋅=RDC Pwire
IRMS max
,
2
------------------------- 60mΩ=<
RDC ρCu lturn N⋅
π
4
--- d2M⋅⋅
----------------------- 60mΩ<⋅=
AN1606 APP LICATION NO TE
12/18
m)
were f is the input frequency.
Imposing <10Vac the peak of voltage variation over 400Vo, the Co value will results >318
µ
F; the commercial
value is 330
µ
F
Power Devices.
The selection of the power devices is dependent upon the topology and the size of the application.
Operating in continuous current mode, fast reverse recovery diodes are needed.
The TURBOSWITCH "STM family", in the 600V voltage range, offers a very good solution for the two boost
diodes, the STTH8R06FP has been chosen.
The insulated TO-220 package makes it easy to assemble the parts on a heat sinke.
Concerning the Powermos requirements, a 500V blocking voltage (Bvdss) is needed, for this application.
The chip selection is more complex. To find the best solution, it must be considered all the parameters that affect
the power dissipation and to compare the results in terms of a cost to benefit ratio. The devices used in the 800W
application (2+2), are the type STY34NB50F.
The four Powermos are effic iently dr iven without any add itional buffer, thanks to th e smart char acteristi cs of the
integrated driver.
Figure 10. 800W SCHEMATHIC DIAGRAM.
Co Po
2π2f∆fo Vo⋅⋅⋅⋅⋅
---------------------------------------------------=
L4981A/B
4
1
20 8 2
11
6
18
17
12
14
3
95
15 16
7
10
19
F1
C1
L1
D5D6
R9R10
C3
NTC
C4
R11
R12
R14
R15
C5
R17
C6
C7
R18
C8
R19
C10
R21
C12
13
L2a
L2b
L2c
DETAIL for L2
L2b
L2c
L2a
Vcc
Vcc
L3
Vcc
D1+D2+D3+D4
R1
Dz1C2
R2D7D8R3R4
D9D10 R5
R6
Q1Q2Q3Q4
R7
Q5
D11 D12
R8
D13
R13 R16
R20
R22
C13
R23
C14
C15 C16
R24 R25 R26
R27 R28 R29
R30 R31
R32 R33
Input
C11
13/18
AN1606 APPLICATION NOTE
B.O.M. for 800W Bridgeless Evaluation Circuit.
L
2,#(1/ 50+50)
# sense transformer; L
3#(1/50)
# sense transformer
#Ferrites H y _perm.' Diam.=20mm
D
1,2,3,4
; D
7,8,9,10,11,12,13
= 1N4148 ; Dz
1
= 1N4746; Q
5
= BS170
L
1
=450
µ
H; => E66*33*27-18+18 turns 3mm/gapped# 20 wires //m=0.4 mm each.
D
5,6
= STTH8R06FP; Q
1,2,3,4
=STY34NB50F
Note:
For the evaluation circuit and external coupled inductor EMC where utilized.
The filter has been achieved as follows: -
Coupled inductor (30 + 30) turns; wire diameter = 0.8mm on a toroidal (40x17x9 mm): -
Magnetizing inductance (each half inductor) Lm=8mH and a leakage inductance, Ld=50
µ
H.
Scaling down the application.
As a second step, based on the same circuit, a 600W P.F.C. has been built.
The target specification designed for server application is.
600W Targ et:
1- Wide range input mains 110Vrms to 220Vrms.
2- Output power = 600W.
2- Output voltage = 400Vdc.
The switching frequency has been set at 75kH z to use a reduced size and high performance PowerMOS.
Name Value Name Value Name Value Name Value Name Value
R1
68
ΩR2,3,4,5 10
ΩR6
1.8
Ω R7100
Ω R8 5 Ω
R92.7
kΩ R10 1.5
kΩ R11,12,14,15 1
MΩR13
22
kΩR16 25.5 kΩ
R17 3.9kΩR18 27
k
ΩR19 220 kΩR20 2.7 kΩR21 5.6 kΩ
R22,24,27 30 kΩR23,30,31,32,33 150 kΩR25,26,28,29 499 kΩR34 12 kΩRSN 12 Ω
C1,3
1
µ
F
C2
220
µ
F
C4
330
µ
F
C510 nF C6
1
µ
F
C71.8 nF C8
1
µ
F
C10 120 nF C11 1 nF C12 5.6 nF
C13 470 nF C14 2.7 nF C15 100 nF C16 390 nF
NTC
2.5
B57364
F1
20A
AN1606 APP LICATION NO TE
14/18
Boost Inductor design.
The boost inductor has been design as been previously described .
For the 600W application, the nominal current ripple has been set around 22%, gives requires the inductance
value L=440
µ
H.
The inductor requirements can be met using the core set type E55/28/21, characterized with the following key
parameters:
A = 357mm^2; lcore = 123mm; m_core =>1600;
Vcore = 43.7mm^3
The needed air gap is: l
ap
=2.5mm.
Using the relation g), Vcore>38.8mm^3
The result confirms that the core is good enough.
Using the relation
h)
, the resulting N=42.
For the 600W, the coil has been realized with 21 turns +21 turns.
For minimize the high frequency losses, the "multiple wire" solution has been used.
Imposing the copper losses (Pcu = 3.8W), it has been used 14 wires having a diameter d = 0.4 mm each.
Output Capacitor.
For the selection of C
O
, the relation as been described in (m). The commercial value = 330
µ
F/450V used for
the 800W application is still good for the 600W application.
Power Devices.
For the two boost diodes, as for the 800W application, the STTH8R06FP has been used.
Concerning the Powermos, the devices used in the 600W version application are two STW26NM50F.
15/18
AN1606 APPLICATION NOTE
Figure 11. 600W SCHEMATHIC DIAGRAM.
B.O.M. for 600W version Brid geless Evaluation Circuit.
L
2,#(1/ 50+50)
# sense transformer ; L
3#(1/50)
# sense transformer
#Ferrites H y _perm.' Diam.=20mm
D
1,2,3,4
D
8,9,11,12 ,13
=1N4148; Dz
1
=1N4746; Q
5
= BS170.
Name Value Name Value Name Value Name Value Name Value
R1
68
ΩR3,4
10
ΩR6
6.8
Ω R7
100
Ω R8
6.8
Ω
R9
2.7 k
Ω R10
1.5 k
Ω R11,12,14,15
1 M
ΩR13
22 k
ΩR16
25.5 k
Ω
R17
3.9k
ΩR18
33 k
ΩR19
220 k
ΩR20
2.7 k
ΩR21
5.6 k
Ω
R22,24,27
30 k
ΩR23,30,31,32,33
150 k
ΩR25,26,28,29
499 k
ΩR34
12 k
Ω
C1,3
1
µ
F
C2
220
µ
F
C4
330
µ
F
C510 nF C6
1
µ
F
C71.8 nF C8
1
µ
F
C10 120 nF C11 1 nF C12 5.6 nF
C13 470 nF C14 2.7 nF C15 100 nF C16 390 nF
NTC
2.5
B 57364 F1 15 A
L4981A/B
4
1
20 8 2
11
6
18
17
12
14
3
95
15
16
7
10
19
F1
C1
L1
D5D6
R9R10
C3
NTC
C4
R11
R12
R14
R15
C5
R17
C6
C7
R18
C8
R19
C10
R21
C12
13
L2a
L2b
L2c
DETAIL for L2
L2b
L2c
L2a
Vcc
Vcc
L3
Vcc
D1+D2+D3+D4
R1
Dz1C2
D8R3R4
D9
R6
Q2Q
3
R7
Q5
D11 D12
R8
D13
R13 R16
R20
R22
C13
R23
C14
C15 C16
R24 R25 R26
R27 R28 R29
R30 R31
R32 R33
Input
C11
R36
R35
C9
AN1606 APP LICATION NO TE
16/18
L1=440
µ
H; => E55*28*21-21+21 turns 2.5mm/gapped# 14 w ires // m=0.4 mm each.
D
5,6
= STTH8R06FP; Q
2,3
= STW26NM50F
Note:
For the evaluation circuit and external coupled inductor EMC where utilized.
The filter has been achieved as follows: -
Coupled inductor (30 + 30) turns; wire diameter = 0.8mm on a toroidal (40x16x8.5 mm): -
Magnetizing inductance (each half inductor) Lm=8mH and a leakage inductance, Ld=50uH.
Conclusion:
The innovative bridgel ess PFC confi guration as desc ribed in this application note has been successful ly tested.
Details have been presented how to implement the technology, which should prove interesting to designers.
Figure 12 shows the test results of efficiency and power dissipation for the application's 800W prototype.
Figure 12.
EFFICIENCY
92
93
94
95
96
97
98
88 110 132 154 176 198 220 242 264
[%]
Vin
B.Less
Standard PFC
P0=800 W
DISSIPATED POWER
0
10
20
30
40
50
60
70
80
88 110 132 154 176 198 220 242 264
Vin
[w]
B.Less
Standard PFC
P0=800 W
EFFICIENCY
92
93
94
95
96
97
98
88 110 132 154 176 198 220 242 264
[%]
Vin
B.Less
Standard PFC
P0=800 W
EFFICIENCY
92
93
94
95
96
97
98
88 110 132 154 176 198 220 242 264
[%]
Vin
B.Less
Standard PFC
P0=800 WP0=800 W
DISSIPATED POWER
0
10
20
30
40
50
60
70
80
88 110 132 154 176 198 220 242 264
Vin
[w]
B.Less
Standard PFC
P0=800 W
DISSIPATED POWER
0
10
20
30
40
50
60
70
80
88 110 132 154 176 198 220 242 264
Vin
[w]
B.Less
Standard PFC
DISSIPATED POWER
0
10
20
30
40
50
60
70
80
88 110 132 154 176 198 220 242 264
Vin
[w]
B.Less
Standard PFC
B.Less
Standard PFC
P0=800 WP0=800 W
17/18
AN1606 APPLICATION NOTE
Evaluation results for the 800W version.
Evaluation results for the 600W version.
References: -
a)
P arsad N. Enjeti, R. Martinez "A high per formance single phase A C to DC r ectifier with input power factor
correction" IEEE AP EC'93
b)
Alexandre Ferrari de Souza and Ivo Barbi "A new ZVS Semi resonant High Power Factor Rectifier with Re-
duced Conduction Losses"
IEE TRANSACTIONS ON INDUSTRIAL ELECTRON ICS, VOL.46, NO.1 FEBRUARY 1999.
c)
STM Application Notes AN628; AN824.
STMicroelectronics @ www.st.com, http://ccd.sgp.st.com/stonline/books/index.htm
@Vin=110Vac: Nominal power
Vout Pout Pin PF TDH Efficiency
395VDC 800W 860W 0.999 4 94%
@Vin=220Vac: Nominal power
395VDC 800W 824W 0.997 8 97%
@Vin=110Vac: Nominal power
Vout Pout Pin PF TDH Efficiency
395VDC 652W 700W 0.998 6.7 93%
@Vin=220Vac: Nominal power
395VDC 652W 624W 0.994 9 96.5%
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by i m pl i cat i on or oth erwi se under any pat ent or pat ent r i ghts of S T M i croelectroni cs. Spec i ficat i ons m ent i oned i n this public at ion are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics product s are not
authorized f or use as c ritical com ponents in li fe su pport dev i ces or sy st ems wi t hout exp ress wri tt en approva l of STMi croelectr onics.
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18/18
AN1606 APP LICATION NO TE
