ICS9250-10 Integrated Circuit Systems, Inc. Frequency Timing Generator for Pentium II Systems General Description The ICS9250-10 is a single chip clock for Intel Pentium II. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces EMI by 8dB to 10 dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-10 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Block Diagram Features Generates the following system clocks: - 3 CPU (2.5V) 66.6/100 MHz (up to 133MHz through I2C selection) - 9 SDRAM (3.3V) up to 133MHz - 8 PCI (3.3 V) @33.3MHz - 2 IOAPIC (2.5V) @16.67 or 33.3MHz - 2 Hublink clocks (3.3 V) @ 66.6 MHz - 2 USB (3.3V) @ 48 MHz ( Non spread spectrum) - 1 REF (3.3V) @ 14.318 MHz Supports spread spectrum modulation , down spread 0 to -0.5% I2C support for power management Efficient power management scheme through PD# Uses external 14.138 MHz crystal Pin Configuration 56-Pin 300 mil SSOP *60K ohm pull-up to VDD on indicated inputs. Power Groups Pentium II is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9250-10 Rev K 12/14/01 VDD0, GND0 = REF & Crystal VDD1, GND1 = 3V66 [1:0] VDD2, GND2 = PCICLK[7:0] VDD3, GND3 = PLL core VDD4, GND4 = 48MHz [1:0] VDD5, GND5 = SDRAM_F, SDRAM [7:0] VDDL0, GNDL0 = CPUCLK [2:0] VDDL1, GNDL1 = IOAPIC [1:0] ICS9250-10 Pin Descriptions PIN NUMBER 3 X1 IN 4 X2 OUT DESCRIPTION Latched input at Power On. this determines the IOAPIC frequency. When a "0" is latched, IOAPIC Freq=16.67MHz When "1" is latched, IOAPIC Freq=33.3MHz This pin has a 60K internal pull-up. 3.3V, 14.318MHz reference clock output. Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) 5, 6, 14, 17, 23, 24, 35, 41, 47 GND (0:5) PWR Ground pins for 3.3V supply 8, 7 3V66 [1:0] OUT 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B PWR 3.3V power supply OUT 3.3V PCI clock outputs, with Synchronous CPUCLKS OUT 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t s f o r U S B 1 P I N NA M E FREQ_APIC REF0 2, 9, 10, 21, VDD (0:5) 22, 27, 33, 38, 44 20,19,18,16, PCICLK[7:0] 15,13,12,11 TYPE IN OUT 25, 26 48MHz (0:1) 28, 29 FS (0:1) IN Function Select pins. Determines CPU frequency, all output functionality. Please refer to Functionality table on page 3. 30 SDATA IN Data input for I2C serial input. 31 SCLK IN Clock input of I2C input 32 PD# IN 36, 37, 39, 40, 42, SDRAM [7:0] 43, 45, 46 OUT Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. 3.3V output running 100MHz. All SDRAM outputs can be turned off through I2C 34 SDRAM_F OUT 3.3V free running 100MHz SDRAM not affected by I2C 56,48 GNDL [1:0] PWR Ground for 2.5V power supply for CPU & APIC CPUCLK [2:0] OUT 2.5V Host bus clock output. 66MHz or 100MHz depending on FS (0:1) pins Refer page 3. 51, 53 VDDL (0:1) PWR 2.5V power suypply for CPU & IOAPIC 54, 55 IOAPIC [1:0] OUT 2.5V clock outputs running at 16.67MHz or 33.3MHz. 49,50,52 2 ICS9250-10 Functionality Table FS1 FS0 CPU SDRAM 3V66 PCICLK 48MHz REF0 IOAPIC 0 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z 0 1 TCLK/2 TCLK/4 TCLK/4 TCLK/8 TCLK/2 TCLK TCLK/16 1 0 66 MHz 100 MHz 66 MHz 33 MHz 48 MHz 14.318MHz 16.67MHz 1 1 100 MHz 100 MHz 66 MHz 33MHz 48 MHz 14.318MHZ 16.67MHz Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 48MHz Osc VCOs 0 LOW LOW LOW LOW LOW LOW OFF OFF 1 ON ON ON ON ON ON ON ON Select Functions FS1 FS0 Notes 0 0 Tristate 0 1 Test Mode 1 0 Active CPU = 66MHz 1 1 Active CPU = 100MHz 3 Notes Tristate Test Mode ICS9250-10 Power Down Waveform Note 1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz Maximum Allowed Current Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 2.625V All static inputs = Vddq3 or GND Max 2.5V supply consumption Max discrete cap loads, Vddq2 = 3.465V All static inputs = Vddq3 or GND Powerdown Mode (PWRDWN# = 0 10mA 10mA Full Active 66MHz SEL1, 0 = 10 70mA 280mA Full Active 100MHz SEL1, 0 = 11 100mA 280mA 810E Condition 4 ICS9250-10 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. ICS (Slave/Receiver) The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 5 ICS9250-10 Byte 5:ICS Reserved Functionality and frequency select register (Default=0) Bit Desctiption PWD Bit7 ICS RESERVED BIT (Needs to be 0 clock to operate normal) 0 Bit6 ICS RESERVED BIT (Needs to be 0 clock to operate normal) 0 Bit5 ICS RESERVED BIT (Needs to be 0 clock to operate normal) 0 Bit (4,3,0) Bit (4,3,0) CPUCLK SDRAM MHz MHz 3V66 MHz PCICLK MHz 100 66.67 33.33 70.67 106 70.67 35.33 0 74.66 112 74.67 37.33 1 1 82.66 124 82.66 41.33 1 0 0 63.5 95.25 63.5 31.75 0 1 0 1 68.67 103 68.67 34.33 0 1 1 0 72.67 109 72.67 36.33 0 1 1 1 88.66 133 88.66 44.33 1 0 0 0 100 100 66.67 33.33 1 0 0 1 106 106 70.67 35.33 1 0 1 0 11 2 112 74.67 37.33 1 0 1 1 12 4 124 82.66 41.33 1 1 0 0 95.25 95.25 63.5 31.75 1 1 0 1 10 3 103 68.67 34.33 1 1 1 0 109 109 72.67 36.33 1 1 1 1 133 133 88.66 44.33 FS0 (HW) SEL3 (Bit4) SEL2 (Bit3) SEL1 (Bit0) 0 0 0 0 66.67 0 0 0 1 0 0 1 0 0 0 XXXX Note 1 Bit2 Not used (Needs to be 1 for normal clock operation) 1 Bit1 Not used (Needs to be 1 for normal clock operation) 1 Note1: Default at power-up will be for latched logic inputs to define frequency, as diplayed by Bit 3. 6 ICS9250-10 Byte 0: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Pin# Bit 3 Bit 2 Bit 1 Bit 0 26 25 49 Name Reserved Reserved Reserved Reserved SpreadSpectrum (1=On/0=Off) 48MHz 1 48MHz 0 CPUCLK2 PWD 0 0 0 1 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) 1 (Active/Inactive) 1 1 1 (Active/Inactive) (Active/Inactive) (Active/Inactive) PWD 1 1 1 1 1 1 1 1 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) PWD 1 1 1 1 1 1 1 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Byte 1: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 36 37 39 40 42 43 45 46 Name SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0 Byte 2: Control Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 20 19 18 16 15 13 12 - Name PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 Reserved Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default 7 ICS9250-10 Byte 3: Reserved Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved PWD 0 0 0 0 0 0 0 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) PWD 0 0 0 0 0 0 0 0 Description (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) (Active/Inactive) Byte 4: Reserved Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# - Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default Absolute Maximum Ratings Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 4.6 V I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. 8 ICS9250-10 Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage SYMBOL VIH Input Low Voltage VIL Input High Current IIH Input Low Current VIN = VDD -5 5 A IIL1 VIN = 0 V; Inputs with no pull-up resistors -5 2 IIL2 VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz CL = Max loads; Select @ 66 MHz CL = Max loads; Select @ 100 MHz -200 -100 97 91 100 275 267 110 105 130 310 300 CL = Max loads; Select @ 133 MHz CL = 0 pF; Select @ 66 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 133 MHz CL = Max loads; Select @ 66 MHz CL = Max loads; Select @ 100 MHz 278 8 11 13 22 31 350 10 15 20 70 100 37 130 IDD3.3PD CL = Max loads; Select @ 133 MHz CL = Max loads 220 400 IDD.25PD Input address VDD or GND <1 14.32 10 16 Input Frequency Fi Pin Inductance Lpin CIN Transition time 1 1 Settling time 1 Clk Stabilization 1 Delay 1 MAX UNITS VDD+0.3 V V IDD2.5OP Input Capacitance TYP 0.8 Operating Supply Current 1 MIN 2 VSS-0.3 IDD3.3OP Powerdown Current CONDITIONS VDD = 3.3 V 12 A 7 Logic Inputs Output pin capacitance CINX X1 & X2 pins Ttrans 6 27 mA mA mA A MHz nH 5 COUT mA pF pF 45 pF To 1st crossing of target frequency 5 ms Ts From 1st crossing to 1% target frequency 5 ms TST AB tPZH,tPZL From VDD = 3.3 V to 1% target frequency 5 ms Output enable delay (all outputs) 1 10 ns tPHZ,tPLZ Output disable delay (all outputs) 1 10 ns Guaranteed by design, not 100% tested in production. 9 ICS9250-10 Electrical Characteristics - CPU TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Output Impedance RDSP2B1 RDSN2B1 MIN TYP VO = VDD*(0.5) 13.5 16 45 13.5 2 21 45 VOH2B VO = VDD*(0.5) IOH = -1 mA V Output Low Voltage VOL2B IOL = 1 mA 0.4 V Output High Current IOH2B Output Low Current IOL2B Output Impedance Output High Voltage Rise Time 1 VOH @ MIN = 1.0 V -27 VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V -68 -9 27 VOL @ MAX = 0.3 V MAX UNITS -27 54 11 30 mA mA tr2B VOL = 0.4 V, VOH = 2.0 V 0.4 1.45 1.6 ns tf2B VOH = 2.0 V, VOL = 0.4 V 0.4 1.35 1.6 ns dt2B VT = 1.25 V 45 51 55 % tsk2B VT = 1.25 V 114 175 ps tjcyc-cyc2B VT = 1.25 V 157 250 ps MIN TYP MAX UNITS VO = VDD*(0.5) 12 14 55 12 2.4 14.5 55 VOH1 VO = VDD*(0.5) IOH = -1 mA V Output Low Voltage VOL1 IOL = 1 mA 0.55 V Output High Current IOH1 Output Low Current IOL1 Fall Time 1 1 Duty Cycle 1 Skew window Jitter, Cycle-to-cycle 1 CONDITIONS 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 3V66 TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Output Impedance RDSP1B1 RDSN1B1 Output Impedance Output High Voltage Rise Time Fall Time 1 1 1 Duty Cycle 1 Skew window Jitter, Cycle-to-cycle 1 1 CONDITIONS VOH @ MIN = 1.0 V -33 VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V -108 -9 30 VOL @ MAX = 0.4 V -33 95 29 38 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1.3 1.6 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.29 1.6 ns dt1 VT = 1.5 V 45 51.9 55 % tsk1 VT = 1.5 V 77 175 ps tjcyc-cyc1 VT = 1.5 V 129 500 ps Guaranteed by design, not 100% tested in production. 10 ICS9250-10 Electrical Characteristics - IOAPIC TA = 0 - 70C; VDDL = 2.5 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Output Impedance RDSP4B1 RDSN4B1 MIN TYP VO = VDD*(0.5) 9 16 30 9 2 20 30 VOH4B VO = VDD*(0.5) IOH = -1 mA V Output Low Voltage VOL4B IOL = 1 mA 0.4 V Output High Current IOH4B Output Low Current IOL4B Output Impedance Output High Voltage Rise Time Fall Time 1 1 1 Duty Cycle 1 Skew window Jitter, Asolute 1 1 CONDITIONS VOH @ MIN = 1.0 V -27 VOH @ MAX = 2.375 V VOL @ MIN = 1.2 V -68 -9 27 VOL @ MAX = 0.3 V MAX UNITS -27 54 11 30 mA mA tr4B VOL = 0.4 V, VOH = 2.0 V 0.4 1.4 1.6 ns tf4B VOH = 2.0 V, VOL = 0.4 V 0.4 1.45 1.6 ns dt4B VT = 1.25 V 45 49.9 55 % tsk4B VT = 1.25 V 20 250 ps tabs VT = 1.25 V 127 500 ps MIN TYP MAX UNITS VO = VDD*(0.5) 10 12 24 VO = VDD*(0.5) VOH @ MIN = 2.0 V 10 -54 15 -92 24 -16 -46 Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Impedance RDSP3B1 RDSN3B1 Output High Current IOH3 Output Low Current IOL3 Output Impedance Rise Time Fall Time 1 1 1 Duty Cycle 1 Skew window Jitter, Cycle-to-cycle 1 1 VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V 54 VOL @ MAX = 0.4 V 68 29 53 mA mA tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 1 1.6 ns tf3 VOH = 2.4 V, VOL = 0.4 V 0.4 1.1 1.6 ns dt3 VT = 1.5 V 45 50.5 55 % tsk3 VT = 1.5 V 148 250 ps VT = 1.5 V, 66, 100 MHz 152 250 ps tjcyc-cyc3 Guaranteed by design, not 100% tested in production. 11 ICS9250-10 Electrical Characteristics - PCI TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL Output Impedance RDSP1B1 RDSN1B1 MIN TYP VO = VDD*(0.5) 12 15 55 12 2.4 15 55 VOH1 VO = VDD*(0.5) IOH = -1 mA V Output Low Voltage VOL1 IOL = 1 mA 0.55 V Output High Current IOH1 Output Low Current IOL1 Output Impedance Output High Voltage Rise Time 1 VOH @ MIN = 1.0 V -33 VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V -106 -14 30 VOL @ MAX = 0.4 V MAX UNITS -33 94 29 38 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 0.4 1.75 2 ns tf1 VOH = 2.4 V, VOL = 0.4 V 0.4 1.55 2 ns dt1 VT = 1.5 V 45 50.5 55 % tsk1 VT = 1.5 V 270 500 ps tjcyc-cyc1 VT = 1.5 V 160 500 ps MIN TYP MAX UNITS VO = VDD*(0.5) 20 29 60 20 2.4 27 60 VOH15 VO = VDD*(0.5) IOH = -1 mA V Output Low Voltage VOL5 IOL = 1 mA 0.55 V Output High Current IOH5 Output Low Current IOL5 Fall Time 1 1 Duty Cycle 1 Skew window Jitter, Cycle-to-cycle 1 CONDITIONS 1 Guaranteed by design, not 100% tested in production. Electrical Characteristics - REF, 48MHz_0(Pin25) TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL Output Impedance RDSP5B1 RDSN5B1 Output Impedance Output High Voltage Rise Time Fall Time 1 1 1 Duty Cycle Jitter, absolute 1 CONDITIONS VOH @ MIN = 1.0 V -29 VOH @ MAX = 3.135 V VOL @ MIN = 1.95 V -54 -11 29 VOL @ MAX = 0.4 V -23 54 16 27 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 0.4 2.35 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 0.4 2.65 4 ns dt5 VT = 1.5 V 45 52 55 % tabs VT = 1.5 V, 332 500 ps Guaranteed by design, not 100% tested in production. 12 ICS9250-10 Electrical Characteristics - 48MHz_1 (Pin 26) TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 20-30 pF (unless otherwise specified) PARAMETER SYMBOL Output Impedance RDSP3B1 RDSN3B1 MIN TYP VO = VDD*(0.5) 10 15 24 10 2.4 15 24 VOH3 VO = VDD*(0.5) IOH = -1 mA V Output Low Voltage VOL3 IOL = 1 mA 0.55 V Output High Current IOH3 Output Low Current IOL3 Output Impedance Output High Voltage Rise Time Fall Time 1 1 1 Duty Cycle 1 Jitter, Cycle-to-cycle 1 CONDITIONS VOH @ MIN = 2.0 V -54 VOH @ MAX = 3.135 V VOL @ MIN = 1.0 V -82 -20 54 VOL @ MAX = 0.4 V MAX UNITS -46 95 28 53 mA mA tr3 VOL = 0.4 V, VOH = 2.4 V 0.4 1.1 1.6 ns tf3 VOH = 2.4 V, VOL = 0.4 V 0.4 1.3 1.6 ns dt3 VT = 1.5 V 45 53 55 % tjcyc-cyc3B VT = 1.5 V 130 250 ps Guaranteed by design, not 100% tested in production. 13 ICS9250-10 Group Offset Waveforms Group Skews at Common Transition Edges: (CPU = 66MHz) CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf. GROUP SYMBOL CONDITIONS MIN CPU @ 1.25V, 3V66 @ 1.5V CPU to 3V66 SCPU1-3V66 0 (Note: 180 offset between CPU & 66MHz CPU @ 1.25V, SDRAM @ 1.5V CPU to SDRAM SCPU2-SDRAM 0 (Note: 180 offset between CPU & 66MHz 1.5 3V66 to PCI S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V IOAPIC to PCI SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V 0 1 TYP MAX UNITS 500 ps 500 ps 4 500 ns ps Guarenteed by design, not 100% tested in production. Group Skews at Common Transition Edges: (CPU = 100MHz) CPU & IOAPIC load (lumped) = 20pf; PCI, SDRAM, 3V66 LOAD (LUMPED) = 30pf. GROUP SYMBOL CONDITIONS MIN CPU @ 1.25V, 3V66 @ 1.5V 0 CPU to 3V66 SCPU1-3V66 (Note: 180 offset between CPU & 100MHz CPU @ 1.25V, SDRAM @ 1.5V CPU to SDRAM SCPU2-SDRAM 0 (Note: 180 offset between CPU & 100MHz 1.5 3V66 to PCI S3V66-PCI 3V66 @ 1.5V, PCI @ 1.5V IOAPIC to PCI SIOAPIC-PCI IOAPIC @ 1.25V, PCI @1.5V 0 1 Guarenteed by design, not 100% tested in production. 14 TYP MAX UNITS 500 ps 500 ps 4 500 ns ps ICS9250-10 General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance. Notes: 1) All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram. 2) 47 ohm / 56pf RC termination should be used on all over 50MHz outputs. 3) Optional crystal load capacitors are recommended. Capacitor Values: C1, C2 : Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01F ceramic Connections to VDD: 15 ICS9250-10 SSOP Package SYMBOL A A1 A2 B C D E e H h L N X COMMON DIMENSIONS MIN. NOM. MAX. .095 .101 .110 .008 .012 .016 .088 .090 .092 .008 .010 .0135 .005 .006 .0085 See Variations .292 .296 .299 0.025 BSC .400 .406 .410 .010 .013 .016 .024 .032 .040 See Variations 0 5 8 .085 .093 .100 VARIATIONS AC AD MIN. .620 .720 D NOM. .625 .725 N MAX. .630 .730 48 56 Ordering Information ICS9250yF-10 Example: ICS XXXX y F - PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 16 PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.