PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM SYNCHRONOUS DRAM MT48LC32M16S2 MT48LC16M16T2 MT48LC16M16B2 Features * * * * * * * * * * * * * MT48V16M16B2 MT48H32M16S2 MT48H16M16T2 MT48H16M16B2 1 2 3 A VSS DQ15 B DQ14 C 4 5 6 7 8 9 VSSQ VDDQ DQ0 VDD DQ13 VDDQ VSSQ DQ2 DQ1 DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 E DQ8 CS#(1) VSS VDD LDQM DQ7 F UDQM CLK CKE CAS# RAS# WE# G A12 A11 A9 BA0 BA1 CS#(0) H A8 A7 A6 A0 A1 A10 J VSS A5 A4 A3 A2 VDD Marking LC V H1 16M16 32M16 NOTE: The # symbol indicates signal is active LOW. Each Die S2 T2 B2 Configuration 32 Meg x 16 16 Meg x 16 8 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks Refresh Count FG 8K 8K Row Addressing 8K (A0-A12) 8K (A0-A12) Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1) Column Addressing 512 (A0-A8) 512 (A0-A8) -8 Table 1: None Key Timing Parameters ACCESS TIME NOTE: 1. Contact Micron for availability. Part Number Example: 09005aef80906b6e 256mb_512mbSDRAM_twindie_1.fm - Rev. C 10/03 EN SPEED GRADE CLOCK FREQUENCY CL=2* SETUP TIME HOLD TIME -8 100 MHz 8.0ns 2.5ns 1.0ns *CL= CAS (READ) latency MT48LC32M16S2FG-8 PRODUCTS MT48V16M16T2 Figure 1: Ball Assignment (Top View) 54-Ball FBGA Low voltage power supply Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes Self Refresh Mode 64ms, 8,192-cycle refresh LVTTL-compatible inputs and outputs Deep Power Down Partial Array Self Refresh power-saving mode Temperature Compensated Self Refresh (TCSR) Options * VDD\VDDQ 3.3V\3.3V 2.5V\2.5V or 1.8V 1.8V\1.8V * Configurations 16 Meg x 16 (4 Meg x 16 x 4 banks) 32Meg x 16 (8 Meg x 16 x 4 banks) * Die Options Both Die Functional Top Die Only Functional Bottom Die Only Functional * Plastic Package - OCPL1 54-ball FBGA (8mm x 14mm) * Timing (Cycle Time) 10ns @ CL = 2 (100 MHz) * Operating Temperature Commercial (0oC to +70oC) MT48V32M16S2 1 (c)2003 Micron Technology, Inc. All rights reserved. AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 2: 512Mb TwinDie SDRAM Part Numbers PART NUMBER VDD VDDQ MT48LC32M16S2 MT48LC16M16T2 MT48LC16M16B2 MT48V32M16S2 MT48V16M16T2 MT48V16M16B2 MT48H32M16S2 MT48H16M16T2 MT48H16M16B2 3.3V 3.3V 3.3V 2.5V 2.5V 2.5V 1.8V 1.8V 1.8V 3.3V 3.3V 3.3V 2.5V or 1.8V 2.5V or 1.8V 2.5V or 1.8V 1.8V 1.8V 1.8V CONFIGURATION 8 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks 8 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks 8 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks FUNCTIONAL DIE BOTH TOP BOTTOM BOTH TOP BOTTOM BOTH TOP BOTTOM General Description The Micron(R) TwinDieTM 512Mb SDRAM is a highspeed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured by stacking two 256Mb, 16Megx16 devices. Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous interface. They are organized with 16 DQs with 4 banks of 67,108,864 bits, comprising of 8,192 rows by 512 columns by 16 bits wide. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to 09005aef80906b6e 256mb_512mbSDRAM_twindie_1.fm - Rev. C 10/03 EN be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V or 2.5V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. NOTE: 1. Throughout the data sheet, the various figures and text may refer to CS0# and CS1# as "CS#." The CS# term is to be interpreted for single die operation, unless specifically stated otherwise. 2. Complete functionality is described throughout the document and any one page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. Any specific requirement takes precedence over a general statement. 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Functionality (Per Die). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Deep power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Commands Per Die . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 POWER-DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Concurrent AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 TwinDie Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Commands (TwinDie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 09005aef80906b6e 256mb_512mbSDRAM_twindieTOC.fm - Rev. C 10/03 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Notes (Single Die) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Rev C, 10/27/2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Rev B, 02/27/03 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Rev A, 11/25/02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 09005aef80906b6e 256mb_512mbSDRAM_twindieTOC.fm - Rev. C 10/03 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Ball Assignment (Top View) 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Block Diagram 16 Meg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Activating a Specific Row In a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 READ to WRITE with Extra Clock Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE To READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 WRITE To PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Terminating a WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Deep Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 READ With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 WRITE With Auto Precharge Interrupted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Initialize And Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power-down Mode1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Clock Suspend Mode1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 READ - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 READ - With Auto Precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Single READ - Without Auto Precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Single READ - With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Alternating Bank Read Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Read - Full-page Burst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Read DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Write - Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Write - With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Single Write - Without Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Single Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Alternating Bank Write Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Write - Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Write - DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 FGBA "FG" Package 54-pin, 8mm x 14mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 09005aef80906b6e 256mb_512mbSDRAM_twindieLOF.fm - Rev. C 10/03 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 512Mb TwinDie SDRAM Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 54-Ball FBGA Ball Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Truth Table - Commands And DQM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Truth Table - Current State Bank n - Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Truth Table - Current State Bank n - Command To Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 DC Electrical Characteristics And Operating Conditions - "LC" Version . . . . . . . . . . . . . . . . . . . . . . . .36 DC Electrical Characteristics And Operating Conditions - "V" Version . . . . . . . . . . . . . . . . . . . . . . . . .36 DC Electrical Characteristics And Operating Conditions - "H" Version. . . . . . . . . . . . . . . . . . . . . . . . .37 IDD Specifications And Conditions (Both Die - S2 Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 IDD7 - Self Refresh Current Options- S2 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Electrical Characteristics And Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .39 AC Functional Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 09005aef80906b6e 256mb_512mbSDRAM_twindieLOT.fm - Rev. C 10/03 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 2: Functional Block Diagram CS#0 CLK CKE# CS#1 TOP BOTTOM DIE DIE Command Addresses DQ0-15, DQM 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 3: Functional Block Diagram 16 Meg x 16 SDRAM CKE CLK COMMAND DECODE CS# 0 CS# 1 WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1 MODE REGISTER REFRESH 13 COUNTER 12 ROWADDRESS MUX 13 13 BANK0 ROWADDRESS LATCH & DECODER 8192 BANK0 MEMORY ARRAY (8,192 x 512 x 16) 2 DQML, DQMH SENSE AMPLIFIERS 16 8192 I/O GATING DQM MASK LOGIC READ DATA LATCH WRITE DRIVERS 2 A0-A12, BA0, BA1 15 ADDRESS REGISTER 2 BANK CONTROL LOGIC DATA OUTPUT REGISTER 16 16 512 (x16) 2 DQ0DQ15 DATA INPUT REGISTER COLUMN DECODER 9 COLUMNADDRESS COUNTER/ LATCH 9 NOTE: This device is a 512Mb SDRAM part made up of two stacked 256Mb SDRAM components. The above drawing illustrates one of the 256Mb SDRAM components. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 3: 54-Ball FBGA Ball Descriptions BALL NUMBERS SYMBOL TYPE DESCRIPTION F2 CLK Input F3 CKE Input G9, E2 CS#(0) CS#(1) Input F7, F8, F9 CAS#, RAS#, WE# LDQM, UDQM Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Clock Enable: CKE activates (HIGH) and deactactivates (LOW) the CLK signal. Deactivating the CLK provides POWER-DOWN and SELFREFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. CS#(0) (BOTTOM DIE) is used to select the 256Mb chip, CS#(1) (TOP DIE) is used to select the 256Mb chip. Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the command being entered. G7, G8 BA0, BA1 Input H7, H8, J8, J7, J3, J2, H3, H2, H1, G3, H9, G2, G1 A0-A12 Input A8, B9, B8, C9, C8, D9, D8, E9, E1, D2, D1, C2, C1, B2, B1, A2 A7, B3, C7, D3 A3, B7, C3, D7, A9, E7, J9 A1, E3, J1 DQ0DQ15 I/O VDDQ Supply Supply Supply Supply E8, F1 VSSQ VDD VSS 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when during a READ cycle. LDQM corresponds to DQ0DQ7, UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered same state when referenced as DQM. Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ, WRITE or PRECHARGE command is being applied. These pins also provide the op- code during a LOAD MODE REGISTER command Address Inputs: A0-A12 are sampled during the ACTIVE command (rowaddress A0-A11) and READ/WRITE command (column-address A0-A8; with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command. Data Input/Output: Data bus DQ Power: Provide isolated power to DQs for improved noise immunity. DQ Ground: Provide isolated ground to DQs for improved noise immunity. Power Supply: Voltage dependant on option. Ground 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Functional Description Functionality (Per Die) The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured by stacking two 256Mb, 16Megx16 devices. Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous interface. They are organized with 16 DQs with 4 banks of 67,108,864 bits, comprising of 8,192 rows by 512 columns by 16 bits wide. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 512Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, highspeed, random-access operation. The 512Mb SDRAM is designed to operate in 3.3V or 2.5V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering die intitialization, register definition, command descriptions, and device operation on a per die basis unless otherwise noted. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100s delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100s period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied. Once the 100s delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command. Register Definition Mode Register The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 4. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power. Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use. Address A12 (M12) is undefined but should be driven LOW during loading of the Mode Register. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Burst Length Figure 4: Mode Register Definition Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 4. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A9 (x16) when the burst length is set to two; by A2-A9 (x16) when the burst length is set to four; and by A3-A9 (x16) when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached. BA1 BA0 A12 14 0 13 0 12 A11 A10 11 10 Reserved* A9 9 WB 8 7 Op Mode A6 A5 A4 6 5 4 CAS Latency A3 A2 3 Mode Register (Mx) Burst Length M2 M1 M0 M3 = 0 M3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type 0 Sequential 1 Interleaved M6 M5 M4 11 0 Burst Length M3 Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 4. Address Bus A0 A1 1 2 BT *Should program M12, M11, M10 = "0, 0, 0" to ensure compatibility with future devices. Burst Type 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN A7 A8 CAS Latency 0 0 0 Reserved 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 4: Burst Definition CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 5. Table 5 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. ORDER OF ACCESSES WITHIN A BURST BURST LENGTH 2 4 8 Full Page (y) STARTING COLUMN ADDRESS A0 0 1 A1 A0 0 0 0 1 1 0 1 1 A2 A1 A0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 n = A0A12/11/9 (location 0-y) TYPE = SEQUENTIAL TYPE = INTERLEAVED 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 0-1-2-3 1-0-3-2 2-3-0-1 3-0-1-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Cn, Cn + 1, Cn +2 Cn + 3, Cn + 4... ...Cn - 1, Cn... 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Not Supported Figure 5: CAS Latency T0 T1 T2 T3 READ NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 2 NOTE: 1. For full-page accesses: y = 1,024 (x16). 2. For a burst length of two, A1-A9 (x16) select the block-of-two burst; A0 selects the starting column within the block. T0 T1 T2 T3 COMMAND 3. For a burst length of four, A2-A9 (x16) select the block-of-four burst; A0-A1 select the starting column within the block. READ NOP NOP NOP tLZ tOH DOUT DQ tAC 4. For a burst length of eight, A3-A9 (x16) select the block-of-eight burst; A0-A2 select the starting column within the block. CAS Latency = 3 DON'T CARE UNDEFINED 5. For a full-page burst, the full row is selected and A0-A9 (x16) select the starting column. Operating Mode 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. 7. For a burst length of one, A0-A9 (x16) select the unique column to be accessed, and Mode Register bit M3 is ignored. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN T4 CLK 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Write Burst Mode The Extended Mode Register is programmed via the Mode register Set command (BA1=1, BA0=0) and retains the stored information until it is programmed again or the device loses power. The Extended Mode Register must be programmed with M6 through M12 set to "0". The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating these requirements results in unspecified operation. The Extended Mode Register must be programmed in order to use this device properly. When M9 = 0, the burst length programmed via M0M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses. Table 5: CAS Latency ALLOWABLE OPERATING FREQUENCY (MHZ) SPEED CAS LATENCY = 2 -8 100 Temperature Compensated Self Refresh Figure 6: Extended Mode Register BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus 14 13 12 11 10 9 Extended Mode Register (Ex) 1 0 8 7 6 All have to be set to "0" A4 A5 Driver Strength 5 4 DS TCSR 3 2 1 0 PASR A3 Maximum Case Temp 1 1 RFU 0 70C 0 Half Strength 0 1 Full Strength 0 1 45C 1 0 RFU A2 A1 A0 0 0 0 Four Banks 0 0 1 Two Banks (BA1=0) 0 1 0 One Bank (BA1=BA0=0) 0 1 1 RFU 1 0 0 RFU 1 0 1 Half Bank (BA1=BA0=0) 1 1 0 Quarter Bank (BA1=BA0=0) 1 1 1 RFU NOTE: Temperature Compensated Self Refresh allows the controller to program the Refresh interval during SELF REFRESH mode, according to the case temperature of the Mobile Ram device. This allows great power savings during SELF REFRESH during most operating temperature ranges. Only during extreme temperatures would the controller have to select a TCSR level that will guarantee data during SELF REFRESH. Every cell in the DRAM requires refreshing due to the capacitor losing its charge over time. The refresh rate is dependent on temperature. At higher temperatures a capacitor loses charge more quickly than at lower temperatures, requiring the cells to be refreshed more often. Historically, during Self Refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected. Thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures. Setting M4 and M3, allow the DRAM to accommodate more specific temperature regions during SELF REFRESH. There are four temperature settings, which will vary the SELF REFRESH current according to the selected temperature. This selectable refresh rate will save power when the DRAM is operating at normal temperatures. Self Refresh Coverage E14 and E13 (BA1 and BA0) must be "1, 0" to select the Extended Mode Register (vs. the base Mode Register). Partial Array Self Refresh For further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. The refresh options are Four Bank; all four banks, Two Bank; banks 0 and 1, One Bank; bank 0, Half Bank; bank 0 with row address MSB 0; Quarter Bank; bank 0 with row address 2 MSBs 0. WRITE and READ commands can still occur during standard oper- Extended Mode Register The Extended Mode Register controls the functions beyond those controlled by the Mode Register. These additional functions are special features of the Mobile Ram device. They include Temperature Compensated Self Refresh (TCSR) control and Partial Array Self Refresh (PASR). 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Driver Strength ation, but only the selected banks will be refreshed during SELF REFRESH. Data in banks that are disabled will be lost. Extended mode register bit A5 must be used to set the DQ output drive strength. Full drive strength is suitable for systems in which the SDRAM component is placed on a module. Half drive strength is recommended for point-to-point or other applications with reduced output loading. The half-strength can be used for point-to-point applications. Point-to-point systems are usually lightly loaded with a memory controller accessing one to eight SDRAM components on the memory bus with module stubs between these devices. Driver strength chosen should be load dependent. The lighter the load, the less driver strength that is needed for the outputs. Deep power Down Deep Power Down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the device. Data will not be retained once the device enters Deep Power Down Mode. This mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS held high at the rising edge of the clock, while CKE is low. This mode is exited by asserting CKE high. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Commands Per Die Table 6 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear following the Operation section; these tables provide current state/next state information. Table 6: Truth Table - Commands And DQM Operation NAME (FUNCTION) CS# RAS# CAS# WE# DQM X X X ADDR DQS NOTES X X X X 3 4 COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) H L L L X H L H X H H L X H H H L/H8 X X Bank/Row Bank/Col WRITE (Select bank and column, and start WRITE burst) DEEP POWER DOWN PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable Write Inhibit/Output High-Z L H L L L/H8 Bank/Col Valid 4 L L L H L L H H L L L H X X X X Code X X X X 9 5 6, 7 L - L - L - L - X L H Op-Code - X Active High-Z 2 8 8 NOTE: 1. 2. 3. 4. 5. 6. 7. 8. 9. CKE is HIGH for all commands shown except SELF REFRESH. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW. A0-A12 provide row address, and BA0, BA1 determine which bank is made active. A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't Care." This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). Standard SDRAM parts assign this command sequence as Burst Terminate. For Mobile Ram devices, the Burst Terminate command is assigned to the Deep Power Down function. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM COMMAND INHIBIT WRITE The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected. The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A9 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The Mode Register is loaded via inputs A0-A11 (A12 should be driven LOW.) See Mode Register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. PRECHARGE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A12 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank. The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. READ AUTO PRECHARGE ACTIVE Auto precharge is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A9 (x16) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet. Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to tRAS and may remain in self refresh mode for an indefinite period beyond that. The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for tXSR because time is required for the completion of any internal refresh in progress. Upon exiting the self refresh mode, AUTO REFRESH commands must be issued every 7.81s or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. BURST TERMINATE The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet. AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required. All active banks must be PRECHARGED prior to issuing a AUTO REFRESH command. The AUTO REFRESH command should not be issued until the minimum tRP has been met after the PRECHARGE command as shown in the operations section. The addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during an AUTO REFRESH command. The 512Mb SDRAM requires 8,192 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 7.81s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 8,192 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every 64ms. Operation Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 7). After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 8, which covers any case where 2 < t RCD (MIN)/tCK - 3. (The same procedure is used to convert other specification limits from time units to clock cycles.) A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by t RC. SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become "Don't Care" with the exception of CKE, which must remain LOW. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM READs Figure 7: Activating a Specific Row In a Specific Bank READ bursts are initiated with a READ command, as shown in Figure 9. The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 10 shows general timing for each possible CAS latency setting. CLK CKE HIGH CS# RAS# CAS# WE# ROW ADDRESS A0-A12 Figure 9: Read Command CLK BANK ADDRESS BA0, BA1 CKE HIGH DON'T CARE CS# RAS# A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by t RRD. CAS# WE# A0-A9: x16 Figure 8: Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK 3 T0 T1 T2 T3 COLUMN ADDRESS A9, A11, A12: x16 T4 ENABLE AUTO PRECHARGE CLK A10 COMMAND ACTIVE NOP NOP READ or WRITE DISABLE AUTO PRECHARGE BA0,1 tRCD BANK ADDRESS DON'T CARE DON'T CARE 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 10: CAS Latency T0 T1 T2 READ NOP NOP Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A full-page burst will continue until terminated. (At the end of the page, it will wrap to the start address and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for CAS latencies of two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed random read accesses can be performed to the same bank, as shown in Figure 12, or each subsequent READ may be performed to a different bank. T3 CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 2 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND tLZ tOH DOUT DQ tAC CAS Latency = 3 DON'T CARE UNDEFINED Figure 11: Consecutive READ Bursts T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP X = 1 cycle BANK, COL b DOUT n+2 DOUT n+1 DOUT n DQ DOUT n+3 DOUT b CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP READ NOP NOP X = 2 cycles BANK, COL b DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 DOUT b CAS Latency = 3 TRANSITIONING DATA DON'T CARE NOTE: Each READ command may be to any bank. DQM is LOW. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 12: Random READ Accesses T0 T1 T2 T3 T4 T5 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DOUT n DQ NOP NOP DOUT x DOUT a DOUT m CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ READ READ READ ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m NOP DOUT a DOUT n DQ NOP DOUT x NOP DOUT m CAS Latency = 3 TRANSITIONING DATA DON'T CARE NOTE: Each READ command may be to any bank. DQM is LOW. Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/ O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a singlecycle delay should occur between the last read data and the WRITE command. The DQM input is used to avoid I/O contention, as shown in Figure 13 and Figure 14 on page 21. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 14 on page 21, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 13 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 14 shows the case where the additional NOP is needed. 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 13: READ to WRITE T0 T1 T2 T3 A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s). In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts. Full-page READ bursts can be truncated with the BURST TERMINATE command, and fixed-length READ bursts may be truncated with a BURST TERMINATE command, provided that auto precharge was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 15 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst. T4 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP WRITE BANK, COL b tCK tHZ DOUT n DQ DIN b tDS TRANSITIONING DATA NOTE: DON'T CARE A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required. Figure 14: READ to WRITE with Extra Clock Cycle T0 T1 T2 T3 T4 T5 CLK DQM COMMAND READ ADDRESS BANK, COL n NOP NOP NOP NOP WRITE BANK, COL b tHZ DOUT n DQ DIN b tDS TRANSITIONING DATA NOTE: DON'T CARE A CAS latency of three is used for illustration. The READ command may be to any bank, and the WRITE command may be to any bank. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 15: Terminating a READ Burst T0 T1 T2 T3 T4 T5 T6 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP X = 1 cycle DOUT n DQ DOUT n+2 DOUT n+1 DOUT n+3 CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND READ ADDRESS BANK, COL n NOP NOP NOP BURST TERMINATE NOP NOP NOP X = 2 cycles DOUT n DQ DOUT n+1 DOUT n+2 DOUT n+3 CAS Latency = 3 NOTE: DQM is LOW. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN TRANSITIONING DATA 22 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM WRITEs the start address and continue.) Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixed-length WRITE burst may be immediately followed by data for a WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided coincident with the new command applies to the new command. An example is shown in Figure 18 (Write to Write). Data n + 1 is either the last of a burst of two or the last desired of a longer burst. The 512Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed random write accesses within a page can be performed to the same bank, as shown in Figure 19, or each subsequent WRITE may be performed to a different bank. WRITE bursts are initiated with a WRITE command, as shown in Figure 16 Write command. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z and any additional input data will be ignored (see Figure 17) Write Burst. A full-page burst will continue until terminated. (At the end of the page, it will wrap to Figure 16: WRITE Command Figure 17: WRITE Burst T0 T1 T2 T3 COMMAND WRITE NOP NOP NOP ADDRESS BANK, COL n CLK CKE CLK HIGH CS# RAS# CAS# DIN n DQ DIN n+1 WE# NOTE: Burst length = 2. DQM is LOW. A0-A9: x16 COLUMN ADDRESS TRANSITIONING DATA A9, A11, A12: x16 DON'T CARE Figure 18: WRITE to WRITE ENABLE AUTO PRECHARGE A10 T0 T1 T2 COMMAND WRITE NOP WRITE ADDRESS BANK, COL n DISABLE AUTO PRECHARGE CLK BA0, BA, 1 BANK ADDRESS DON'T CARE DQ DIN n TRANSITIONING DATA BANK, COL b DIN n+1 DIN b DON'T CARE NOTE: DQM is LOW. Each WRITE command may be to any bank. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 20. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that auto precharge was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued t WR after the clock edge at which the last desired input data element is registered. The auto precharge mode requires a tWR of at least one clock plus time, regardless of frequency. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 21. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. The precharge can be issued coincident with the first coincident clock edge (T2 in Figure 21) on an A1 Version and with the second clock on an A2 Version (Figure 21.) In the case of a fixedlength burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixed-length burst with auto precharge. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixedlength or full-page bursts. Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 22, where data n is the last desired data element of a longer burst. Figure 19: Random WRITE Cycles T0 T1 T2 T3 COMMAND WRITE WRITE WRITE WRITE ADDRESS BANK, COL n BANK, COL a BANK, COL x BANK, COL m DIN n DIN a DIN x DIN m CLK DQ TRANSITIONING DATA NOTE: Each WRITE command may be to any bank. DQM is LOW. Figure 20: WRITE To READ T0 T1 T2 T3 T4 T5 COMMAND WRITE NOP READ NOP NOP NOP ADDRESS BANK, COL n DOUT b DOUT b+1 CLK DQ DIN n BANK, COL b DIN n+1 TRANSITIONING DATA NOTE: 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN DON'T CARE 24 DON'T CARE The WRITE command may be to any bank, and the READ command may be to any bank. DQM is LOW. CAS latency = 2 for illustration. Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 21: WRITE To PRECHARGE T0 T1 T2 T3 T4 T5 T6 NOP ACTIVE NOP CLK tWR @ tCLK 15ns DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE BANK (a or all) BANK a, COL n BANK a, ROW t WR DQ DIN n DIN n+1 tWR = tCLK < 15ns DQM t RP COMMAND ADDRESS WRITE NOP NOP PRECHARGE NOP NOP ACTIVE BANK (a or all) BANK a, COL n BANK a, ROW t WR DQ DIN n+1 DIN n TRANSITIONING DATA DON'T CARE NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two. Figure 22: Terminating a WRITE Burst T0 T1 COMMAND WRITE BURST TERMINATE ADDRESS BANK, COL n (ADDRESS) DIN n (DATA) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. T2 CLK DQ NEXT COMMAND POWER-DOWN Power-down occurs if CKE is registered low coincident with a NOP or COMMAND INHIBIT when no accesses are in progress. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may NOTE: DQMs are LOW. TRANSITIONING DATA DON'T CARE PRECHARGE The PRECHARGE command (see Figure 23) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (tRP) 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting tCKS). (See Figure 24.) NOP input conditions for a minimum of 200us. Issue PRECHARGE commands for all banks. Issue eight or more AUTO REFRESH commands. Issue a MODE REGISTER, set command to initialize mode register. Issue a EXTENDED MODE REGISTER set command to initialize the extended mode register. (See figure 26) Figure 23: PRECHARGE Command Figure 25: Deep Power Down CLK CKE (( )) (( )) CLK HIGH (( )) (( )) CKE CS# (( )) (( )) CS# (( )) (( )) RAS# RAS# (( )) (( )) CAS# CAS# (( )) (( )) WE# WE# A0-A9, A11, A12 Enter deep power-down mode. Exit deep power-down mode. All Banks A10 DON'T CARE Bank Selected CLOCK SUSPEND BANK ADDRESS BA0, BA1 The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the DQ pins remains driven; and burst counters are not incremented, as long as the clock is suspended. (See examples in Figure 26 and Figure 27.) Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge. DON'T CARE Figure 24: Power-Down (( )) (( )) CLK tCKS CKE > tCKS (( )) COMMAND (( )) (( )) NOP NOP All banks idle Input buffers gated off Enter power-down mode. Exit power-down mode. ACTIVE tRCD tRAS tRC DON'T CARE DEEP POWER DOWN BURST READ/SINGLE WRITE Deep Power Down mode is a maximum power savings feature achieved by shutting off the power to the entire memory array of the device. Data will not be retained once Deep Power Down mode is executed. Deep Power Down mode is entered by having all banks idle then /CS and /WE held low with /RAS and /CAS high at the rising edge of the clock, while CKE is low. CKE must be held low during Deep Power Down. In order to exit Deep Power Down mode, CKE must be asserted high. After exiting, the following sequence is needed in order to enter a new command. Maintain 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one), regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0). 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 26: Clock Suspend During WRITE Burst T0 T1 NOP WRITE T2 T3 T4 T5 NOP NOP DIN n+1 DIN n+2 Concurrent AUTO PRECHARGE An access command to (READ or WRITE) another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless theSDRAMsupportsCONCURRENTAUTOPRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below. READ with auto precharge 1. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 28). 2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 29). WRITE with auto precharge 3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the dataout appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 30). 4. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 31). CLK CKE INTERNAL CLOCK COMMAND BANK, COL n ADDRESS DIN n DIN DON'T CARE NOTE: For this example, burst length = 4 or greater, and DM is LOW. Figure 27: Clock Suspend During READ Burst T0 T1 T2 T3 T4 T5 T6 CLK CKE INTERNAL CLOCK COMMAND READ ADDRESS BANK, COL n DQ NOP NOP DOUT n NOP NOP DOUT n+1 TRANSITIONING DATA DOUT n+2 NOP DOUT n+3 DON'T CARE NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and DQM is LOW. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 28: READ With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND NOP BANK n Internal States READ - AP BANK n Page Active NOP READ - AP BANK m READ with Burst of 4 NOP NOP NOP NOP Idle Interrupt Burst, Precharge tRP - BANK m t RP - BANK n Page Active BANK m BANK n, COL a ADDRESS Precharge READ with Burst of 4 BANK m, COL d DOUT a DQ DOUT a+1 DOUT d DOUT d+1 CAS Latency = 3 (BANK n) CAS Latency = 3 (BANK m) NOTE: DQM is LOW. TRANSITIONING DATA DON'T CARE Figure 29: READ With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States READ - AP BANK n Page Active NOP NOP NOP READ with Burst of 4 WRITE - AP BANK m NOP NOP Interrupt Burst, Precharge Idle tRP - BANK n Page Active BANK m ADDRESS NOP Write-Back WRITE with Burst of 4 BANK n, COL a t WR - BANK m BANK m, COL d 1 DQM DOUT a DQ DIN d DIN d+1 DIN d+2 DIN d+3 CAS Latency = 3 (BANK n) NOTE: 1. DQM is HIGH at T2 to prevent DOUT-a+1 from contending with DIN-d at T4. TRANSITIONING DATA 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 28 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 30: WRITE With Auto Precharge Interrupted by a READ T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active READ - AP BANK m NOP WRITE with Burst of 4 DIN a DQ NOP Precharge tWR - BANK n tRP - BANK n NOP tRP - BANK m READ with Burst of 4 BANK n, COL a ADDRESS NOP Interrupt Burst, Write-Back Page Active BANK m NOP BANK m, COL d DOUT d+1 DOUT d DIN a+1 CAS Latency = 3 (BANK m) NOTE: 1. DQM is LOW. DON'T CARE TRANSITIONING DATA Figure 31: WRITE With Auto Precharge Interrupted by a WRITE T0 T1 T2 T3 T4 T5 T6 T7 CLK COMMAND BANK n Internal States NOP WRITE - AP BANK n Page Active NOP NOP WRITE with Burst of 4 WRITE - AP BANK m NOP Interrupt Burst, Write-Back tWR - BANK n BANK m ADDRESS DQ Page Active Precharge t WR - BANK m Write-Back BANK m, COL d DIN a+1 DIN a+2 NOTE: 1. DQM is LOW. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN NOP tRP - BANK n WRITE with Burst of 4 BANK n, COL a DIN a NOP DIN d DIN d+1 TRANSITIONING DATA 29 DIN d+2 DIN d+3 DON'T CARE Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 7: CKE N-1 Truth Table - CKE CKE L L L H H L H H N CURRENT STATE COMMAND N Power-Down X Self Refresh X Clock Suspend X Power-Down COMMAND INHIBIT or NOP Deep Power-Down X Self Refresh COMMAND INHIBIT or NOP Clock Suspend X All Banks Idle COMMAND INHIBIT or NOP All Banks Idle DEEP POWER DOWN All Banks Idle AUTO REFRESH Reading or Writing VALID See Truth Table 3 (page 28) ACTION N Maintain Power-Down Maintain Self Refresh Maintain Clock Suspend Exit Power-Down Exit Deep Power-Down Exit Self Refresh Exit Clock Suspend Power-Down Entry Deep Power-Down Entry Self Refresh Entry Clock Suspend Entry NOTES 5 8 6 7 8 NOTE: 1. 2. 3. 4. 5. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. Current state is the state of the SDRAM immediately prior to clock edge n. COMMANDnis the command registered at clock edge n, and ACTIONn is a result of COMMANDn. All states and sequences not shown are illegal or reserved. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that tCKS is met). 6. Exiting self refresh at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during tXSR period. 7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock edge n + 1. 8. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on traditional SDRAM components. For Mobile Ram devices, this command sequence is assigned to Deep Power Down. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 8: Truth Table - Current State Bank n - Command To Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Active Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) CS# H L L L L L L L L L L L L L L L L RAS# CAS# X H L L L L H H L H H L H H H L H X H H L L H L L H L L H H L L H H WE# X H H H L L H L L H L L L H L L L COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) ACTIVE (Select and activate row) AUTO REFRESH LOAD MODE REGISTER PRECHARGE READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Deactivate row in bank or banks) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE (Truncate READ burst, start PRECHARGE) DEEP POWER DOWN READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE (Truncate WRITE burst, start PRECHARGE) DEEP POWER DOWN NOTES 7 7 11 10 10 8 10 10 8 9 10 10 8 9 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7 on page 30) and after tXSR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Table 9 on page 33. Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the row active state. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is met, the SDRAM will be in the all banks idle state. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. 6. All states and sequences not shown are illegal or reserved. 7. Not bank-specific; requires that all banks are idle. 8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging. 9. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on traditional SDRAM components. For Mobile Ram devices, this command sequence is assigned to Deep Power Down. 10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 11. Does not affect the state of the bank and acts as a NOP to that bank. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 9: Truth Table - Current State Bank n - Command To Bank m (Notes: 1-6; notes appear below and on next page) CURRENT STATE Any Idle Row Activating, Active, or Precharging Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) Read (With Auto Precharge) Write (With Auto Precharge) CS# RAS# CAS# WE# H L X L L L L L L L L L L L L L L L L L L L L X H X L H H L L H H L L H H L L H H L L H H L X H X H L L H H L L H H L L H H L L H H L L H X H X H H L L H H L L H H L L H H L L H H L L COMMAND (ACTION) COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start new READ burst) WRITE (Select column and start WRITE burst) PRECHARGE ACTIVE (Select and activate row) READ (Select column and start READ burst) WRITE (Select column and start new WRITE burst) PRECHARGE NOTES 7 7 7, 10 7, 11 9 7, 12 7, 13 9 7, 8, 14 7, 8, 15 9 7, 8, 16 7, 8, 17 9 NOTE: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been interrupted by bank m's burst. 9. Burst in bank n continues as initiated. 10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 11). 11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered (Figure 13 and Figure 14 on page 21). DQM should be used one clock prior to the WRITE command to prevent bus contention. 12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 20 on page 24), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m. 13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 18 on page 23). The last valid WRITE to bank n will be datain registered one clock prior to the READ to bank m. 14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 28 on page 28). 15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 29 on page 28). 16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 30 on page 29). 17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where t WR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 31 on page 29). 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM TwinDie Operation ACTIVE The 512Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured by stacking two 256Mb, 16Megx16 devices. Each of these 256Mb devices is configured as a quad bank DRAM with a synchronous interface. They are organized with 16 DQs with 4 banks of 67,108,864 bits, comprising of 8,192 rows by 512 columns by 16 bits wide. Each die operates independently of the other. They share supply, command, CKE, address and data pins, but each have unique chip select pins. It is not allowed to perform an ACTIVE command to both die simultaneously, except during the initialization sequence. READ Only one SDRAM die may be driving the DQ lines at a time. It is required for a unique chip select (CS0# or CS1#) to be asserted for each READ command. WRITE It is recommended to only WRITE to one die at a time as both die share the same data and data mask signals. INITIALIZATION By synchronizing both of the chip select pins (CS0#, CS1#), it is possible to initialize both die simultaneously, and is the recommended procedure. PRECHARGE It is allowed to perform a PRECHARGE command to both die simultaneously, but it is suggested that the PRECHARGE commands be staggered to provide a distributed current flow. Register Definition MODE REGISTER If both die are to be configured identically, it is OK to access both mode registers simultaneously, otherwise sequential operation between the die is permitted. AUTO PRECHARGE An AUTO PRECHARGE command can only occur as part of a READ or WRITE command. It is possible to initiate an AUTO PRECHARGE to both die simultaneously. Commands (TwinDie) NO OPERATION (NOP) BURST TERMINATE The NO OPERATION (NOP) command is used to instruct the selected SDRAM die to perform NOP (CS0# LOW with RAS#, CAS#, and WE# HIGH and / or CS#1 LOW with RAS#, CAS#, and WE# HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. It is allowed to perform a NOP command to both die simultaneously. It is allowed to perform a BURST TERMINATE command to both die simultaneously, but not expected as only one die may be READ from at a time. AUTO REFRESH All banks within a die must be idle before an AUTO REFRESH command is issued. It is recommended that AUTO REFRESH commands are staggered to provide a distributed current flow. LOAD MODE REGISTER The LMR command may be issued independently or simultaneously to the die. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN SELF REFRESH The SELF REFRESH command may be issued to both die simultaneously. 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Absolute Maximum Ratings Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD/VDDQ Supply Relative to Vss(3.3V) . . . . . . . . . . . . . . . . -1V to +4.6V Relative to Vss(2.5V) . . . . . . . . . . . . . . . -0.5V to +3.6V Relative to Vss(1.8V) . . . . . . . . . . . . . . -0.35V to +2.8V Voltage on Inputs, NC or I/O Pins Relative to Vss(3.3V . . . . . . . . . . . . . . . . . . -1V to +4.6V Relative to Vss(2.5V) . . . . . . . . . . . . . . . -0.5V to +3.6V Relative to Vss(1.8V) . . . . . . . . . . . . . . -0.35V to +2.8V Operating Temperature TA (Commercial). . . . . . . . . . . . . . . . . . . . 0C to +70C Storage Temperature (plastic) . . . . . -55C to +150C Table 10: DC Electrical Characteristics And Operating Conditions - "LC" Version Notes: 1, 5, 6; notes appear on page 41 PARAMETER/CONDITION SYMBOL MIN MAX UNITS Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Data Output High Voltage: Logic 1; All inputs Data Output Low Voltage: Logic 0; All inputs Input Leakage Current: Any input 0V VIN VDD (All other pins not under test = 0V) VDD, VDDQ VIH VIL VOH VOL II 3 2 -0.3 2.4 -5 3.6 VDDQ + 0.3 0.8 0.4 5 V V V V V A Output Leakage Current: DQs are disabled; 0V VOUT VDDQ IOZ -5 5 A NOTES 22 22 Table 11: DC Electrical Characteristics And Operating Conditions - "V" Version Notes: 1, 5, 6; notes appear on page 41 PARAMETER/CONDITION SYMBOL Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Data Output High Voltage: Logic 1; All inputs Data Output Low Voltage: Logic 0; All inputs Input Leakage Current: Any input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; 0V VOUT VDDQ 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 36 VDD VDDQ VIH VIL VOH VOL II IOZ MIN MAX 2.3 2.7 1.65 2.7 0.8 * VDDQ VDDQ + 0.3 -0.3 0.3 VDDQ - 0.2 0.2 -5 5 -5 5 UNITS V V V V V V A NOTES 22 22 A Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 12: DC Electrical Characteristics And Operating Conditions - "H" Version Notes: 1, 5, 6; notes appear on page 41 PARAMETER/CONDITION SYMBOL VDD VDDQ VIH VIL VOH VOL II Supply Voltage Input High Voltage: Logic 1; All inputs Input Low Voltage: Logic 0; All inputs Data Output High Voltage: Logic 1; All inputs Data Output Low Voltage: Logic 0; All inputs Input Leakage Current: Any input 0V VIN VDD (All other pins not under test = 0V) Output Leakage Current: DQs are disabled; 0V VOUT VDDQ MIN MAX 1.7 1.9 1.7 1.9 0.8 * VDDQ VDDQ + 0.3 -0.3 0.3 VDDQ - 0.2 0.2 -1.0 1.0 IOZ -1.5 1.55 UNITS NOTES V V V V V V A 22 22 A Table 13: IDD Specifications And Conditions (Both Die - S2 Version) Notes: 1, 5, 6, 11, 13; notes appear on page 41; VDD = +3.3V 0.3V or +2.5V0.2V1 MAX PARAMETER/CONDITION SYMBOL -8 UNITS NOTES Operating Current: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) Standby Current: Power-Down Mode; CKE = LOW; All banks idle Standby Current: Active Mode; CS# = HIGH; CKE = HIGH; All banks active after tRCD met; No accesses in progress Operating Current: Burst Mode; Page burst; READ or WRITE; All banks active Auto Refresh Current: CS# = HIGH; CKE = HIGH IDD1 150 mA 3, 18, 19, 32 IDD2 1 mA 32 IDD3 50 mA 3, 12, 19, 32 IDD4 210 mA t RFC = tRFC (MIN) IDD5 330 mA 3, 18, 19, 32 3, 12, 18, 19, 32, 33 RFC = 7.81s IDD6 5 mA ID8 20 uA t Deep Power Down 34 NOTE: 1. IDD values for VDD = VDDQ = 1.8V TBD Table 14: IDD7 - Self Refresh Current Options- S2 Version Temperature Compensated Self Refresh, Both Die - S2 Version Notes: 1, 5, 6, 11, 13; notes appear on page 41; VDD = +3.3V 0.3V or +2.5V0.2V1 TEMPERATURE COMPENSATED SELF REFRESH PARAMETER/CONDITION MAX TEMPERATURE -8 / -10 UNITS NOTES 70C 45C 1.3 1.0 mA mA 4 4 Self Refresh Current: CKE 0.2V NOTE: 1. IDD values for VDD = VDDQ = 1.8V TBD 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 15: Capacitance Note: 2; notes appear on page 41 PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 38 SYMBOL MIN MAX UNITS CI 1 CI 2 CIO TBD TBD TBD TBD TBD TBD pF pF pF Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 16: Electrical Characteristics And Recommended AC Operating Conditions Notes: 5, 6, 8, 9, 11; notes appear on page 41 AC CHARACTERISTICS -8 PARAMETER Access time from CLK (pos. edge) MAX UNITS NOTES CL = 3 SYMBOL t MIN 7 ns 27 CL = 2 t 8 ns AC(3) AC(2) 1 ns t AS 2.5 ns CLK high-level width t CH 3 ns CLK low-level width t 3 ns Address hold time t Address setup time Clock cycle time AH CL CL = 3 t 8 ns 23 CL = 2 t 10 ns 23 1 ns CKS 2.5 ns CMH 1 ns 2.5 ns 1 ns CK(3) CK(2) CKE hold time t CKE setup time t CKH CS#, RAS#, CAS#, WE#, DQM hold time t CS#, RAS#, CAS#, WE#, DQM setup time t CMS Data-in hold time t Data-in setup time t Data-out high-impedance time DH DS 2.5 ns CL = 3 t 7 ns 10 CL = 2 t 8 ns 10 HZ(3) HZ(2) LZ 1 ns t OH 2.5 ns Data-out hold time (noload) tOHN 1.8 ACTIVE to PRECHARGE command t RAS 48 t RC 80 ns RCD 20 ns Data-out low-impedance time t Data-out hold time (load) ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay t Refreshperiod(8,192rows) t AUTO REFRESH period t 20 ns RRD ns WRITE recovery time t Exit SELF REFRESH to ACTIVE command t T 0.5 WR 1CLK+ 7ns 15 80 XSR 39 ns 20 t 1.2 28E ms RP t Transition time 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 80 28 ns t PRECHARGE command period ACTIVE bank a to bank b command 64 REF RFC ns 120,000 28E ns 7 ns 24, 28E 25 28E ns Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Table 17: AC Functional Characteristics Notes: 5, 6, 8, 9, 11; notes appear on page 41 PARAMETER SYMBOL -8 UNITS NOTES CCD 1 t 17 CKED 1 t 14 t PED 1 t 14 t DQD 0 t 17 DQM to data mask during WRITEs t DQM 0 t 17 DQM to data high-impedance during READs t DQZ 2 t 17 WRITE command to input data delay t DWD 0 t 17 Data-into ACTIVE command t DAL 5 t 15, 21 Data-into PRECHARGE command t DPL 2 t 16, 21 Last data-in to burst STOP command t BDL 1 t 17 Last data-in to new READ/WRITE command t 1 t 17 Last data-in to PRECHARGE command t RDL 2 t 16, 21 LOADMODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command t MRD 2 t 26 ROH(3) t READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN t CDL CK CK CK CK CK CK CK CK CK CK CK CK CK CL=3 t 3 t 17 CL = 2 t 2 t 17 ROH(2) 40 CK CK Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Notes (Single Die) 1. All voltages referenced to VSS. 2. This parameter is sampled. VDD, VDDQ = +3.3V; Tj = 25C; pin under test biased at 1.4V, f = 1 MHz. 3. IDD is dependent on output loading and cycle rates.Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is ensured. 6. An initial pause of 100s is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease in a proportional amount by the amount the frequency is altered for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 8ns for -8. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns after the first clock delay, after the last WRITE is executed. 25. Precharge mode only. 26. JEDEC and PC100, PC133 specify three clocks. 27. tAC for -8 at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. For -8, CL = 3, tCK = 10ns; For -8, CL = 2, tCK = 8ns. Q 30pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z. 11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with timing referenced to VIH/2 crossover point. If the input transition time is longer than 1 ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 32: Initialize And Load Mode Register T1 T0 CLK (( )) (( )) T3 T5 T7 T9 T19 T29 (( )) (( tCK ) ) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) tCKS tCKH CKE (( )) (( )) COMMAND (( )) (( )) DQM/DQML, DQMH (( )) (( )) (( )) (( )) A0-A9, A11, A12 (( )) (( )) (( )) (( )) CODE (( )) (( )) A10 (( )) (( )) (( )) (( )) CODE (( )) (( )) BA0, BA1 (( )) (( )) DQ (( )) tCMH tCMS NOP PRE (( )) (( )) (( )) (( )) LMR4 (( )) (( )) LMR4 (( )) (( )) PRE3 (( )) (( )) (( )) (( )) AR4 AR4 (( )) (( )) ACT4 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) CODE (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) RA CODE ( ( ALL BANKS )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) RA (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA (( )) (( )) (( )) (( )) tMRD tRP tAS tAH ALL BANKS tAS tAH tAS (( )) (( )) High-Z tAH tAS (( )) (( )) BA0 = L, BA1 = H (( )) (( )) tRP tMRD BA0 = L, BA1 = L tAH T = 100s Power-up: VDD and CLK stable Load Extended Mode Register tRFC tRFC Load Mode Register DON'T CARE NOTE: 1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) command. 2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address 3. Optional refresh command. 4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur prior to an Active command. 5. Device timing is -8 with 100MHz clock. -8 SYMBOL MIN -8 MAX UNITS SYMBOL MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 2 t 8 ns t 80 CK ns t 10 ns t 20 ns t 1 ns AH AS CH CL CK (CL=3) CK (CL=2) CKH 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN CKS CMH CMS MRD3 RFC RP 42 t Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 33: Power-down Mode1 T0 CLK (( )) CKE (( )) (( )) COMMAND (( )) (( )) tCK T1 tCKH tCKS Tn + 1 (( )) (( )) tCH tCMS tCMH (( )) NOP NOP (( )) AUTO REFRESH (( )) NOP NOP (( )) AUTO REFRESH (( )) (( )) (( )) (( )) (( )) (( )) A0-A9, A11, A12 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) A10 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) BA0, BA1 DQ ALL BANKS SINGLE BANK (( )) (( )) (( )) T = 100s MIN ALL BANKS High-Z Tp + 2 Tp + 3 (( )) (( )) (( )) DQM/ DQML, DQMH Tp + 1 tCMS tCMH (( )) PRECHARGE (( )) NOP (( )) (( )) (( )) (( )) (( )) tCMS tCMH To + 1 tCL (( )) (( )) LOAD MODE REGISTER tAS NOP tAH 5 ROW CODE tAS ACTIVE tAH ROW CODE BANK (( )) tRP Power-up: VDD and CLK stable Precharge all banks tRFC tRFC AUTO REFRESH AUTO REFRESH tMRD Program Mode Register 1, 3, 4 DON'T CARE UNDEFINED -8 SYMBOL MIN t 1 t 2.5 t -8 MAX UNITS SYMBOL MIN MAX UNITS ns t 10 ns ns t 1 ns 3 ns t 2.5 ns t 3 ns t 1 ns t 8 ns t 2.5 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS NOTE: 1. Violating refresh requirements during power-down may result in a loss of data. 2. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 34: Clock Suspend Mode1 T0 T1 T2 tCK CLK T3 T4 T5 T6 T7 T8 NOP WRITE T9 tCL tCH tCKS tCKH CKE tCKS tCKH tCMS tCMH COMMAND READ NOP NOP NOP NOP NOP tCMS tCMH DQM/ DQML, DQMU A0-A9, A11, A12 tAS tAH COLUMN m 2 tAS tAH tAS tAH COLUMN e 2 A10 BA0, BA1 BANK BANK tAC tOH tAC DQ tHZ DOUT m tLZ DOUT m + 1 tDS tDH Din e Din + 1 DON T CARE UNDEFINED -8 SYMBOL3 MIN -8 SYMBOL3 MAX UNITS t 7 ns t 2.5 ns t 8 ns t 1 ns AC (3) AC (2) CKS CMH MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 7 ns t 8 ns t 8 ns t 10 ns t 1 ns t 1 ns t 2.5 ns AH AS CH CL CK (3) CK (2) CKH CMS DH DS HZ (3) HZ (2) LZ OH NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 35: Auto Refresh Mode T0 CLK T1 T2 tCK tCH tCKS tCKH tCMS tCMH COMMAND PRECHARGE NOP AUTO REFRESH NOP (( )) (( )) ( ( NOP )) AUTO REFRESH NOP (( )) (( )) DQM / DQML, DQMH A0-A9, A11, A12 ALL BANKS A10 SINGLE BANK tAS BA0, BA1 To + 1 (( )) (( )) tCL (( )) CKE DQ Tn + 1 (( )) (( )) (( )) ( ( NOP )) ACTIVE (( )) (( )) (( )) (( )) (( )) (( )) ROW (( )) (( )) (( )) (( )) ROW tAH (( )) (( )) BANK(S) High-Z (( )) (( )) (( )) tRP BANK (( )) tRFC tRFC Precharge all active banks DON'T CARE -8 SYMBOL1 MIN -8 MAX SYMBOL1 UNITS MIN MAX UNITS t 1 ns t 1 ns t 2.5 ns t 2.5 ns t 3 ns t 1 ns t 3 ns t 2.5 ns t 8 ns t 80 ns t 10 ns t 20 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS RFC RP NOTE: 1. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 36: Self Refresh Mode T0 CLK T1 tCK tCL tCH T2 tCKS tCMS COMMAND tCMH NOP AUTO REFRESH (( )) (( )) (( ) ) or COMMAND NOP ( ( (( )) (( )) (( )) (( )) A0-A9, A11,A12 (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) ALL BANKS SINGLE BANK tAS BA0, BA1 DQ To + 2 INHIBIT AUTO REFRESH )) DQM/ DQML, DQMU A10 To + 1 (( )) (( )) (( )) tCKH PRECHARGE (( )) (( )) tRAS(MIN)1 CKE tCKS Tn + 1 (( )) (( )) tAH BANK(S) High-Z (( )) (( )) tRP Precharge all active banks tXSR Enter self refresh mode Exit self refresh mode (Restart refresh time base) DON'T CARE CLK stable prior to exiting self refresh mode -8 SYMBOL MIN -8 MAX UNITS SYMBOL MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 48 t 8 ns t 20 ns t 10 ns t 80 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS RAS RP XSR 120,000 ns NOTE: 1. No maximum time limit for Self Refresh. tRAS(MIN) applies to non-Self Refresh mode. 2. tXSR requires minimum of two clocks regardless of frequency or timing. 3. CAS latency indicated in parentheses 4. As a general rule, any time Self Refresh is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have been refreshed via the Auto Refresh command at the distributed refresh rate, tREF, or faster. However, the following exception is allowed. Self Refresh mode may be re-entered any time after exiting, provided all of the following conditions are met: a. The DRAM had been in the Self Refresh Mode for a minimum of 64ms prior to exiting. b. tXSR is not violated. c. At least two Auto Refresh commands are performed during each 7.81s interval while the DRAM remains out of Self Refresh mode. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 37: READ - Without Auto Precharge T0 T1 T2 tCK CLK T3 T4 T5 NOP NOP T6 T7 T8 NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP PRECHARGE tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAS COLUMN m 2 ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW ROW SINGLE BANK DISABLE AUTO PRECHARGE tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tLZ tRCD tAC tOH DOUT m + 1 BANK tAC tOH tOH DOUT m + 2 DOUT m + 3 tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED -8 SYMBOL3 MIN -8 SYMBOL3 MAX UNITS t 7 ns t 1 ns t 8 ns t 2.5 ns AC (3) AC (2) CMH CMS MIN MAX UNITS t 1 ns t 7 ns t 2.5 ns t 8 ns t 3 ns t 1 ns t 3 ns t 2.5 ns t 8 ns t 48 t 10 ns t 80 ns t 1 ns t 20 ns t 2.5 ns t 20 ns AH AS CH CL CK (3) CK (2) CKH CKS HZ (3) HZ (2) LZ OH RAS RC RCD RP 120,000 ns NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 38: READ - With Auto Precharge T0 T1 T2 tCK CLK tCKS T3 T4 T5 NOP NOP 1 T6 T7 T8 NOP ACTIVE tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ tCMS NOP NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 COLUMN m 2 ROW tAS A10 tAH ROW tAH BANK BANK BANK tAC tOH tAC DQ DOUT m tLZ tRCD tAC tOH DOUT m + 1 tAC tOH tOH DOUT m + 2 DOUT m + 3 tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED -8 SYMBOL3 MIN -8 SYMBOL3 MAX UNITS t 7 ns t 1 ns t 8 ns t 2.5 ns AC (3) AC (2) CMH CMS MIN MAX UNITS t 1 ns t 7 ns t 2.5 ns t 8 ns t 3 ns t 1 ns t 3 ns t 2.5 ns t 8 ns t 48 t 10 ns t 80 ns t 1 ns t 20 ns t 2.5 ns t 20 ns AH AS CH CL CK (3) CK (2) CKH CKS HZ (3) HZ (2) LZ OH RAS RC RCD RP 120,000 ns NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses1 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 39: Single READ - Without Auto Precharge T0 T1 T2 tCK CLK T3 T4 T5 NOP NOP T6 1 T7 T8 tCL tCH tCKS tCKH CKE tCMS tCMH COMMAND ACTIVE NOP READ PRECHARGE NOP ACTIVE NOP tCMS tCMH DQM/ DQML, DQMH tAS A0-A9, A11, A12 COLUMN m2 ROW tAS ROW tAH ALL BANKS ROW A10 tAS BA0, BA1 tAH ROW DISABLE AUTO PRECHARGE tAH BANK SINGLE BANKS BANK BANK(S) tAC DQ tOH DOUT m tLZ tRCD BANK tHZ tRP CAS Latency tRAS tRC DON'T CARE UNDEFINED -8 SYMBOL3 MIN -8 SYMBOL3 MAX UNITS t 7 ns t 1 ns t 8 ns t 2.5 ns AC (3) AC (2) CMH CMS MIN MAX UNITS t 1 ns t 7 ns t 2.5 ns t 8 ns t 3 ns t 1 ns t 3 ns t 2.5 ns t 8 ns t 48 t 10 ns t 80 ns t 1 ns t 20 ns t 2.5 ns t 20 ns AH AS CH CL CK (3) CK (2) CKH CKS HZ (3) HZ (2) LZ OH RAS RC RCD RP 120,000 ns NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a "manual" PRECHARGE. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 40: Single READ - With Auto Precharge1 T0 T1 T2 tCK CLK tCKS T3 T4 T5 T6 NOP3 READ NOP T7 T8 tCL tCH tCKH CKE tCMS tCMH COMMAND ACTIVE NOP3 NOP tCMS NOP ACTIVE NOP tCMH DQM/ DQML, DQMH tAS A0-A9, A11 tAS A10 COLUMN m2 tAH ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW tAH BANK BANK BANK tAC t OH DOUT m DQ tRCD CAS Latency tHZ tRP tRAS tRC DON'T CARE UNDEFINED -8 SYMBOL4 MIN -8 SYMBOL4 MAX UNITS t 7 ns t 1 ns t 8 ns t 2.5 ns AC (3) AC (2) CMH CMS MIN MAX UNITS t 1 ns t 7 ns t 2.5 ns t 8 ns t 3 ns t 1 ns t 3 ns t 2.5 ns t 8 ns t 48 t 10 ns t 80 ns t 1 ns t 20 ns t 2.5 ns t 20 ns AH AS CH CL CK (3) CK (2) CKH CKS HZ (3) HZ (2) LZ OH RAS RC RCD RP 120,000 ns NOTE: 1. 2. 3. 4. For this example, the burst length = 1, and the CAS latency = 2. x16: A11 and A12 = "Don't Care" READ command not allowed else tRAS would be violated CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 41: Alternating Bank Read Accesses1 T0 T1 T2 tCK CLK T3 T4 T5 NOP ACTIVE T6 T7 T8 READ NOP ACTIVE tCL tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAS A10 COLUMN m 2 tAH COLUMN b 2 ROW ENABLE AUTO PRECHARGE ROW ENABLE AUTO PRECHARGE ROW tAS BA0, BA1 tAH ROW ROW ROW tAH BANK 0 BANK 0 BANK 3 tAC DQ tAC tOH DOUT m tLZ tRCD - BANK 0 BANK 3 tAC tOH DOUT m + 1 BANK 0 tAC tOH tAC tOH DOUT m + 2 tAC tOH DOUT m + 3 DOUT b tRP - BANK 0 CAS Latency - BANK 0 tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tRCD - BANK 1 tRRD CAS Latency - BANK 1 DON'T CARE UNDEFINED -8 SYMBOL3 MIN -8 SYMBOL3 MAX UNITS t 7 ns t 1 ns t 8 ns t 2.5 ns AC (3) AC (2) CMH CMS MIN MAX UNITS t 1 ns t 1 ns t 2.5 ns t 2.5 ns t 3 ns t 48 t 3 ns t 80 ns t 8 ns t 20 ns t 10 ns t 20 ns t 1 ns t 20 ns t 2.5 ns AH AS CH CL CK (3) CK (2) CKH CKS LZ OH RAS RC RCD RP RRD 120,000 ns NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 51 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 42: Read - Full-page Burst T0 T1 T2 tCL CLK T3 T4 T5 T6 (( )) (( )) tCK tCH tCKS 1 Tn + 1 Tn + 2 Tn + 3 Tn + 4 tCKH (( )) (( )) CKE tCMS COMMAND tCMH ACTIVE NOP READ tCMS NOP NOP NOP tCMH A0-A9, A11, A12 tAS A10 BURST TERM NOP tAH (( )) (( )) tAH BANK (( )) (( )) BANK tAC tAC tAC tOH DOUT m+1 tLZ tRCD tAC ( ( tOH ) ) tOH DOUT m DQ DOUT (( )) m+2 (( )) tAC tAC tOH tOH tOH DOUT m-1 Dout m DOUT m+1 tHZ 1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row CAS Latency Full page completed DON'T CARE Full-page burst does not self-terminate. 3 Can use BURST TERMINATE command. -8 SYMBOL4 NOP (( )) (( )) COLUMN m 2 ROW tAS BA0, BA1 tAH ROW NOP (( )) (( )) DQM/ DQML, DQMH tAS (( )) (( )) NOP MIN UNDEFINED -8 SYMBOL4 MAX UNITS t 7 ns t 2.5 ns t 8 ns t 1 ns 2.5 ns AC (3) AC (2) CKS CMH MIN MAX UNITS t 1 ns t t 2.5 ns t 7 ns t 3 ns t 8 ns t 3 ns t 1 ns t 8 ns t 2.5 ns t 10 ns t 20 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CMS HZ (3) HZ (2) LZ OH RCD NOTE: 1. 2. 3. 4. For this example, the CAS latency = 2. x16: A11 and A12 = "Don't Care" Page left open; no tRP. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 43: Read DQM Operation1 T0 T1 T2 tCK CLK tCKS tCKH tCMS tCMH T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 DISABLE AUTO PRECHARGE tAH BANK BANK tAC DQ DOUT m tLZ tRCD tAC tOH tAC tOH tOH DOUT m + 2 DOUT m + 3 tLZ tHZ tHZ CAS Latency DON'T CARE UNDEFINED -8 SYMBOL3 MIN -8 SYMBOL3 MAX UNITS t 7 ns t 2.5 ns t 8 ns t 1 ns 2.5 ns AC (3) AC (2) CKS CMH MIN MAX UNITS t 1 ns t t 2.5 ns t 7 ns t 3 ns t 8 ns t 3 ns t 1 ns t 8 ns t 2.5 ns t 10 ns t 20 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CMS HZ (3) HZ (2) LZ OH RCD NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 44: Write - Without Auto Precharge1 T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE NOP ACTIVE tCMS tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS ROW tAH ALL BANKs ROW A10 tAS BA0, BA1 ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS tDH DIN m DQ tDS tDH tDS DIN m + 1 tDH tDS DIN m + 2 BANK tDH DIN m + 3 t WR 3 tRCD tRAS tRP tRC DON'T CARE -8 SYMBOL4 MIN -8 MAX SYMBOL4 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 48 t 8 ns t 80 ns t 10 ns t 20 ns t 1 ns t 20 ns t 2.5 ns t 15 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RAS RC RCD RP WR 120,000 ns NOTE: 1. 2. 3. 4. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. x16: A11 and A12 = "Don't Care" CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 45: Write - With Auto Precharge1 T0 tCK CLK tCKS tCKH tCMS tCMH T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP NOP NOP NOP NOP ACTIVE tCH CKE COMMAND ACTIVE NOP WRITE tCMS tCMH DQM/ DQML, DQMH tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ROW ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 ROW tAH BANK BANK tDS tDH DIN m DQ BANK tDS tDH DIN m + 1 tDS tDH tDS DIN m + 2 tDH DIN m + 3 tRCD tRAS tRP tWR tRC DON'T CARE -8 SYMBOL3 MIN -8 MAX SYMBOL3 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 48 t 8 ns t 80 ns t 10 ns t 20 ns t 1 ns t 20 ns t 2.5 ns t 1 ns 1 CLK +7ns - t AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RAS RC RCD RP WR 120,000 ns NOTE: 1. For this example, the burst length = 4. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 46: Single Write - Without Auto Precharge1 T0 tCK CLK T1 T2 tCL T3 T4 T5 NOP4 NOP4 T6 T7 T8 ACTIVE NOP tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE PRECHARGE NOP tCMS tCMH DQM/ DQML, DQMH tAS A0-A9, A11, A12 tAS A10 COLUMN m 3 tAH ALL BANKS ROW tAS BA0, BA1 tAH ROW ROW tAH DISABLE AUTO PRECHARGE SINGLE BANK BANK BANK BANK tDS BANK tDH DIN m DQ tRCD tRAS tRP t WR 2 tRC DON'T CARE UNDEFINED -8 SYMBOL5 MIN -8 MAX SYMBOL5 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 48 t 8 ns t 80 ns t 10 ns t 20 ns t 1 ns t 20 ns t 2.5 ns t 15 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RAS RC RCD RP WR 120,000 ns NOTE: 1. 2. 3. 4. 5. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. x16: A11 and A12 = "Don't Care" PRECHARGE command not allowed else tRAS would be violated CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 47: Single Write with Auto Precharge T0 tCK CLK tCKS tCKH tCMS tCMH T1 tCL T2 T3 T4 T5 T6 T7 T8 WRITE NOP NOP NOP T9 tCH CKE COMMAND NOP4 ACTIVE NOP4 NOP4 tCMS NOP ACTIVE tCMH DQM/ DQML, DQMH tAS A0-A9, A11, A12 tAH COLUMN m3 ROW tAS tAH ROW ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 ROW tAH BANK BANK tDS BANK tDH DIN m DQ tRCD3 tRAS tRP tWR2 tRC DON'T CARE UNDEFINED -8 SYMBOL5 MIN -8 MAX SYMBOL5 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 48 t 8 ns t 80 ns t 10 ns t 20 ns t 1 ns t 20 ns t 2.5 ns t 1 ns 1 CLK + 7ns ns t AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RAS RC RCD RP WR 120,000 ns NOTE: 1. 2. 3. 4. 5. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency. x16: A11 and A12 = "Don't Care" WRITE command not allowed else tRAS would be violated. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 48: Alternating Bank Write Accesses1 T0 tCK CLK T1 T2 tCL T3 T4 T5 T6 T7 T8 T9 NOP NOP ACTIVE tCH tCKS tCKH tCMS tCMH CKE COMMAND ACTIVE NOP WRITE tCMS NOP ACTIVE NOP WRITE tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 3 ROW tAS tAH ENABLE AUTO PRECHARGE tAS BA0, BA1 ROW ENABLE AUTO PRECHARGE ROW A10 COLUMN b 3 ROW ROW ROW tAH BANK 0 BANK 0 tDS tDH DIN m DQ BANK 1 tDS tDH DIN m + 1 tDS BANK 1 tDH tDS DIN m + 2 tDH DIN m + 3 tDS tDH DIN b BANK 0 tDS tDH DIN b + 1 tDH tDS DIN b + 2 tRP - BANK 0 tWR - BANK 0 tRCD - BANK 0 tDS tDH DIN b + 3 tRCD - BANK 0 tRAS - BANK 0 tRC - BANK 0 tWR - BANK 1 tRCD - BANK 1 tRRD DON'T CARE -8 SYMBOL4 MIN -8 MAX SYMBOL4 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 48 t 8 ns t 80 ns t 10 ns t 20 ns t 1 ns t 20 ns t 2.5 ns t 20 ns t 1 ns t Note 2 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RAS RC RCD RP RRD WR 120,000 ns NOTE: 1. 2. 3. 4. For this example, the burst length = 4. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE. x16: A11 and A12 = "Don't Care" CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 49: Write - Full-page Burst T0 T1 T2 tCL CLK T3 T4 T5 (( )) (( )) tCK tCH tCKS tCKH COMMAND tCMH ACTIVE NOP WRITE NOP NOP NOP tCMS tCMH tAS A10 (( )) (( )) NOP BURST TERM tAH (( )) (( )) tAH BANK (( )) (( )) BANK tDS tDH tDS DIN m DQ tDH tDS DIN m + 1 tDH DIN m + 2 tDS tDH DIN m + 3 tRCD (( )) (( )) tDS tDH DIN m - 1 1,024 (x16) locations within same row 2,048 (x8) locations within same row 4,096 (x4) locations within same row Full-page burst does not self-terminate. Can use BURST TERMINATE command to stop.2, 3 Full page completed DON'T CARE -8 SYMBOL4 NOP (( )) (( )) COLUMN m 1 ROW tAS BA0, BA1 tAH ROW tAS Tn + 3 (( )) (( )) DQM/ DQML, DQMH A0-A9, A11, A12 Tn + 2 (( )) (( )) CKE tCMS Tn + 1 MIN -8 MAX SYMBOL4 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 1 ns t 8 ns t 2.5 ns t 10 ns t 20 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RCD NOTE: 1. x16: A11 and A12 = "Don't Care." 2. tWR must be satisfied prior to PRECHARGE command. 3. Page left open; no tRP. 4. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 50: Write - DQM Operation1 T0 T1 T2 tCK CLK tCKS tCKH tCMS tCMH T3 T4 T5 NOP NOP T6 T7 T8 NOP NOP NOP tCL tCH CKE COMMAND ACTIVE NOP READ tCMS NOP tCMH DQM/ DQML, DQMU tAS A0-A9, A11, A12 tAH COLUMN m 2 ROW tAS tAH ENABLE AUTO PRECHARGE ROW A10 tAS BA0, BA1 DISABLE AUTO PRECHARGE tAH BANK BANK tAC DQ DOUT m tLZ tRCD tAC tOH tAC tOH tOH DOUT m + 2 tLZ tHZ DOUT m + 3 tHZ CAS Latency DON'T CARE UNDEFINED -8 SYMBOL3 MIN -8 MAX SYMBOL3 UNITS MIN MAX UNITS t 1 ns t 2.5 ns t 2.5 ns t 1 ns t 3 ns t 2.5 ns t 3 ns t 1 ns t 8 ns t 2.5 ns t 10 ns t 20 ns t 1 ns AH AS CH CL CK (3) CK (2) CKH CKS CMH CMS DH DS RCD NOTE: 1. For this example, the burst length = 4. 2. x16: A11 and A12 = "Don't Care" 3. CAS latency indicated in parentheses. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 60 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved. PRELIMINARY 256Mb and 512Mb: x16 TwinDie MOBILE SDRAM Figure 51: FGBA "FG" Package 54-pin, 8mm x 14mm 1.250 0.075 SEATING PLANE 0.10 C 0.100 0.013 C 6.40 1.80 0.05 CTR 0.80 TYP 54X 0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.33 BALL A9 1.6 0 MAX BALL A1 ID BALL A1 ID BALL A1 0.80 TYP CL 6.40 14.00 0.10 3.20 0.05 7.00 0.05 CL 3.20 0.05 4.00 0.05 MOLD COMPOUND: EPOXY NOVOLAC 8.00 0.10 SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: O .27mm NOTE: 1. All dimensions in millimeters max/min or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. Data Sheet Designation Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, the Micron logo, and TwinDie are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. 09005aef80906b6e 256mb_512mbSDRAM_twindie_2.fm - Rev. C 10/03 EN 61 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2003 Micron Technology, Inc. All rights reserved.