MT48V16M16T2FG-8 - Micron Technology, Inc.

‡PRODUCTS AND SPECIFICATIONS DISC USSED HEREIN ARE FOR EVAL UATION AND REFERENCE PURPOSES ONLY AND ARE SU BJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUC TS ARE ONLY WARRANTED BY MICR ON TO MEET MIC RON’S PRODUC TION DATA SHEET S PE CIFICATIONS.

09005aef80906b6e

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY‡

SYNCHRONOUS

DRAM

MT48LC32M16S2 MT48LC16M16T2 MT48LC16M16B2

MT48V32M16S2 MT48V16M16T2 MT48V16M16B2

MT48H32M16S2 MT48H16M16T2 MT48H16M16B2

Features

• Low voltage power supply

• Fully synchronous; a ll signals registered on positive

• edge of system clock

• Internal pipelined operation; column address can

be changed e very cloc k cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes C ON CURRENT AUTO

PRECHARGE, a nd Auto Refresh Modes

• Self Refresh Mode

• 64ms, 8,192-cycle refresh

• LVTTL-compatible inputs and outputs

• Deep Power Down

• Par tial Array Self Refresh power-saving mode

• Temperature Compensated Self Refresh (TCSR)

Part Number Example:

MT48LC32M16S2FG-8

NOTE: The # symbol indicates signal is active LOW.

*CL= CAS (READ) latency

Options Marking

•V

DD\VDDQ

3.3V\3.3V LC

2.5V\2.5V or 1.8V V

1.8V\1.8V H1

NOTE:

1. Contact Micron for availability.

• Configurations

16 Meg x 16 (4 Meg x 16 x 4 banks) 16M16

32Meg x 16 (8 Meg x 16 x 4 banks) 32M16

•Die Options

Both Die F u nc ti ona l S2

Top Die Only Functional T2

Bottom Die On l y Fu ncti onal B2

•Plastic Package - OCPL

54-ball FBGA (8mm x 14mm) FG

• Timin g (Cycle Time)

10ns @ CL = 2 (100 MHz) -8

•Operating Temperature

Commercial (0oC to +70oC) None

Each Die 32 Meg x 16 16 Meg x 16

Con f iguration 8 Meg x 16 x 4 banks 4 Meg x 16 x 4 banks

Refres h Co un t 8K 8K

Row Addressing 8K (A0-A12) 8K (A0-A12)

Bank Addressing 4 (BA0, BA1) 4 (BA0, BA1)

Column Addressing 512 (A0-A8) 512 (A0-A8)

Table 1: Key Timing Parameters

SPEED

GRADE CLOCK

FREQUENCY

ACCESS TIME SETUP

TIME HOLD

TIME

CL=2*

-8 100 MHz 8.0ns 2.5ns 1.0ns

Figure 1: Ball Assignment (Top View)

54-Ball FBGA

1 2 3 4 5 6 7 8

DQ14

DQ12

DQ10

DQ8

UDQM

A12

DQ15

DQ13

DQ11

DQ9

CS#(1)

CLK

A11

CKE

CAS#

BA0

DQ0

DQ2

DQ4

DQ6

LDQM

RAS#

BA1

DQ1

DQ3

DQ5

DQ7

WE#

CS#(0)

A10

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

General D e scrip tion

The Micron® TwinDie™ 512Mb SDRAM is a high-

speed CMOS, dynamic random-access memory con-

taining 536,870,912 bits. It is internally configured by

stacking two 256Mb, 16Megx16 devices. Each of these

256Mb devices is configured as a quad bank DRAM

with a sy nchron ous inter fac e. They are org anized wi th

16 DQs with 4 banks of 67,108,864 bits, comprising of

8,192 rows by 512 columns by 16 bits wide.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and con-

tinue for a programmed number of locations in a

programmed sequ ence. Accesses begin wit h the regis-

tration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed

(BA0, BA1 select the bank; A0-A12 select the row). The

address bits registered coincident with the READ or

WRITE command are used to select the starting col-

umn lo cation fo r the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a bu rs t termi na te option. An a ut o prechar g e

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst

sequence.

The 512Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This

architecture is c ompatible with the 2n rule of prefetch

architectures, but it also allows the column address to

be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one bank

while accessing one of the other three banks will hide

the precharge cycles and provide seamless, high-

speed, ran dom-access operation.

The 512Mb SDRAM is design ed to ope r at e i n 3.3V or

2.5V memory systems. An auto refresh mode is pro-

vided, along with a power-saving, power-down mode.

All inpu ts and outputs are LVTTL-compat ible.

SDRAMs offer substantial advances in DRAM oper-

ating performance, including the ability to synchro-

nously burst data at a high data rate with automatic

column-address generation, the ability to interleave

betwe en i n terna l ban ks to hide precharge t i me an d th e

capability to randomly change column addresses on

each cloc k cycle during a burst access.

NOTE: 1. Throughout the data sheet, the various fig-

ures and text ma y refer to CS0# and CS1# as

“CS#.” The CS# term is to be interpreted for

single die operation, unless specifically

stated otherwise.

2. Complete functionality is described

throug ho ut the doc ument and any one page

or diagram may have been simplified to

convey a topic and may not be inclusive of

all requirements.

Any specific requirement takes precedence over a

general statement.

Table 2: 512Mb TwinDie SDRAM Part Numbers

PART NUMBER VDD VDDQ CONFIGURATION FUNCTIONAL DIE

MT48LC32M16S2 3.3V 3.3V 8 Meg x 16 x 4 banks BOTH

MT48LC16M16T2 3.3V 3.3V 4 Meg x 16 x 4 banks TOP

MT48LC16M16B2 3.3V 3.3V 4 Meg x 16 x 4 banks BOTTOM

MT48V32M16S2 2.5V 2.5V or 1.8V 8 Meg x 16 x 4 banks BOTH

MT48V16M16T2 2.5V 2.5V or 1.8V 4 Meg x 16 x 4 banks TOP

MT48V16M16B2 2.5V 2.5V or 1.8V 4 Meg x 16 x 4 banks BOTTOM

MT48H32M16S2 1.8V 1.8V

8 Meg x 16 x 4 banks BOTH

MT48H16M16T2 1.8V 1.8V

4 Meg x 16 x 4 banks TOP

MT48H16M16B2 1.8V 1.8V

4 Meg x 16 x 4 banks BOTTOM

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Functionality (Per Die). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Write Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Extended Mode Reg ister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Temperature Compensated Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Deep power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Commands Per Die. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

COMMAND INHIBIT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

READs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

WRITEs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

POWER-DOWN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

DEEP POWER DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

CLOCK SUSPEND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

BURST READ/SINGLE WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Concurrent AUTO PRECHARGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

TwinDie Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

MODE REGISTE R. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Commands (TwinDie) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

LOAD MODE REGISTER. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

AUTO PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Absolute Maxi mum Rati ngs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Notes (Single Die) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Rev C, 10/27/2003 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Rev B, 02/27/03. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

Rev A, 11/25/02. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

List of Figures

Figure 1: Ball Assignment (T op View) 54-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 2: Functiona l Block Diagr am . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 3: Functional Block Diagram 16 M eg x 16 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Figure 4: Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Figure 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Figure 6: Extended Mode R egist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 7: Activat ing a Specific Row In a Specif ic B ank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 8: Example: Meeting RCD (MIN) When 2 < RCD (MIN)/ CK 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 9: Read Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Figure 10: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 11: Consecutive READ Bursts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 12: Ran dom READ Access es . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 13: READ to WRIT E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 14: READ to WRIT E wit h Ex t ra Clo ck Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Figure 15: Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 16: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 17: WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 18: WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 19: Ran dom WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 20: WRITE To READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Figure 21: WRITE To PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 22: Terminating a WRITE Burs t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Figure 23: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 24: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Figure 25: Deep Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 26: Clock Suspend During WRITE Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 27: Clock Suspend During READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Figure 28: READ With Auto Precharge Interrup ted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 29: READ With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Figure 30: WRITE With Auto Precharge Interrup ted by a READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 31: WRITE With Auto Precharge Interrupted by a WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Figure 32: Initialize And Load Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 33: Power-down Mode1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 34: Clock Suspend Mode1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 35: Auto Refresh Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 36: Self Refr es h Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 37: READ – Without Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 38: READ – With Auto Precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 39: Single READ – Without Auto Precharge 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 40: Single READ – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 41: Alternating Bank Read Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 42: Read – Fu ll-page B urst 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 43: Read DQM Operation1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 44: Write – Wi thout Auto P recharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 4

Figure 45: Write – With Auto Precharge1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 4 6 : Single W rite – W ithout Auto Prechar g e1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Figure 47: Single Write with Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 48: Alternating Bank Write Accesses1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Figure 49: Write – Full-page Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 50: Write – DQM Operation1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 51: FGBA “FG” Package 54-pin, 8mm x 14mm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

List of Tables

Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 2: 512Mb TwinDie SDRAM Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

Table 3: 54-Ball FBGA Ball Descri ption s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

Table 5: CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Table 6: Truth Table – Commands And DQM Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Table 7: Truth Table – CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Table 8: Truth Table – Current State Bank n - Command To Bank n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Table 9: Truth Table – Current State Bank n – Command To Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Table 10: DC Electrical Characteristics And Operating Conditions - “LC” Version. . . . . . . . . . . . . . . . . . . . . . . .36

Table 11: DC Electrical Characteristics And Operating Conditions - “V” Version . . . . . . . . . . . . . . . . . . . . . . . . .36

Table 12: DC Electrical Characteristics And Operating Conditions - “H” Version. . . . . . . . . . . . . . . . . . . . . . . . .37

Table 13: IDD Specifications And Condition s (Both Die – S2 Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 14: IDD7 - Self Refresh Curren t Options– S2 Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Table 15: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Table 16: Electrical Charact e ristics And Recommended AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . .39

Table 17: AC Functional Char act eristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

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Figure 2: Functional Block Diagram

CS#1

Command

DQ0-15,

DQM

CS#0

CLK

CKE#

Addresses

TOP

DIE BOTTOM

DIE

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

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Figure 3: Functi onal Block Diagram 16 Meg x 16 SDRAM

NOTE:

This device is a 512Mb SDRAM part made up of two stacked 256Mb SDRAM components. The above drawing illus-

trates one of the 256Mb SDRAM components.

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS# 1

WE#

CKE

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTER

COMMAND

DECODE

A0-A12,

BA0, BA1

DQML,

DQMH

ADDRESS

512

(x16)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 512 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0-

DQ15

16 DATA

INPUT

DATA

OUTPUT

BANK1BANK2 BANK3

2 2

REFRESH

COUNTER

CS# 0

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

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Table 3: 54-Ball FBGA Ball Descriptions

BALL NUMBERS SYMBOL TYPE DESCRIPTION

F2 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

F3 CKE Input Clock Enable: CKE activates (HIGH) and deactactivates (LOW) the CLK signal.

Deactivatin g the CLK provides POWER- DOWN and SELFREFRESH ope ration (all

banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK

SUSPEND operatio n (burst/access in progress). C KE is synchronou s except after

the device enters power-down and self refresh modes, where CKE becomes

asynchronous until after exiting the same mode. The input buffers, including

CLK, are disabled during power-down and self refresh modes, providing low

standby power. CKE may be tied HIGH.

G9, E2 CS#(0)

CS#(1) Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH.

CS# provides for external bank selection on systems with multiple banks. CS#

is considered part of the command code. CS#(0) (BOTTOM DIE) is used to

select the 256Mb chip, CS#(1) (TOP DIE) is used to select the 256Mb chip.

F7, F8, F9 CAS#,

RAS#,

WE#

Input Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the

command being entered.

E8, F1 LDQM,

UDQM Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal for

write accesses and an output enable signal for read accesses. Input data is

masked during a WRIT E cy cle. The output buf f ers are plac ed in a High-Z s tat e

(two-clock latency) when during a READ cycle. LDQM corresponds to DQ0-

DQ7, UDQM corresponds to DQ8-DQ15. LDQM and UDQM are considered

same state when referenced as DQM.

G7, G8 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also prov ide the

op- code during a LOAD MODE REGISTER command

H7, H8, J8, J7, J3,

J2, H3, H2, H1, G3,

H9, G2, G1

A0-A12 Input Address Inputs: A0-A12 are sampled during the ACTIVE command (row-

address A0-A11) and READ/WRITE command (column-address A0-A8; with

A10 defining auto precharge) to select one location out of the memory array

in the respective bank. A10 is sampled during a PRECHARGE command to

determine if all banks are to be precharged (A10 HIGH) or bank selected by

BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD

MODE REGISTER command.

A8, B9, B8, C9, C8,

D9, D8, E9, E1, D2,

D1, C2, C1, B2, B1,

DQ0-

DQ15 I/O Data Input/Output: Data bus

A7, B3, C7, D3 VDDQSupply DQ Power: Provide isolated power to DQs for improved noise immunity.

A3, B7, C3, D7, VSSQSupply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

A9, E7, J9 VDD Supply Power Supply: Voltage dependant on option.

A1, E3, J1 VSS Supply Ground

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Functio n a l D e scrip tion

The 512Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 536,870,912 bits. It

is internally configured by stacking two 256Mb,

16M egx16 devices. Each of these 256Mb devices is con-

figured as a quad bank DRAM with a synchronous

interface. They ar e organized with 16 DQs with 4 banks

of 67,108,864 bits, comprisin g of 8,192 rows by 512 col-

umns by 16 bits wide.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and con-

tinue for a programmed number of locations in a

programmed sequ ence. Accesses begin wit h the regis-

tration of an ACTIVE command, which is then fol-

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed

(BA0, BA1 select the bank; A0-A12 select the row). The

address bits registered coincident with the READ or

WRITE command are used to select the starting col-

umn lo cation fo r the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

page, with a bu rs t termi na te option. An a ut o prechar g e

function may be enabled to provide a self-timed row

precharge that is initiated at the end of the burst

sequence.

The 512Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This

architecture is c ompatible with the 2n rule of prefetch

architectures, but it also allows the column address to

be changed on every clock cycle to achieve a high-

speed, fully random access. Precharging one bank

while accessing one of the other three banks will hide

the precharge cycles and provide seamless, high-

speed, random-access operation.

The 512Mb SDRAM is designed to operate in 3.3V or

2.5V memory systems. An auto refresh mode is pro-

vided, along with a power-saving, power-down mode.

All inpu ts and outputs are LV TTL-compat ible.

SDRAMs offer substantial advances in DRAM oper-

ating performance, including the ability to synchro-

nously burst data at a high data rate with automatic

column-address generation, the ability to interleave

betwe en i n tern al ban ks to hide pr ec harge time an d t he

capability to randomly change column addresses on

each cloc k cycle during a burst access.

Prior to no rmal operation , the SDRAM must be ini-

tialized. The following sections provide detailed infor-

mation covering die intitialization, register definition,

command descriptions, and device operation on a per

die basis unle ss otherwise noted.

Function a lity (Per Die)

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other

than those specified may result in undefined opera-

tion. Onc e power is appl ie d to VDD an d VDD Q (si mul-

taneously) and the clock is stable (stable clock is

defined as a signal cycling within timing constraints

specified for the clock pin), the SDRAM requires a

100µs delay prior to issuing any command other than a

COMMAND INHIBIT or NOP. Starting at some point

during this 100µs period and continuing at least

through the end of this period, COMMAND INHIBIT

or NOP commands should be applied.

Once th e 1 0 0µs de l ay has been satisfi e d wi th a t least

one COMMAND INHIBIT or NOP command having

been applied, a PRECHARGE command should be

applied. All banks must then be precharged, thereby

plac ing the device in the all ban ks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles

are complete, the SDRAM is ready for Mode Register

programming. Because the Mode Register will power

up in an unknown state, it should be loaded prior to

applying any operationa l command.

Mode Register

The Mode Register is used to define the specific

mode of operation of the SDRAM. This definition

include s the se lection of a burs t length , a burst type, a

CAS latency, an operating mode and a write burst

mode, as shown in Figure4. The Mode Register is pro-

grammed via the LOAD MODE REGISTER command

and will retain the stored information until it is pro-

gra mmed ag ai n o r the devi c e loses power.

Mode Register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-

leaved), M4-M6 specify the CAS latency, M7 and M8

specify the operating mode, M9 specifies the write

burst mode, and M10 and M11 are reserved for future

use. Address A12 (M12) is undefined but should be

driven LOW during loading of the Mode Register.

The Mode Register must be loaded when all banks

are idle, and the controller must wait the specified

time before initiating the subsequent operation. Vio-

lating either of these requirements will result in

unspecified operation.

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

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Bur s t Le ng th

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as

shown in Figure4. The burst length determines the

maximum number of column locations that can be

accessed for a given RE AD or WRITE command . Burst

lengths of 1, 2, 4 or 8 locations are available for both

the sequential and the interleaved burst types, and a

full-page burst is available for the sequential type. The

full-p age b urst is used in conj unction with th e BURST

TERMINATE command to generate arbitrary burst

lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A1-A9 (x16) when the burst length is set to

two; b y A2-A 9 (x 16) when th e burs t leng th is set to four;

and by A3-A9 (x16) when the burst length is set to

eight. The remaining (least significant) address bit(s) is

(are) used to select the starting location within the

block. Full-page bursts wrap within the page if the

boundary is reached.

Burst Type

Accesses within a given burst may be programmed

to be either sequent ia l or inter l eav ed; this is refer red to

as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the bu r st length, the bur s t ty p e and the start-

ing column address, as shown in Table 4.

Figure 4: Mode Register Defini t ion

14 10

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A9 A7 A6 A5 A4 A3

A8 A2 A1 A0

Mode Register (Mx)

Address Bus

976543

8210

M6-M0

M8 M7

Op Mode

A10

A11

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = “0, 0, 0”

to ensure compatibility

with future devices.

A12

BA0

13 12

BA1

0 0

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NOTE: 1. For full-page acc e sses: y = 1,024 (x16).

2. For a burst length of two, A1-A9 (x16) select

the block-of-two burst; A0 selects the start-

ing colum n wit hin the block.

3. For a burst length of four, A2-A9 (x16) select

the block-of-four burst; A0-A1 select the

starting column within the block.

4. For a burst length of eight, A3-A9 (x16)

select the block-of-eight burst; A0-A2 select

the starting column within the block.

5. For a full-page burst, the full row is selected

and A0-A9 (x16) select the start ing column.

6. Whenever a boundary of the block is

reached within a giv en sequence above, the

following access wr ap s w ithin the bl o ck.

7. For a burst length of one, A0-A9 (x16) select

the unique column to be accessed, and

Mod e Register bit M3 is ignored.

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the

availa bili ty of the f irst pi ece of outp ut data . The la tency

can be set to two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

by clock edge n + m. The DQs will start driving as a

result of the clock edge one cycle earlier (n + m - 1),

and provided that the relevant access times are met,

the data will be valid by clock edge n + m. For example,

assumi ng that the cl ock cycle tim e is s uch tha t all rele-

vant ac cess times are met, if a READ command i s re gis -

tered at T0 and the latency is programmed to two

clocks, the DQs will start driving after T1 and the data

will be valid by T2, as shown in Figure 5. Table 5 below

indicates the operating frequencies at which each CAS

laten cy setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result. Figure 5: CAS Latency

Operati ng Mo de

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values

for M7 and M8 are reserved for future use and/or test

modes. The programmed burst length applies to both

READ and W RITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with

future versions may result.

Table 4: Burst Definition

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN A BURST

TYPE =

SEQUENTIAL TYPE = INTERLEAVE D

2A0

00-1 0-1

11-0 1-0

4A1A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

8 A2A1A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

Page

(y)

n = A0-

A12/11/9

(location

0-y)

Cn, Cn + 1, Cn

+ 2

Cn + 3, Cn +

4…

…Cn - 1,

Cn…

Not Supported

CLK

T2T1 T3T0

CAS Latency = 3

OUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

OUT

tOH

COMMAND NOPREAD

tAC

NOP

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Write Burst Mode

When M9 = 0, the burst length programmed via M0-

M2 applies to both READ and WRITE bursts; when M9

= 1, the programmed burst length applies to READ

bursts, but write accesses are single-location (non-

burst) accesses.

Figure 6: Extended Mode Register

NOTE: E14 and E13 (BA1 and BA0) must be “1, 0 ” to

select the Extended Mode Register (vs. the

base Mode Register).

Extended Mode Register

The Extended Mode Register controls the functions

beyond those controlled by the Mode Register. These

addit ional func tions are spe cial features o f the Mobile

Ram device. They include Temperature Compensated

Self Refresh (TCSR) control and Partial Array Self

Refresh (P ASR).

The Extended Mode Register is programmed via the

Mode register Set command (BA1=1, BA0=0) and

retains the stored information until it is programmed

agai n or the d evice loses power.

The Extended Mode Register must be programmed

with M6 through M12 set to “0”. The Extended Mode

bursts are in progress, and the controller must wait the

specif ied tim e before i nitiati ng any subseq uent opera-

tion. Violating these requirements results in unspeci-

fied opera tion.

The Extended Mode Register must be programmed

in order to use this device properly.

Temperature Compensated Self Refresh

Temperature Compensated Self Refresh allows the

controller to program the Refresh interval during SELF

REFRESH mode, according to the case temperature of

the Mobile Ram device. This allows great power sav-

ings during SELF REFRESH during most operating

temperature ranges. Only during extreme tempera-

tures would the controller have to select a TCSR level

that will guarantee data during SELF REFRESH.

Every cell in the DRAM requires refreshing due to

the capacitor losing its charge over time. The refresh

rate is dependent on temperature. At higher tempera-

tures a capacitor loses charge more quickly than at

lower t emperatures, requirin g the cells t o be refreshed

more often. Historically, during Self Refresh, the

refresh rate has been set to accommodate the worst

case, or highest temperature range expected.

Thus, during ambient temperatures, the power con-

sumed during refresh was unnecessarily high, because

the refresh rate was set to accommodate the higher

temperatures. Setting M4 and M3, allow the DRAM to

accommodate more specific temperature regions dur-

ing SELF REFRESH. There are four temperature set-

tings, which will vary the SELF REFRESH current

according to the selected temperature. This selectable

refresh rate will save power when the DRAM is operat-

ing at normal temperatures.

Partial Array Self Refresh

For further power savings during SELF REFRESH,

the PASR feature allows the controller to select the

amount of memory that will be refreshed during SELF

REFRESH. The refresh options are Four Bank; all four

banks, Two Bank; banks 0 and 1, One Bank; bank 0,

Half Bank; bank 0 with row address MSB 0; Quarter

Bank; bank 0 with row address 2 MSBs 0. WRITE and

READ commands can still occur during standard oper-

Table 5: CAS Latency

SPEED

ALLOWABLE OPERATING

FREQUENCY (MHZ)

CAS

LATENCY = 2

-8 £ 100

Maximum Case TempA4 A3

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A11BA0

1011121314

A12

PASRTCSR1

0All have to be set to "0"

BA1

RFU

1 1

70˚C

0 0

45˚C

RFU

1 0

Self Refresh Coverage

Four Banks

Two Banks (BA1=0)

One Bank (BA1=BA0=0)

RFU

Half Bank (BA1=BA0=0)

A2 A1 A0

000

001

111

Quarter Bank (BA1=BA0=0)

RFU

Driver StrengthA5

Half Strength

Full Strength

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ation, but only the selected banks will be refreshed

during SELF REFRESH. Data in banks that are disabled

will be lost.

Deep power Down

Deep Power Down is an operating mode to achieve

maximum power reduction by eliminating the power

of the whole memor y array of the device. Data will not

be retained once the device enters Deep Power Down

Mode.

This mode is entered by having all banks idle then

/CS and /WE held low with /RAS and /CAS held high at

the rising edge of the clock, while CKE is low. This

mode is exited by asserting CKE high.

Driver Strength

Extended mode register bit A5 must be used to set

the DQ output drive strength. Full drive strength is

suitable for systems in which the SDRAM component

is placed on a module. Half drive strength is recom-

mended for point-to-point or other applications with

reduced output loading .

The half-strength can be used for point-to-point

applicat ion s. Point-to- point systems are usually light ly

loaded with a memory controller accessing one to

eight SDRAM components on the memory bus with

module stubs between these devices. Driver strength

chosen should be load dependent. The lighter the

load, the less driver strength that is needed for the out-

puts.

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Commands Per Die

Tab le 6 provides a quic k reference of ava ilable com-

mands. This is followed by a written description of

each command. Three additional Truth Tables appear

following the Operation section; these tables provide

current state/next state information.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW.

3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.

4. A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW dis-

ables the auto precharge feature; BA0, BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are “Don’t

Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-c lock dela y) and READs (two-cloc k delay).

9. Standard SDRAM parts assign this command sequence as Burst Terminate. For Mobile Ram devices, the Burst Terminate

command is assigned to the Deep Power Down function.

Table 6: Truth Table – Commands And DQM Operation

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQS NOTES

COMMAND INHIBIT (NOP) HXXXX X X

NO OPERATION (NOP) LHHHX X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) LHLH

L/H8Bank/Col X 4

WRITE (Select bank and column, and start WRITE

burst) LHLL

L/H8Bank/Col Valid 4

DEEP POWER DOWN LHHLX X X 9

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SE LF REFRESH LLLHX X X 6, 7

(Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ----L - Active8

Write Inhibit/Output High-Z ----H -High-Z8

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COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM,

regardless of whether the CLK signal is enabled. The

SDRAM is effectively deselected. Operations already in

progress are not aff ec ted.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

perform a NOP to an SDRAM which is selected (CS# is

LOW). This prevents unwanted commands from being

registered during idle or wait states. Operations

already in progress are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-A11 (A12

should be driven LOW.) See Mode Register heading in

the Register Definition section. The LOAD MODE

banks a re idle, and a subsequent executable c omma nd

cannot b e issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a part icular b ank for a sub sequent acce ss. The

value on the BA0, BA1 inputs selects the bank , and the

address provided on inputs A0-A12 selects the row.

This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A PRE-

CHARGE command must be issued before opening a

different row in the same bank.

READ

The R EAD com mand is used t o initiate a burs t read

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0-A9 (x16) selects the starting column loca-

tion. The value on input A10 determines whether or

not auto precharge is used. If auto precharge is

selected, the row being accessed will be precharged at

the end of the READ burst; if auto precharge is not

selected, the row will remain open for subsequent

accesse s. Read data appe ars on the DQs subje ct to th e

logic level on the DQM inputs two clocks earlier. If a

given DQM signal was registered HIGH, the corre-

sponding DQs will be High-Z two clocks later; if the

DQM signal was registered LOW, the DQs will provide

valid data.

WRITE

The WRITE command is used to initiate a burst

write access to an active row. The value on the BA0,

BA1 inputs selects the bank, and the address provided

on inputs A0-A9 (x16) selects the starting column loca-

tion. The value on input A10 determines whether or

not auto precharge is used. If auto precharge is

selected, the row being acce ssed will be precharged at

the end of the WRITE burst; if auto precharge is not

selected, the row will remain open for subsequent

acces ses . I n put dat a appea ring on the D Qs is wri tten to

the memory array subject to the DQM input logic level

appearing coincident with the data. If a given DQM

signal is registered LOW, the corresponding data will

be written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs will be ignored,

and a W RIT E w ill n ot be ex ecu t ed to t ha t byte/c o lu mn

location.

PRECHARGE

The PRECHARGE command is used to deactivate

the open r ow in a partic ular bank or the op en ro w in a ll

banks. The bank(s) will be available for a subsequent

row access a speci fied ti me (tRP ) afte r the PRE CHARGE

command is issued. Input A10 determines whether

one or all banks are to be precharged, and in the case

where only one bank is to be precharged, inputs BA0,

BA1 select the ban k. Otherwise BA0, BA1 are treated as

“Don’t Care.” Once a bank ha s be en precharged , it is in

the idle state and m ust be ac tivate d pri or to an y READ

or WRITE commands b e ing issued to that bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the

same individual-bank PRECHARGE function

described above, without requiring an explicit com-

mand. This is accomplished by using A10 to enable

auto precharge in conjunc tion with a spe cific REA D or

WRITE command. A PRECHARGE of the bank/row

that i s addr e ssed with the READ or WRITE command is

automatically performed upon completion of the

READ or WRITE burst, except in the full-page burst

mode, where auto precharge does not apply. Auto pre-

charge is nonpersistent in that it is either enabled or

disabled for each individual READ or WRITE com-

mand.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. The user

must not issue another command to the same bank

until the precharge time (tRP) is completed. This is

determined as if an explicit PRECHARGE command

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was issued at the earliest possible time, as described

for each burst type in the Operation section of this

data sheet.

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most

rec ent ly reg is tere d RE A D or WR IT E c omm a nd p ri or to

the BURST TERMINATE command will be truncated,

as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the SDRAM and is analogous to CAS#-BEFORE-RAS#

(CBR) REFRESH in conventional DRAMs. This com-

mand is nonpersistent, so it must be issued each time

a refresh is required. All active banks must be PRE-

CHARGED prior to issuing a AUTO REFRESH com-

mand. The AUTO REFRESH command should not be

issued until the minimum tRP has been met after the

PRECHARGE command as shown in the operations

section.

The addressing is generated by the internal refresh

controller. This makes the address bits “Don’t Care”

during an AUTO REFRESH command. The 512Mb

SDRAM requires 8,192 AUTO REFRESH cycles every

64ms (tREF), regardless of width option. Providing a

distributed AUTO REFRESH command every 7.81µs

will meet th e refresh requirement and ensure tha t e ac h

row is refreshed. Alternatively, 8,192 AUTO REFRESH

commands can be issued in a burst at the minimum

cycle rate (tRC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to reta in

data in the SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the

SDRAM retains data without external clocking. The

SELF REFRESH command is initiated like an AUTO

REFRESH command except CKE is disabled (LOW).

Once the SELF REFRESH command is registered, all

the inputs to th e SDRAM become “ Don’t Care” with t he

exception of CKE, which must remain LOW.

Once self refresh mode is e ngaged, th e SDRAM pro-

vides its own internal clocking, causing it to perform

its own AUTO REFRESH cycles. The SDRAM must

remain in self refresh mode for a minimum period

equal to tRAS and may remain in self refresh mode for

an indefinite perio d beyond that.

The procedure for exiting self refresh requires a

sequence of commands. First, CLK must be stable (sta-

ble clock is defined as a signal cycling within timing

constraints specified for the clock pin) prior to CKE

going back HIGH. Once CKE is HIGH, the SDRAM

must have NOP commands issued (a minimum of two

clocks) for tXSR because time is required for the com-

pletion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH

commands must be issu ed every 7 .81µs or less a s both

SELF REFRESH and AUTO REFRESH utilize the row

refresh c ounter.

Operation

Bank/Row Activation

Before any READ or WRITE commands can be

issued to a bank within the SDRAM, a row in that bank

must be “opened.” This is accomplished via the

ACTIVE command, which selects both the bank and

the row to be activated (see Figure 7).

After ope ning a row (issuin g an ACTIVE comm and),

a READ or WRITE command may be issued to that row,

subject to the tRCD specification. tRCD (MIN) should

be divided by the clock period and rounded up to the

next whole number to determine the earliest clock

edge after the ACTIVE command on which a READ or

WRITE command ca n be entered. For example, a tRCD

specification of 20ns with a 125 MHz clock (8ns

period) results in 2.5 clocks, rounded to 3. This is

reflected in Figure 8, which covers any case where 2 <

tRCD (MIN)/tCK - 3. (The same procedure is used to

convert other specification limits from time units to

clock cycles.) A subsequent ACTIVE command to a dif-

ferent row in the same bank can only be issued after

the previous active row has been “closed” (pre-

charge d) . T he mi ni mu m t im e i n terval between succes -

sive ACTIVE commands t o the same bank is defined by

tRC.

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Figure 7: Activating a Specific Row In a

Specific Bank

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row-access over-

head. The minimum time inter val between successive

ACTIVE commands to different banks is defined by

tRRD.

Figur e 8: Example: Meeting RCD (MIN)

When 2 < RCD (MIN)/ CK 3

READs

READ bursts are initiated with a READ command, as

shown in Figure9.

The starting column and bank addresses are pro-

vided with the READ command, and auto precharge is

either enabled or disabled for that burst access. If auto

precharge is enabled, the row being accessed is pre-

charged at the completion of the burst. For the generic

READ commands used in the following illustrations,

auto precharge is disabled.

During READ bursts, the valid data-out element

from the star ting column address will be available fol-

lowing the CAS latency after the READ command.

Each subsequent data-out element will be valid by the

next positive clock edge. Figure 10 shows general tim-

ing for eac h pos sib l e CAS la ten c y se tti ng .

Figure 9: Read Command

CS#

WE#

CAS#

RAS#

CKE

CLK

A0-A12 ROW

ADDRESS

DON’T CARE

HIGH

BA0, BA1 BANK

ADDRESS

CLK

T2T1 T3T0

COMMAND NOPACTIVE READ or

WRITE

NOP

RCD

DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0-A9: x16

A10

BA0,1

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A9, A11, A12: x16

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Figure 10: CAS Latency Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-

Z. A full-page bu rst will continu e until ter minated. (At

the end of th e page , it wi ll wra p to the start addr ess and

continue.) Data from any READ burst may be trun-

cated with a subsequent READ command, and data

from a fixed-length READ burst may be immediately

followed by data from a READ command. In either

case, a continuous flow of data can be maintained. The

first dat a elemen t from the new bu rst f ollo ws eith er the

last element of a completed burst or the last desired

data element of a longer burst that is being truncated.

The new READ command should be issued x cycles

befor e the c lock edge at which th e last desi r ed data ele-

ment is valid, where x equals the CAS latency minus

one. This is sho wn in Figure 11 for CAS latencies of two

and three; data element n + 3 is either the last of a

burst of four or the last desired of a longer burst. The

512Mb SDRAM uses a pipelined architecture and

ther efor e does not re quir e the 2n rule as sociat ed with a

prefetch architecture. A READ command can be initi-

ated on any clock cycle following a previous READ

command. Full-speed random read accesses can be

performed to t he sa me bank, a s sh own in Figure 12, or

each subsequent READ may be performed to a differ-

ent bank.

Figure 11: Consecutive READ Bursts

CLK

T2T1 T3T0

CAS Latency = 3

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

UNDEFINED

CLK

T2T1 T3T0

CAS Latency = 2

DOUT

tOH

COMMAND NOPREAD

tAC

NOP

DON’T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

DOUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

BANK,

COL b

DOUT

n + 1 D

OUT

n + 2 D

OUT

n + 3 D

OUT

READ NOP

X = 2 cycles

CAS Latency = 3

TRANSITIONING DATA

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Figure 12: Random READ Accesses

Data from any REA D bu rst may be tr uncate d w ith a

subsequent WRITE command, and data from a fixed-

length READ burst may be immediately followed by

data from a WRITE command (subject to bus turn-

around limitations). The WRITE burst may be initiated

on the clock edge immediately following the last (or

last desired) data element from the READ burst, pro-

vided that I/ O contention can be avoided. In a given

system design, there may be a possibility that the

device driving the input data will go Low-Z before the

SDRAM DQs go High-Z. In this case, at least a single-

cycle delay should occur between the last read data

and the WRITE command.

The DQM input is used to avoid I/O contention, as

shown in Figure 13 and Figure 14 on page 21. The

DQM signal must be asserted (HIGH) at least two

clocks prior to the WRITE command (DQM latency is

two clocks for output buffers) to suppress data-out

from the READ. Once the WRITE command is regis-

tered, the DQs will go High-Z (or remain High-Z),

regardless of the state of the DQM signal; provided the

DQM was active on the clock just prior to the WRITE

command that truncated the READ command. If not,

the second WRITE will be an invalid WRITE. For exam-

ple, if DQM was LOW during T4 in Figure 14 on

page 21, then the WRITEs at T5 and T7 would be valid,

while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the

WRITE command (DQM latency is zero clocks for

input buffers) to ensure that the written data is not

masked. Figure13 shows the case where the clock fre-

quency allows for bus contention to be avoided with-

out adding a NOP cycle, and Figure 14 shows the case

where the additional NOP is needed.

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK,

COL n

DON’T CARE

OUT

READ

NOTE: Each READ command may be to any bank. DQM is LOW.

READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK,

COL n

OUT

READ READ READ NOP

BANK,

COL aBANK,

COL xBANK,

COL m

CAS Latency = 2

CAS Latency = 3

TRANSITIONING DATA

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Figure 13: READ to WRITE

Figure 14: READ to WRITE with Extra

Clock Cycle

A fixed-length READ burst may be followed by, or

truncated with, a PRECHARGE command to the same

bank (pr ovided that aut o precharge wa s not acti va ted),

and a full-page burst may be truncated with a PRE-

CHARGE command to the same bank. The PRE-

CHARGE command should be issued x cycles before

the clock edge at which the last desired data elemen t is

valid, where x equals the CAS latency minus one. This

is shown in Figure 11 for each possible CAS latency;

data element n + 3 is either the last of a burst of four or

the last desired of a longer burst. Following the PRE-

CHARGE command, a subsequent command to the

same b an k cannot be issued unt il tRP is met. Note that

part of the row precharge time is hidden during the

access of the last data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the

optimum time (as described above) provides the same

operation that would result fr om the same fixed-length

burst with auto precharge. The disadvantage of the

PRECHARGE command is that it requires that the

command and address buses be available at the

approp riate t ime to iss ue the comman d; the advant age

of the PRECHARGE command is that it can be used to

truncate fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length

READ bursts may be truncated with a BURST TERMI-

NATE command, provided that auto precharge was

not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at

which the last desired data element is valid, where x

equals the CAS latency minus one. This is shown in

Figure 15 for each possible CAS latency; data element

n + 3 is the last desired data element of a longer burst.

DON’T CARE

READ NOP NOP WRITE

NOP

CLK

T2T1 T4T3T0

DQM

DQ DOUT n

COMMAND

DIN b

ADDRESS BANK,

COL nBANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ

command may be to any bank, and the WRITE command

may be to any bank. If a burst of one is used, then DQM is

not required.

TRANSITIONING DATA

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

DQ DOUT n

T2T1 T4T3T0

COMMAND

ADDRESS BANK,

COL n

WRITE

DIN b

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

TRANSITIONING DATA

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Figure 15: Terminating a READ Burst

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

BURST

TERMINATE NOP

DON’T CARE

NOTE: DQM is LOW.

CLK

DQ DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

DOUT

n + 1 DOUT

n + 2 DOUT

n + 3

BURST

TERMINATE NOP

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

TRANSITIONING DATA

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WRITEs

WRITE b ursts are initiated with a WRITE com mand,

as shown in Figure 16 Write command.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge

is either enabled or disabled for that access. If auto

precharge is enabled, the row being accessed is pre-

charged at the completion of the burst. For the generic

WRITE commands used in the following illustrations,

auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered coincident with the WRITE com-

mand. Subsequent data elements will be registered on

each success ive positive clock edge. Upon completion

of a fixed-length burst, assuming no other commands

have been initiated, the DQs will remain High-Z and

any additional input data will be ignored (see

Figure 17) Write Burst. A full-page burst will continue

until termi n ated. (At the end of the page, it will wr a p to

the start address and continue.) Data for any WRITE

burst may be truncated with a subsequent WRITE

command, and data for a fixed-length WRITE burst

may be immediately followed by data for a WRITE

command. The new WRITE command can be issued

on any clock following the previous WRITE command,

and the data provided coincident with the new com-

mand applies to the new command. An example is

shown in Figure 18 (Write to Write). Data n + 1 is either

the last of a burst of two or the last desired of a longer

burst. The 512Mb SDRAM uses a pipelined architec-

ture and therefore does not require the 2n rule associ-

ated with a prefetch architecture. A WRITE command

can be initiated on any clock cycle follow ing a previous

WRITE command. Full-speed random write accesses

within a page can be performed to the same bank, as

sho wn in Figure19, or each subsequent WRITE may be

performed to a different bank.

Figure 16: WRITE Command Figure 17: WRITE Burst

Figure 18: WRITE to WRITE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A10

DON’T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0-A9: x16

A9, A11, A12: x16

BA0, BA, 1 BANK

ADDRESS

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

NOP NOP

DON’T CARE

WRITE

DIN

n + 1

NOP

BANK,

COL n

NOTE: Burst length = 2. DQM is LOW.

TRANSITIONING DATA

CLK

T2T1T0

COMMAND

ADDRESS

NOPWRITE WRITE

BANK,

COL nBANK,

COL b

n + 1 D

NOTE: DQM is LOW. Each WRITE command may

be to any bank.

DON’T CARE

TRANSITIONING DATA

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Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-

length WRITE burst may be immediately followed by a

READ command. Once the READ command is regis-

tered, the data inputs will be ignored, and WRITEs will

not be executed. An example is shown in Figure 20.

Data n + 1 is either the last of a burst of two or the last

desired of a longer burst.

Data for a fixed-length WRITE burst may be fol-

lowed by, or truncated with, a PRECHARGE command

to the same bank (provided that auto precharge was

not activated), and a full-page WRITE burst may be

truncated with a PRECHARGE command to the same

bank. The PRECHARGE command should be issued

tWR after the cl ock edge at which the last des ired input

data element is registered. The auto precharge mode

requires a tWR of at least one clock plus time, regard-

less of frequency. In addition, when truncating a

WRITE burst, the DQM signal must be used to mask

input data for the clock edge prior to, and the clock

edge coincident with, the PRECHARGE command. An

example is shown in Figure21. Dat a n + 1 is either the

last of a burst of two or the last desired of a longer

burst. Following the PRECHARGE command, a subse-

quent command to the same bank cannot be issued

until tRP is met. The precharge can be issued coinci-

dent with the first coincident clock edge (T2 in

Figure21) on an A1 Version and with the second clock

on an A2 Version (Figure 21.) In the case of a fixed-

length burst being executed to completion, a PRE-

CHARGE command issued at the optimum time (as

described above) provides the same operation that

would result from the same fixed-length burst with

auto precharge. The disadvantage of the PRECHARGE

command is that it requires that the command and

address buses be available at the appropriate time to

issue th e comm and ; the a dva nt ag e of th e PRECHARG E

command is that it can be used to truncate fixed-

length or full-page bursts.

Fixed-length or full-page WRITE bursts can be trun-

cated with the BURST TERMINATE command. When

truncating a WRITE burst, the input data applied coin-

cident with the BURST TERMINATE command will be

ignored. The last data written (provided that DQM is

LOW at that time) will be the input data applied one

clock previous to the BURST TERMINATE command.

This is shown in Figure 22, where data n is the last

desired data element of a longer burst.

Figure 19: Random WRITE Cycles

Figure 20: WRITE To READ

DON’T CARE

CLK

DQ DIN

T2T1 T3T0

COMMAND

ADDRESS

WRITE

BANK,

COL n

DIN

aDIN

xDIN

WRITE WRITE WRITE

BANK,

COL aBANK,

COL xBANK,

COL m

NOTE: Each WRITE command may be to any bank. DQM is LOW.

TRANSITIONING DATA

DON’T CARE

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOPWRITE

BANK,

COL n

DIN

nDIN

n + 1 DOUT

READ NOP NOP

BANK,

COL b

NOP

DOUT

b + 1

T4 T5

NOTE: The WRITE command may be to any bank, and the READ command

may be to any bank. DQM is LOW. CAS latency = 2 for illustration.

TRANSITIONING DATA

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Figure 21: WRITE To PRECHAR GE

Figure 22: Terminating a WRITE Burst

PRECHARGE

The PRECHARGE command (see Figure23) is used

to deactivate the open row in a particular bank or the

open row in all banks. The bank(s) will be available for

a subsequent row access some specified time (tRP)

after the precharge command is issued. Input A10

determines whether one or all banks are to be pre-

charged, and in the case where only one bank is to be

precharged, inputs BA0, BA1 select the bank. When al l

banks are to be precharged, inputs BA0, BA1 are

treated as “Don’t Care.” Once a bank has been pre-

charged, it is in the idle state and must be activated

prior to any READ or WRITE commands being issued

to that bank.

POWER-DOWN

Power-down occurs if CKE is registered low coinci-

dent with a NOP or COMMAND INHIBIT when no

accesses are in progress. If power-down occurs when

all bank s are idle, this mode is referred to as precharge

power-down; if power-down occurs when there is a

row active in any bank, this mode is referred to as

active power-down. Entering power-down deactivates

the input and output buffers, excluding CKE, for maxi-

mum power savings while in standby. The device may

DON’T CARE

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

DIN

nDIN

n + 1

ACTIVE

tRP

BANK

(a or all)

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOPWRITE

PRECHARGE

NOPNOP

DIN

nDIN

n + 1

ACTIVE

tRP

BANK

(a or all)

NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

BANK a,

ROW

NOP

tWR @ tCLK ≥ 15ns

tWR = tCLK < 15ns

TRANSITIONING DATA

DON’T CARE

CLK

T2T1T0

COMMAND

ADDRESS BANK,

COL n

WRITE BURST

TERMINATE NEXT

COMMAND

DIN

(ADDRESS)

(DATA)

NOTE: DQMs are LOW.

TRANSITIONING DATA

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not remain in the power-down state longer than the

refresh period (64ms) since no refresh operations are

perf ormed in this mode.

The power-down state is exit ed by r eg i st ering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired

clock edge (meeting tCKS). (See Figure24.)

Figure 23: PRECHARGE Command

Figure 24: Power-Down

DEEP POWER DOWN

Deep Power Down mode is a maximum power sav-

ings feature achieved by shutting off the power to the

entire memory array of the device. Data will not be

retained once Deep Power Down mode is executed.

Deep Power Down mode is entered by having all banks

idle then /CS and /WE held low with /RAS and /CAS

high at the rising edge of the clock, while CKE is low.

CKE must be held low during Deep Power Down.

In order to exit Deep Power Down mode, CKE must

be asserted high. After exiting, the following sequence

is needed in order to enter a new command . Maintain

NOP input conditions for a minimum of 200us. Issue

PRECHARGE commands for all banks. Issue eight or

more AUTO RE FRESH comm ands . I ss ue a MODE REG-

ISTE R, s et co mmand to in itializ e mo de regi s te r. Issu e a

EXTENDED MODE REGISTER set command to initial-

ize the extended mode register. (See figure 26)

Figure 25: Deep Power Down

CLOCK SUSPEND

The clock suspend mode occurs when a column

access/ burst is i n progress and CKE is registered LOW.

I n the clock sus pend mode , t he internal cl ock is deac ti-

vated, “freezing” the synchronous logic.

For each positive clock edge on which CKE is sam-

pled LOW, the next internal positive clock edge is sus-

pended. Any command or data present on the input

pins at the time of a suspended internal clock edge is

ignored; any data present on the DQ pins remains

driven; and burst counters are not incremented, as

long as the clock is suspended. (See examples in

Figure 26 and Figure 27.)

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will

resume on the subs eq uent positive cl ock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the Mode

mands result in the a ccess of a single colu mn location

(burst of one), regardless of the programmed burst

length . REA D c omm and s acce ss col umns a ccording to

the programmed burst length and sequence, just as in

the normal mode of operation (M9 = 0).

DON’T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

HIGH

All Banks

Bank Selected

A0-A9, A11, A12

BA0, BA1 BANK

ADDRESS

DON’T CARE

tRAS

tRCD

tRC

All banks idle Input buffers gated off

Exit power-down mode.

()()

tCKS > tCKS

COMMAND

NOP ACTIVE

Enter power-down mode.

NOP

CLK

CKE

()()

DON’T CARE

Exit deep power-down mode.

()()

Enter deep power-down mode.

CLK

CKE

CS#

WE#

CAS#

RAS#

()()

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Figure 26: Clock Suspend During WRITE

Burst

Figure 27: Clock Suspend During READ

Burst

Concurrent AUTO PRECHA RGE

An access command to (READ or WRITE) another

bank while an access command with auto precharge

enabled is executing is not allowed by SDRAMs, unless

theSDRAMsupportsCONCURRENTAUTOPRE-

CHARGE. Micron SDRAMs support CONCURRENT

AUTO PRECHARGE. Four cases where CONCURR ENT

AUTO PRECHARGE occurs are defined below.

READ with auto precharge

1. Interrupted by a READ (with or without auto pre-

charge): A READ to bank m will interrupt a READ

on bank n, CAS latency lat er. The PRE CHARGE to

bank n will begin when the READ to bank m is

registered (Figure 28).

2. Interrupted by a WRITE (with or without auto pre-

charge): A WRITE to bank m will interrupt a READ

on bank n when registered. DQM should be used

two clocks prior to the WRITE command to pre-

vent bus contention. The PRECHARGE to bank n

will begi n wh en the WRITE to b ank m is r egistered

(Figure 29).

WRITE with auto precharge

3. Interrupted by a READ (with or without AUTO

PRECHARGE): A READ to bank m will interrupt a

WRITE on bank n when registered, with the data-

out app eari ng CAS latenc y l ater. The PRECHARGE

to bank n will begin after tWR is met, where tWR

begins when the READ to bank m is registered.

The last valid WRITE to bank n will be data-in reg-

istered one clock prior to the READ to bank m

(Figure 30).

4. Interrupted by a WRITE (with or without auto pre-

charge): A WRITE to bank m will interrupt a

WRITE on bank n when registered. The PRE-

CHARGE to bank n will begin after tWR is met,

where tWR begins when the WRITE to bank m is

registered. The last valid data WRITE to bank n

will be data registered one clock prior to a WRITE

to bank m (Figure 31).

DON’T CARE

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOPNOP

CLK

T2T1 T4T3 T5T0

CKE

INTERNAL

CLOCK

NOP

n + 1 D

n + 2

NOTE: For this example, burst length = 4 or greater, and DM

is LOW.

DON’T CARE

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK,

COL n

NOP

OUT

n + 1 D

OUT

n + 2 D

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

TRANSITIONING DATA

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Figure 28: READ With Auto Pre cha r g e Interrupt ed by a REA D

Figure 29: READ With Auto Precharge Interrupted by a WRITE

DON’T CARE

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

READ - AP

BANK nNOP NOPNOPNOP

DOUT

a + 1 DOUT

dDOUT

d + 1

NOP

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

NOTE: DQM is LOW.

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States t

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4 Precharge

RP - BANK ntRP - BANK m

CAS Latency = 3 (BANK n)

TRANSITIONING DATA

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

NOPNOPNOPNOP

DIN

d + 1

DIN

dDIN

d + 2 DIN

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

NOTE: 1. DQM is HIGH at T2 to prevent D

OUT

-a+1 from contending with D

-d at T4.

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States t

Page

Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active WRITE with Burst of 4 Write-Back

RP -

BANK

ntWR -

BANK

CAS Latency = 3 (BANK n)

READ - AP

BANK n

DON’T CARE

TRANSITIONING DATA

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Figure 30: WRITE With Auto Precharge Interrupted by a READ

Figure 31: WRITE With Auto Precharge Interrupted by a WRITE

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP

BANK nNOPNOPNOPNOP

DIN

a + 1

DIN

NOP NOP

BANK n

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

BANK n,

COL aBANK m,

COL d

READ - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

ttRP - BANK m

DOUT

dDOUT

d + 1

CAS Latency = 3 (BANK m)

RP - BANK n

WR - BANK n

TRANSITIONING DATA

DON’T CARE

CLK

T2T1 T4T3 T6T5T0

COMMAND WRITE - AP

BANK nNOPNOPNOPNOP

DIN

d + 1

DIN

a + 1 DIN

a + 2

DIN

aDIN

d + 2 DIN

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

NOTE: 1. DQM is LOW.

BANK n,

COL aBANK m,

COL d

WRITE - AP

BANK m

Internal

States

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active WRITE with Burst of 4 Write-Back

WR - BANK ntRP - BANK ntWR - BANK m

TRANSITIONING DATA

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NOTE:

1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDnis the command registered at clock edge n, and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided

that tCKS is met).

6. Exiting self refresh at cloc k edge n w ill put the dev ice in the a ll ba nks id le state once tXSR is m et. C OMMAND INHIBIT or

NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP com-

mands must be provided during tXSR period.

7. After exiting clock suspend at clock edg e n, the dev ice will resume ope ration an d reco gnize the nex t com man d at clock

edge n + 1.

8. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on tradi-

tional SDRAM components. For Mobile Ram devices, this command sequence is assigned to Deep Power Down.

Table 7: Truth Table – CKE

CKEN-1 CKENCURRENT STATE COMMANDNACTIONNNOTES

L L Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

Clock Suspend X Maintain Clock Suspend

L H Powe r-Down COMMAND INHIBIT or NOP Exit Power-Down 5

Deep Power-Down X Exit Deep Power-Down 8

Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6

Clock Suspend X Exit Clock Suspend 7

H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry

All Banks Idle DEEP POWER DOWN Deep Power-Down Entry 8

All Banks Idle AUTO REFRESH Self Refresh Entry

Reading or Writing VALID Clock Suspend Entry

H H See Truth Table 3 (page 28)

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NOTE:

1. This table applies when CKE n-1 was HIGH and CKEn is HIGH (see Table 7 on page 30) and after tXSR has been met (if the

previous state was self refresh).

2. This table is bank-specific, except where noted , i.e., the curr ent state i s fo r a specific bank and the co mmand s shown are

those allowed to be issued to that bank when in t hat state . Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or

been termina ted.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or

been termina ted.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP com-

mands, or allowable commands to the other bank should be issued on any clock edge occurring during these states.

Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Table 9

on page 33.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,

the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,

the bank will be in the row active state.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP

has been met. Once tRP is met, the bank will be in the idle state.

Write w /Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP

has been met. Once tRP is met, the bank will be in the idle state.

5. The following states must not be interrupted b y any executable command; COMMAND INHIBIT or NOP commands m ust

be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRC is met. Once tRC is

met, the SDRAM will be in the all banks idle state.

Table 8: Truth Table – Current State Bank n - Command To Bank n

(Notes: 1-6; notes appear below and on next page)

CURRENT

STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

LHHH

NO OPERATION (NOP/Continue previous operatio n)

Idle L L H H ACTIVE (Select and activate row)

LLLH

AUTO REFRESH 7

LLL L

LOAD MODE REGISTER 7

LLHL

PRECHARGE 11

Row Active L H L H READ (Select column and start READ burst) 10

LHL L

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Deactivate row in bank or banks) 8

Read

(Auto

Precharge

Disabled)

LHL H

READ (Select column and start new READ burst) 10

LHL L

WRITE (Select column and start WRITE burst) 10

LLHL

PRECHARGE (Truncate READ burst, start PRECHARGE) 8

LHH L

DEEP POWER DOWN 9

Write

(Auto

Precharge

Disabled)

LHL H

READ (Select column and start READ burst) 10

LHL L

WRITE (Select column and start new WRITE burst) 10

LLHL

PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

LHH L

DEEP POWER DOWN 9

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Accessing Mode

met. On ce tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is

met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Deep Power-Down is a power savings feature of this Mobile SDRAM device. This command is Burst Terminate on tradi-

tional SDRAM components. For Mobile Ram devices, this command sequence is assigned to Deep Power Down.

10.READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

11.Does not affect the state of the bank and acts as a NOP to that bank.

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NOTE:

1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been met (if the pre-

vious state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com-

mands shown are thos e allowed to be issued to bank m (assuming that bank m is in such a state that the given command

is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data burs ts/acces ses and no

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or

been termina ted.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or

been termina ted.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when tRP

has been met. Once tRP is met, the bank will be in the idle state.

Write w /Auto

Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when tRP

has been met. Once tRP is met, the bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current

state only.

Table 9: Truth Table – Current State Bank n – Command To Bank m

(Notes: 1-6; notes appear below and on next page)

CURRENT

STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

LHHH

NO OPERATION (NOP/Continue previous operation)

Idle X X X X Any Command O therwise A llowed to Ba nk m

Row

Activating,

Active, or

Precharging

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start READ burst) 7

LHL L

WRITE (Select column and start WRITE burst) 7

LLHL

PRECHARGE

Read

(Auto

Precharge

Disabled)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start new READ burst) 7, 10

LHL L

WRITE (Select column and start WRITE burst) 7, 11

LLHL

PRECHARGE 9

Write

(Auto

Precharge

Disabled)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start READ burst) 7, 12

LHL L

WRITE (Select column and start new WRITE burst) 7, 13

LLHL

PRECHARGE 9

Read

(With Auto

Precharge)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start new READ burst) 7, 8, 14

LHL L

WRITE (Select column and start WRITE burst) 7, 8, 15

LLHL

PRECHARGE 9

Write

(With Auto

Precharge)

LLHH

ACTIVE (Select and activate row)

LHL H

READ (Select column and start READ burst) 7, 8, 16

LHL L

WRITE (Select column and start new WRITE burst) 7, 8, 17

LLHL

PRECHARGE 9

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6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been in terrupted

by bank m’s burst.

9. Burst in bank n continues as initiated.

10.For a READ without auto precharg e interrupted by a READ (with or without auto precha rge), the READ to bank m will

interrupt the READ on bank n, CAS latency later (Figure 11).

11.For a READ without auto pre charge interrupte d by a WRITE (with or without auto pre charge), the WR ITE to ba nk m wi ll

interrupt the READ on bank n when registered (Figure 13 and Figure 14 on page 21). DQM should be used one clock

prior to the WRITE command to prevent bus contention.

12.For a WRITE without auto precha rge inte rrupted by a READ (wi t h or without auto prec ha rge), the RE AD to bank m will

interrupt the WRITE on bank n when registered (Figure 20 on page 24), with the data-out appearing CAS latency later.

The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13.For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

will interrupt the WRITE on bank n when registered (Figure 18 on page 23). The last valid WRITE to bank n will be data-

in registered one clock prior to the READ to bank m.

14.For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the READ on ba nk n, CAS la tenc y l ater. The PRECHARGE to b ank n will begin when the READ to ba nk m is reg-

istered (Figure 28 on page 28).

15.For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the READ on ba nk n when registered. DQM should be used two cloc ks prior to the WRI TE command to prevent

bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 29 on page 28).

16.For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to

bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to

bank n will be data-in registered one clock prior to the READ to bank m (Figure 30 on page 29).

17.For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where t WR

begins whe n the WRITE to bank m is registe red. The la st valid WRI TE to bank n will b e data regi stered on e clock p rior to

the WRITE to bank m (Figure 31 on page 29).

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TwinDie Operation

The 512Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 536,870,912 bits. It

is internally configured by stacking two 256Mb,

16M egx16 devices. Each of these 256Mb devices is con-

figured as a quad bank DRAM with a synchronous

interface. They ar e organized with 16 DQs with 4 banks

of 67,108,864 bits, comprisin g of 8,192 rows by 512 col-

umns by 16 bits wide.

Each die operates independently of the other. They

share supply, command, CKE, address and data pins,

but each have unique chip select pins.

INITIALIZATION

By synchronizing both of the chip select pins (CS0#,

CS1#), it is possible to initialize both die simulta-

neously, and is the recommended procedure.

MODE REGISTER

If both die are to be configured identically, it is OK to

access both mode registers simultaneously, otherwise

sequential operation betw een the die is permitted.

Commands (TwinDie)

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected SDRAM die to perform NOP

(CS0# LOW with RAS#, CAS#, and WE# HIGH and / or

CS#1 LO W with RAS#, CAS#, and WE# HIGH). This pre-

vent s u nwan ted commands fro m bei n g regis tered dur-

ing idle or wait states. Operations already in progress

are not affected. It is allowed to perform a NOP com-

mand to both die simultaneously.

LOAD MODE REGISTER

The LMR command may be issued independently

or simult aneous ly to the die.

ACTIVE

It is not allowed to perform an ACTIVE command to

both die simultaneously, except during the initializa-

tion sequence.

READ

Only one SDRAM die may be driving the DQ lines at

a time. It is required for a unique chip select (CS0# or

CS1#) to be asserted for each READ command.

WRITE

It is recommended to only WRITE to one die at a

time as both die share the same data and data mask

signals.

PRECHARGE

It is allowed to perform a PRECHARGE command to

both die simultaneously, but it is suggested that the

PRECHARGE comma nds be stag g ered to provide a dis-

tributed current flow.

AUTO PRECHARGE

An AUTO PRECHARGE com mand can on ly oc cur a s

part of a READ or WRITE command. It is possible to

initiate an AUTO PRECHARGE to both die simulta-

neously.

BURST TERMINATE

It is allowed to perform a BURST TERMINATE com-

mand to both die simultaneously, but not expected as

only one die may be READ from at a time.

AUTO REFRESH

All banks within a die must be idle before an AUTO

REFRESH command is iss ued. It is recomme nded that

AUTO REFRESH commands are staggered to provide a

distributed curr ent flow.

SELF REFRESH

The SELF REFRESH command may be issued to

both die simultaneously.

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Absolute Maximum Ratings

Voltage on VDD/VDDQ Supply

Relative to Vss(3.3V) . . . . . . . . . . . . . . . . -1V to +4.6V

Relative to Vss(2.5V) . . . . . . . . . . . . . . . -0.5V to +3.6V

Relative to Vss(1.8V) . . . . . . . . . . . . . . -0.35V to +2.8V

Voltage on Inputs, NC or I/O Pin s

Relative to Vss(3.3V . . . . . . . . . . . . . . . . . .-1V to +4.6V

Relative to Vss(2.5V) . . . . . . . . . . . . . . . -0.5V to +3.6V

Relative to Vss(1.8V) . . . . . . . . . . . . . . -0.35V to +2.8V

Operating Tem peratu re

TA (Commercial). . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Sto rage Temperature (plastic) . . . . . -55°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W

Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other condi-

tions above those indicated in the operational sections

of this specification is not implied. Exposure to abso-

lute maximum rating conditions for extended periods

may affect reliability.

Table 10: DC Electrical Characteristics And Operating Conditions - “LC” Version

Notes: 1, 5, 6; notes appear on page 41

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD, VDDQ3 3.6 V

Input High Voltage: Logic 1; All inputs VIH 2VDDQ + 0.3 V22

Input Low Voltage: Logic 0; All inputs VIL -0.3 0.8 V 22

Data Output High Voltage: Logic 1; All inputs VOH 2.4 - V

Data Output Low Voltage: Logic 0; All inputs VOL -0.4V

Input Leakage Current:

Any input 0V £ VIN £ VDD (All other pins not under test = 0V) II-5 5 µA

Output Leakage Current: DQs are disabled; 0V £ VOUT £ VDDQIOZ -5 5 µA

Table 11: DC Electrical Characteristics And Operating Conditions - “V” Version

Notes: 1, 5, 6; notes appear on page 41

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 2.3 2.7 V

VDDQ 1.65 2.7 V

Input High Voltage: Logic 1; All inputs VIH 0.8 * VDDQVDDQ + 0.3 V 22

Input Low Voltage: Logic 0; All inputs VIL -0.3 0.3 V 22

Data Output High Voltage: Logic 1; All inputs VOH VDDQ - 0.2 - V

Data Output Low Voltage: Logic 0; All inputs VOL -0.2V

Input Leakage Current:

Any input 0V £ VIN £ VDD (All other pins not under test = 0V) II-5 5 µA

Output Leakage Current: DQs are disabled; 0V £ VOUT £ VDDQIOZ -5 5 µA

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Table 12: DC Electrical Characteristics And Operating Conditions - “H” Version

Notes: 1, 5, 6; notes appear on page 41

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

Supply Voltage VDD 1.7 1.9 V

VDDQ1.7 1.9V

Input High Voltage: Logic 1; All inputs VIH 0.8 * VDDQVDDQ + 0.3 V 22

Input Low Voltage: Logic 0; All inputs VIL -0.3 0.3 V 22

Data Output High Voltage: Logic 1; All inputs VOH VDDQ - 0.2 - V

Data Output Low Voltage: Logic 0; All inputs VOL -0.2V

Input Leakage Current:

Any input 0V £ VIN £ VDD (All other pins not under test = 0V) II-1.0 1.0 µA

Output Leakage Current: DQs are disabled; 0V £ VOUT £ VDDQIOZ -1.5 1.55 µA

Table 13: IDD Specifications And Conditi o ns (Both Die – S2 Version )

Notes: 1, 5, 6, 11, 13; notes appear on page 41; VDD = +3.3V ±0.3V or +2.5V±0.2V1

MAX

PARAMETER/CONDITION SYMBOL -8 UNITS NOTES

Operating Current: Active Mode;

Burst = 2; READ or WRITE; tRC = tRC (MIN) IDD1150 mA 3, 18,

19, 32

Standby Current: Power-Down Mode;

CKE = LOW; All banks idle IDD21mA 32

Standby Current: Active Mode; CS# = HIGH;

CKE = HIGH; All banks active after tRCD met; No

accesses in progress

IDD350 mA 3, 12,

19, 32

Operating Current: Burst Mode; Page burst;

READ or WRITE; All banks active IDD4210 mA 3, 18,

19, 32

Auto Refresh Current:

CS# = HIGH; CKE = HIGH tRFC = tRFC

(MIN) IDD5330 mA 3, 12,

18, 19,

32, 33

tRFC = 7.81µs IDD65mA

Deep Power Down ID820 uA 34

NOTE:

1. IDD values for VDD = VDDQ = 1.8V TBD

Table 14: IDD7 - Self Refresh Current Options– S2 Version

Temperature Compensated Self Refresh, Both Die – S2 Version

Notes: 1, 5, 6, 11, 13; notes appear on page 41; VDD = +3.3V ±0.3V or +2.5V±0.2V1

TEMPERATURE COMPENSATED SELF REFRESH

PARAMETER/CONDITION MAX

TEMPERATURE -8 / -10 UNITS NOTES

Self Refresh Current: CKE £ 0.2V 70°C 1.3 mA 4

45°C 1.0 mA 4

NOTE:

1. IDD values for VDD = VDDQ = 1.8V TBD

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Table 15: Capacitance

Note: 2; notes appear on page 41

PARAMETER SYMBOL MIN MAX UNITS

Input Capacitance: CLK CI1TBD TBD pF

Input Capacitance: All other input-only pins CI2TBD TBD pF

Input/Output Capacitance: DQs CIO TBD TBD pF

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Table 16: Electrical Characteristics And Recommended AC Operating Conditions

Notes: 5, 6, 8, 9, 11; notes appear on page 41

AC CHARACTERISTICS -8

PARAMETER SYMBOL MIN MAX UNITS NOTES

Access time from CLK (pos. edge) CL = 3 tAC(3) 7ns27

CL = 2 tAC(2) 8ns

Address hold time tAH 1ns

Address setup time tAS 2.5 ns

CLK high-level width tCH 3ns

CLK low-level width tCL 3ns

Clock cycle time CL = 3 tCK(3) 8ns23

CL = 2 tCK(2) 10 ns 23

CKE hold time tCKH 1ns

CKE setup time tCKS 2.5 ns

CS#, RAS#, CAS#, WE#, DQM hold time tCMH 1ns

CS#, RAS#, CAS#, WE#, DQM setup time tCMS 2.5 ns

Data-in hold time tDH 1ns

Data-in setup time tDS 2.5 ns

Data-out high-impe dan ce time CL = 3 tHZ(3) 7ns10

CL = 2 tHZ(2) 8ns10

Data-out low-imp edance time tLZ 1ns

Data-out hold time (load) tOH 2.5 ns

Data-out hold time (noload) tOHN1.8 ns 28

ACTIVE to PRECHARGE command tRAS 48 120,000 ns

ACTIVE to ACTIVE command period tRC 80 ns 28E

ACTIVE to READ or WRITE delay tRCD 20 ns

Refreshperiod(8,192rows) tREF 64 ms

AUTO REFRESH period tRFC 80 ns 28E

PRECHARGE command period tRP 20 ns

ACTIVE bank a to bank b command tRRD 20 ns

Transition time tT0.5 1.2 ns 7

WRITE recovery time tWR 1CLK+ 7ns ns 24, 28E

15 25

Exit SELF REFRESH to ACTIVE command tXSR 80 ns 28E

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Table 17: AC Functional Characteristics

Notes: 5, 6, 8, 9, 11; notes appear on page 41

PARAMETER SYMBOL -8 UNITS NOTES

READ/WRITE command to READ/WRITE

command tCCD 1tCK 17

CKE to clock disable or power-down entry

mode tCKED 1tCK 14

CKE to clock enable or power-down exit

setup mode tPED 1tCK 14

DQM to input data delay tDQD 0tCK 17

DQM to data mask during WRITEs tDQM 0tCK 17

DQM to data high-impedance during READs tDQZ 2tCK 17

WRITE command to input data delay tDWD 0tCK 17

Data-into ACTIVE command tDAL 5tCK 15, 21

Data-into PRECHARGE command tDPL 2tCK 16, 21

Last data-in to burst STOP command tBDL 1tCK 17

Last data-in to new READ/WRITE command tCDL 1tCK 17

Last data-in to PRECHARGE command tRDL 2tCK 16, 21

LOADMODE REGISTER command to ACTIVE

or REFRESH command tMRD 2tCK 26

Data-out to high-impedance from

PRECHARGE command CL=3 tROH(3) 3tCK 17

CL = 2 tROH(2) 2tCK 17

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Notes (Singl e Die)

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; Tj

= 25°C; pin under test biased at 1.4V, f = 1 MHz.

3. IDD is dependent on output loading and cycle

rates.Specified values are obtained with mini-

mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to

indicate cycle time at which proper operation

over the ful l temperature rang e (0°C £ TA £ 70°C) is

ensured.

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,

before proper device operation is ensured. (VDD

and VDDQ must be powered up simultaneously.

VSS and V SSQ must be at same potential.) The two

AUTO REFRESH command wake-ups should be

repeated any time the tREF ref res h req u ire m en t is

exceeded.

7. AC charac teri s ti cs as sume tT = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between

VIH and VIL (or between VIL and VIH) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10. tHZ defines the time at which the output achieves

the open circuit condition; it is not a reference to

VOH or VOL. The last valid data element will meet

tOH before going High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH =

3V, with timing referenced to VIH/2 crossover

point. If the input transition time is longer than 1

ns, the n the tim ing is referenced a t VIL (MAX) and

VIH (MIN) and no longer at the VIH/2 crossover

point.

12. Other input signals are allowed to transition no

more than once every two clocks and are other-

wise at valid VIH or VIL levels.

13. IDD specifications are tested after the device is

pro p erly ini ti a l i z e d.

14. Timing actually specified by tCKS; clock(s) speci-

fied a s a re ference o nly at mi nimum cycle rate.

15. Timing actually specified by tWR plus tRP; clock ( s)

specified as a reference only at minimum cycle

rate.

16. Timing actually spec ified by tWR.

17. Required clocks are specified by JEDEC function-

alit y an d are not de pende nt on a ny timi ng param-

eter.

18. The IDD curr ent will i ncr ease or d ecr eas e in a p ro-

por tional am ount by the am ount t he frequency i s

altered for the test conditio n.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on tCK = 8ns for -8.

22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse

width £ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. VIL under-

shoot: VIL (MIN) = -2V for a pulse width £ 3ns.

23. The clock fr equen cy mu st remain constant (sta bl e

clock is defined as a signal cycling within timing

constraints specified for the clock pin) during

access or precharge states (READ, WRITE, includ-

ing tWR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (tRP) begins 7ns after the first clock delay,

after the last WRITE is executed.

25. Precharge mode only.

26. JEDEC and PC100, PC133 specify three clocks.

27. tAC for -8 at CL = 3 with no load is 4.6ns and is

guaranteed by design.

28. For -8, CL = 3, tCK = 10ns; For -8, CL = 2, tCK = 8ns.

Q30pF

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

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Figure 32: Initiali ze And Load Mode Regi ster

NOTE:

1. The two AUTO RE FRESH c ommand s at T9 and T19 may be applied be fore eit her LOA D MODE REG ISTER (LMR) comman d.

2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE

command, RA = Row Address, BA = Bank Address

3. Optional refresh command.

4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must occur

prior to an Active command.

5. Device timing is -8 with 100MHz clock.

CKE

BA0, BA1

Load Extended

Mode Register Load Mode

tCKS

Power-up:

VDD and

CLK stable

T = 100µs

tCKH

()()

DQM/DQML,

DQMH

()()

DQ High-Z

A0-A9, A11, A12

A10

ALL BANKS

CLK

tCK

COMMAND LMR

NOP PRE

LMR

ACT

tCMH tCMS

BA0 = L,

BA1 = H

tAS tAH tAS tAH

BA0 = L,

BA1 = L

()()

CODE CODE

tAS tAH

CODE CODE

()()

PRE

ALL BANKS

tAH

()()

T0 T1 T3 T5 T7 T9 T19 T29

DON’T CARE

()()

()()()()()()()()()()

()()

tRP tMRD tMRD tRP tRFC tRFC

()()

-8

SYMBOL MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (CL=3) 8ns

tCK (CL=2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tMRD32tCK

tRFC 80 ns

tRP 20 ns

-8

SYMBOL MIN MAX UNITS

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Figure 33: Power-down Mode1

NOTE:

1. Violating refresh requirements during power-down may result in a loss of data.

2. CAS latency indicated in parentheses.

tCH

tCL

tCK

CKE

CLK

COMMAND

BA0, BA1 BANK

tRFC tMRD

tRFC

AUTO REFRESH AUTO REFRESH Program Mode Register 1, 3, 4

tCMH

tCMS

Precharge

all banks

()()

tRP

()()

tCKS

Power-up:

VDD and

CLK stable

T = 100µs

MIN

PRECHARGE NOP AUTO

REFRESH NOP

LOAD MODE

()()

AUTO

REFRESH

ALL

BANKS

()()

High-Z

tCKH

()()

DQM/

DQML, DQMH

()()

()()()()

()()

NOP

()()

tCMH

tCMS tCMH

tCMS

A0-A9, A11, A12 ROW

tAH 5

tAS

CODE

()()

A10 ROW

tAH

tAS

CODE

()()

ALL BANKS

SINGLE BANK

()()

DON’T CARE

UNDEFINED

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

-8

SYMBOL MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

-8

SYMBOL MIN MAX UNITS

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Figure 34: Clock Suspend Mode1

NOTE:

1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses

tCH

tCL

tCK

tAC

tLZ

DQM/

DQML, DQMU

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

DOUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

Din

tAC tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOP NOPNOPREAD WRITE

DON T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

Din

+ 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

-8

SYMBOL3MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

-8

SYMBOL3MIN MAX UNITS

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Figure 35: Au to Refresh Mode

NOTE:

1. CAS latency indicated in parentheses.

tCH

tCL

tCK

CKE

CLK

tRFC RFC

()()

tRP

()()

COMMAND

tCMH

tCMS

NOPNOP

()()

BANK

ACTIVE

AUTO

REFRESH

()()

NOPNOPPRECHARGE

Precharge all

active banks

AUTO

REFRESH

High-Z

BA0, BA1

BANK(S)

()()

tAH

tAS

tCKH

tCKS

()()

NOP

()()

DQM /

DQML, DQMH

A0-A9, A11, A12 ROW

()()

ALL BANKS

SINGLE BANK

A10 ROW

()()

DON’T CARE

T0 T1 T2 Tn + 1 To + 1

-8

SYMBOL1MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tRFC 80 ns

tRP 20 ns

-8

SYMBOL1MIN MAX UNITS

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Figur e 36: Self Refresh Mode

NOTE:

1. No maximum time limit for Self Refresh. tRAS(MIN) applies to non-Self Refresh mode.

2. tXSR requires minimum of two clocks regardless of frequency or timing.

3. CAS latency indicated in parentheses

4. As a general rule, any time Self Refresh is exited, the DRAM may not re-enter the Self Refresh Mode until all rows have

been refreshed via the Auto Refresh command at the distributed refresh rate, tREF, or faster. However, the following

exception is allowed. Self Refresh mode may be re-entered any time after exiting, provided all of the following condi-

tions are met:

a. The DRAM had been in the Self Refresh Mode for a minimum of 64ms prior to exiting.

b. tXSR is not violated.

c. At least two Auto Refresh commands are performed during each 7.81µs interval while the DRAM remains out of Self

Refresh mode.

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

()()()()

()()

DON’T CARE

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE NOP NOP or COMMAND

INHIBIT

()()

BA0, BA1 BANK(S)

()()

High-Z

tCKS

AUTO

REFRESH

tRAS(MIN)

()()

tCKH

tCKS

DQM/

DQML, DQMU

()()

A0-A9, A11,A12

()()

ALL BANKS

SINGLE BANK

A10

()()

T0 T1 T2 Tn + 1 To + 1 To + 2

()()

≥

-8

SYMBOL MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tRAS 48 120,000 ns

tRP 20 ns

tXSR 80 ns

-8

SYMBOL MIN MAX UNITS

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Figure 37: READ – Without Auto Precharge

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM/

DQML, DQMU

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tHZ

tOH

DOUT m + 3

tAC tOH

tAC

DOUT m + 2DOUT m + 1

COMMAND

tCMH

tCMS

PRECHARGENOPNOP NOPACTIVE NOP READ NOP ACTIVE

DISABLE AUTO PRECHARGE SINGLE BANK

DON’T CARE

UNDEFINED

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

-8

SYMBOL3MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

-8

SYMBOL3MIN MAX UNITS

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Figure 38: REA D – With Auto Precharge 1

NOTE:

1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses1

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

DQM/

DQML, DQMU

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

DOUT m

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

DON’T CARE

UNDEFINED

tHZ

tOH

OUT

m + 3

tAC tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

-8

SYMBOL3MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

-8

SYMBOL3MIN MAX UNITS

256Mb and 512Mb: x16

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Figure 39: Single R EAD – Without Auto Precharge 1

NOTE:

1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK(S) BANK

ROW

BANK

tHZ

tCMH

tCMS

NOPNOPNOP PRECHARGE

ACTIVE NOP READ ACTIVE NOP

DISABLE AUTO PRECHARGE SINGLE BANKS

DON’T CARE

UNDEFINED

COLUMN m

tCKH

tCKS

T0 T1 T2 T3 T4 T5 T6 T7 T8

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

COMMAND

-8

SYMBOL3MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

-8

SYMBOL3MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

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Figure 40: Single READ – With Auto Precharge1

NOTE:

1. For this example, the burst length = 1, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

3. READ command not allowed else tRAS would be violated

4. CAS latency indicated in parentheses.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD CAS Latency

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK BANK

ROW

BANK

DON’T CARE

UNDEFINED

tHZ

tOH

OUT

tAC

COMMAND

tCMH

tCMS

NOP3READACTIVE NOP NOP3ACTIVENOP

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

NOP NOP

-8

SYMBOL4MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

-8

SYMBOL4MIN MAX UNITS

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Figure 41: Altern ati n g Bank Read Accesses1

NOTE:

1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

DQM/

DQML, DQMU

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

DON’T CARE

UNDEFINED

tOH

OUT

m + 3

tAC tOH

tAC

OUT

m + 2D

OUT

m + 1

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP READ NOP ACTIVE

tOH

OUT

tAC tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0 BANK 0 BANK 3 BANK 3 BANK 0

CKE

tCKH

tCKS

COLUMN m

COLUMN b

T0 T1 T2 T4T3 T5 T6 T7 T8

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 1 CAS Latency - BANK 1

tRC - BANK 0

RRD

-8

SYMBOL3MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tLZ 1ns

tOH 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

tRRD 20 ns

-8

SYMBOL3MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

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Figure 42: Read – Full-page Burst 1

NOTE:

1. For this example, t he CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

3. Page left open; no tRP.

4. CAS latency indicated in parentheses.

tCH

tCL tCK

tAC

tLZ

tRCD CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC tOH

OUT

m+1

ROW

tHZ

tAC tOH

OUT

tAC tOH

OUT

m+2

tAC tOH

OUT

m-1

tAC tOH

Dout m

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

()()

Full page completed

1,024 (x16) locations within same row

2,048 (x8) locations within same row

4,096 (x4) locations within same row

DON’T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

()()

NOP

()()

tAH

tAS

BANK

()()

BANK

tCKH

tCKS

()()

COLUMN m

T0 T1 T2 T4T3 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

-8

SYMBOL4MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

tRCD 20 ns

-8

SYMBOL4MIN MAX UNITS

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Figure 43: Read DQM Operation1

NOTE:

1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses.

tCH

tCL

tCK

tRCD CAS Latency

DQM/

DQML, DQMU

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

tAC

DOUT m

tOH

DOUT m + 3DOUT m + 2

ttHZ LZ

tCMH

COMMAND

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

-8

SYMBOL3MIN MAX UNITS

tAC (3) 7ns

tAC (2) 8ns

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tHZ (3) 7ns

tHZ (2) 8ns

tLZ 1ns

tOH 2.5 ns

tRCD 20 ns

-8

SYMBOL3MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

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Figure 44: Write – Without Auto Precharge1

NOTE:

1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = “Don’t Care”

4. CAS latency indicated in parentheses.

DISABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMU

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

DON’T CARE

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE PRECHARGE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

ROW

BANK

ROW

ACTIVE

NOP

ALL BANKs

-8

SYMBOL4MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

tWR 15 ns

-8

SYMBOL4MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

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Figure 45: Write – With Auto Precharge1

NOTE:

1. For this example, the burst length = 4.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR

DON’T CARE

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE NOP ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

-8

SYMBOL3MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

tWR 1 CLK

+7ns -

-8

SYMBOL3MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Figure 46: Single Write – Without Auto Precharge1

NOTE:

1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = “Don’t Care”

4. PRECHARGE command not allowed else tRAS would be vi olated

5. CAS latency indicated in parentheses.

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK BANK

ROW

BANK

tWR

tDH

tDS

COMMAND

tCMH

tCMS

NOP4

NOP4PRECHARGEACTIVE NOP WRITE ACTIVENOP NOP

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

DON’T CARE

UNDEFINED

-8

SYMBOL5MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

tWR 15 ns

-8

SYMBOL5MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Figure 47: Single Write with Auto Precharge

NOTE:

1. For this example, the burst length = 1, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 14ns to 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = “Don’t Care”

4. WRITE command not allowed else tRAS would be violated.

5. CAS latency indicated in parentheses.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD3

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

ROW

BANK

tWR2

COMMAND

tCMH

tCMS

NOP4NOP4NOPACTIVE NOP4WRITE NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tCKH

tCKS

NOP NOP

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8 T9

DON’T CARE

UNDEFINED

-8

SYMBOL5MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

tWR 1 CLK +

7ns ns

-8

SYMBOL5MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Figure 48: Alter nating B a nk Write Accesses1

NOTE:

1. For this example, the burst length = 4.

2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.

3. x16: A11 and A12 = “Don’t Care”

4. CAS latency indicated in parentheses.

tCH

tCL

tCK

CLK

DON’T CARE

tDH

tDS

m + 1 D

m + 2 D

m + 3

COMMAND

tCMH

tCMS

NOP NOPACTIVE NOP WRITE NOP NOP ACTIVE

tDH

tDS tDH

tDS

ACTIVE WRITE

tDH

tDS

b + 1 D

b + 3

tDH

tDS tDH

tDS

ENABLE AUTO PRECHARGE

DQM/

DQML, DQMU

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0 BANK 0 BANK 1 BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b

COLUMN m

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0 t

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

tRC - BANK 0

RRD

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

-8

SYMBOL4MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRAS 48 120,000 ns

tRC 80 ns

tRCD 20 ns

tRP 20 ns

tRRD 20 ns

tWR Note 2 ns

-8

SYMBOL4MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Figure 49: Write – Full-page Burst

NOTE:

1. x16: A11 and A12 = “Don’t Care.”

2. tWR must be satisfied prior to PRECHARGE command.

3. Page left open; no tRP.

4. CAS latency indicated in parentheses.

tCH

tCL tCK

tRCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does

not self-terminate.

Can use BURST TERMINATE

command to stop.2, 3

()()

Full page completed DON’T CARE

COMMAND

tCMH

tCMS

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

()()

tDH

tDS

m + 1 D

m + 2 D

m + 3

tDH

tDS tDH

tDS

m - 1

tDH

tDS

tAH

tAS

BANK

()()

BANK

tCMH

tCKH

tCKS

()()

1,024 (x16) locations within same row

2,048 (x8) locations within same row

4,096 (x4) locations within same row

COLUMN

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

-8

SYMBOL4MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRCD 20 ns

-8

SYMBOL4MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

Figure 50: Write – DQM Operation1

NOTE:

1. For this example, the burst length = 4.

2. x16: A11 and A12 = “Don’t Care”

3. CAS latency indicated in parentheses.

tCH

tCL

tCK

tRCD CAS Latency

DQM/

DQML, DQMU

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

DON’T CARE

UNDEFINED

tAC

OUT

tOH

OUT

m + 3D

OUT

m + 2

ttHZ LZ

tCMH

COMMAND NOPNOP NOPACTIVE NOP READ NOPNOP NOP

tHZ

tAC tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m

T0 T1 T2 T4T3 T5 T6 T7 T8

-8

SYMBOL3MIN MAX UNITS

tAH 1ns

tAS 2.5 ns

tCH 3ns

tCL 3ns

tCK (3) 8ns

tCK (2) 10 ns

tCKH 1ns

tCKS 2.5 ns

tCMH 1ns

tCMS 2.5 ns

tDH 1ns

tDS 2.5 ns

tRCD 20 ns

-8

SYMBOL3MIN MAX UNITS

256Mb and 512Mb: x16

TwinDie MOBILE SDRAM

PRELIMINARY

09005aef80906b6e Mic ron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca tio ns without noti ce.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Inter ne t: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron , t he M logo, the Micron logo, and TwinDie are trademarks and/or service mark s of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 51: FGBA “FG” Package 54-pin, 8mm x 14mm

NOTE:

1. All dimensions in millimeters max/min or typical where noted.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

Data Sheet Designation

Prel iminar y : This data she et cont ains initial c harac-

terization limits that are subject to change upon full

characterization of production devices.

BALL A1 ID

1.6 0 MAX

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or

62% Sn, 36% Pb, 2%Ag

SOLDER BALL PAD: Ø .27mm

14.00 ±0.10

BALL A1

BALL A9

BALL A1 ID

0.80 TYP

1.80 ±0.05

CTR

7.00 ±0.05

8.00 ±0.10

4.00 ±0.053.20 ±0.05

3.20 ±0.05

1.250 ±0.075

0.100 ±0.013

SEATING PLANE

6.40

0.10 C

54X ∅0.35

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER IS Ø 0.33