LTC4283
1
Rev. A
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Negative Voltage
Hot Swap Controller with
Energy Monitor
The LT C
®
4283 negative voltage hot swap controller drives
an external N-channel MOSFET to allow a board to be
safely inserted and removed from a live backplane. The
device features programmable current limit with foldback
and independently adjustable inrush current to optimize
the MOSFET safe operating area (SOA). The SOA timer
limits MOSFET temperature rise for reliable protection
against overstresses.
An I2C interface and onboard gear-shift ADC allow moni-
toring of board current, voltage, power, energy, and fault
status. An available single-wire broadcast mode simplifies
the interface by eliminating two isolators. The included
EEPROM provides black-box capturing and nonvolatile
configuration of fault behavior.
Additional features respond to input UV/OV, interrupt the
host when a fault has occurred, notify when output power
is good, detect insertion of a board, turn off the MOSFET
if an external supply monitor fails to indicate power good
within a timeout period, and auto-reboot after a program-
mable delay following a host commanded turn-off.
–48V/600W Hot Swap Controller with Telemetry
LTC4283 Startup Behavior
APPLICATIONS
n Allows Safe Insertion into Live –48V Backplanes
n Protects MOSFET with SOA Timer
n Programmable 15mV to 30mV Current Limit Sense
Voltage with 2% Accuracy and Adjustable Foldback
n 8-Bit to 16-Bit Gear-Shift ADC with 0.5% Accuracy
n Monitors Voltages, Currents, Power and Energy
n Nonvolatile Configuration and Fault Recording
n Floating Topology for Rugged High Voltage Operation
n Selectable Inrush Control: dV/dt or Current Limit
n I2C/SMBus or Single-Wire Broadcast Interfaces
n Min/Max ADC Measurement Logging with Alerts
n Reboots on I2C Command with Programmable Delay
n Adjustable Input UV/OV Thresholds and Hysteresis
n 38-Pin 5mm × 7mm QFN Package
n Telecom Infrastructure
n –48V Distributed Power Systems
n Servers and Data Centers
n Power Monitors
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. patents, including 8230151, 7382167, 9634480, 9634481, 10263414.
487k
1µF
0.5mΩ
4×1k IN SERIES
0.25W EACH
0.1µF
4
4
4
5.11k
PSMN4R8-100BSE ×2
470Ω
100k
14.3k
10k
200k
5.11k
200k
100nF
500µF
4.7nF
68nF
18.2k
1.13M
RTN
UVH
UVL
OV
–48V
INPUT
ADIN
TMR
V
EE
INTV
CC
SENSE
+
GATE
DRAIN
V
Z
V
IN
RTNS
SCL
SDAI
SDAO
ALERT#
ADIO
PGIO
LTC4283
RTN
(SHORT PIN)
V
EE
DRNS
EN#
UV = 38.6V
UV RELEASE AT 43.1V
OV = 71.9V
OV RELEASE AT 70.7V
VEE
4283 TA01a
VEE
VEE
V
EE
V
EE
RAMP
SENSE–
V
OUT
+
–
V
LOAD
25ms/DIV 4283 TA01b
VGATE
10V/DIV
VOUT
50V/DIV
–48V INPUT
50V/DIV
IINRUSH
5A/DIV
CONTACT
BOUNCE
128ms DEBOUNCE
LTC4283
2
Rev. A
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TABLE OF CONTENTS
EN# Pin ...................................................................32
ON Bit ..................................................................... 32
Turning the LTC4283 On and Off ............................33
Configuring PGIO and ADIO Pins ............................33
Design Examples ....................................................34
Example 1: Design Procedure for Systems with
Large Input Steps ...................................................34
Example 2: Design Procedure for Systems with
Regulated Inputs .....................................................38
Layout Considerations ............................................ 41
Reboot on I2C Command ........................................ 41
Data Converters ......................................................42
EEPROM .................................................................45
Fault Log .................................................................46
Digital Interface ...................................................... 47
Bus Compatibility .................................................... 47
START, REPEATED START and STOP Conditions ...48
ACK/NACK ..............................................................48
I2C Device Addressing ............................................48
Transfer Protocol Types .......................................... 48
Command Codes and Register Addressing .............50
Write Protocols .......................................................50
Read Protocols .......................................................50
Read Page and Write Page Protocols .....................50
Byte Ordering .........................................................50
ALERT# and Alert Response Protocol .....................50
Stuck Bus Reset ..................................................... 51
Data Synchronization and Arbitration ..................... 51
Single-Wire Broadcast ............................................ 52
Register Tables .......................................................54
Package Description ..................................... 72
Revision History .......................................... 73
Typical Application ....................................... 74
Related Parts .............................................. 74
Features ..................................................... 1
Applications ................................................ 1
Typical Application ........................................ 1
Description.................................................. 1
Absolute Maximum Ratings .............................. 3
Order Information .......................................... 3
Pin Configuration .......................................... 3
Electrical Characteristics ................................. 4
I2C Timing Diagram ....................................... 9
Typical Performance Characteristics .................. 10
Pin Functions .............................................. 13
Block Diagram ............................................. 16
Operation................................................... 17
Applications Information ................................ 18
Input Power Supply ................................................ 18
Turn-On Sequence ..................................................20
Inrush Control .........................................................22
Power Good Monitors and PGI Fault .......................23
Turn-Off Sequence ..................................................23
Overcurrent Protection ........................................... 24
SOA Timer ..............................................................24
Overcurrent Fault and Auto-Retry ........................... 26
Current Limit Adjustment ........................................ 27
Current Limit Foldback ............................................27
FET Bad Fault and Auto-Retry .................................28
Input Step and Optimum Output Ramp ...................29
Overvoltage Fault and Auto-Retry ...........................29
Undervoltage Fault and Auto-Retry .........................30
FET Short Fault ....................................................... 31
Power Failed Fault ...................................................31
External Fault and Auto-Retry ................................. 31
Cooling Delay ..........................................................31
Resetting Faults ...................................................... 32
Alarms ....................................................................32
LTC4283
3
Rev. A
For more information www.analog.com
PIN CONFIGURATIONABSOLUTE MAXIMUM RATINGS
Supply Voltage:
VIN ...................................................... –0.3V to 12.5V
INTVCC .................................................. –0.3V to 5.5V
Input Voltages
VZ (Note 3)............................................. –0.3V to 16V
DRAIN (Note 4) ..................................... –0.3V to 3.2V
EN# (Note 5) ............................................ –0.3V to 6V
UVL, UVH .............................................. –0.3V to 16V
ADIN1-4, ADR0, ADR1, DRNS, OV, RTNS,
SCL, SDAI, SENSE+, SENSE–,
VOUTTH, WP .........................–0.3V to INTVCC + 0.3V
Output Voltages
GATE, PGIO1-4 ............................ –0.3V to VIN + 0.3V
VREF ..................................................... –0.3V to 4.5V
ADIO1-4, RAMP, TMR ............ –0.3V to INTVCC + 0.3V
ALERT#, SDAO ...................................... –0.3V to 5.5V
Input Currents:
VZ ......................................................................50mA
DRAIN ...............................................................1.5mA
EN# ......................................................................5mA
Operating Ambient Temperature Range
LTC4283C ................................................ 0°C to 70°C
LTC4283I .............................................–40°C to 85°C
LTC4283H .......................................... –40°C to 125°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1 and 2)
13 14 15 16
TOP VIEW
39
VEE
UHF PACKAGE
38-LEAD (5mm × 7mm) PLASTIC QFN
TJMAX = 150°C, θJA = 34°C/W, θJC = 2°C/W
EXPOSED PAD (PIN 39) IS V
EE
, CONNECTION OPTIONAL
17 18 19
38 37 36 35 34 33 32
24
25
26
27
28
29
30
31
8
7
6
5
4
3
2
1EN#
UVL
UVH
OV
VREF
VOUTTH
ADIN1
ADIN2
ADIN3
ADIN4
VEE
SENSE–
SDAI
SDAO
ALERT#
VEE
PGIO4
PGIO3
PGIO2
PGIO1
ADIO4
ADIO3
ADIO2
ADIO1
VZ
VIN
INTVCC
WP
ADR1
ADR0
SCL
SENSE+
GATE
DRAIN
DRNS
RTNS
RAMP
TMR
23
22
21
20
9
10
11
12
ORDER INFORMATION
TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC4283CUHF#PBF LTC4283CUHF#TRPBF 4283 38-Lead (5mm × 7mm) Plastic QFN 0°C to 70°C
LTC4283IUHF#PBF LTC4283IUHF#TRPBF 4283 38-Lead (5mm × 7mm) Plastic QFN –40°C to 85°C
LTC4283HUHF#PBF LTC4283HUHF#TRPBF 4283 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
LTC4283
4
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power Supply
VIN Shunt Regulated Voltage at VIN IIN + IVZ = 4mA l10.8 11.5 12 V
∆VIN Load Regulation at VIN IIN + IVZ = 4mA to 35mA l250 500 mV
IIN VIN Supply Current VIN = 10.5V l2.5 4 mA
VIN(UVLO) VIN Undervoltage Lockout Threshold VIN Rising l7.5 8.1 8.6 V
∆VIN(UVLO) VIN Undervoltage Lockout Hysteresis l0.4 0.5 0.6 V
IVZ VZ Input Current VIN = 10.5V, VZ = 15V l20 µA
INTVCC Internal 5V LDO Voltage ILOAD = 1mA to 30mA, IIN + IVZ = 35mA l4.75 5.05 5.35 V
VCC(UVLO) INTVCC Undervoltage Lockout Threshold INTVCC Rising l3.65 4 4.3 V
∆VCC(UVLO) INTVCC Undervoltage Lockout Hysteresis l0.12 0.2 0.3 V
Gate Drive
VGATE Gate Drive Voltage for GATE lVIN – 0.3 VIN VIN + 0.3 V
VGATE(TH) Gate High Threshold for Asserting Power
Good
GATE Rising lVIN – 2.1 VIN – 1.8 VIN – 1.5 V
VGATE(HYST) Gate High Hysteresis l0.3 0.7 1.1 V
IGATE(UP) GATE Pull-Up Current VGATE = 4V l–80 –100 –150 µA
IGATE(DN) GATE Fast Pull-Down Current ∆VSENSE = VILIM(FAST) + 10mV, VGATE = 7V l1 2.3 4 A
GATE Current Limit Pull-Down Current ∆VSENSE = VILIM + 5mV, VGATE = 7V l25 50 100 mA
GATE Turn Off Pull-Down Current TMR, OV, EN# = High, UVL = Low,
VGATE = 7V
l8 18 40 mA
On/Off Timing
tPHL(SENSE) ∆VSENSE High to GATE Low Propagation
Delay
ILIM = 0000b, ∆VSENSE Steps from 0mV to
100mV, VGATE < 3V, GATE Open
l60 150 ns
tPHL(GATE) GATE Turn Off Propagation Delay TMR, OV, EN# = High, UVL = Low, VGATE < 3V,
GATE Open
l0.5 1 µs
tDL(DB) Debounce Delay, Auto-Retry Delay
Following Undervoltage or PGI Fault
l115 128 141 ms
tDL(PG) Power Good Delay l230 256 282 ms
tDL(PGIWD) Power Good Input Watchdog Timer l461 512 563 ms
tDL(RTRY) Auto-Retry Delay Following Overcurrent,
FET Bad or External Fault (Table11)
COOLING_DL = 000b – 111b l±10 %
tDL(RTCRST) Auto-Retry Counter Reset Delay OC_RETRY, FET_BAD_RETRY = 01b, 10b l14.8 16.4 18 s
tDL(FETBAD) FET Bad Fault Timer Delay (Table11) FTBD_DL = 00b – 11b l±10 %
tDL(RBT) Auto-Reboot Delay (Table23) After RBT_EN Bit is Set Via I2C Interface,
RBT_DL = 000b – 111b
l±10 %
dV/dt Control
IRAMP RAMP Output Current Startup Only, dV/dt Control Enabled l–2.25 –2.5 –2.75 µA
IRAMP(DN) RAMP Discharge Current VRAMP = 1.2V l1 4 10 mA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)
LTC4283
5
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Drain Monitor
VD,PG(TH) DRAIN Input Threshold for Power Good DRAIN Falling l2 2.05 2.1 V
∆VD,PG(HYST) DRAIN Input Hysteresis for Power Good 20 mV
VD,FET(TH) DRAIN Input Threshold for FET Bad Timer
and TMR Pull-Up Current (Table11)
DRAIN Rising, VDTH = 00b – 11b l±10 %
∆VD,FET(HYST) DRAIN Input Hysteresis with VD,FET(TH) 10 mV
IDRAIN DRAIN Input Current VDRAIN = 200mV l0 ±0.1 µA
VDRAIN = 2 V l0 ±1 µA
Current Limit
VILIM Current Limit Voltage DAC Zero-Scale ILIM = 0000b, C-Grade (Note 6)
ILIM = 0000b, I-, H-Grade
l
l
14.7
14.5
15
15
15.3
15.5
mV
mV
Current Limit Voltage DAC Full-Scale ILIM = 1111b, C-Grade (Note 6)
ILIM = 1111b, I-, H-Grade
l
l
29.4
29
30
30
30.6
31
mV
mV
Current Limit Voltage DAC INL l0 ±50 µV
aSTARTUP Current Limit Foldback Factor at Startup RTNS = 1.8V, DRNS = 0, 1.8V FB = 01b l45 50 55 %
FB = 10b l16 20 24 %
FB = 11b l7 10 13 %
aNORMAL Current Limit Foldback Factor in Normal
Operation
RTNS = DRNS = 1.8V FB = 01b l45 50 55 %
FB = 10b l15 20 26 %
FB = 11b l6 10 16 %
VILIM(FAST) Fast Pull-Down Sense Threshold Voltage ILIM = 0000b l20 30 40 mV
ILIM = 1111b l47 60 70 mV
ISENSE+SENSE+ Input Current SENSE+ = 33mV l0 ±1 µA
ISENSE–SENSE– Input Current SENSE– = SENSE+ = 0 l–8 –17 –35 µA
TMR Pin Function
ITMR(UP) TMR Pull-Up Current in Current Limit
Onset DRNS = 0V, TMR = 1V l–1.5 –2 –2.5 µA
Startup in Foldback dV/dt Control Disabled,
DRNS = 1.8V, TMR = 1V
FB = 00b l–192 –202 –212 µA
FB = 01b l–96 –102 –108 µA
FB = 10b l–39 –42 –45 µA
FB = 11b l–20 –22 –24 µA
Startup in dV/dt dV/dt Control Enabled, DRNS = 1.8V,
TMR = 1V
l–192 –202 –212 µA
Hard Short in Normal Operation DRNS = 1.8V, TMR = 1V l–192 –202 –212 µA
ITMR(DN) TMR Pull-Down Current DRAIN < VD,FET(TH) or Start into dV/dt
Control, THERM_TMR = 0, TMR = 1V
l1.6 2 2.3 µA
ITMR(RST) TMR Reset Current EN# = High, TMR = 1V l3 5 8 mA
VTMRH(TH) TMR Fault Threshold TMR Rising l2.028 2.048 2.068 V
VTMRH(HYST) TMR Fault Hysteresis 20 mV
VTMRL(TH) TMR Low Status Threshold TMR Falling l80 100 120 mV
VTMRL(HYST) TMR Low Hysteresis 20 mV
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)
LTC4283
6
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Pins
VUVH(TH) UVH Input Threshold UVH Rising l2.028 2.048 2.068 V
VUVL(TH) UVL Input Threshold UVL Falling l1.815 1.833 1.851 V
∆VUV(HYST) Built-In UV Hysteresis UVH and UVL Tied Together l204 215 226 mV
dVUV(HYST) UVH, UVL Minimum Hysteresis 11 mV
VUVLR(TH) UVL Reset Threshold UVL Falling l1 1.024 1.05 V
∆VUVLR(HYST) UVL Reset Hysteresis 21 mV
VOV(TH) OV Input Threshold OV Rising l1.392 1.406 1.42 V
∆VOV(HYST) OV Input Hysteresis l10 24 38 mV
VOUTL(TH) VOUT Low Threshold RTNS – DRNS Falling, VOUTTH = 0.8V lVOUTTH
– 0.06
VOUTTH VOUTTH +
0.06
V
∆VOUTL(HYST) VOUT Low Hysteresis 40 mV
VEN#(TH) EN# Input Threshold EN# Falling l1.248 1.28 1.312 V
∆VEN#(HYST) EN# Input Hysteresis 18 mV
VWP(TH) WP Input Threshold WP Rising l1.2 1.65 2.1 V
∆VWP(HYST) WP Input Hysteresis 100 mV
VINPUT(TH) ADIO1-4, PGIO1-4 Input Threshold ADIO1-4, PGIO1-4 Rising l1.248 1.28 1.312 V
∆VINPUT(HYST)
ADIO1-4, PGIO1-4 Input Hysteresis 18 mV
IINPUT DRNS, EN#, OV, RTNS, UVL, UVH,
VOUTTH, WP Input Current
DRNS, EN#, OV, RTNS, UVL, UVH, VOUTTH,
WP = 3V
l0 ±1 µA
Output Pins
VOL ADIO1-4, PGIO1-4 Output Low Voltage I = 5mA l0.15 0.4 V
ILEAK ADIO1-4, PGIO1-4 Leakage Current ADIO1-4 = INTVCC, PGIO1-4 = VIN l0 ±1 µA
VREF VREF Output Voltage IVREF = –200µA, 0, 400µA l1.01 1.024 1.038 V
rREF VREF to ADC VFS Ratio IVREF = –200µA, 0, 400µA l0.495 0.5 0.505
ADC
Resolution (No Missing Codes) (Note 6) RTNS, ADIN1-4, ADIO1-4,
DRNS, DRAIN, (SENSE+ –
SENSE–), Power
ADC = 000b l8 Bits
ADC = 010b l10 Bits
ADC = 100b l12 Bits
ADC = 110b l14 Bits
ADC = xx1b l14 16 Bits
(ADIN2 – ADIN1),
(ADIN4 – ADIN3),
(ADIO2 – ADIO1),
(ADIO4 – ADIO3)
ADC = 000b l7 Bits
ADC = 010b l9 Bits
ADC = 100b l11 Bits
ADC = 110b l13 Bits
ADC = xx1b l13 15 Bits
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)
LTC4283
7
Rev. A
For more information www.analog.com
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VFS Full-Scale Voltage Single-Ended Inputs 2.048 V
Differential Inputs 32.768 mV
LSB LSB Step Voltage RTNS, ADIN1-4, ADIO1-4,
DRNS, DRAIN
ADC = 000b 8 mV
ADC = 010b 2 mV
ADC = 100b 0.5 mV
ADC = 110b 0.125 mV
ADC = xx1b 0.03125 mV
SENSE+ – SENSE–ADC = 000b 128 µV
ADC = 010b 32 µV
ADC = 100b 8 µV
ADC = 110b 2 µV
ADC = xx1b 0.5 µV
ADIN2 – ADIN1,
ADIN4 – ADIN3,
ADIO2 – ADIO1,
ADIO4 – ADIO3
ADC = 000b 256 µV
ADC = 010b 64 µV
ADC = 100b 16 µV
ADC = 110b 4 µV
ADC = xx1b 1 µV
VOS Offset Error (Note 7) Single-Ended Inputs l0 ±0.125 % VFS
Differential Inputs l0 ±0.25 % VFS
INL Integral Nonlinearity (Note 7) ADIN1-4, ADIO1-4, RTNS, DRNS, DRAIN,
SENSE+ – SENSE–
l±0.01 ±0.06 % VFS
ADIN2 – ADIN1, ADIN4 – ADIN3,
ADIO2 – ADIO1,
ADIO4 – ADIO3
l±0.02 ±0.12 % VFS
FSE Full-Scale Error (Note 7) Single-Ended Inputs, C-Grade (Note 6)
Single-Ended Inputs, I-, H-Grade
l
l
±0.5
±0.7
%
%
Differential Inputs, C-Grade (Note 6)
Differential Inputs, I-, H-Grade
l
l
±1
±1.2
%
%
Power, C-Grade (Note 6)
Power, I-, H-Grade
l
l
±1
±1.2
%
%
Energy l±5 %
fCONV Refresh Rate in Continuous Mode
(Table12)
l±5 %
RADIN(SE) ADIN1-4, ADIO1-4 Input Impedance,
Single-Ended
V = 3V l3 MΩ
IADIN(SE) ADIN1-4, ADIO1-4 Input Current,
Single-Ended
V = 3V l0 ±1 µA
IADIN(DIFF) ADIN1, ADIN3, ADIO1, ADIO3 Input
Current, Differential Mode
ADIN1, ADIN3, ADIO1, ADIO3 = 0, ADIN2,
ADIN4, ADIO2, ADIO4 = 0
l–3 –7 µA
ADIN2, ADIN4, ADIO2, ADIO4 Input
Current, Differential Mode
ADIN2, ADIN4, ADIO2, ADIO4 = 33mV l0 ±1 µA
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)
ELECTRICAL CHARACTERISTICS
LTC4283
8
Rev. A
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I2C Interface
VADR(H) ADR0, ADR1 Input High Threshold lINTVCC
– 0.85
INTVCC
– 0.55
INTVCC
– 0.25
V
VADR(L) ADR0, ADR1 Input Low Threshold l0.4 0.7 1 V
IADR(IN) Allowable Leakage Current l±10 µA
VALERT#(OL) ALERT# Output Low Voltage I = 5mA l0.15 0.4 V
VSDAO(OL) SDAO Output Low Voltage I = 20mA l0.25 0.6 V
ISDAO,ALERT# SDAO, ALERT# Input Current SDAO, ALERT# = INTVCC l0 ±1 µA
VSDAI,SCL(TH) SDAI, SCL Input Threshold l1.5 1.75 2 V
ISDAI,SCL SDAI, SCL Input Current SDAI, SCL = INTVCC l0 ±1 µA
I2C Interface Timing (Note 6)
fSCL(MAX) Maximum SCL Clock Frequency 400 kHz
tLOW Minimum SCL Low Period 0.65 1.3 µs
tHIGH Minimum SCL High Period 50 600 ns
tBUF(MIN) Minimum Bus Free Time Between Stop/
Start Condition
0.12 1.3 µs
tHD,STA(MIN) Minimum Hold Time After (Repeated)
Start Condition
140 600 ns
tSU,STA(MIN) Minimum Repeated Start Condition
Set-Up Time
30 600 ns
tSU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns
tHD,DATI(MIN) Minimum Data Hold Time Input –100 0 ns
tHD,DATO(MIN) Minimum Data Hold Time Output 300 600 900 ns
tSU,DAT(MIN) Minimum Data Set-Up Time Input 30 100 ns
tSP(MAX) Maximum Suppressed Spike Pulse Width 50 110 250 ns
tRST Stuck-Bus Reset Time SCL or SDAO Held Low 26 30 34 ms
CXSCL, SDA Input Capacitance SDAI Tied to SDAO 5 10 pF
Single-Wire Broadcast Timing
fBC Broadcast Data Rate (Table11) l±10 %
EEPROM
Endurance 1 Cycle = 1 Write (Notes 8, 9) l10,000 Cycles
Data Retention (Notes 8, 9) l20 Years
tWRITE EEPROM Write Time per Byte l1.2 2.2 3 ms
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2)
LTC4283
9
Rev. A
For more information www.analog.com
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All Currents into device pins are positive and all currents out
of device pins are negative. All voltages are referenced to VEE unless
otherwise specified.
Note 3: When VZ is connected to VIN, an internal shunt regulator limits the
voltage to a minimum of 11V. Driving the pins above 11V may damage the
part. These pins can be safely biased by a higher voltage using a resistor
or current source that limits the current below 50mA.
Note 4: An internal clamp limits DRAIN to a minimum of 3.2V. Driving
this pin to voltages above the clamp may damage the part. The pin can
be safely tied to higher voltages through a resistor that limits the current
below 1.5mA.
Note 5: An internal clamp limits EN# to a minimum of 6V. Driving this pin
to voltages above the clamp may damage the part. The pin can be safely
tied to higher voltages through a resistor that limits the current below 5mA.
Note 6: Guaranteed by design and characterization. Not tested in
production.
Note 7: Tested at 12-bit resolution and guaranteed for other resolutions by
design and characterization.
Note 8: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls.
Note 9: EEPROM endurance and retention will be degraded when TJ > 85°C.
I2C TIMING DIAGRAM
tSP
tBUF
tSU,STO
tSP
tHD,STA
START
CONDITION
STOP
CONDITION
tSU,STA
tHD,DATI
tHD,DATO
REPEATED START
CONDITION
REPEATED START
CONDITION
tSU,DAT
SDA
SCL
tHD,STA
4283 TD
ELECTRICAL CHARACTERISTICS
LTC4283
10
Rev. A
For more information www.analog.com
GATE Fast Pull-Down Current vs
GATE Voltage
Current Limit Voltage Error vs
ILIM Code Current Limit Foldback Profiles
SENSE INPUT = 40mV
V
ILIM(FAST)
= 30mV
GATE VOLTAGE (V)
0
2
4
6
8
10
12
0
0.5
1.0
1.5
2.0
2.5
3.0
GATE FAST PULL-DOWN CURRENT (A)
4283 G07
50 UNITS
ILIM CODE
0
2
4
6
8
10
12
14
16
–2
–1
0
1
2
V
ILIM
ERROR (%)
4283 G08
V
ILIM
= 15mV
V
RTNS
= 1.8V
FB = 00
01
10
11
LPFB = 0
LPFB = 1
POWER GOOD LATCHED
V
RTNS
– V
DRNS
(V)
0
0.3
0.6
0.9
1.2
1.5
1.8
0
5
10
15
20
CURRENT LIMIT VOLTAGE (mV)
4283 G09
TYPICAL PERFORMANCE CHARACTERISTICS
Shunt Regulator Voltage vs
Input Current VZ Input Current vs Temperature INTVCC Voltage vs Load Current
GATE Output High Voltage vs
Leakage Current
GATE Pull-Down Current vs
SENSE Input Voltage
GATE Turn-Off Time vs
SENSE Input Voltage
V
IN
INPUT CURRENT (mA)
0
5
10
15
20
25
30
35
11.0
11.2
11.4
11.6
11.8
12.0
V
IN
VOLTAGE (V)
4283 G01
I
GATE
(µA)
0
–25
–50
–75
–100
–125
–150
0
2
4
6
8
10
12
V
GATE
(V)
4283 G04
V
Z
= 15V
V
IN
= 10.5V
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
0
1
2
3
4
5
V
Z
INPUT CURRENT (µA)
4283 G02
V
GATE
= 7V, V
ILIM
= 15mV
FAST PULL-DOWN
CURRENT LIMIT
SENSE INPUT VOLTAGE (mV)
0
20
40
60
80
100
0.001
0.01
0.1
1
10
GATE PULL-DOWN CURRENT (A)
4283 G05
I
IN
= 35mA
LOAD CURRENT (mA)
0
5
10
15
20
25
30
4.96
4.98
5.00
5.02
5.04
5.06
5.08
INTV
CC
VOLTAGE (V)
4283 G03
GATE FALLING FROM 11.5V TO 3V
FAST PULL-DOWN
C
GATE
= 100nF
GATE OPEN
SENSE INPUT VOLTAGE (mV)
0
20
40
60
80
100
0.01
0.1
1
10
100
1k
GATE TURN-OFF TIME (µs)
4283 G06
V
ILIM
= 15mV
LTC4283
11
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
TMR Pull-Up Current vs DRNS
Voltage
TMR Pull-Up Current vs SENSE
Input Voltage
ADIO Output Low Voltage vs Load
Current
PGIO Output Low Voltage vs Load
Current
VREF Output Voltage vs Load
Current
ADC Full-Scale Error vs
Temperature
CURRENT
LIMIT
100% V
ILIM
98% V
ILIM
50% V
ILIM
20% V
ILIM
10% V
ILIM
V
DRNS
(V)
0
0.6
1.2
1.8
2.4
3
0
100
200
300
400
TMR PULL-UP CURRENT (µA)
4283 G10
∆VSENSE1 =
∆VSENSE1 =
∆VSENSE1 =
∆VSENSE1 =
∆VSENSE1 =
T
A
= –40°C
T
A
= 25°C
T
A
= 85°C
T
A
= 125°C
LOAD CURRENT (mA)
0
5
10
15
20
0
0.20
0.40
0.60
0.80
1.00
PGIO OUTPUT LOW VOLTAGE (V)
4283 G13
V
ILIM
= 15mV
V
DRAIN
> V
D,FET(TH)
POWER GOOD LATCHED
CURRENT LIMIT
V
DRNS
= 1.8V
V
DRNS
= 1.2V
V
DRNS
= 0.6V
V
DRNS
= 0V
∆V
SENSE1 (mV)
0
2
4
6
8
10
12
14
16
0
50
100
150
200
250
TMR PULL-UP CURRENT (µA)
4283 G11
LOAD CURRENT (µA)
–400
–200
0
200
400
600
1.022
1.023
1.024
1.025
1.026
VREF VOLTAGE (V)
4283 G14
T
A
= –40°C
T
A
= 25°C
T
A
= 85°C
T
A
= 125°C
LOAD CURRENT (mA)
0
5
10
15
20
0
0.20
0.40
0.60
0.80
ADIO OUTPUT LOW VOLTAGE (V)
4283 G12
TEMPERATURE (°C)
–50
–25
0
25
50
75
100
125
–0.2
–0.1
0
0.1
0.2
0.3
ADC FULL-SCALE ERROR (%)
4283 G15
Voltage ADC Total Unadjusted
Error (TUE) vs Code
Current ADC Total Unadjusted
Error (TUE) vs Code 12-Bit Voltage ADC INL vs Code
INPUT = VRTNS
RESOLUTION = 12-BIT
CODE
0
1024
2048
3072
4096
–0.10
–0.05
0
0.05
0.10
TUE (%)
4283 G16
INPUT = SENSE+ – SENSE–
RESOLUTION = 12-BIT
CODE
0
1024
2048
3072
4096
–0.10
–0.05
0
0.05
0.10
TUE (%)
4283 G17
INPUT = V
RTNS
CODE
0
1024
2048
3072
4096
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
INL (LSB)
4283 G18
LTC4283
12
Rev. A
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
12-Bit Voltage ADC DNL vs Code 12-Bit Current ADC INL vs Code 12-Bit Current ADC DNL vs Code
16-Bit Voltage ADC Noise
Histogram
16-Bit Current ADC Noise
Histogram
12-Bit ADC Input Signal Attenuation
(Low Frequencies)
INPUT = V
RTNS
CODE
0
1024
2048
3072
4096
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
DNL (LSB)
4283 G19
V
RTNS
= 1.024V
1LSB = 31.25µV
CODE VARIATION (LSB)
–3
–2
–1
0
1
2
3
0
1000
2000
3000
4000
5000
6000
NUMBER OF READINGS
4283 G22
INPUT = SENSE+ – SENSE–
CODE
0
1024
2048
3072
4096
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
INL (LSB)
4283 G20
SENSE+ – SENSE– = 16.4mV
1LSB = 500nV
CODE VARIATION (LSB)
–3
–2
–1
0
1
2
3
0
2000
4000
6000
8000
NUMBER OF READINGS
4283 G23
INPUT = SENSE+ – SENSE–
CODE
0
1024
2048
3072
4096
–1.0
–0.8
–0.6
–0.4
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
DNL (LSB)
4283 G21
INPUT = V
RTNS
FREQUENCY (Hz)
0
25
50
75
100
125
150
–50
–40
–30
–20
–10
0
REJECTION (dB)
4283 G24
INPUT = V
RTNS
REJECTION LIMITED BY
QUANTIZATION NOISE
FREQUENCY (kHz)
0
50
100
150
200
–80
–60
–40
–20
0
REJECTION (dB)
4283 G25
59 UNITS
260°C 3 CYCLES
INPUT = V
ADIN1
FSE SHIFT (%)
–0.4
–0.2
0
0.2
0.4
0.6
0
5
10
15
20
NUMBER OF UNITS
4283 G26
59 UNITS
260°C 3 CYCLES
V
ILIM
SHIFT (%)
–1
–0.5
0
0.5
1
0
5
10
15
20
25
NUMBER OF UNITS
4283 G27
12-Bit ADC Input Signal Attenuation
(Extended Frequencies) ADC FSE Shift Due to IR Reflow VILIM Shift Due to IR Reflow
LTC4283
13
Rev. A
For more information www.analog.com
PIN FUNCTIONS
ADIN1 – ADIN4 (Pins 7 – 10): ADC Inputs. A single-ended
voltage between 0V and 2.048V applied to each ADIN
is measured by the on-chip ADC. Two differential volt-
ages ADIN2 – ADIN1 and ADIN4 – ADIN3, if enabled, are
also measured by the ADC with a full scale of 32.768mV.
Connect to VEE if unused.
ADIO1 – ADIO4 (Pins 20 – 23): General Purpose Inputs/
Outputs and ADC Inputs. Configurable to logic inputs and
general purpose outputs (open-drain). See Table13 for
details. The single-ended voltages at ADIOs are measured
by the ADC with a full scale of 2.048V. The differential volt-
ages ADIO2 – ADIO1 and ADIO4 – ADIO3, if enabled, are
also measured by the ADC with a full scale of 32.768mV.
Connect to VEE if unused.
ADR0, ADR1 (Pin 33, Pin 34): Serial Bus Address Inputs.
Connecting to VEE, OPEN or INTVCC configures one of nine
possible addresses, with one dedicated to the single-wire
broadcast mode. Do not bias with an external supply. See
Table1 in Applications Information for address decoding.
ALERT# (Pin 29): Fault Alert Output. Open-drain logic
output that pulls to VEE when a fault occurs to alert the
host controller. A fault alert is enabled by the FAULT_
ALERT and ADC_ALERT registers. See Tables 15 and 16
in Applications Information for details. Connect to VEE if
unused.
DRAIN (Pin 15): Drain Sense Input. Connect an external
100k resistor between this pin and the drain terminal of
the N-channel MOSFET. A DRAIN voltage below 2.048V is
one of the conditions to assert power good outputs. When
DRAIN voltage is above a voltage configurable between
72mV and 203mV, the FET Bad fault timer is started and
the TMR output current is enabled when not in current
limit. DRAIN is internally clamped to a minimum of 3.2V.
DRNS (Pin 16): Attenuated Drain Sense Input. Connect to
the tap of an external resistive divider between the drain
terminal of the N-channel MOSFET and V
EE
to monitor
the drain voltage. DRNS coupled with RTNS monitors the
output voltage for the load, which controls dV/dt inrush
current and current limit foldback. DRNS operates from
0 to 2.8V. Connect to VEE if unused.
EN# (Pin 1): Device Enable Input. Pull low to enable the
GATE output to turn-on after a startup debounce delay.
When pulled high, GATE is turned off. A high-to-low tran-
sition clears faults. Transitions are recorded. Requires
external pull-up. Debouncing with an external capacitor
is recommended when used to monitor board present.
Connect to VEE if unused.
Exposed Pad (Pin 39): Exposed Pad may be left open or
connected to device ground (VEE).
GATE (Pin 14): N-Channel MOSFET Gate Drive Output.
GATE is pulled high by internal current sources (>80μA)
when V
IN
and INTV
CC
cross the UVLO thresholds, UV and
OV conditions are satisfied, no other faults are present
and the debounce delay expires. The GATE voltage higher
than VIN – 1.8V satisfies one of the conditions to assert
power good outputs. Upon a low impedance output short,
a 2.3A fast pull-down current is immediately activated.
INTVCC (Pin 36): 5V Internal Supply Output. The output of
the internal linear regulator sources up to 30mA with an
UVLO threshold of 4V. The supply powers the data con-
verters, logic control circuitry, I
2
C interface and EEPROM.
Bypass with 1μF capacitor to VEE. INTVCC is not current
limited. When driving INTVCC with an external supply, VIN
and VZ must be left open or connected to INTVCC.
OV (Pin 4): Overvoltage Detection Input. Connect to an
external resistive divider from VEE. When OV is above its
threshold of 1.406V, the GATE output pulls low to turn
off the MOSFET and an overvoltage fault is recorded. The
overvoltage fault does not affect the status of the power
good outputs. Connect to VEE if unused.
PGIO1, PGIO2 (Pin 24, Pin 25): General Purpose
Inputs/Outputs. Configurable to sequenced, inverted
and non-inverted power good outputs, general purpose
logic inputs and open-drain outputs. See Table 12 in
Application Information for details. If the PGIO2_ACLB
bit in CONTROL_1 register 0x0A is set, PGIO2 is config-
ured as inverted current limit engagement indicator after
startup. Connect to VEE if unused.
LTC4283
14
Rev. A
For more information www.analog.com
PIN FUNCTIONS
PGIO3 (Pin 26): General Purpose Input/Output.
Configurable to inverted and non-inverted power good
watchdog input (PGI# and PGI), general purpose logic
input and open-drain output. See Table12 in Application
Information for details. Connect to VEE if unused.
PGIO4 (Pin 27): General Purpose Input/Output.
Configurable to inverted and non-inverted external fault
input (EXT_ FAULTIN# and EXT_FAULTIN), general pur-
pose logic input and open-drain output. See Table12 in
Application Information for details. Connect to INTVCC if
unused.
RAMP (Pin 18): Ramp Control. Connect a capacitor
between RAMP and V
EE
to set inrush current in dV/dt
startup mode. During the dV/dt control, RAMP acts as
an attenuated output and feeds a fixed 2.5μA current
through the RAMP capacitor to set the slew rate of the
output voltage. The dV/dt inrush control is disabled after
startup when power good signals are asserted. Leave
open ifunused.
RTNS (Pin 17): RTN Sense Input. Connect to the tap of an
external resistive divider between RTN and VEE to monitor
the board input voltage. When selected, the RTNS voltage
is measured by the ADC and used to calculate the input
power. Monitors the output voltage for the load when cou-
pled with DRNS, which controls dV/dt inrush current and
current limit foldback. Operates from 0V to 2.8V. Connect
to INTVCC if unused.
SCL (Pin 32): Serial Bus Clock Input. Data at SDAI is
shifted in and data at SDAO is shifted out on rising edges
of SCL. This is a high impedance input that is generally
connected to the output of the incoming isolator driven by
the SCL port of the master controller. An external pull-up
resistor or current source is required. Pull up to INTVCC
if unused.
SDAI (Pin 31): Serial Bus Data Input. This is a high imped-
ance input used for shifting in command bits, data bits,
and SDAO acknowledge bits. An external pull-up resistor
or current source is required. Normally connected to the
output of the incoming isolator that is driven by the SDA
port of the master controller. Pull up to INTVCC if unused.
SDAO (Pin 30): Serial Bus Data Output. Open-drain out-
put used for sending data back to the master controller
or acknowledging a write operation. An external pull-up
resistor or current source is required. Normally con-
nected to the input of the outgoing isolator that outputs
to the SDA port of the master controller. In the single-wire
broadcast mode, SDAO sends out selected data that is
Manchester encoded with an internal clock. The broadcast
bit rate is configurable between 2Mbit/s and 32kbit/s.
SENSE
+
(Pin 13): Positive Current Sense Kelvin Input.
Connect to the high side of the current sense resistor.
The active current limit amplifier controls GATE to limit
the sense voltage SENSE+ – SENSE– from 15mV to
30mV, configurable in 1mV steps. SENSE+ – SENSE– is
also measured by the ADC with a full scale of 32.768mV.
Connect to VEE if unused.
SENSE– (Pin 12): Negative Current Sense Kelvin Input.
Connect to the low side of the current sense resistor.
TMR (Pin 19): Timer Current Output. The current sourced
out of TMR is proportional to the power dissipation in the
MOSFET. If an RC network that represents the thermal
behavior of the MOSFET is connected between TMR and
VEE, the voltage at TMR represents the real-time tempera-
ture rise of the MOSFET. When the TMR voltage reaches
its threshold of 2.048V that corresponds to T
J(MAX)
of the
MOSFET, GATE pulls low to turn off the MOSFET and an
overcurrent fault is logged. If a single capacitor is con-
nected between TMR and VEE, TMR sets the delay for
MOSFET turn-off based on the power dissipation in the
MOSFET. In this mode the 2μA pull-down current must
be enabled to discharge the capacitor when the MOSFET
power drops to near zero. When EN# is low, TMR is dis-
charged by a 5mA current. Connect to VEE if unused.
LTC4283
15
Rev. A
For more information www.analog.com
PIN FUNCTIONS
UVH (Pin 3): Undervoltage High Level Input. Connect to
an external resistive divider from VEE. If UVH rises above
2.048V and UVL is above 1.833V, the GATE output pulls
high to turn on the MOSFET. A capacitor of at least 10nF
between UVH and VEE prevents transients and switching
noise from affecting the UV threshold. Connect to INTVCC
if unused.
UVL (Pin 2): Undervoltage Low Level Input. Connect to
an external resistive divider from V
EE
. If UVL drops below
1.833V and UVH is below 2.048V, the MOSFET is turned
off. Pulling below 1.024V resets faults and allows the
MOSFET to turn back on when undervoltage is cleared.
Connect to INTVCC if unused.
VEE (Pin 11 and Pin 28): Negative Supply Voltage Input
and Device Ground. Connect to the negative side of the
power supply. The connection between any component
and device ground must be made to a dedicated plane that
connects directly to VEE, not to the main current-carrying
trace of −48V on the board.
VIN (Pin 37): Positive Supply Input to the Device. Connect
to VZ directly or through an external buffer transistor
driven by VZ. The voltage at VIN is internally regulated
at 11.5V. An undervoltage lockout (UVLO) circuit holds
the GATE output low until VIN is above 8.1V. Bypass with
at least 0.1μF capacitor to VEE. If it is desired to log fault
information into EEPROM upon brown-out, bypass V
IN
with at least 68μF capacitor to VEE (See Applications
Information for details).
VOUTTH (Pin 6): Output Low Threshold Input. Connect
to an external reference voltage for output voltage low
threshold. RTNS – DRNS below VOUTTH sets the VOUT
low status bit. RTNS – DRNS above VOUTTH satisfies one
of the conditions to assert power good outputs. Connect
to VEE if unused.
VREF (Pin 5): Reference Voltage Output. Regulated at
1.024V or half of the ADC full-scale. Sources up to 200μA
and sinks up to 400μA. It can drive a capacitive load of up
to 10nF. Leave open if unused.
VZ (Pin 38): Shunt Regulator Input. Operates with a bias
of 20μA to 30mA. Connect to the positive supply (RTN)
through a dropping resistor. To supply external loads with
VIN, use VZ to drive an external buffer transistor with the
emitter or source connected to VIN. Bypass with a 0.1μF
capacitor to VEE.
WP (Pin 35): EEPROM Write Protect Input. All write oper-
ations to the EEPROM except fault logging are blocked
when the voltage at WP is above 1.65V.
LTC4283
16
Rev. A
For more information www.analog.com
BLOCK DIAGRAM
+
–
4
4
4
4
PGIO1
TMR
WP
WP
1.65V
INTVCC
2µA
VEE
VEE
INTVCC
VEE
2.048V
TMRH
DRAIN
ADR0
ADR1
SCL
SDAI
SDAO
ALERT#
VEE
VIN RAMP
4283 BD
+
–
0.1V
TMRL
+
–
72mV TO 203mV
DC2
+
–
2.048V
DC1
+
–
VIN – 1.8V
GATE
3.2V
GC
+
–
16
16
48
ENERGY
1.28V
PGIC
4×
100µA
∆VSENSE × VDRNS
ADIO1
VEE
VEE
+
–
1.28V
ADIC
4×
ADIO2
ADIO3
ADIO4
PGIO2
PGIO3
PGIO4
+
–
EN#
1.28V EN
OV
+
–
1.833V UVL
+
–
2.048V
UVH
+
–
1.406V
OV
+
–
VRTNS – VDRNS
VOUTL
ADIN4
SENSE–
SENSE+
ADIN1
ADIN2
ADIN3
UVH
UVL
VREF 1.024V
VOUTTH
+
–
62.5x
I2C
INTERFACE
REGISTERS
UVLO:
VIN = 8.1V
INTVCC = 4V
VZVIN
CONTROL
LOGIC
5V
11.5V
EEPROM
MUX/
PREAMP
16
POWER
ACC1
OSC
MULTIPLIER
32
TIME
ACC2
MIN/
MAX
LOG
ADC2
VPWR
(RTNS/DRNS)
DRNS
16
ADC1
DRNSGATE RTNS
FOLDBACK
dV/dt CONTROL
FST
30mV TO
60mV
ACL
15mV TO
30mV
+
–
+
–
+
–
+
–
+
–
+
–
VCC
LTC4283
17
Rev. A
For more information www.analog.com
OPERATION
The LTC4283 is designed to turn a board’s supply voltage
on and off in a controlled manner, allowing the board to
be safely inserted or removed from a live, power sys-
tem. In normal operation after a startup debounce delay,
the LTC4283 turns on the external N-channel MOSFET,
passing the power to the load. The inrush control dur-
ing startup is configurable between two methods. One is
programmable active current limiting with an adjustable
foldback factor. The other is constant dV/dt ramp control
of the output voltage using a capacitor connected between
RAMP and V
EE
. The inrush current is a function of the
RAMP capacitor, the load capacitor and the attenuated
load voltage seen between RTNS and DRNS.
An 11.5V shunt regulator on VIN powers the LTC4283
with an external dropping resistor from the system RTN
node. It also provides the gate drive. An optional buffer
transistor driven by VZ boosts sourcing capability to sup-
ply external loads.
An internally generated 5V supply on INTVCC supplies
the logic control circuits, communication interface, data
converters and EEPROM. Prior to turning on the MOSFET,
both VIN and INTVCC voltages must exceed their under-
voltage lockout thresholds. In addition, the control inputs
UVH, UVL, OV, EN#, PGIO3 and PGIO4 are monitored by
comparators. The MOSFET is held off until all startup con-
ditions are met.
The DRAIN, RTNS − DRNS and GATE voltages are moni-
tored to determine if power is available for the load. Two
power good signals are sequenced on PGIO1 and PGIO2,
each with a delay that is twice the startup debounce delay.
Additionally, PGIO3 serves as a watchdog input to monitor
the output of the DC/DC module. If the module output fails
to come up, the LTC4283 turns off the MOSFET. PGIO4
defaults as an external fault input (inverted). PGIO1-4 can
also be configured into general purpose inputs or outputs.
An overcurrent fault at the output may result in excessive
MOSFET power dissipation during Active Current Limiting
(ACL). To limit this power, the ACL amplifier regulates
the SENSE+ – SENSE− voltage at precise, programmable
values (15mV to 30mV in 1mV steps). When the output
voltage is low, power dissipation is further reduced by
folding back the current limit, with the foldback ratio con-
figurable to 10%, 20%, or 50% of nominal. In the event
of a catastrophic output short when the sensed current
is twice of the current limit, fast response comparator
immediately pulls the GATE pin down with 2.3A.
When active current limiting is engaged, TMR is pulled up
by a current that is proportional to the power dissipation
in the MOSFET. With an RC network representing the ther-
mal behavior of the MOSFET connected between TMR and
VEE, the TMR voltage is proportional to the temperature
rise in the MOSFET. When TMR voltage reaches its thresh-
old of 2.048V (representing TJ(MAX) of the MOSFET), the
overcurrent fault is logged and GATE turns off, allowing
protection of the MOSFET based on true SOA. TMR can
also be configured to drive a single capacitor. Following
the overcurrent fault, the LTC4283 can either latch off the
MOSFET or auto-retry after a cooling delay. Both the retry
delay and the number of retries are configurable, too. The
LTC4283 also logs and responds to other faults including
overvoltage, undervoltage, FET bad, Power Good Input
(PGI) fault, FET short and external fault.
Included in the LTC4283 is a pair of analog to digital con-
verters (ADCs). The ADCs are configurable from 8-bit at
1kHz to 16-bit at 1Hz in five settings. As shown in the
Block Diagram, ADC1 continuously monitors the current
sense voltage between SENSE
+
and SENSE
−
. ADC2 is syn
-
chronized to ADC1 and measures the attenuated input
voltage at RTNS or the attenuated MOSFET drain voltage
at DRNS plus one of the fourteen auxiliary inputs. Every
time the ADCs finish taking a measurement, the current
sense voltage is multiplied by the measurement of the
RTNS or DRNS voltage to provide a power measurement.
Every time power is measured, it is added to an energy
accumulator that tracks the input energy or the energy
consumption of the MOSFET. The energy accumulator
can generate an optional alert upon overflow, and can
LTC4283
18
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
OPERATION
be preset to allow it to overflow after a given amount
of energy is reached. A time accumulator tallies energy
increments; dividing the results of the energy accumulator
by the time accumulator gives the average system power.
The minimum and maximum of each ADC measurement
and power are stored, and optional alerts may be gener-
ated if a measurement is above or below user configurable
8-bit thresholds.
An internal EEPROM provides nonvolatile configuration of
the LTC4283 operation behaviors and parameters. It also
records fault information and selected ADC data. Seven
bytes of uncommitted memory are reserved for general
purpose storage.
An I2C/SMBus interface accesses the ADC data registers
and allows the host to poll the device and determine if
a fault has occurred. If the ALERT# line is used as an
The LTC4283 is ideally suited for high availability dis-
tributed power systems, allowing a board to be safely
inserted or removed from a live negative voltage back-
plane. Figure1 shows a basic 600W application circuit.
Figure2 shows a more complete application circuit in
a dual-feed system with board insertion detection and
opto-coupling.
Input Power Supply
The LTC4283 features a floating topology that allows a
wide operating voltage range and is robust to faults. For
a –48V system, supply to the LTC4283 is derived from
the –48V RTN through an external shunt resistor RIN to
the V
IN
and V
Z
pins (Figure1). An internal shunt regulator
clamps V
IN
to 11.5V relative to V
EE
and provides power to
the GATE driver. VZ acts as the shunt path of the regula-
tor. A bypass capacitor of at least 0.1μF is recommended
between VIN/VZ and VEE. If EEPROM fault log is enabled
interrupt, the host can respond to a fault in real time. A
reboot command turns off the MOSFET and automati-
cally restarts after a configurable delay. The SDA line is
divided into SDAI (input) and SDAO (output) to facili-
tate opto-coupling with the system host. Two three-state
pins, ADR0 and ADR1, are used to decode eight device
addresses.
The communication interface can also be configured
through ADR0 and ADR1 for a single-wire broadcast
mode, sending ADC data and faults status through SDAO
to the host without clocking the SCL line. This single-
wire, one-way communication simplifies system design
by eliminating two opto-couplers on SCL and SDAI that
are required by an I2C interface. The transmission speed
is configurable from 32kHz to 2MHz with four settings.
(see Fault Log), the minimum bypass capacitance at VIN
for the fault log operation to complete upon an undervolt-
age or power loss condition is
CIN ≥15 µF
mA
�
�
�
�
�
�•(IIN(MAX) +IEXTERNAL )
An internal 5V linear regulator that derives from the 11.5V
supply powers data converters, logic control circuits, I2C
interface and EEPROM. The 5V output is available at the
INTVCC pin for driving external circuits. A bypass capaci-
tor of 1μF is recommended between INTVCC and VEE. To
only test data converters or program EEPROM, the main
–48V supply is not needed. Instead, a 5V supply may be
applied between INTV
CC
and V
EE
, with V
IN
and V
Z
con-
nected to INTVCC.
RIN should be chosen to accommodate the maximum sup-
ply current requirement of the LTC4283 (IIN(MAX) = 4mA)
plus the supply current required by any external devices
LTC4283
19
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure1. –48V/600W Hot Swap Controller with SOA Timer and Current Limited Inrush Control
driven by VIN and INTVCC at the minimum supply voltage,
VS(MIN) and the maximum VIN voltage, VIN(MAX):
RIN ≤
V
S(MIN)
–V
IN(MAX)
IIN(MAX)+IEXTERNAL
The maximum power dissipation in the resistor is
PMAX =
VS(MAX) �VIN(MIN)
( )
2
R
IN
If the power dissipation of R
IN
is too high for a single resis-
tor, use multiple resistors in series, which provides addi-
tional clearance spacing for high voltage surges. Another
option uses an external NPN transistor (QIN) as illustrated
in Figure2b. Each of VIN and VZ should be bypassed with
a capacitor of at least 0.1μF. In this case RZ is chosen
according to
RZ≤VS(MIN) – VIN(MAX) – VBE
IIN(MAX)+IEXTERNAL
�
+20µA
where VBE and β are the base-emitter voltage and DC
current gain of the NPN transistor, respectively and 20μA
represents the minimum VZ operating current. The maxi-
mum power dissipation of QIN is
PQIN,MAX = (VS(MAX) – VIN(MIN)) • IIN(MAX)
RIN or RZ may be split into multiple segments in order
to achieve the desired standoff voltage or dissipation.
Whereas 1206 size resistors are commonly rated for
200V working and 400V peak, pad spacing and circuit
board design rules may limit the working rating to as
little as 100V.
For applications at very high voltages (>300V), a high
voltage MOSFET can be used. Figure3 shows an appli-
cation circuit with a depletion mode N-channel MOSFET
that can withstand up to 1000V drain-to-source voltage.
In this case RZ is chosen according to
RZ≤
V
S(MIN)
–V
IN(MAX)
– V
GS
20µA
R3
487k
1%
C
VCC
1µF
0.5mΩ
2mΩ ×4
R
S1
R
IN
4×1k IN SERIES
0.25W EACH
C
IN
0.1µF
4
4
4
R
DB
5.11k
1%
M1A
PSMN4R8-100BSE
R
G1A
10Ω
R
G1
470Ω
R
D
100k
R2
14.3k
1%
R1
10k
1%
R
RT
200k
1%
R
RB
5.11k
1%
R
DT
200k
1%
C
G1
100nF
C
L
500µF
C
UV
100nF
M1B
PSMN4R8-100BSE
R
G1B
10Ω
C
E2
4.7nF
C
E1
68nF
R
E2
18.2k
1%
R
E1
1.13M
1%
–48V RTN
UVH
UVL
OV
–48V INPUT
ADIN1-4
TMR
V
EE
INTV
CC
SENSE+
GATE
DRAIN
V
Z
V
IN
RTNS
SCL
SDAI
SDAO
ALERT#
ADIO1-4
PGIO1-4
LTC4283
–48V RTN
(SHORT PIN)
V
EE
DRNS
DVDT = 0
THERM_TMR = 1
ILIM = 0001
FB = 11
FB_DIS = 0
LPFB = 1
EN#
UV = 38.6V
UV RELEASE AT 43.1V
OV = 71.9V
OV RELEASE AT 70.7V
V
EE
V
EE
V
EE
V
EE
V
EE
RAMP
SENSE–
4283 F01
BATTERY OPERATED
(SUBJECT TO –36V INPUT STEPS)
V
OUT
VLOAD
+
–
LTC4283
20
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
where VGS is the gate-to-source voltage of the MOSFET
(positive for an enhancement mode and negative for a
depletion mode transistor) . When using an enhancement
mode transistor, VZ voltage must be kept lower than its
absolute maximum of 16V:
VZ(MAX) = VIN(MAX) + VGS < 16V
In Figure2b and Figure3, the voltage drop and power
dissipation in the NPN or the MOSFET may be augmented
by the use of one or more resistors in series with the col-
lector or drain. If an external 12V supply is available on
the application board, it may be used to drive the VIN pin
directly as shown in Figure4.
Turn-On Sequence
The following conditions must be satisfied before the
turn-on sequence is started. First the voltage at VIN must
exceed the undervoltage lockout level of 8.1V. Next the
internal supply INTVCC must cross its 4V undervoltage
lockout level. This generates a 1.3ms power-on-reset
delay. After the delay times out, the voltages at UVH, UVL
and OV must satisfy UVH > 2.048V, UVL > 1.833V and
OV < 1.406V to indicate that the input power is within the
acceptable range, and EN# must be pulled low. All the
above conditions must be satisfied throughout the dura-
tion of the startup debounce delay of 128ms. If any of the
above conditions is violated during the delay, the delay is
reset and restarted. After the delay expires, if the ON bit
in CONTROL_1 register 0x0A is high, the LTC4283 turns
on the MOSFET. Otherwise, the MOSFET will be turned
on (without additional delay) when the ON bit is set to 1
through the I2C interface. When all turn-on conditions are
satisfied, the FET_ON_STATUS bit in SYSTEM_STATUS
register 0x00 is set to 1, indicating the MOSFET is com-
manded on.
Figure2a. –48V/600W Dual-Feed Hot Swap Controller with LTC4283 (Part One)
R
H
750Ω
1%
4
4
0.5mΩ
R
S1
R2
20k
1%
R1
10k
1%
C
E1
4.7nF
C
E2
68nF
R
E1
18.2k
1%
R
E2
1.13M
1%
C
UV
100nF
Q3
2N5401
R4
100k
R5
100k
100A
R8
10k
R6
100k
R7
100k
C
EN
1µF
R10
100k
HZS5C1
100A
100A
100A
R9
10k
R
RT
200k
1%
R
RB
5.11k
1%
R3
499k
1%
Q4
2N5401
R11
5.62k
1%
R12
20k
1%
RTN A
UVH
UVL
OV
–48V B
ADIN1-4
TMR
V
EE
SENSE–
SENSE+
RAMP
ADIO1-4
LTC4283
DVDT = 0
THERM_TMR = 1
PWRGD_RESET_CNTRL = 1
ILIM = 0001
FB = 11
FB_DIS = 1
LPFB = 1
4283 F02a
EN#
UV = 32.4V
UV RELEASE AT 35.3V
OV = 74.5V
OV RELEASE AT 73.2V
V
EE
LTC4371
RTN B
–48V A
LTC4355
1N4148
×2
RTNS
A
B
BACKPLANE
PLUG-IN
CARD
V
EE
2mΩ
×4
VOUTTH
VREF
V
EE
BATTERY OPERATED
(SUBJECT TO –36V INPUT STEPS)
LTC4283
21
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Figure2b. –48V/600W Dual-Feed Hot Swap Controller with LTC4283 (Part Two)
M1A
PSMN4R8-100BSE
M1B
PSMN4R8-100BSE
R
G1A
10Ω
R
G1B
10Ω
R
D
100k
R
DT
200k
1%
R
G1
470Ω
C
G1
100nF
C
L
500µF
R
DB
5.11k
1%
Q
IN
BCP56
R
Z
100k
C
VCC
1µF
R13
5.1k
R14
5.1k
R15
5.1k
R16
5.1k
R17
5.1k
R18
5.1k
Q5
HCPL-0300
Q6
6N139
R19
5.1k
Q7
MOC207
Q10
6N139
R22
5.1k
Q8
Q9
R20
0.51k
R21
0.51k
R
L
343Ω, 2.4k
28.7W, ×7
0805
MBRM5100
4283 F02b
INTV
CC
GATE
DRAIN
V
Z
V
IN
SCL
SDAI
SDAO
ALERT#
PGIO4
LTC4283
DRNS
A
B
V
EE
PGIO3
PGIO1
PGIO2
CASE
VIN–
VOUT–
VOUT–
VIN–
VOUT+
VIN+
VOUT+
VIN+
FLTR100V10
FILTER
MODULE
CASE
JW050A1
-
E
POWER
MODULE
ON
V
DD
GND
RST
LTC2900
V
DD
MICRO-
CONTROLLER
SCL
SDA
ALERT
RST
HCPL-
2630
DUAL
100V
OV TRANSIENT
RESERVOIR
CAPACITOR
V
EE
V
EE
V
EE
V
EE
V
EE
GND
V
EE
VOUT
VLOAD
+
–
CIN
0.1µF
CZ
0.1µF
RTN
–48V
R
Z
1M
C
Z
0.1µF
C
IN
0.1µF
M
IN
IXTY08N100D2
V
Z
V
IN
LTC4283
4283 F03
V
EE
DEPLETION-
MODE
–48V
C
IN
0.1µF
V
Z
V
IN
LTC4283
V
EE
V
EE
EXTERNAL
12V
SUPPLY*
V
EE
4283 F04
*MUST COMPLY WITH MAXIMUM
RATING OF VIN PIN
The turn-on sequence continues by charging up GATE
with 100μA current source. When the GATE voltage
reaches the MOSFET threshold voltage, the MOSFET
begins to turn on and the inrush current charges the
load capacitor CL to ramp the MOSFET drain towards
VEE in a controlled manner (see Inrush Control). When
the MOSFET drain is ramped down to VEE or the output
is ramped up to the supply voltage, GATE is pulled up to
VIN and the MOSFET is fully enhanced. The GATE_HIGH
bit in SYSTEM_STATUS register 0x00 is set when GATE is
above VIN – 1.8V. Figure5 illustrates the startup sequence
of the LTC4283.
During the power-on-reset delay of 1.3ms, the fault regis-
ters are cleared and the control registers are loaded with
the data held in the corresponding EEPROM registers.
The power-on-reset can be detected using the PORB bit
in register 0x0E, which will be cleared when INTVCC dips
below 3.8V. Set this bit to 1 in normal operating condi-
tions and keep monitoring this bit. A 0 from subsequent
reading indicates a power-on-reset has occurred.
Figure3. The LTC4283 Can Operate to >300V
Using a Depletion Mode N-Channel MOSFET
Figure4. Using an External 12V Supply
LTC4283
22
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Inrush Control
Inrush current control can be configured in two ways.
First, if the DVDT bit in CONTROL_1 register 0x0A is set
to 1, the inrush current is controlled in dV/dt mode by
an external capacitor connected between RAMP and VEE
(the RAMP capacitor, CR), as shown in Figure6. In dV/dt
mode, the inrush current is limited by controlling a con-
stant output voltage ramp rate (dV/dt). During startup,
when the GATE voltage reaches the MOSFET threshold
voltage, RAMP outputs a fixed 2.5μA current to charge
CR while the inrush current charges load capacitor CL.
During dV/dt control the LTC4283 regulates the RAMP
to the attenuated load voltage between RTNS and DRNS
with an offset:
VRAMP = VRTNS – VDRNS + 0.18V
and regulates the inrush current to a fixed value that is a
function of the attenuation ratio, r and the ratio between
load capacitance and RAMP capacitance:
IINRUSH =2.5µA •r •
C
L
C
R
The attenuation ratio r is set by the external resistive divid-
ers at RTNS (RRT and RRB) and DRNS (RDT and RDB) in
Figure6:
r=
R
RT
+R
RB
R
RB
=
R
DT
+R
DB
R
DB
RTNS and DRNS represent the attenuated input voltage
and MOSFET drain voltage, respectively. The differential
Figure5. LTC4283 Turn-On Sequence
–48V
INPUT
UVLO AND UV CLEARED
128ms
GATE
VIN – 1.8V
4283 F05
CURRENT
PGIO1
PWRGD1#
READY
PWRGD2#
READY
INTERNAL
POWER
GOOD
INRUSH
(LATCHED)
LOAD1
LOAD1 + LOAD2
MOSFET
VDS
2.048V
PGIO2
PGIO3
FAULTY POWER GOOD INPUT
NORMAL POWER GOOD INPUT
256ms
512ms
256ms
Figure6. dV/dt Inrush Control Using RAMP Capacitor
R
IN
C
IN
M1
RS
R
RT
200k
1%
R
RB
5.11k
1%
C
L
C
R
R
DT
200k
1%
R
DB
5.11k
1%
–48V
RTN
–48V
INPUT
V
EE
SENSE–
SENSE+
GATE
V
Z
V
IN
RTNS
LTC4283
V
EE
V
EE
RAMP
V
LOAD
V
OUT
DRNS
+
–
4283 F06
V
EE
LTC4283
23
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
voltage between RTNS and DRNS therefore represents
the attenuated load voltage. The operation range of VRTNS,
VDRNS and VRTNS – VDRNS is from 0V to 2.8V.
The dV/dt control is only active during initial startup.
After the turn-on sequence is completed and power good
signals are activated, the dV/dt inrush control mode is
disabled and RAMP is discharged with a 4mA current.
RAMP will also be discharged under any GATE turn-off
conditions. In the dV/dt mode the inrush current must be
set lower than the folded back current limit level to avoid
triggering the current limit (see below).
The second inrush control mechanism is active cur-
rent limiting. This is enabled by clearing the DVDT bit in
CONTROL_1 register 0x0A. In this mode the inrush cur-
rent is regulated to the folded back current limit:
IINRUSH = ILIM • aSTARTUP
where ILIM is the current limit and aSTARTUP is the startup
foldback factor. ILIM is determined by the current limit
sense voltage VILIM and the sense resistance RS.
ILIM =
V
ILIM
R
S
VILIM is configurable from 15mV to 30mV in 1mV steps.
aSTARTUP is configurable to 10%, 20%, 50% and 100%
(no foldback) of current limit. During startup the current
limit foldback profile is flat and does not change with
output voltage. See Current Limit Adjustment and Current
Limit Foldback for details. In this mode the RAMP capaci-
tor CR at the RAMP pin no longer takes effect. If CR is
omitted, RAMP must be left open.
Power Good Monitors and PGI Fault
After the MOSFET is turned on, the following conditions
must be met before the power good signals are activated.
First, the DRAIN voltage must fall below 2.048V to indicate
the MOSFET drain is low. Second, RTNS − DRNS must be
higher than the external threshold voltage at VOUTTH to
indicate the output voltage is high. Last, GATE voltage must
satisfy the GATE high (>VIN – 1.8V) condition. When all
three conditions are met, an internal power good signal is
latched, the PG_STATUS bit in SYSTEM_STATUS register
0x00 is set, and a series of three delay cycles are started
as illustrated in Figure5. When the first delay of 256ms
expires, the first power good signal PGIO1 turns on the
first load. When the second delay of 256ms expires, the
second power good signal PGIO2 can be used to turn on
a second load.
Following the two 256ms delays, a third delay of 512ms is
started for monitoring PGIO3 as a power good input (PGI)
watchdog. Before this delay expires, PGIO3 must be pulled
low or high (polarity configurable by register 0x10) by an
external supply monitor to indicate the load is working prop-
erly. Otherwise, the MOSFET is turned off and a PGI fault is
logged in FAULT register 0x04. The MOSFET is allowed to
auto-retry after a delay of 128ms following the PGI fault if
the PGI_RETRY bit in CONTROL_2 register 0x0B is set to
1. Both power good signals and the power good input can
be configured into inverted or non-inverted polarity using
PGIO_CONFIG_1 register 0x10 (see Table12). To disable
the PGI watchdog, connect PGIO3 to V
EE
or INTV
CC
depend-
ing on the configured polarity, or configure PGIO3 as gen-
eral purpose input or output using register 0x10.
Power good signals are reset in two configurable ways.
If the PWRGD_RESET_CNTRL bit in CONTROL_1 reg-
ister 0x0A is set to 1, power good signals are reset by
an output low condition as indicated by RTNS − DRNS
< VOUTTH. In Figure2a VOUTTH is biased at 0.8V, so
power good signals will be reset when RTNS – DRNS
drops below 0.8V, which corresponds to VOUT < 32V. If
the PWRGD_RESET_CNTRL bit is cleared, power good
signals are reset by any GATE turn-off conditions except
overvoltage fault. When the power good signals are reset,
the power good delays and the PGI delay are also reset.
Turn-Off Sequence
In any of the following conditions, the MOSFET is turned
off by pulling down the GATE pin with 18mA current
source and the FET_ON_STATUS bit in SYSTEM_STATUS
register 0x00 is cleared.
1. VIN is lower than 7.6V (VIN undervoltage lockout).
2. INTVCC is lower than 3.8V (INTVCC undervoltage
lockout).
3. EN# is high.
4. ON bit in CONTROL_1 register 0x0A is cleared.
LTC4283
24
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
5. OV is higher than 1.406V (overvoltage fault).
6. UVL is lower than 1.833V and UVH is lower than
2.048V (undervoltage fault).
7. TMR reaches its 2.048V threshold (overcurrent fault).
8. DRAIN rises above 2.048V or GATE dips below VIN
– 1.8V and this condition lasts longer than a pre-
configured delay (FET bad fault).
9. PGIO3, when configured as PGI#/PGI input, is high/
low when the PGI check delay of 512ms expires
(PGIfault).
10. PGIO4 pin, when configured as EXT_FAULT#/EXT_
FAULT, is low/high (external fault).
11. The RBT_EN bit in REBOOT register 0xA2 is set.
For condition 8, if the FET_BAD_TURN_OFF bit in
CONTROL_1 register 0x0A is cleared, the MOSFET
remains on following a FET bad fault. For condition 10,
if the EXT_FAULT_TURN_OFF bit in CONFIG_3 register
0x0F is cleared, the MOSFET remains on following an
external fault. For condition 11, the LTC4283 will automat-
ically reboot after a programmable delay. See Reboot on
I2C Command. For each independent GATE turn-off fault,
the LTC4283 can be configured to latch off the MOSFET
or go into an auto-retry sequence after the fault occurs.
Overcurrent Protection
The LTC4283 features two levels of protection from short-
circuit and overcurrent conditions. Load current is moni-
tored by SENSE+ and SENSE− pins and sense resistor.
There are two distinct thresholds for the sense voltages:
VILIM and VILIM(FAST). VILIM is configurable from 15mV to
30mV in 1mV steps and VILIM(FAST) is always twice VILIM.
See Current Limit Adjustment for details.
If the sense voltage reaches VILIM, GATE is pulled down
by 50mA current until the active current limit loop is
engaged. In the event of a catastrophic short-circuit or
a sudden input step, where the sense voltage reaches
V
ILIM(FAST)
, the GATE is immediately pulled down by a
2.3A current to limit peak current through the MOSFET.
When the sense voltage drops to VILIM, the active current
limit loop is engaged.
SOA Timer
During active current limit, the power dissipation in the
MOSFET is large. If this power dissipation persists, the
MOSFET can reach temperatures that cause damage.
MOSFET manufacturers specify the safe limits on operat-
ing voltage, current and time as a curve referred to as the
Safe Operating Area (SOA). Commonly, a circuit breaker
timer sets a maximum time for the MOSFET to operate in a
current limit mode. When this timer expires, the MOSFET
is turned off to protect it from overheating. Traditional
circuit breakers often employ a fixed current charging an
external capacitor. The minimum timer timeout must be
set to allow the worst-case operating condition, such as
completely charging a large bypass capacitor at output
during startup or riding through a large input step. Then
upon fault conditions such as an output short-circuit at
full supply voltage, the MOSFET must withstand the large
power throughout the entire timer duration. Therefore,
the MOSFET must be selected to withstand the worst-
case SOA condition that occurs during any possible nor-
mal operating condition or fault condition. This not only
substantially increases the cost of the MOSFET, but also
complicates the design procedure and MOSFET selection.
The LTC4283 features a circuit breaker timer that better
fits the SOA of the MOSFET. When active current limit is
engaged, the OC_STATUS bit in FAULT_STATUS register
0x03 is set, and the TMR pin is activated and charged up
by a current proportional to the power dissipation in the
MOSFET. A proper electric model (RC network) is selected
to represent the thermal behavior of the MOSFET. When
this RC network is connected between TMR and VEE, the
TMR voltage is proportional to the rise in the MOSFET junc-
tion temperature. The LTC4283 compares the TMR voltage
to a fixed threshold voltage of 2.048V, which represents
the maximum allowable junction temperature rise in the
MOSFET. When the TMR voltage crosses this threshold,
the LTC4283 turns off the MOSFET. Therefore, to provide
an appropriate protection of a MOSFET, one simply selects
the MOSFET that meets the SOA requirement for allowable
operating conditions such as startup and input step. The
MOSFET is automatically turned off before it is subject to
any condition that would exceed its SOA rating.
LTC4283
25
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Case 1. If active current limit is engaged in normal opera-
tion (power good signals are asserted), the TMR pull-up
current of the LTC4283 is proportional to the attenu-
ated drain voltage of the MOSFET at DRNS (top line in
Figure7). This is proportional to the power dissipation
since the current through the MOSFET is fixed during
current limit (provided that foldback is disabled in normal
operation by setting the FB_DIS bit in CONFIG_1 register
0x0D). The TMR pull-up current in this condition is:
ITMR(UP)=111.1
µA
V
⎡
⎣
⎢⎤
⎦
⎥• VDRNS+2µA
where 111.1µA/V is the transconductance. The TMR pull-
up current reaches 202µA at V
DRNS
=1.8V, which is tested
and specified. The offset of 2μA is introduced to guarantee
a minimum pull-up current that prevents TMR from hang-
ing in a resistive short-circuit condition.
The above equation also applies to startup in dV/dt mode
(DVDT bit in CONTROL_1 register 0x0A = 1), when the
current limit is triggered under a fault condition such as
a short-circuit. The accelerated timeout combined with
startup foldback (see Current Limit Foldback) protects
MOSFET from overstress.
Case 2. During startup in dV/dt mode when current limit
is not engaged, TMR pull-up current is disabled:
ITMR(UP) = 0
In this case a 2μA pull down current holds TMR low if
the THERM_TMR bit in control register 0x0A is set. This
avoids undesired timeout before the load capacitor is fully
charged by the inrush current, which is set to such a low
level that the power dissipation in MOSFET is insignificant.
Case 3. If current limit is engaged during startup in current
limit mode (DVDT bit in CONTROL_1 register 0x0A = 0),
the TMR pull-up current is reduced by the foldback ratio:
ITMR(UP) =αSTARTUP •111.1
µA
V
⎡
⎣
⎢⎤
⎦
⎥• VDRNS +2µA
where aSTARTUP is the startup foldback ratio that is con-
trolled by the FB bits in CONFIG_1 register 0x0D (see
Current Limit Foldback). The reduction keeps the trans-
conductance unchanged compared to that in normal
operation with foldback disabled.
Case 4. If current limit is not engaged, either in normal
operation or during startup in current limit mode, the
TMR pull-up current is gated by the DRAIN voltage. If
DRAIN is lower than its threshold, V
D,FET(TH)
, the TMR
pull-up current is disabled. VD,FET(TH) is programmable
from 72mV to 203mV in geometric scale using the VDTH
bits in CONFIG_2 register 0x0E. This is a typical case in
normal operating conditions when the MOSFET is fully
enhanced. If DRAIN is higher than VD,FET(TH), an internal
multiplier charges up TMR with a current approximately
proportional to power dissipation in the MOSFET:
If ΔV
SENSE
≥0.1V
ILIM
,
ITMR(UP) =111.1 µA
V
⎡
⎣
⎢⎤
⎦
⎥• VDRNS •ΔVSENSE
VILIM
– 0.1
⎛
⎝
⎜⎞
⎠
⎟+2µA
If ΔVSENSE <0.1VILIM,
ITMR(UP) =2µA
Figure7 shows the TMR pull-up currents vs V
DRNS
at four
different ∆VSENSE levels below current limit.
If using an RC network representing the MOSFET thermal
model between TMR and VEE, the THERM_TMR bit in
CONTROL_1 register 0x0A must be set to 1 to disable
the internal 2μA pull-down current. The total resistance
in the RC network provides the discharge path to TMR.
Figure7. TMR Pull-Up Current vs ∆VSENSE and DRNS Voltage
∆VSENSE =
100% V
ILIM
96.7% V
ILIM
50% V
ILIM
20% V
ILIM
10% V
ILIM
DRNS VOLTAGE (V)
0
0.5
1
1.5
2
2.5
3
0
50
100
150
200
250
300
350
TMR PULL-UP CURRENT (µA)
4283 F07
LTC4283
26
Rev. A
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APPLICATIONS INFORMATION
The configuration of the RC network for a particular
MOSFET starts with selection of a desired number of
resistive and capacitive elements and their values in ther-
mal domain based on the thermal impedance plot pro-
vided by the MOSFET manufacturer. Three resistors and
three capacitors are usually enough to fit the plot fairly
well from 10μs to 100ms, which covers the timing range
of typical operating and fault conditions. Two resistors
and two capacitors may provide an acceptable accuracy
for some MOSFETs or conditions. If better fitting accuracy
or wider fitting range is desired, more elements may be
used. After the thermal RC network is configured, the
thermal quantities are then converted to electric quanti-
ties according to
R
E
=k •R
�
CE=C�
k
where RE and CE are electric resistance and capacitance,
respectively and Rθ and Cθ are thermal resistance and
capacitance, respectively. The conversion constant k is
given by
k=VDS,MAX •ID,MAX
ITMR(UP),MAX
•VTMR(TH)
�TMAX
where VDS,MAX and ID,MAX are the maximum drain-
to-source voltage and maximum drain current of the
MOSFET, respectively, ITMR(UP),MAX is the TMR pull-up
current corresponding to the maximum power dissipa-
tion PMAX = VDS,MAX • ID,MAX, VTMR(TH) is TMR threshold
voltage (2.048V), and ∆TMAX is the maximum allowable
temperature rise of the MOSFET. For example, if VDS,MAX
= 72V, ID,MAX = 32A, ITMR(UP),MAX = 202μA (at VDRNS
= 1.8V, in current limit) and ∆T
MAX
= 65°C (maximum
junction temperature of MOSFET = 150°C and ambient
temperature = 85°C), k = 3.6 • 105 [V2/°C]. An RC network
consisting of two resistors and capacitors that represent
the electric model for the thermal behavior of PSMN4R8-
100BSE is show in Figure2a.
The LTC4283 also allows a single capacitor connected
between TMR and VEE (see Figure13). In this case, the
THERM_TMR bit in the CONTROL_1 register must be
cleared to enable the internal 2μA pull-down current.
Once enabled, the 2μA pull-down current keeps TMR low
in normal conditions when the pull-up current is disabled.
When the pull-up current is enabled under fault conditions,
the 2μA pull-down is switched off. A minimum capaci-
tance must be selected to keep the MOSFET on during
worst-case operating conditions, and the MOSFET must
be selected to withstand the worst-case SOA condition
during normal operating or fault conditions. Regardless
of the value of the THERM_TMR bit, when EN# is higher
than its 1.28V threshold, TMR is discharged by a 5mA
current. When TMR is below 0.1V, the TMR_LOW bit in
SYSTEM_STATUS register 0x00 is set to 1.
Overcurrent Fault and Auto-Retry
Under an overcurrent condition, when the active current
limit loop is engaged and TMR is being charged up, the
overcurrent present bit, OC_STATUS, in FAULT_STATUS
register 0x03 is set. When the TMR voltage reaches its
2.048V threshold, the overcurrent fault bit, OC_FAULT, in
the FAULT register 0x04 is set and the GATE pin is pulled
down to turn off the MOSFET.
After the MOSFET is turned off, the OC_STATUS bit is
cleared. The MOSFET is allowed to turn on again after a
cooling delay if the OC_RETRY bits in CONTROL_2 register
0x0B have not been cleared. The auto-retry cooling delay
is configurable from 512ms to 65.5s in binary scale using
the COOLING_DL bits in CONFIG_2 register 0x0E (See
Table11). During the cooling delay the DELAY_STATUS
bit in REBOOT register 0xA2 is set to 1 to indicate the delay
timer is running. It will be cleared when the delay expires.
The number of retries following an overcurrent fault can be
configured to 1, 7 or infinity using the OC_RETRY bits (see
Table10). If a finite retry number is selected, a retry coun-
ter reset timer of 16.4s is started upon the retry following
an overcurrent fault. If the next overcurrent fault occurs
before the timer times out, the retry counter increments
and the timer is restarted. Otherwise the retry counter
is restarted. When the programmed number of retries is
reached, the MOSFET will be latched off if the next over-
current fault occurs before the counter reset timer times
out. During startup when power good conditions are not
met, the counter reset timer is disabled. The retry counter
and the counter reset timer for the overcurrent fault are
independent of those for the FET bad fault.
LTC4283
27
Rev. A
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APPLICATIONS INFORMATION
If the OC_RETRY bits in the CONTROL_2 register 0x0B
have been cleared, the MOSFET will remain off until the
OC_FAULT bit is reset (see Resetting Faults). When the
OC_FAULT bit is reset, the MOSFET is allowed to turn on
after the auto-retry delay expires.
Current Limit Adjustment
The current limit voltage, VILIM, is programmable between
15mV and 30mV in 1mV steps through the I2C interface
using the ILIM bits in CONFIG_1 register 0x0D. The
default values are stored in EE_CONFIG_1 register 0xAD
in the onboard EEPROM. The fast GATE pull-down sense
voltage, VILIM(FAST), is set to twice of VILIM through the
whole configuration range. The fine scales are useful in
adjusting the sense voltage to achieve a given current
limit using the limited selection of standard sense resis-
tor values available around 1mΩ. The adjustability allows
the LTC4283 to reduce available current for light loads
or increase it in anticipation of a surge. This feature also
enables the use of board-trace as sense resistors by trim-
ming the sense voltage to match measured copper resis-
tance during final test. The measured copper resistance
may be written to the undedicated scratch pad area of the
EEPROM (0xE9-0xEF) so that it is available to scale ADC
current measurements.
Current Limit Foldback
The LTC4283 current limit can be configured to fold back
to four levels: 10%, 20%, 50% and 100% (no foldback) of
full current limit using the FB bits in the CONFIG_1 regis-
ter 0x0D. During the startup inrush control the foldback
profile is flat (Figure8a), resulting in a constant current
limit. This is to protect the MOSFET more effectively upon
a resistive output short during startup. With a traditional
resistive foldback profile, if the output short resistance is
the same as the slope of the foldback profile, the foldback
has no effect and a MOSFET with larger SOA must be
selected to withstand the full stress, substantially increas
-
ing the MOSFET cost.
After the internal power good signal is latched (see Power
Good Monitors and PGI Fault), the LTC4283 goes into
normal operation and the foldback is determined by the
attenuated output voltage for the load, RTNS – DRNS
(Figure8b). If the output voltage or RTNS – DRNS drops
to 0V in an event such as a catastrophic output short, the
current limit sense voltage is folded back to the ratio con-
figured by the FB bits. As shown in Figure8b, the foldback
ratio increases linearly with RTNS – DRNS and reaches
100% when RTNS – DRNS reaches 0.9V, which corre-
sponds to the minimum supply voltage of an application.
Above 0.9V the current limit sense voltage stays constant
unless the load power foldback (LPFB) bit in the CONFIG_1
register 0x0D is set. If the LPFB bit is set, the current
limit sense voltage decreases linearly to 50% when RTNS
– DRNS reaches 1.8V (corresponding to the maximum
supply voltage). This profile approximately tracks the load
power when the output voltage increases with a constant
powerload.
Figure8a. Current Limit Foldback During Startup
Figure 8b. Current Limit Foldback in Normal Operation
VRTNS – VDRNS (V)
VRTNS = 1.8V
0
V
ILIM
(%)
100
50
20
10
00.9
4283 F08a
1.8
FB = 11
FB = 10
FB = 01
FB = 00
VRTNS – VDRNS (V)
0
V
ILIM
(%)
100
50
20
10
00.9
4283 F08b
1.8
11
10
01
LPFB = 0
LPFB = 1
FB = 00
VRTNS = 1.8V
LTC4283
28
Rev. A
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APPLICATIONS INFORMATION
The LTC4283 foldback profile can differentiate an output
short fault from an allowed input step. Upon an output
short, RTNS – DRNS drops and current limit is folded
back to protect the MOSFET from overstress. In the event
of an input step, RTNS – DRNS increases while the load
is charged up. The current limit either stays constant or
approximates constant load power (based on the LPFB
bit) to approach the optimum output ramp and minimize
the temperature rise of the MOSFET (see Input Step and
Optimum Output Ramp). This is superior to a foldback
profile capacitance based upon VDS or power dissipation
of the MOSFET. In that case, the output short and input
step conditions cannot be differentiated, often resulting
in unwanted turn-off upon an input step.
Foldback in normal operation can be independently dis-
abled by setting the FB_DIS bit in the CONFIG_1 register
0x0D. With this configuration foldback is only effective
during startup, and it should only be used when an RC
network representing the thermal model of the MOSFET
is connected to TMR. If a single capacitor is used, it is
recommended to enable foldback in normal operation by
clearing the FB_DIS bit for more conservative protection
of the MOSFET. Note that the load power foldback con-
trolled by the LPFB bit is not affected by the FB_DIS bit.
FET Bad Fault and Auto-Retry
In a hot swap application several possible faults can
prevent the MOSFET from turning on fully. A damaged
MOSFET may have leakage from gate to drain or have
degraded RDS(ON). Debris on the board may also pro-
duce leakage or a short from the GATE pin to VEE or the
MOSFET drain. In these conditions the LTC4283 may not
be able to pull the GATE pin high enough to fully enhance
the MOSFET, or the MOSFET may not reach the intended
RDS(ON) when the GATE pin is fully enhanced. This can
put the MOSFET in a condition where the power in the
MOSFET is higher than its continuous power capability,
even though the current is below the current limit. The
LTC4283 monitors the integrity of the MOSFET in two
ways, and acts on both of them in the same manner.
First, the LTC4283 monitors the MOSFET drain voltage
at the DRAIN pin. A comparator detects a DRAIN high
condition whenever DRAIN is above a reference voltage,
VD,FET(TH) that can be configured to 72mV, 102mV,
143mV or 203mV (geometric scale) using the VDTH bits
in the CONFIG_2 register 0x0E. Second, the LTC4283
monitors the GATE voltage. If the MOSFET is turned on,
but the GATE voltage is lower than V
IN
– 1.8V, a GATE low
condition is detected.
When either a DRAIN high or a GATE low condition is
present when the MOSFET is commanded on, the FET_
BAD_STATUS bit in FAULT_STATUS register 0x03 is
set and an internal FET bad fault timer is started. The
FTBD_DL bits in CONFIG_2 register 0x0E configures the
timer duration to 256ms, 512ms, 1.02s and 2.05s. If
the DRAIN voltage falls below VD,FET(TH) and the GATE
low condition is cleared before the timer times out, the
FET_BAD_STATUS bit is cleared and the timer is reset.
If the timer does time out, the FET_BAD_FAULT bit in
FAULT register 0x04 is set and the MOSFET is turned off
if the FET_BAD_TURN_OFF bit in CONTROL_1 register
0x0A has been set. The DRAIN high condition also acti-
vates TMR pull-up current when not in current limit (see
SOA Timer).
Note that during startup while the load is being charged,
the FET_BAD_STATUS bit is set and the FET bad fault
timer is running. To avoid undesired turn-off, the timer
duration must be configured long enough for the load to
be fully charged.
After the MOSFET is turned off following a FET bad fault,
the FET_BAD_STATUS bit is cleared. The MOSFET is
allowed to turn on again after a cooling delay if the FET_
BAD_RETRY bits in CONTROL_2 register 0x0B have not
been cleared. The cooling delay is the same as that for an
overcurrent fault and is configurable from 512ms to 65.5s
in binary scale using the COOLING_DL bits in CONFIG_2
register 0x0E (see Table11). During the cooling delay the
DELAY_STATUS bit in REBOOT register 0xA2 is set. It will
be cleared when the delay expires. The FET_BAD_RETRY
bits configures the number of retries following a FET bad
fault to 1, 7 or infinity (see Table10). If a finite retry
number is selected, a retry counter reset timer of 16.4s is
started upon the retry following a FET bad fault. If the next
FET bad fault occurs before the timer expires, the retry
counter increments and the timer is reset. Otherwise the
LTC4283
29
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
retry counter is reset. The retry counter and the counter
reset timer for the FET bad fault are independent of those
for the overcurrent fault.
If the FET_BAD_RETRY bits in CONTROL_2 register 0x0B
have been cleared, the MOSFET will remain off until the
FET_BAD_FAULT bit is reset (see Resetting Faults) or the
FET_BAD_TURN_OFF bit is cleared through I2C. In either
of those two cases, the MOSFET is allowed to turn on after
the auto-retry delay expires.
Input Step and Optimum Output Ramp
In events such as battery hot swapping or supply surge,
the input voltage may experience a sudden step. The mag-
nitude of the input step, ∆V, can be as large as tens of
volts. As long as the input voltage does not exceed the
overvoltage limit, the input step is not a fault condition
and the system should stay on and operate through it.
In the presence of the load capacitor, the output does
not follow the input immediately, but rather ramps up
from the initial supply voltage to the new supply voltage
while charging the load capacitor. The VDS of the MOSFET
initially jumps to ∆V and then ramps down. Additionally,
during the output ramp the MOSFET not only carries the
load current, IL but also the capacitance charging cur-
rent, ICL, so the total power dissipation in the MOSFET
can be very large. If a large input step is possible, it is
usually the worst-case operating condition for the SOA of
the MOSFET, and a proper MOSFET must be selected to
withstand the stress.
In such a condition, the minimum temperature rise of the
MOSFET is achieved when I
CL
matches I
L
, or the total cur-
rent is twice the load current. In other words, the current
limit should be set to twice the load current during the
output ramp:
ILIM(OPT) = 2 • IL
This is in contrast to the concept of foldback that is used
to protect the MOSFET in a short-circuit condition. The
foldback profile of the LTC4283 automatically takes care
of both input step and output short-circuit conditions by
relating the foldback ratio to the output voltage for the
load instead of V
DS
of the MOSFET. See Figure8b and
Current Limit Foldback for details. Additionally, if the load
follows a constant power relationship, the LPFB bit in
CONFIG_1 register 0x0D can be set to enable load power
foldback so that the current limit approximately tracks
twice the load current during the output ramp. The wave-
forms in Figure9 show how the LTC4283 responds to a
–36V to –72V input step to achieve the optimum output
ramp rate. Note that the power good signals on PGIO1 and
PGIO2 are not interrupted during an input step.
Figure9. LTC4283 Responds to –36V to –72V Input Step
with a Constant Power Load
INPUT
MOSFET
V
DS
GATE
–36V
36V
–72V
72V
VLOAD
36V
VIN
MOSFET VTH
CURRENT
ILIM = LOAD + INRUSH
LOAD
LOAD
LOAD
4283 F09
Overvoltage Fault and Auto-Retry
The OV pin can be used to monitor a supply overvoltage
condition using an external resistive divider. An overvolt-
age fault occurs when OV rises above its 1.406V thresh-
old. This condition turns off the MOSFET immediately and
sets the OV_STATUS bit in FAULT_STATUS register 0x03
and the OV_FAULT bit in FAULT register 0x04. Note that
the power good signals are not affected by the overvoltage
fault. If OV subsequently falls back below the threshold
LTC4283
30
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
minus hysteresis of 24mV, the OV_STATUS bit is cleared
and the MOSFET will be allowed to turn on again (without
delay) unless overvoltage auto-retry has been disabled by
clearing the OV_RETRY bit in CONTROL_2 register 0x0B.
Undervoltage Fault and Auto-Retry
The LTC4283 features two undervoltage pins, UVH and
UVL, for precise undervoltage monitoring and adjustable
hysteresis. UVH has an accurate rising threshold:
VUVH(TH) = 2.048V, UVH rising
UVL has an accurate falling threshold:
VUVL(TH) = 1.833V, UVL falling
Both pins have a small built-in hysteresis, dVUV (11mV
typical). With either a rising or a falling input supply, the
undervoltage comparator works in such a way that both
UVH and the UVL have to cross their threshold for the
comparator output to change state.
The UVH, UVL and OV threshold ratio is designed to
match the standard telecom operating range of 43V to
71V and UV hysteresis of 4.5V when UVH and UVL are
connected together as in Figure1, where the UV hyster-
esis referred to UVL is:
∆VUV(HYST) = VUVH(TH) – VUVL(TH) = 0.215V
Using R1 = 10k, R2 = 14.3k and R3 = 487k as in Figure1
gives a typical operating range of 43.1V and 70.7V, with
an undervoltage shutdown threshold of 38.6V and an
overvoltage shutdown threshold of 71.9V.
The UV hysteresis can be adjusted by separating UVH and
UVL with a resistor R
H
as shown in Figure10. To increase
the UV hysteresis, place the UVL tap above the UVH tap
as in Figure10a. To reduce the UV hysteresis, place the
UVL tap under the UVH tap as in Figure10b. UV hysteresis
referred to UVL is given by:
If VUVL ≥ VUVH,
�VUVL(HYST) = � VUV(HYST) +2.048V • RH
R1+R2
If VUVL < VUVH,
�VUVL(HYST) = � VUV(HYST) – 2.048V •
R
H
R1+R2 +R
H
In the latter case, the minimum UV hysteresis allowed is
the built-in hysteresis of UVH and UVL:
∆VUVL(HYST,MIN) = dVUV = 11mV
which occurs when RH reaches its maximum value:
RH(MAX) = 0.11 • (R1 + R2)
LTC4283 ensures that the UV comparator is immune to
chattering even when RH is larger than RH(MAX).
An undervoltage fault occurs when UVL falls below
1.833V and UVH falls below 2.048V − dVUV. This condi-
tion turns off the MOSFET and sets the UV_STATUS bit
in FAULT_STATUS register 0x03 and the UV_FAULT bit
in FAULT register 0x04.
Following the undervoltage fault, the UV_STATUS bit is
cleared when the UVH pin rises above 2.048V and UVL
rises above 1.833V + dVUV. After a delay of 128ms, the
MOSFET will be allowed to turn on again unless the
undervoltage auto-retry has been disabled by clearing
the UV_RETRY bit in CONTROL_2 register 0x0B.
When power is applied to the device, if UVL is below
the 1.833V threshold and UVH is below 2.048V − dVUV
after INTVCC crosses its undervoltage lockout threshold
of 4V, an undervoltage fault will be logged in FAULT reg-
ister 0x04 and can be cleared using the I2C interface after
power-up.
Figure10. Adjustment of Undervoltage Thresholds
for Larger (10a) or Smaller (10b) Hysteresis
UVL
UVH
OV
OV
UVH
UVL
R3
487k
1%
R2
13.3k
1%
R1
10k
1%
R
H
1k
1%
R3
487k
1%
R2
13.3k
1%
R1
10k
1%
R
H
1k
1%
–48V RTN
–48V INPUT
TURN-ON = 44.9V
TURN-OFF = 38.6V
HYSTERESIS = 6.3V
TURN-ON = 43.1V
TURN-OFF = 40.2V
HYSTERESIS = 2.9V
–48V RTN
–48V INPUT
4283 F10
a)
b)
LTC4283
31
Rev. A
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APPLICATIONS INFORMATION
Because of the compromises of selecting from a table of
discrete resistor values (1% resistors in 2% increments,
0.1% resistors in 1% increments), best possible OV and
UV accuracy is achieved using separate dividers for each
pin, This increases the total number of resistors from
three or four to as many as six, but maximizes accu-
racy, greatly simplifies calculations and facilitates running
changes to accommodate multiple standards or custom-
ization without any board changes.
To improve noise immunity, put the resistive divider to
the UV and OV pins close to the chip and keep traces to
RTN and VEE short. A 0.1μF capacitor from UVH or UVL
(and OV through resistor R2 as in Figure10) to VEE helps
reject supply noise.
FET Short Fault
A FET short fault will be reported if the data converter
measures a current sense voltage between SENSE+ and
SENSE− greater than 255μV while the MOSFET is turned
off. This condition sets the FET_SHORT_STATUS bit in
FAULT_STATUS register 0x03 and the FET_SHORT_
FAULT bit in FAULT register 0x04.
Power Failed Fault
The LTC4283 continuously monitors the output voltage for
the load. The differential voltage between RTNS and DRNS
represents the attenuated output voltage for the load. An
output low status will be reported if RTNS – DRNS is lower
than the external reference voltage at VOUTTH. This con-
dition sets the VOUT_LOW status bit in FAULT_STATUS
register 0x03. If this condition occurs after the internal
power good signal is latched, the POWER_FAILED fault
bit in FAULT register 0x04 will also be set. This fault does
not turn off the MOSFET. After RTNS – DRNS rises above
VOUTTH, the VOUT_LOW bit is cleared.
External Fault and Auto-Retry
PGIO4 can be configured as EXT_ FAULT# or EXT_FAULT
using PGIO_CONFIG_1 register 0x10 bits [7:6] to monitor
an external fault condition. If the input polarity is con-
figured as EXT_ FAULT#, an external fault occurs when
PGIO4 falls below its 1.28V threshold. This condition
sets the EXT_FAULT_STATUS bit in FAULT_STATUS
register 0x03 and the EXT_FAULT bit in FAULT register
0x04. This condition also turns off the MOSFET if the
EXTFLT_TURN_OFF bit in CONFIG_3 register 0x0F has
been set. When PGIO4 subsequently rises above 1.28V,
the EXT_FAULT_STATUS bit is cleared. After an auto-retry
delay, the MOSFET will be allowed to turn on again unless
the external fault auto-retry has been disabled by clearing
the EXT_FAULT_RETRY bit in CONTROL_2 register 0x0B.
The auto-retry delay for the external fault is configurable
from 512ms to 65.5s in binary scale using the COOLING_
DL bits in CONFIG_2 register 0x0E. During the delay the
DELAY_STATUS bit in REBOOT register 0xA2 is set to 1.
It will be cleared when the delay expires.
In Figure11, PGIO4 is configured as EXT_FAULT and
used to monitor MOSFET temperature. When the MOSFET
temperature rises above 115°C, the EXT_FAULT bit in
FAULT register 0x04 is set and the MOSFET is turned off.
If the EXTFLT_TURN_OFF bit in CONFIG_3 register 0x0F
has been cleared, an external fault condition at PGIO4 will
not turn off the MOSFET. Regardless of the value of the
EXTFLT_TURN_OFF bit, if the EXT_FAULT_ALERT bit in
FAULT_ALERT register 0x15 is set, the high state of the
EXT_FAULT bit in FAULT register 0x04 will generate an
alert by pulling ALERT# low.
PGIO1-4 and ADIO1-4, when configured as general pur-
pose inputs, can be used to monitor external conditions
without turning the MOSFET off or generating alerts. If
any of these pins is pulled above the 1.28V threshold,
the associated input status bit in INPUT_STATUS register
0x02 is set.
Figure11. Use PGIO4/EXT_FAULT to Turn Off
MOSFET when Drain Temperature Exceeds 115°C
C1
10nF
R
TH
*
470Ω at 25°C
4.7k at 115°C
R1
13.7k
1%
INTV
CC
LTC4283
V
EE
PGIO4
TDK/EPCOS
B59421A0115A062
*R
TH
PLACED NEAR MOSFET DRAIN
4283 F11
PGIO4_CONFIG = 01b
EXTFLT_TURN_OFF = 1
Cooling Delay
The cooling delay (configurable by the COOLING_DL bits,
0x0E [3:1]) after an overcurrent fault, FET bad or external
LTC4283
32
Rev. A
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fault, will not be interrupted by any other fault. If, before
expiration of the cooling delay, another overcurrent, FET
bad or external fault occurs, the cooling delay will restart
and extend the total cooling time. During the cooling delay
the DELAY_STATUS bit 0xA2 [1] is set to indicate the delay
timer is running. This bit resets when the delay expires. The
cooling delay can be terminated by initiating an I2C reboot
command, and is also terminated by UVLO (INTV
CC
< 3.8V).
Resetting Faults
Faults are reset with any of the following conditions. First,
writing zeros to FAULT register 0x04 will clear the associ-
ated fault bits. Second, the entire FAULT register is cleared
when the ON bit in CONTROL_1 register 0x0A goes from
high to low, or if INTVCC falls below its 3.8V undervolt-
age lockout. EN# falling from high to low also clears the
entire FAULT register. Finally, when UVL is pulled below its
1.024V reset threshold, all fault bits in the FAULT register
are cleared. When UVL is brought back above 1.024V but
below 1.833V, the UV_FAULT bit is set if UVH is below
2.048V. This can be avoided by holding UVH above
2.048V while toggling UVL to reset faults.
Fault bits with associated fault conditions that are still pres-
ent (as indicated in FAULT_STATUS register 0x03) cannot
be cleared. The FAULT register will not be cleared when
auto-retrying. When auto-retry of a specific GATE turn-
off fault is disabled using CONTROL_2 register 0x0B, the
existence of the associated fault bit keeps the MOSFET
off. After the fault bit is cleared and the associated retry
delay expires, the MOSFET is allowed to turn on again. If
auto-retry of a fault is enabled, then a high state of the
associated fault status bit in 0x03 will hold the MOSFET off
and the FAULT register is ignored. Subsequently, when the
condition causing the fault is cleared (and so is the fault
status bit in 0x03), the MOSFET is allowed to turn on again.
Alarms
Besides the fault bits and the EN#_CHANGED bit, the
LTC4283 also logs ADC alarms in ADC_ALARM_LOG
registers 0x05-0x09 when ADC results are higher than
the pre-configured MAX thresholds or lower than the
pre-configured MIN thresholds. In addition, when the tick
counter or energy meter overflows, the TICK_OVERFLOW
bit or METER_OVERFLOW bit is logged into METER_
CONTROL register 0x84. Finally, when EEPROM is writ-
ten through I2C, the EEPROM_WRITTEN bit is logged into
ADC_ALARM_LOG register 0x05. Similar to the fault bits,
these alarm bits indicate the history of corresponding
conditions and do not reflect the present status of the
conditions. Any alarm bit can only be reset by two meth-
ods: writing a zero to the alarm bit using I2C or bringing
INTVCC below its undervoltage lockout voltage.
EN# Pin
EN# has a 1.28V logic threshold relative to V
EE
with a
maximum leakage current of 1μA at 3V. It must be pulled
low and remain low during the 128ms debounce delay.
When the delay expires, the MOSFET is allowed to turn-
on. An internal clamp limits EN# to a minimum of 6V. The
pin can be safely connected to higher voltages through a
resistor that limits the current up to 5mA. It can be used
to monitor board present as shown in Figure2.
The EN# bit in SYSTEM_STATUS register 0x00 indicates
the present state of EN#, and the EN#_CHANGED bit in
ADC_ALARM_LOG_1 register 0x05 is set high whenever
EN# changes state. The EN#_CHANGED bit can be cleared
using the same methods as those for resetting faults (see
Resetting Faults) except pulling EN# from high to low.
Pulling EN# from high to low sets the EN#_CHANGED bit
while clearing the entire FAULT register 0x04.
ON Bit
The ON bit in CONTROL_1 register 0x0A allows one to
turn on (ON bit = 1) and turn off (ON bit = 0) the MOSFET
through the I2C interface. There is no debounce delay
associated with this bit, so the MOSFET is immediately
turned on after the bit is flipped from 0 to 1 while all other
turn-on conditions are met.
When the ON bit is changed from 1 to 0, the MOSFET
is turned off and all bits in FAULT register 0x04 plus the
EN#_CHANGED bit in ADC_ALARM_LOG_1 register 0x05
are cleared.
LTC4283
33
Rev. A
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Turning the LTC4283 On and Off
Many methods of on/off control are possible using the
EN#, UV/OV, PGIO3 or PGIO4 pins along with the I2C port.
EN# works well with logic inputs or floating switch con-
tacts; I
2
C control is intended for systems where the board
operates only under command of a central control proces-
sor and UV (UVH, UVL) and OV are useful with signals
reference to RTN, as are PGIO3 and PGIO4 when config-
ured as power good input and external fault, respectively.
On/off control is possible with or without I2C intervention.
Further, the LTC4283 may reside on either the remov-
able board or on the backplane. Even when operating
autonomously, the I2C port can still exercise control over
the GATE output. UV, OV and other fault conditions seize
control as needed to turn off the GATE output, regardless
of the state of EN# or the I2C port. Figure12 shows three
configurations of on/off control of the LTC4283.
Ejector Switch or Backplane Connection Sense with
Insertion Debounce Delay. A high state of EN# turns the
GATE output off. A low state of EN# turns the GATE output
on with a debounce delay of 128ms. Figure12a shows an
ejector switch or backplane connection driving EN# as an
on/off control with extra insertion debounce delay through
the RC constant. This circuit works in both backplane and
board resident applications.
Short Pin to RTN. Figure12b uses the UV divider string to
detect board insertion. This method achieves an insertion
debounce delay of 128ms and works equally well in both
backplane and board resident applications.
I2C Only Control. The circuit in Figure 12c locks out
EN# and controls the GATE output with the ON bit in
CONTROL_1 register 0x0A. To default on or off at power-
up, program the corresponding EEPROM bit (bit[7] in
EE_CONTROL_1 register 0xAA) to 1 or 0, respectively.
Any of the PGIO1–PGIO4 or ADIO1–ADIO4 pins, when
configured as general purpose input, can be used to moni-
tor a connection sense or other control signal. When the
ON bit in CONTROL_1 register 0x0A changes from 0 to
1, the LTC4283 turns on the GATE output without a delay.
The I2C port can also be used to write a fault bit in FAULT
register 0x04 to turn off the GATE output if the corre-
sponding fault has been configured to latch off the GATE
output using CONTROL_2 register 0x0B. To turn the GATE
output back on afterwards, clear the fault bit. The GATE
output will be turned on after an auto-retry delay (except
for OV). If a fault has been configured to auto-retry (in
either finite or infinite times), setting the corresponding
fault bit through I2C will not turn off the GATE output.
Configuring PGIO and ADIO Pins
The LTC4283 has four PGIO pins and four ADIO pins, all
of which can be configured as general purpose inputs/
outputs using PGIO_CONFIG_1 register 0x10 and ADIO_
CONFIG register 0x12. Additionally, PGIO1 and PGIO2 can
be configured as two sequential inverted or non-inverted
power good signals, PGIO3 can be configured as inverted
or non-inverted power good input signal (see Power Good
Monitors and PGI Fault), and PGIO4 can be configured as
Figure12. On/Off Control of the LTC4283
10nF
1M
100k
INTV
CC
LTC4283
4283 F12a
V
EE
EN#
SHORT PIN
OR SWITCH
a) Contact Debounce Delay upon Insertion for Use with
an Ejector Switch or Backplane Connection Sense
–48V
INPUT
–48V
RTN
487k
24.3k
b) Short Pin Connection Sense to RTN
LTC4283
V
EE
EN#
–48V
INPUT
–48V
RTN
UVL
UVH
4283 F12b
LTC4283
V
EE
SCL
–48V INPUT
EN#
SDAI
SDAO
I
2
C
0xAA BIT[7] = 1/0 FOR DEFAULT ON/OFF
c) I2C Only Control
4283 F12c
LTC4283
34
Rev. A
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inverted or non-inverted external fault (see External Fault
and Auto-Retry). When configured as general purpose
outputs, the output data for PGIO1–PGIO4 and ADIO1–
ADIO4 are stored in bits[7:4] in PGIO_CONFIG_2 register
0x11 and bits[3:0] in ADC_CONFIG register 0x12, respec-
tively. When selected, ADIO1–ADIO4 are also monitored
by the on-board ADC (see Data Converters).
If the PGIO2_ACLB bit in CONTROL_1 register 0x0A is
set, PGIO2 is configured as an inverted indicator of active
current limit after startup. During startup PGIO2 is held
low. After the internal power good signal is latched, if the
OC_STATUS bit in FAULT_STATUS register 0x03 is 0,
PGIO2 goes high impedance. If the OC_STATUS bit is set
to indicate that active current limit is engaged, PGIO2 is
pulled low.
Regardless of the configurations, PGIO1–PGIO4 and
ADIO1–ADIO4 all have comparators monitoring the volt-
age on these pins with a threshold of 1.28V. The results
are stored in INPUT_STATUS register 0x02.
Design Examples
Example 1: Design Procedure for Systems with Large
Input Steps
Consider a battery operated system with maximum load
power of 600W, a supply voltage range of –36V to –72V
(–36V to –72V input step is allowed), and a load capaci-
tance of CL = 500µF as shown in Figure2.
The maximum load current is calculated as
IL(MAX) =PL(MAX)
VS(MIN)
=600W
36V =16.7A
Step 1. Configure current limit and select current sense
resistor. Since a –36V to –72V input step is a valid operat-
ing condition, the current limit should be twice the maxi-
mum load current to minimize the temperature rise in the
MOSFET following a large input step:
ILIM = 2 • IL(MAX) = 33.3A
With a constant power load, when the load voltage ramps
from 36V to 72V following the input step, the load cur-
rent is halved. The LPFB (load power foldback) bit in
CONFIG_1 register 0x0D is set to 1 so that the current
limit will be maintained at approximately twice the load
current during the output ramp.
Sense resistor is selected assuming they will carry the
maximum current, or 33.3A in this example. Selection is
a matter of total cost, sense voltage (configurable from
15mV to 30mV in 1mV steps), allowable dissipation, avail-
ability of discrete resistance values, using multiple devices
to reduce the sensing errors associated with high current
density at the interface between the PCB and resistor, and
using multiple devices to ballast current flow across a
wide path, between 2 or more connectors, or between
2 or more MOSFET. These factors are iterated until an
acceptable solution is found. First, determine the num-
ber of resistors needed to handle the total sense power.
Compute the total sense power starting with the minimum
sense voltage or 15mV:
PS = VILIM(MIN) • ILIM = 15mV • 33.3A = 500mW
Second, compute the number of resistors needed to
handle this power. For example, 1206 resistors are rated
for 250mW dissipation. A conservative design is half as
much, or 125mW.
NRS =
P
S
125mW
=
500mW
125mW
=4
Thus at least four parallel 1206 resistors are needed for
each channel. Third, compute the resistance value:
RS=VILIM
I
LIM
=15mV
33.3A =450µ�
Four resistors of 1.8mΩ each would give the correct
sense resistance. Fourth, use the closest next-larger avail-
able sense resistor value and adjust the sense voltage as
needed to restore the current. In this case, a 2mΩ sense
resistor value is selected and the sense voltage is adjusted
to 16mV. Recompute the numbers:
RS=
2m�
4
=500µ�
ILIM =
16mV
500µ�=32A
PS = 16mV • 32A = 512mW
LTC4283
35
Rev. A
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The power dissipation of each resistor package is now
512mW/4 = 128mW. The current limit is now 32A, close
enough to the optimum value of 33.3A. The above process
might be iterated for several combinations of different
resistor counts, different package sizes, and even com-
binations of mixed resistor values.
When a specific design is actually built, there can be small
inaccuracies in the current sensing owing to contact and
copper trace resistances. An immediate remedy without
changing sense resistors is to readjust the sense voltage
in 1mV steps. For instance, moving sense voltage from
16mV to 17mV gives a 6.25% increase in current.
Step 2. Select resistive dividers for DRNS (drain sense),
RTNS (RTN sense) and VOUTTH (output low threshold).
DRNS and RTNS serve multiple purposes. First, they are
the inputs to a differential amplifier that measures the
attenuated load voltage for dV/dt control at startup (see
Inrush Control). In the event of an output overload or
short-circuit, the current limit foldback profile in normal
operation depends upon the differential input between
RTNS and DRNS that represents the output voltage across
the load. The current limit starts to fold back when RTNS –
DRNS drops below 0.9V and reaches the minimum when
RTNS – DRNS drops to zero (see Current Limit Foldback).
Additionally, in current limit the DRNS input monitors the
MOSFET’s VDS and uses this information to scale the TMR
pull-up current accordingly. When not in current limit,
DRNS monitors VDS and serves as one input to a mul-
tiplier which generates the TMR pull-up current. Finally,
RTNS and DRNS also serve as inputs to the ADCs so that
the input voltage and MOSFET drain voltage can be read
remotely. RTNS and DRNS have a maximum useable input
voltage of 2.8V, so resistive dividers are required.
To select resistive dividers for RTNS and DRNS, compute
the divider ratio r using the maximum supply voltage:
r=
V
S(MAX)
1.8V =72V
1.8V =40
where 1.8V is the operating point of DRNS at which the
TMR pull-up current is tested and specified. The result-
ing ADC measurement full scale for input (at RTNS) and
MOSFET drain (at DRNS) voltages is
VFS(MEAS) = r • 2.048V = 40 • 2.048V = 81.92V
which gives a LSB size of 20mV in 12-bit mode. If it was
desired to measure gross overvoltage inputs, such as
100V, then a decision would have to be made to sacrifice
control dynamic range in favor of ADC measurement range
by using a higher divider ratio. An alternative approach
is to use ADIN1–ADIN4 inputs for ADC measurements,
leaving RTNS and DRNS for control purpose only.
With 72V load voltage corresponding to RTNS – DRNS =
1.8V, in normal operation the current limit starts to fold
back when load voltage drops below 36V (or RTNS – DRNS
< 0.9V) in overload conditions. This means there is no fold-
back in normal operating input range between −36V and
−72V, allowing the MOSFET to pass the full load current.
Standard values of 200k and 5.11k give a divider ratio of
40.1. DRNS and RTNS must use identical dividers. While
the exact ratio is not important, matching between them
is very important. For this reason, 1% resistor tolerance
is the minimum requirement; 0.25% or 0.1% is better.
VOUTTH pin sets the threshold of RTNS − DRNS that
indicates the low limit of the output voltage to reset
power good signals if the PWRGD_RESET_CNTRL bit in
CONTROL_1 register 0x0A is set to 1. The low limit is
set below the minimum input voltage, so 32V is selected
in this example. With a divider ratio of 40 on DRNS and
RTNS, the VOUTTH threshold is 32V/40 = 0.8V. This
voltage may be realized with a resistive divider between
INTVCC (5V) and VEE, or for a better tolerance, between
VREF (1.024V) and VEE. For the latter case, a divider of
5.62k and 20k as shown in Figure2a results in 0.8V at
VOUTTH. The source current of VREF is 40μA, well within
its specified limit of 200μA.
Step 3. Design the overcurrent timer behavior. The TMR
pin can be configured into a SOA timer or a single capaci-
tor timer. The SOA timer requires an RC network repre-
senting the MOSFET thermal model to be connected to
TMR (see SOA Timer). At least two resistors and two
capacitors are needed for minimum accuracy of the ther-
mal behavior. More RC elements are desired for better
accuracy. Thus the cost and board area are larger than
the single-capacitor timer. The benefit of the SOA timer is
that the TMR voltage represents the temperature rise of
LTC4283
36
Rev. A
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the MOSFET and its trip threshold represents the maxi-
mum allowable peak temperature of the MOSFET. With the
SOA timer, selection of a MOSFET is much simpler: it just
needs to meet the worst-case operation requirements. In
fault conditions such as output short, the SOA timer auto-
matically protects the MOSFET by turning it off once the
maximum allowable peak temperature is reached (TMR
tripped). With the single capacitor timer, the minimum
capacitor must first be selected to keep the MOSFET on
during worst-case operating conditions, then the MOSFET
must be selected to withstand the worst-case SOA condi-
tions during normal operating and fault conditions. The
cost of a MOSFET selected based on the single capacitor
timer may be substantially higher than that using the SOA
timer. It is recommended to use the SOA timer for applica-
tions with large input steps. In this example the TMR pin
is configured as an SOA timer by setting the THERM_TMR
bit in CONTROL_1 register 0x0A to 1, which disables the
internal TMR pull-down current.
With the SOA timer protecting the MOSFET, current limit
foldback may be disabled after startup. This can be done
by setting the FB_DIS bit in CONTROL_1 register 0x0A
to 1. The foldback during startup is not affected by the
FB_DIS bit.
Step 4. Select the MOSFET. With the SOA timer, two oper-
ating requirements must be met: (1) the R
DS(ON)
must
be low enough to carry maximum load current; (2) the
SOA must be sufficient to stand the worst-case operating
condition. The selection for the RDS(ON) requirement is a
combination of total MOSFET cost and maximum desired
dissipation per package. For the maximum current of 32A,
two 5mΩ devices result in 1.28W per device. With air
flow 1.28W dissipation is acceptable and a third device is
unnecessary. The chosen MOSFETs are two PSMN4R8-
100BSE devices (each RDS(ON) < 4.8mΩ). The compo-
nents selected so far are shown in Figure1 and Figure2.
The worst-case MOSFET drain voltage with maximum
allowable load is
VD(ON),MAX =
I
LIM
•R
DS(ON),MAX
2=
32A • 4.8m�
2
=76.8mV
The DRAIN threshold VD,FET(TH) must be set higher than
this number with sufficient margin to account for com-
ponent inaccuracies and temperature coefficient. When
the MOSFET drain voltage is higher than this threshold,
two things will happen. First, the FET_BAD_STATUS bit
in FAULT_STATUS register 0x03 will be set and the FET
bad timer will be started. When the timer expires the FET_
BAD_FAULT bit in FAULT register 0x04 will be set and the
MOSFET will be turned off if the FET_BAD_TURN_OFF bit
in CONTROL_1 register 0x0A has been set. Second, the
TMR pull-up current will be enabled even if current limit
is not engaged. This current is produced by an internal
multiplier monitoring the power dissipation in the chan-
nel. VD,FET(TH) has four discrete settings: 72mV, 102mV,
143mV and 203mV. In this example 143mV is selected by
setting the VDTH bits in CONFIG_2 register 0x0E to 10b.
A large input step is usually the worst-case operating
condition for SOA. To verify the temperature rise of the
MOSFET, it is necessary to run simulations in this condi-
tion. With the above selected components and configura-
tions, the temperature rise of the MOSFET when riding
through a –36V to –72V input step with full load (600W
and 500μF) is 46°C (simulated with the LTspice SOAtherm
model). At worst-case operating temperature of 85°C, this
translates to 131°C in the MOSFET, which has substantial
margin from the manufacturer specified maximum tem-
perature of 175°C.
Step 5. Design the startup current and FET bad timer. First
the startup mode is selected. As pointed out in Inrush
Control, the startup current (or inrush current) can be
controlled either by a RAMP capacitor in dV/dt mode or
by startup foldback in current limit mode. The current limit
mode is selected in this example, which is a better choice
to work with the SOA timer that has been selected in Step
3. This is because if the dV/dt mode was selected, the
TMR pull-up current would be disabled in normal startup
conditions and the SOA timer would not be able to track
the temperature rise of the MOSFET during startup.
Choice of the charging current is a trade-off between
maximum charging time, maximum inrush current drawn
from the backplane, and more importantly, peak power
dissipated in the MOSFET. When charging a capacitor
from a voltage source, the charging process dissipates
LTC4283
37
Rev. A
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an energy in the pass MOSFET equal to the energy stored
in the capacitor. The maximum input voltage results in the
maximum energy:
EMAX =CL• VS(MAX)
2
=500µF •(72V)
2
=2.59J
This indirectly sets a limit on how quickly the load capaci-
tor can be charged, since the average power dissipation
in the MOSFET is energy/time. In general, the faster the
charge rate, the higher the peak temperature. For this
reason, it is a good idea to lower the inrush current to no
more than necessary to achieve the required startup time.
Therefore, the smallest foldback ratio, 10%, is selected
by setting the FB bits in CONFIG_1 register 0x0D to 11b,
and the startup inrush current is
IINRUSH = ILIM • aFB = 32A • 10% = 3.2A
The maximum startup charging time of the load capacitor
is then computed:
tSTARTUP(MAX) =CL• VS(MAX)
IINRUSH
=
500µF • 72V
3.2A
=11.25ms
This charging time is short enough for most applications.
Simulation shows the temperature rise of the MOSFET
in this worst-case startup condition is 40°C, lower than
that for the –36V to –72V input step calculated in Step 4.
During startup the FET_BAD_STATUS bit is high and
the FET bad timer is running and serves as a watchdog
over the controlled startup. The load capacitor must be
fully charged before this timer expires, or the GATE out-
puts will be turned off if the FET_BAD_TURN_OFF bit in
CONTROL_1 register 0x0A has been set. There is no con-
cern with this example since the maximum charging time
of 11.25ms is much shorter than the minimum FET bad
timer delay (256ms).
Step 6. Select the RC network for the SOA timer follow-
ing the procedure as shown in the SOA Timer section. It
was found that two thermal capacitors and two thermal
resistors provide fairly good curve fitting for the ther-
mal impedance plot of the chosen MOSFET, PSMN4R8-
100BSE in the range between 100μs and 100ms (wide
enough for typical operating conditions of this applica-
tion): Cθ1 = 0.002J/°C, Rθ1 = 0.05°C/W, Cθ2 = 0.03J/°C,
Rθ2 = 0.35°C/W. The conversion constant is given by
k=
V
DS,MAX
•I
D,MAX
ITMR(UP),MAX
•
V
TMR(TH)
ΔTMAX
=
72V • 32A
202µA •2.048V
65°C=3.6 •105V2
°C
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
where ∆TMAX is the maximum allowable temperature rise
and chosen to be 65°C, which corresponds to a maximum
MOSFET temperature of 150°C at an operating tempera-
ture of 85°C, with 25°C margin from the manufacturer
specified maximum temperature of 175°C. The thermal
R and C values are then converted to electric R and C
values as shown in SOA Timer. After the electrical R and C
values are computed, choose the closest next-larger avail-
able resistor value and the closest next-smaller available
capacitor value. Then the resistance corresponding to the
thermal resistance of the board is added to the termination
resistance (the largest one). If the computed resistance
for the board thermal resistance is over 1MΩ, choose
1MΩ. Assuming a 5°C/W board thermal resistance in this
application, it is converted to 5 • 3.6 • 105=1.8MΩ. So
1MΩ is selected. This avoids accuracy degradation due to
board leakage currents. The resulting electrical capacitors
and resistors are CE1 = 4.7nF, RE1 = 18.2k, CE2 = 68nF,
RE2 = 1.13M, as shown in Figure1 and Figure2a.
After the SOA timer is configured, rerun simulations to
ensure TMR does not reach its 2.048V trip point in all
operating conditions including startup and input step.
When it trips in fault conditions such as output over-
load or short-circuit, verify the peak temperature of the
MOSFET matches the proposed maximum temperature.
Iterations of the above procedure may be needed before
the RC network is finalized.
Step 7. Select resistive dividers for UV/OV inputs.
Select resistive dividers so that UV rising threshold is
set just below the minimum input voltage and OV falling
threshold is set just above the maximum input voltage. A
single, 4-resistor divider as shown in Figure2a gives UV
shutdown at 32.4V, UV release at 35.3V, OV shutdown
LTC4283
38
Rev. A
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at 74.5V and OV release at 73.2V. This configured range
is just wide enough to cover the full input voltage range
between 36V to 72V. A 100nF bypass capacitor is selected
to filter out noises at UVL/UVH and OV.
The current ADC has a full scale of 32.768mV. A 0.5mΩ
of sense resistor, gives a full-scale current of 65.5A, with
a 16mA LSB size in 12-bit mode.
Example 2: Design Procedure for Systems with
Regulated Inputs
The second example is a line operated –48V system with
supply tolerance of 10% (–43.2V to –52.8V) and maxi-
mum load power of 800W as shown in Figure13. The load
capacitance is specified as CL = 1000µF.
The maximum load current is calculated as
IL(MAX) =
P
L(MAX)
VS(MIN)
=800W
43.2V =18.5A
Step 1. Configure current limit and select current sense
resistors. Since the input voltage is well regulated, there
is no need to set the current limit to twice the load current
to minimize temperature rise upon a large input step as
in Example 1. The current limit in this example just needs
to cover the maximum load current, with enough margin
to account for device tolerances. Set current limit to 20A,
which provides sufficient margin for the maximum load
current of 18.5A:
ILIM = 20A
Compute the sense power starting with the minimum
sense voltage or 15mV:
PS = VILIM(MIN) • ILIM = 15mV • 20A = 300mW
With 250mW rated 1206 resistors, use 125mW for con-
servative design and the minimum number of sense resis-
tors to handle the power is
NRS =
P
S
125mW
=
300mW
125mW
=2.4
Thus at least 3 parallel 1206 resistors are needed. The
SENSE resistance is
RS=VILIM(MIN)
I
LIM
=15mV
20A =0.75m�
C
V
CC
1µF
1mΩ
R
S1
R
IN
4×1k IN SERIES
0.25W EACH
C
IN
0.1µF
4
4
4
M1
PSMN4R8-100BSE ×2
4283 F13
R
G1A
10Ω
R
G1
470
R
D
100k
R
RT
280k
1%
R
RB
10k
1%
R
DT
280k
1%
C
G1
100nF
C
L
1000µF
C
T
2.2nF
C
R
330nF
R
DB
10k
1%
R5
26.7k
1%
R6
10.2k
1%
R2
200k
1%
R1
10k
1%
C
UV
10nF
R4
383k
1%
R3
10k
1%
COV
10nF
RH
750Ω
1%
–48V RTN
UVH
UVL
OV
–48V INPUT
ADIN
TMR
V
EE
INTV
CC
SENSE+
GATE
DRAIN
V
Z
V
IN
RTNS
SCL
SDAI
SDAO
ALERT#
ADIO
PGIO
LTC4283
V
EE
DRNS
ILIM = 0101
FB = 11
FB_DIS = 0
LPFB = 0
EN#
UV = 38.6V
UV RELEASE AT 40.2V
OV = 55.3V
OV RELEASE AT 54.3V
V
OUT
LOW = 40V
V
EE
V
EE
V
EE
V
EE
V
EE
V
EE
RAMP
SENSE–
LINE OPERATED
(INPUT STEPS LIMITED TO <4V)
V
OUTTH
–48V RTN
(SHORT PIN)
DVDT = 1
THERM-CBTMR = 0
3mΩ ×3
Figure13. –48V/800W Hot Swap Controller with dV/dt Inrush Control
LTC4283
39
Rev. A
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Three resistors of 2.25mΩ each would give the correct
sense resistance. The closest next-larger available sense
resistor value is 3mΩ:
RS=3m�
3
=1m�
Adjust the sense voltage to 20mV to restore the current by
setting the ILIM bits in CONFIG_1 register 0X0D to 0101b:
ILIM =
V
ILIM
R
S
=
20mV
1m�=20A
Recompute the sense power:
PS =20mV • 20A = 400mW
The power dissipation of each resistor package is now
400mW/3 = 133mW, still an acceptable value for 1206
resistors. Sense voltage may need to be readjusted to
account for current sensing inaccuracies such as contact
and copper trace resistances, as explained in Example 1,
Step 1.
Step 2. Select resistive dividers for DRNS (drain sense),
RTNS (RTN sense) and VOUTTH (output low reference).
See Example 1, Step 2 for detailed design considerations.
First compute the divider ratio r for RTNS and DRNS:
r=VS(MAX)
1.8V
=52.8V
1.8V
=29.3
Standard values of 280kΩ and 10kΩ give a divider ratio of
29. The ADC measurement full-scale for input (at RTNS)
and MOSFET drain (at DRNS) voltages is
VFS(MEAS) = r • 2.048V = 29 • 2.048V = 59.4V
which gives a LSB size of 14.5mV in 12-bit mode.
With VLOAD = 29 • 1.8V = 52.2V corresponding to
RTNS–DRNS=1.8V, the current limit starts to fold back
when VLOAD drops below 26.1V in overload conditions.
There is no foldback at normal input between −43.2V
and −52.8V, allowing the MOSFETs to pass the full load
current.
If 40V is chosen as the output voltage threshold to reset
power good signals, with a divider ratio of 29 on DRNS
and RTNS, the VOUTTH threshold is 40V/29 = 1.379V. This
voltage can be obtained with a resistive divider between
INTV
CC
(5V) and V
EE
. The divider ratio is 5V/1.379V =
3.63. A divider of 26.7k and 10.2k as shown Figure13
gives a close enough ratio of 3.62.
Step 3. Design the TMR behavior. See Example 1, Step 3
for general design considerations. Since there is no con-
cern about a large input step after startup, a very short
timer delay is needed for MOSFET turn-off upon a fault
such as output short-circuit. Therefore, the TMR function
is essentially a filtered circuit breaker and a single timer
capacitor on TMR works just fine for this purpose.
It has been found that 20μs of circuit breaker filtering is
sufficient to reject noise encountered in most systems.
The TMR pull-up current is 202μA at maximum overload,
with a voltage threshold of 2.048V. Compute the timer
capacitance, Ct, for 20μs filter delay:
Ct=ITMR(UP),MAX • tFILTER
VTMR(TH)
=202µA •20µs
2.048V =2nF
Select the closest next-larger available capacitance:
Ct = 2.2nF. With single capacitor on TMR, the THERM_
TMR bit in CONTROL_1 register 0x0A must be cleared to
enable the internal 2μA pull down current. Additionally, the
FB_DIS bit in CONTROL_1 register 0x0A should be cleared
to keep foldback enabled after startup to protect MOSFET
from damage upon a low impedance short-circuit.
Step 4. Design the startup current and FET bad timer.
Since in Step 3 the TMR function is designed as a short
circuit-breaker delay, it is desired to use the dV/dt startup
mode so that a small trickle current charges the load
capacitance without triggering current limit. (see dis-
cussions in Example 1, Step 5). The design procedure
involves selecting a RAMP capacitor to set the dV/dt rate
for desired charging current, selecting a proper startup
current limit and checking the temperature rise of the
MOSFET under a resistive short condition.
Choice of the charging current is a trade-off between
maximum charging time and peak temperature of the
MOSFET. As discussed in Example 1, Step 5, the charging
current should be set to a low level that is just necessary
to achieve the required charging time. Suppose an upper
limit of 300ms charging time is desired for a 1000μF load
LTC4283
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capacitor at the maximum input of 52.8V. The necessary
charging current is
I
INRUSH(MIN) =
C
L
• V
S(MAX)
tSTARTUP(MAX)
=1000µF • 52.8V
300ms =176mA
The RAMP capacitor is selected according to
CR=IRAMP •r • CL
I
INRUSH
=2.5µA • 29 • 1000µF
176mA =412nF
An acceptable value is 330nF, resulting in a nominal
inrush of
IINRUSH=IRAMP •r • CL
C
R
=2.5µA • 29 • 1000µF
330nF =220mA
and a maximum startup time of
tSTARTUP(MAX) =CL• VS(MAX)
I
INRUSH
=1000µF • 52.8V
220mA =240ms
which is below the upper limit of 300ms.
The FET bad timer must be set longer than the startup time
for the load capacitor to be fully charged, so it is config-
ured to 512ms by setting the FTBD_DL bits in CONFIG_2
register 0x0E to 01b to account for all tolerances.
The startup current limit should also be configured to a
low level to minimize the temperature rise of the MOSFET
under a resistive short condition, but must be higher than
the dV/dt inrush current to avoid current limit being trig-
gered in normal startup conditions. With a foldback ratio
of 10%, the startup current limit is
ILIM(STARTUP) = 20A • 10% = 2A
which is well above the inrush current of 220mA. Select
the 10% foldback ratio by setting the FB bits in CONFIG_1
register 0x0D to 11b.
Since the inrush current is very low, SOA requirement in
normal startup is not critical. However, the MOSFET must
be able to withstand the resistive short condition during
startup as discussed below.
Step 5. Select a sufficient MOSFET to carry the maximum
load current and withstand the startup stress. The deci-
sion is a combination of MOSFET cost, maximum desired
dissipation, and startup stress. For the maximum cur-
rent of 20A, two PSMN4R8-100BSE (RDS(ON) < 4.8mΩ)
devices result in 0.48W per package, an easily manage-
able dissipation.
With full load the worst-case drain voltage of the MOSFET
is 20A • 2.4mΩ = 48mV. Select 102mV as the DRAIN
threshold for starting FET bad timer and enabling TMR
pull-up current, with sufficient margin to account for inac-
curacies. Set the VDTH bits in CONFIG_2 register 0x0E to
01b for this configuration. See detailed design consider-
ations in Example 1, Step 4.
Step 6. Run simulations to verify temperature rises of
the MOSFET under all operating and fault conditions are
within the acceptable range. This is a necessary step when
using a single capacitor circuit breaker timer as selected
in Step 3.
First, check temperature rise in the MOSFET during
startup. The conditions include normal dV/dt startup to
fully charge the 1000μF load capacitor and a fault condi-
tion in which the MOSFET charges both the load capacitor
and a parallel fault resistor, both at the maximum input
voltage. If temperature rise is too high in normal startup
condition, the inrush current may be reduced by select-
ing a larger RAMP capacitor. If the inrush current must
be reduced less than the value required to achieve the
desired maximum charging time, a larger MOSFET has
to be selected. For the fault condition, the worst-case is
found iteratively by changing the fault resistor value while
monitoring the temperature rise. As a starting point, use
a resistor of V
S(MAX)
/(4 • I
LIM(STARTUP)
) or 52.8/(4 • 2)
= 6.6Ω for this example. If the temperature rise is too
high, startup current limit may be reduced by selecting a
steeper foldback ratio. If the startup current limit must be
reduced to less than or close to the dV/dt inrush required
for the maximum charging time or the foldback ratio
must be reduced below 10%, a larger MOSFET must be
selected. Using the conditions of this example, it is found
the worst-case temperature rise in the MOSFET either in
LTC4283
41
Rev. A
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normal startup condition or with different fault resistors
is lower than 64°C, an acceptable figure. This verifies the
selected MOSFET, PSMN4R8-100BSE, has enough SOA
to handle the worst-case dissipation during startup.
Second, check temperature rises in the MOSFET after
startup when TMR times out under different overload con-
ditions. The worst-case could be shorting the output to
half of the available output voltage so there is no foldback
while the VDS of the MOSFET is still high. If the worst-
case temperature rise is too high, a larger MOSFET must
be selected. In this example, the worst-case temperature
rise is an insignificant value of about 16°C thanks to the
short circuit-breaker delay of 20µs.
Step 7. Select resistive dividers for UV/OV inputs
Although it is possible to use a single, four-resistor (or
three-resistor if UVH and UVL connected together) divider
as shown in Example 1, Step 7, two independent dividers
with 2 (OV) or 2 to 3 (UV) resistors in each divider make it
easier to make non-interactive changes at a later time. The
two dividers as shown in Figure13 gives UV shutdown at
38.6V, UV release at 40.2V, OV shutdown at 55.3V and
OV release at 54.3V, which covers the full input voltage
range of this example. 10nF capacitors filter out noises
on UVL and OV.
With an ADC full scale of 32.768mV, the 1mΩ sense resis-
tance gives a full-scale current of 32.768A and a LSB size
of 8mA in 12-bit mode.
Layout Considerations
To achieve accurate current sensing, Kelvin connections
are required. The minimum trace width for 1oz copper
foil is 0.02" per amp to make sure the trace stays at a
reasonable temperature. Using 0.03" per amp or wider
is recommended. Note that 1oz copper exhibits a sheet
resistance of about 530μΩ/square. Use 2oz or heavier
copper for high current applications.
The VEE pin of the LTC4283 should be connected to a sep-
arate plane from the main –48V input plane. To improve
noise immunity, as shown in Figure14, the VEE connec-
tions of all capacitors, resistive dividers, opto-isolators
and I2C common must be made directly to the local VEE
plane, not the –48V input plane.
The mechanical stress of soldering a part to a board and
the heat of an IR reflow or convection soldering oven
can cause the ADC full-scale error (FSE) and the current
limit voltage (V
ILIM
) to shift. Refer to Typical Performance
Characteristics for ADC FSE and VILIM shifts of 300 units
of LTC4283 after three cycles of the lead-free IR reflow
process.
Figure14. Layout Example of VEE Plane, –48V
Input Plane and Sense Resistor Connection
G
S
–48V INPUT PLANE
VEE PLANE
RS
LTC4283 VEE PIN
ALL CAPACITORS
ALL RESISTIVE DIVIDERS
ALL OPTO-ISOLATORS
I2C COMMON
TIE VEE TO –48V INPUT HERE
4283 F14
TO SENSE–
PIN
TO SENSE+
PIN
D
MOSFET
Reboot on I2C Command
The LTC4283 features a reboot command bit, RBT_EN
in REBOOT register 0xA2. Setting this bit will cause the
LTC4283 to shut down and reboot after a delay. The reboot
delay is programmable from 512ms to 65.5s using the
three RBT_DL bits in the REBOOT register. A reboot delay
allows load capacitance to fully discharge. During the
reboot delay the DELAY_STATUS bit in the REBOOT reg-
ister is set to 1. It will be cleared when the delay expires.
The reboot will also copy the contents of the EEPROM to
volatile registers in the same way as after initial power-up.
On systems where the hot swap controller supplies power
LTC4283
42
Rev. A
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to the I2C master, this allows the master to issue a com-
mand that power cycles the entire board, including itself.
Once set, the RBT_EN bit remains 1 after reboot is com-
pleted. Clear it before issuing the next reboot command.
Data Converters
The LTC4283 incorporates a pair of Sigma-Delta A/D
converters (ADCs) that are configurable from 8-bit at
1kHz conversion rate to 16-bit at 1Hz conversion rate
in five settings using the ADC bits in PGIO_CONFIG_2
register 0x11 (see Table12). In the default continuous
mode, the first ADC (ADC1) continuously monitors the
input current through a sense resistor between SENSE+
and SENSE−. The second ADC (ADC2) is synchronized to
ADC1 and monitors VPWR for power multiplication plus
one of the 14 auxiliary inputs. VPWR is selectable between
the attenuated input voltage at RTNS and the attenuated
MOSFET drain voltage at DRNS using the VPWR_SELECT
bit in CONFIG_3 register 0x0F. The auxiliary inputs include
10 single-ended signals and 4 differential signals and
are selectable using ADC_SELECT registers 0x13-0x14
(see Table14). If multiple auxiliary inputs are selected,
ADC2 will rotate between them in the continuous mode
as illustrated in Figure 15. The AUX_ADC_CH bits in
ADC_STATUS register 0x01 are refreshed at the end of
each conversion to indicate the auxiliary input that com-
pleted the latest measurement (see Table5). If all bits
in ADC_SELECT registers 0x13–0x14 are cleared while
the ADCs are running in continuous mode, ADC1 and
ADC2 continue to measure SENSE+ − SENSE− and VPWR
(RTNS/DRNS), respectively. The auxiliary measurements
of ADC2 are disabled and the data in 0x41–0x79 from
the previous measurement are preserved except 0x4A
(ADIN1), which is overwritten by a small number.
The full-scale voltage of any single-ended input is 2.048V.
For each differential input, one terminal must be at the
same potential of VEE. Normally the negative terminal is at
VEE and the full-scale is 32.768mV. If the positive terminal
is at VEE, the full scale becomes 33.301mV. When using
ADIN1–ADIN4 and ADIO1–ADIO4 as differential inputs,
ADIN1, ADIN3, ADIO1 and ADIO3 must be the negative
terminals, and ADIN2, ADIN4, ADIO2, ADIO4 must be
positive terminals, respectively. Note that for each reso-
lution setting, the resolution of differential auxiliary inputs
of ADC2 is one bit less than that of the SENSE+ − SENSE−
input of ADC1 or the single-ended inputs.
After each conversion of the two synchronized ADCs, the
measured current sense voltage (SENSE+ − SENSE−) is
multiplied by the measured VPWR (RTNS or DRNS) volt-
age to calculate input power or MOSFET power, configu-
rable using the VPWR_SELECT bit in CONFIG_3 register
0x0F. All measured results and calculated power are stored
to corresponding data registers (see Table3). They are
also compared to the minimum and maximum values that
are stored in the minimum and maximum data registers. If
the measurement is a new minimum or maximum value,
then the corresponding minimum or maximum data reg-
isters are updated. Note that all ADC data registers from
0x41 to 0x79 have a length of two bytes or 16 bits, and
the data for all resolutions are left justified.
The ADC measurements are compared to the 8-bit mini-
mum and maximum alarm thresholds that are config
-
ured using registers 0x1B through 0x40 and will set the
ROTATION SEQUENCE OF AUXILIARY INPUTS SELECTED BY ADC_SELECT REGISTERS 0x13-0x14
TIME
ADIN1-4 ADIO1-4 DRNS DRAIN RESERVED RESERVED ADIN2 – ADIN1 ADIN4 – ADIN3 ADIO2 – ADIO1 ADIO4 – ADIO3
• • • ADC1 ADC1 • • • ADC1 ADC1 • • •
SENSE+ – SENSE−SENSE+ – SENSE−SENSE+ – SENSE−SENSE+ – SENSE−
• • • ADC2 ADC2 • • • ADC2 ADC2 • • •
AUX1 VPWR AUX2 VPWR AUXN VPWR AUX1 VPWR
Figure15. LTC4283 ADC Measurement Pattern in Continuous Mode
LTC4283
43
Rev. A
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corresponding ADC alarm bits in ADC_ALARM_LOG
registers 0x05 to 0x09. If the associated ADC alert bit
in ADC_ALERT registers 0x16 to 0x1A is set, an ADC
alarm bit will generate an alert by pulling ALERT# low
and set the ALERT_GENERATED bit in METER_CONTROL
register 0x84.
At the end of each ADC measurement, calculated power is
added to an accumulator that meters energy. The 6-byte
energy meter 0x7A to 0x7F is capable of accumulating
12 days of power at full scale in 12-bit ADC mode, which
is several months at a nominal power level. When the
meter overflows the METER_OVERFLOW bit in METER_
CONTROL register 0x84 is set to 1 and an optional alert
is generated if the METER_OVERFLOW_ALERT bit in
CONFIG_3 register 0x0F is preset to 1. To measure cou-
lombs, the energy meter may be configured to accumulate
current rather than power by setting the INTEGRATE_I bit
in CONFIG_3 register 0x0 F.
The tick counter 0x80 to 0x83 keeps track of how many
times power has been added into the energy meter. Dividing
the energy by the tick count will yield the average power
over the accumulation interval. The 4-byte tick counter
will keep count for 9 years in the 12-bit mode before
overflowing. When it overflows the TICK_OVERFLOW bit
in METER_CONTROL register 0x84 is set to 1 and an
optional alert is generated if the TICK_OVERFLOW_ALERT
bit in CONFIG_3 register 0x0F is preset to 1. Multiplying
the value in the counter by the ADC conversion time yields
the time that the energy meter has been accumulating.
Both the energy accumulator and the tick counter are writ-
able, allowing them to be preloaded with a given energy
and/or time before overflow so that the LTC4283 will gen
-
erate an overflow alert after either a specified amount of
energy has been delivered or time has passed.
The following formulas are used to convert the values
in the ADC data registers into physical units. Since the
data are left justified, the same equations apply to all
resolutions.
To calculate single-ended voltages measured by ADC2:
V=
CODE(word) • 2.048V
2
16
To calculate currents in amperes measured by ADC1 and
differential mode ADC2:
I=
CODE(word) • 32.768mV
216 •R
SENSE
To calculate power in watts:
P=
CODE(word)• 32.768mV • 2.048V
216 •R
SENSE
To calculate energy in joules:
E=CODE(48 Bits) • 32.768mV • 2.048V • tCONV
224 •R
SENSE
where tCONV is the ADC conversion time depending upon
the configured resolution (see Table12).
To calculate coulombs:
Q=CODE(48 Bits) • 32.768mV • tCONV
216 •R
SENSE
To calculate average power over the energy accumulation
period:
PAVG =E
t
CONV
• CODE(COUNTER)
To calculate average current:
IAVG =
Q
t
CONV
• CODE(COUNTER)
To calculate voltage alarm thresholds:
VALARM =
CODE(byte) • 2.048 V
256
To calculate current Alarm threshold in amperes:
IALARM =CODE(byte) • 32.768mV
256 •R
SENSE
To calculate power Alarm threshold in watts:
PALARM =
CODE(byte)• 32.768mV • 2.048V
256 •R
SENSE
LTC4283
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To synchronize multiple bytes of data from the tick coun-
ter and energy meter, use the Read Page protocol (see
Data Synchronization and Arbitration). An I
2
C read latches
the tick counter and energy meter data in buffers while the
tick counter and energy meter still increment. Alternatively
one can set the METER_HALT bit in METER_CONTROL
register 0x84 before reading the data. This will halt the
ticker counter and energy meter. Clear the METER_HALT
bit afterwards to reactivate incrementing.
The LTC4283 ADCs also feature a snapshot mode that
allows a one time measurement of a single data packet:
SENSE+ − SENSE−, VPWR (RTNS or DRNS), and an aux-
iliary input selected by the SNAPSHOT_SEL bits in ADC_
SNAPSHOT register 0x85. To enable the snapshot mode,
set the ADC_HALT bit in the ADC_SNAPSHOT register
to 1 and write the SNAPSHOT_SEL bits for the desired
auxiliary input in one I2C command. At the falling edge of
SCL after bit 0 is received, the ADCs start a single conver-
sion of the selected data packet and the ADC_IDLE bit in
ADC_STATUS register 0x01 is cleared to indicate the data
is not ready. After completing the conversion, the ADCs
are halted, the ADC_IDLE bit is set to indicate the data is
ready, and the AUX_ADC_CH bits in the ADC_STATUS
register are set to indicate the auxiliary input that is just
measured. To make another snapshot measurement, write
the ADC_SNAPSHOT register again. To go back to the
continuous mode, clear the ADC_HALT bit.
The 14 auxiliary inputs with the LTC4283 ADCs allow for
extensive monitoring of board level signals. Figure16
shows an example of using ADIO1–ADIO4 as single-ended
inputs to monitor individual input voltages of a dual-feed
system. The 1.024V VREF is exactly half of the ADC ref-
erence voltage and level shifts the ADIO1–ADIO4 inputs
within measurable range of the ADC. In Figure16 one
input is –36V (VINPUT1) and the other is –72V (VINPUT2).
All node voltages are noted in the circuit. The voltage
values in parenthesis are referred to system ground RTN
and the others are referred to V
EE
. With the ADIO1–ADIO4
voltages measured by the ADC and R1/R2 = R3/R4 = R5/
R6 = R7/R8, the input voltages are
VINPUT1 =(VADIO3 – VADIO1)
R1+R2
R2
VINPUT2 =(VADIO4 – VADIO2 )
R1+R2
R2
The forward voltage drop of the conducting diode D2 is
VD2 =VREF
R7
R8
– VADIO4
R7
+
R8
R8
VREF is ratiometric to the ADC full-scale voltage and can
be measured by ADC with one of the ADIN1–ADIN4 pins
to calibrate out errors.
The circuit in Figure 16 also monitors fuses on both
the RTN and −48V sides. If any one of the four fuses
is open, it can be detected by the ADC measurement of
the corresponding ADIO input: VADIO1 = VREF indicates
fuse F3 is open; VADIO2 = VREF indicates fuse F4 is open;
V
ADIO3
=V
REF
indicates fuse F1 is open; V
ADIO4
= V
REF
indicates fuse F2 is open. Additionally, chassis ground
is monitored with the ADIN1 pin as shown in Figure16.
Figure17 shows an example that monitors individual feed
currents using two differential input pairs. Note that the
ADIN2 – ADIN1 and ADIN4 – ADIN3 inputs have a full
scale of 33.301mV (positive terminals are at VEE), while
the SENSE+ − SENSE− input has a normal full scale of
32.768mV (negative terminals are at VEE).
Figure16. Feed Voltage and Open Fuse Monitoring
F3
D3
F4
F1
F2
D4
D1
D2
R1
1M
0.1%
R3
1M
0.1%
R5
1M
0.1%
R7
1M
0.1%
R2
10k
0.1%
R4
10k
0.1%
R6
10k
0.1%
R8
10k
0.1%
RTN_A
–48V_B
(–72V)
V
EE
ADIO1
LTC4283
4283 F16
RTN_B
–48V_A
(–36V)
ADIO2
ADIO3
ADIO4
ADIN1
VREF
F1 OPEN: V
ADIO3
= V
REF
F2 OPEN: V
ADIO4
= V
REF
F3 OPEN: V
ADIO1
= V
REF
F4 OPEN: V
ADIO2
= V
REF
(–71.3V)
0
71.3V
71.3V
35.3V
–0.7V
1.007V
1.363V
1.720V
1.720V
1.024V
R9
1M
0.1%
CHASSIS
R10
10k
0.1%
LTC4283
45
Rev. A
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The output voltage across the load may be calculated
from the measured RTNS and DRNS voltages. If a direct
measurement of the load voltage is desired, the circuit as
shown in Figure18 may be used.
EEPROM
The LTC4283 has an onboard EEPROM to allow nonvola-
tile configuration and fault logging. The EEPROM registers
are denoted by EE_ in the first column of register Table3.
The EEPROM registers may be read and written like any
other register except that the EEPROM takes about 2.2ms
to write data.
While the EEPROM is writing, the EEPROM_BUSY bit in
the SYSTEM_STATUS register is set. During this time,
the I2C interface will NACK attempted writes to EEPROM
registers. EEPROM registers will return 0xFF if read while
the EEPROM is busy. The FAULT_LOG_CONTROL reg-
ister is tied together with EEPROM and can’t be written
while EEPROM is busy. See the Fault Log section for more
detail. Other registers may be accessed while EEPROM
write is busy. When the EEPROM finishes writing, the
EEPROM_BUSY bit will be cleared and the EEPROM_
WRITTEN bit in the ADC_ALARM_LOG_1 register will
beset.
If the corresponding EEPROM_WRITTEN_ALERT bit in
register ADC_ALERT_1 is set, a rising edge on EEPROM_
WRITTEN will set ALERT_GENERATED in the METER_
CONTROL register. As a result, the ALERT# pin is pulled
down. This will alert the host that the LTC4283 EEPROM
is ready for more accesses.
When the LTC4283 comes out of UVLO or receives a
REBOOT command, the contents of the EEPROM are cop-
ied to the corresponding operating registers. This process
takes about 1.3ms. During this time, the I2C bus is not
available. Any command code received will be NACKed.
Registers in the address range 0x0A through 0x40 corre-
spond to EEPROM locations 0xAA through 0xE0. Register
0x90 corresponds to EEPROM location 0xF0. The seven
EEPROM bytes in the EE_SCRATCH area are available
for any general purpose use. EEPROM is also used to
support the fault logging feature. See details in the Fault
Log section.
The WP pin prevents I2C writes to the EEPROM when
high. Attempts to write to the EEPROM while WP is high
will result in a NACK and no action. Fault log writes can
take place with WP high, except when the LTC4283 is in
single-wire broadcast mode. The EEPROM can be read
regardless of the WP pin setting. The current WP pin
status is available for reading at the WP_STATUS bit in
the REBOOT register.
Factory programmed parts may optionally have the
EEPROM locked. In this case the WP pin has no impact.
No EEPROM writes are possible. Fault logging is also
Figure17. Individual Feed Current and Channel Current Monitoring
R
S1
M1
R
F1
R
F2
F1
F2
D1
D2
GATE
LTC4283
4283 F17
SENSE–
SENSE+
ADIN3
ADIN4
ADIN1
ADIN2
INPUT2
INPUT1
V
EE
R
S1
M1
R1
100k
R3
100k
QP2
QP1
R2
2.49k
R4
2.49k
GATE
LTC4283
–48V
INPUT
V
EE
SENSE–
SENSE+
–48V
RTN
ADIN1
2 × 2N5401
4283 F18
Figure18. Direct Monitoring of Load Voltage
Using a Single ADC Input
LTC4283
46
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APPLICATIONS INFORMATION
disabled when the EEPROM is locked. Bit EE_LOCK in
the METER_CONTROL register is a 1 when the EEPROM
is locked.
Fault Log
The LTC4283’s EEPROM supports a fault logging feature.
Twelve bytes hold a log for a single fault event (Table22).
In addition, a thirteenth byte provides an EEPROM backup
copy for the fault log control register (FAULT_LOG_
CONTROL, register 0x90, see Table21).
Writes to FAULT_LOG_CONTROL always cause a write to
the EEPROM backup byte (EE_FAULT_LOG_CONTROL).
This causes the EEPROM to go busy, disabling access to
all EEPROM registers for about 2.2ms. During this time,
FAULT_LOG_CONTROL can be read but not written. If
another EEPROM register is written first, FAULT_LOG_
CONTROL can’t be written until the busy condition clears.
Conditions Leading to a Fault Log Write. A fault condition
is defined as any condition in which a bit in the FAULT
register (0x04) is set or the EN#_CHANGED bit is set in
the ADC_ALARM_LOG_1 register (0x05).
A fault condition will result in a fault log being written if
several conditions are met:
1. The fault condition causes GATE to be pulled low.
2. VIN is above the UVLO limit.
3. FAULT_LOG_ENABLE in the FAULT_LOG_CONTROL
register (0x90) is set.
4. FAULT_LOG_UNLOCK, FAULT_LOG_START and
FAULT_LOG_DONE in the FAULT_LOG_CONTROL
register are all clear (this ensures any previous fault
log has been completely serviced).
The FET_SHORT_FAULT and POWER_FAILED bits don’t
cause GATE to be pulled low, so they don’t cause a fault
log to be written. Also, the EN#_CHANGED bit doesn’t
cause a fault log to be written if it is set by the falling
edge of EN#.
In addition, fault log writing is disabled if the WP pin is
high while the LTC4283 is in single-wire broadcast mode.
Fault Log Writing Sequence. This sequence takes place
in the LTC4283 in response to a condition that calls for
a fault log write:
1. Freeze a shadow copy of fault bits (register 0x04 and
bit [7] of 0x05).
2. Block I2C access.
3. Set FAULT_LOG_START in the FAULT_LOG_
CONTROL register.
4. Write FAULT_LOG_CONTROL to its backup copy in
EEPROM.
5. Write the 12 bytes of fault information as detailed in
Table22, fault bits come from the shadow copy.
6. Set FAULT_LOG_DONE in FAULT_LOG_CONTROL.
7. Write FAULT_LOG_CONTROL to its backup copy in
EEPROM.
8. Set alert if FAULT_LOG_ALERT is set.
9. Unfreeze the shadow copy of fault bits.
10. Allow I2C access
The I2C bus is blocked for about 31ms (14 time tWRITE).
During this time, any incoming byte from I2C will be
NACKed. If a fault log write starts in the middle of an
I2C read, bytes of 0xFF will be returned to I2C in place of
expected data.
Resolving Fault Priority. When one fault bit is set, more
bits will typically be set soon afterward. With too many
bits set, the original cause of the problem is harder to
determine. The LTC4283’s fault logging logic is designed
to capture the first fault indication and disregard subse-
quent fault bits set until after fault log writing finishes.
The frozen copy of fault bits mentioned in the fault log
writing sequence is part of this philosophy. As soon as
the first fault bit is set which leads to GATE low, the frozen
copy of fault bits is closed and remains closed until after
logging is complete. In the fault log, fault data comes from
the frozen copy. During this time, fault information is still
accumulated in the main fault registers.
LTC4283
47
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Servicing a Fault Log. After one fault log has been written,
further fault log writes will be disabled until the first fault
log has been serviced.
The FAULT_LOG_START and FAULT_LOG_DONE bits
can’t be set or cleared directly by I
2
C accesses. To prevent
an accidental clearing of fault log information, a multi-
byte sequence is required to fully service one fault log so
another fault log can be written. The sequence is:
1. Write FAULT_LOG_CONTROL with FAULT_LOG_
UNLOCK set
2. Write a second time with FAULT_LOG_UNLOCK set
and all other bits clear. This write will clear FAULT_
LOG_START and FAULT_LOG_DONE.
3. Write again with FAULT_LOG_UNLOCK, FAULT_LOG_
START and FAULT_LOG_DONE all clear. At this time,
the FAULT_LOG_ENABLE and FAULT_LOG_ALERT
bits may be set as desired.
Additionally, to avoid inadvertently overwriting the logged
data through I2C, bring WP high during servicing.
Incomplete Fault Logs. A fault condition is a likely pre-
cursor to an overall loss of power in the LTC4283. For
accurate fault logging, the system design must provide
sufficient external capacitance as described in Input
Power Supply to hold INTVCC up during the time required
to write 14 bytes to EEPROM.
The fault log writing sequence described earlier provides
a way to detect if the fault log doesn’t complete suc-
cessfully. The first EEPROM write saves FAULT_LOG_
CONTROL with the FAULT_LOG_START bit set. Then
the final EEPROM write saves FAULT_LOG_CONTROL
with both FAULT_LOG_START and FAULT_LOG_DONE
bits set.
After a loss of power, the FAULT_LOG_CONTROL register
is loaded back from the saved EEPROM copy. If power
was lost before a fault log completed, the FAULT_LOG_
CONTROL register will have FAULT_LOG_START set, but
not FAULT_LOG_END. Also after a loss of power, if the
FAULT_LOG_ALERT bit is set and FAULT_LOG_START,
FAULT_LOG_DONE or FAULT_LOG_UNLOCK are set, the
ALERT# pin will be pulled down to alert the system that
an unserviced fault log remains in the chip.
Digital Interface
The LTC4283 communicates with a bus master using
a serial 2-wire interface, compatible with both I
2
C and
SMBus. The 2-wire interface is supplemented by an
SMBus-compatible ALERT# output. The LTC4283 is
always a bus slave and doesn’t use clock stretching.
Many LTC4283 applications require unidirectional isola-
tors such as opto-couplers between the serial interface
and the host system. For convenience of opto-coupling
with the host, the SDA function is split into SDAI (input)
and SDAO (output). For a conventional SDA line, tie SDAI
and SDAO together.
When using opto-couplers, connect the SDAI pin to the
output of the incoming opto-coupler and connect the
SDAO pin to the input of the outgoing opto-coupler (see
Figure2b). If the ALERT# line is used, connect it in the
same way as the SDAO pin as shown in Figure2b.
Bus Compatibility
The basic LTC4283 serial interface is compliant with I2C
and SMBus AC and DC specifications. The timing is com-
patible with 400Kbit operation for both. This includes the
SMBus legacy tHD:DATO timing of 300ns minimum.
In addition, the LTC4283 supports 1Mbit operation which
is compatible with I2C FastMode+ and SMBus 3.0. To
use this timing, the FAST_I2C_EN bit in the CONFIG_3
register must be set. This bit may be set to 1 as default
by EEPROM, or it can be manually written to 1. If the bit
is 0 before writing, the write must be done at 400Kbit
or less. With FAST_I2C_EN set, tHD:DATO is reduced to
allow higher speed transfers.
The LTC4283 SDAO output is guaranteed to pull down
20mA. This allows the use of a lower value pull-up resistor
to reduce the low-to-high delay time.
LTC4283
48
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START, REPEATED START and STOP Conditions
When the bus is idle, SCL and SDA are high. A bus master
signals the start of a transfer with a START condition.
START is defined by a falling edge on SDA while SCL is
high. The end of the transfer is signaled by a STOP condi-
tion. STOP is defined by a rising edge on SDA while SCL
is high (see Figure19).
In between START and STOP, data and handshake bits are
transferred with a data value on SDA and a high pulse on
SCL. For data or handshake bits, SDA changes only while
SCL is low.
A bus master may also signal a REPEATED START condi-
tion in the middle of a transfer. Like START, REPEATED
START is defined by a falling edge on SDA while SCL is
high. REPEATED START is used in read transfers (see
Transfer Protocol Types).
ACK/NACK
Data is transferred as a series of 8-bit bytes. Following each
data byte is a handshake bit driven by the receiver. SDA
low during this bit is interpreted as acknowledge (ACK).
SDA high is interpreted as not-acknowledge(NACK).
In all cases, a transfer stops after a NACK bit. If the bus
master is sending a data byte, a NACK from the slave
indicates an error condition. If all bytes written are
ACK’ed, the bus master may also terminate a write by
making a STOP condition after the final byte. If the bus
master is receiving a data, it returns NACK after the last
byte it wants to receive. This is normal, no error condition
is implied.
I2C Device Addressing
The bus master addresses a slave by sending a slave
address byte after either a START or REPEATED START
condition. Bit 0 of the slave address byte is high to select
a read transfer and low to select a write. See Transfer
Protocol Types for more detail. The LTC4283 ADR1 and
ADR0 pins can be configured to select its slave addresses
as shown in Table1.
Single-wire broadcast mode replaces the normal serial-
bus interface with a one-wire option which continuously
broadcasts important status from the LTC4283. See more
details in Single-Wire Broadcast.
Transfer Protocol Types
Figure19 shows basic elements of the I
2
C protocol. These
are combined to form complete read and write transfers.
Figures 20 to 26 show the transfer protocol types sup-
ported by the LTC4283.
Table1. LTC4283 Device Addressing
DESCRIPTION
HEX DEVICE
ADDRESS* BINARY DEVICE ADDRESS
LTC4283
ADDRESS PINS
7-Bit 8-Bit a6 a5 a4 a3 a2 a1 a0 R/W# ADR1 ADR0
Mass Write 1F 3E 0 0 1 1 1 1 1 0 X X
Alert Response 0C 19 0 0 0 1 1 0 0 1 X X
0 10 20 0 0 1 0 0 0 0 X L L
1 11 22 0 0 1 0 0 0 1 X L NC
2 12 24 0 0 1 0 0 1 0 X H NC
3 13 26 0 0 1 0 0 1 1 X L H
4 14 28 0 0 1 0 1 0 0 X NC L
5 15 2A 0 0 1 0 1 0 1 X NC NC
6 16 2C 0 0 1 0 1 1 0 X H H
7 17 2E 0 0 1 0 1 1 1 X NC H
8 Single-Wire Broadcast Mode H L
H = Tie to INTVCC; L = Tie to VEE; NC = No connect or open; X = Don’t Care
*8-bit hexadecimal address with LSB R/W bit = 0
7-bit hexadecimal address with MSB a7 = 0
LTC4283
49
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APPLICATIONS INFORMATION
Figure19. General Data Transfer over I2C
a6 - a0 b7 - b0 b7 - b0
9
ACK
4283 F19
ACKACKADDRESSSTART
CONDITION
STOP
CONDITION
R/WDATADATA
89898
S
SDA
SCL
1 - 71 - 71 - 7
P
ADDRESS
001 a3:a0
FROM MASTER TO SLAVE A: ACKNOWLEDGE (LOW)
A: NOT ACKNOWLEDGE (HIGH)
R: READ BIT (HIGH)
W: WRITE BIT (LOW)
S: START CONDITION
SR: REPEATED START CONDITION
P: STOP CONDITION
FROM SLAVE TO MASTER
b7:b0 b7:b0 4283 F20
COMMAND DATAS
0 0 0 0
A A A PW
Figure20. Write Byte Protocol Figure21. Write Word Protocol
Figure22. Write Page Protocol
ADDRESS
001 a3:a0 b7:b0 b7:b0
4283 F21
COMMAND DATAS
0 0 0 0
A A A
b7:b0
DATA
0
A PW
ADDRESS
001 a3:a0 b7:b0 b7:b0
4283 F22
COMMAND DATAS
0 0 0 0
A A A
b7:b0
DATA PW • • • 0
A
Figure23. Read Byte Protocol
Figure24. Read Word Protocol
Figure25. Read Page Protocol
Figure26. Alert Response Protocol
ADDRESS
001 a3:a0
ADDRESS
001 a3:a0b7:b0 b7:b0
4283 F23
COMMAND DATAS SR R
0 0 0 1
A A A
01
A PW
ADDRESS
001 a3:a0
ADDRESS
001 a3:a0b7:b0 b7:b0
4283 F24
COMMAND DATAS SR R
0 0 0 1
A A A
01
A PW
b7:b0
DATA
0
A
ADDRESS
001 a3:a0
ADDRESS
001 a3:a0b7:b0 b7:b0
4283 F25
COMMAND DATA
b7:b0
DATAS SR R
0 0 0 1
A A A
01
A
0
A PW • • •
ALERT
RESPONSE
ADDRESS
DEVICE
ADDRESS
0001100
S R
1 1
4283 F26
A PA
0 001 a3:a0 0
LTC4283
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Command Codes and Register Addressing
The command byte in each transfer contains the register
address for the first byte being accessed. If multiple bytes
are accessed in a transfer, each comes from the address
following the previous byte. For example, when reading
the six-byte ENERGY register, the first byte comes from
address 0x7A, the second byte from address 0x7B, up
through the final byte from address 0x7F (see Table3).
It’s possible to access two different registers in one trans-
fer. For example, the SYSTEM_STATUS and ADC_STATUS
registers can be accessed using a read word transfer
with COMMAND equal 0x00. This addressing method is
common for I2C systems, but differs from SMBus. With
SMBus, each register occupies a single command code,
regardless of register size.
Registers 0x41 to 0x79 are implemented in 16-bit RAM
words as shown in Table3. To save command codes, each
occupies only one register address. Consider a four-byte
read with command code of 0x41. Data will be returned
in this order:
1. Most significant byte of SENSE
2. Least significant byte of SENSE
3. Most significant byte of SENSE_MIN
4. Least significant byte of SENSE_MIN
Write Protocols
For writes, all data bytes come from the bus master and
are acknowledged by the slave. Bit 0 of the slave address
byte is clear to select write. The COMMAND byte contains
the register address for the first byte being written.
A special slave address can be used to implement mass
writes. If multiple LTC4283 chips are on the same serial
bus, the mass write technique can be used to write all of
them at the same time. All LTC4283s respond to a slave
address of 0011_111b with the Read/Write# bit clear.
Bit MASS_WRITE_ENABLE in register CONTROL_1 can
be set to enable mass writes.
Read Protocols
Reads consist of two parts. First the master sends a slave
address byte with bit 0 clear and a COMMAND byte to
select the register to be read from. After this, a REPEATED
START condition and second slave address byte are sent
with bit 0 set (indicating read). The LTC4283 replies with
data after the second slave address byte.
Read Page and Write Page Protocols
Read page and write page refer to transfers larger than
two bytes. Page accesses are convenient for reading
larger registers and for synchronizing data in multiple
registers (see Data Synchronization and Arbitration for
details). If page accesses are required, the PAGE_READ_
WRITE_ENABLE bit in the CONTROL_1 register should be
set. If the bit is not set, accesses to more than two bytes
of data will be terminated. For an attempted page write,
the extra bytes would be NACK’ed. For an attempted page
read, the LTC4283 would return 0xF F.
Byte Ordering
The LTC4283 uses big endian ordering for accessing
multi-byte registers. That means when a 16-bit word
register is accessed, the most significant byte is trans-
ferred first, followed by the least significant byte. This is
common in I2C systems. SMBus systems use little endian
ordering, with least significant byte transferred first.
ALERT# and Alert Response Protocol
The LTC4283 fully supports the SMBus alert response
mechanism. Refer to Figure26:
1. If ALERT# is low, the LTC4283 will acknowledge the
SMBus alert response address (ARA).
2. In the following data byte, the LTC4283 returns its
own slave address, with bit 0 clear. Multiple slave
devices on the bus may be responding to the same
ARA. If a conflict is detected on any bit, the LTC4283
will back off and let the higher priority device continue.
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3. If the LTC4283 successfully transfers its entire slave
address, it will clear its ALERT_GENERATED bit, and
stop pulling ALERT# low.
There are 52 possible conditions to set ALERT_
GENERATED. Each condition (fault or event) has a cor-
responding alert enable bit. Table24 has the list of fault/
event bits and alert enable bits.
For all cases, ALERT_GENERATED will only be set by a
rising edge on the combination of fault/event logically
and’ed with alert enable bit. ALERT_GENERATED is set
whether a fault/event bit is set first or the corresponding
alert enable bit is set first. Once a fault or event bit is set,
it won’t contribute to ALERT_GENERATED again until the
fault or event is cleared.
One event, ADC conversion completed, doesn’t have a
latched status bit. There is a corresponding ADC_CONV_
ALERT bit to enable the ALERT_GENERATED. But when
servicing ALERT#, software won’t have a way to verify that
a completed ADC conversion caused the alert condition.
Due to this limitation, the ADC conversion completed alert
is not useful unless all other alert sources are masked off.
Typically, software will read the event and fault regis-
ters to check status, then write 0’s to clear the bits that
have been serviced. Event and fault bits can also be set
directly by the I
2
C bus. A bit set this way leads to ALERT_
GENERATED set and ALERT# low in the same way as
when the chip sets the bit. ALERT_GENERATED itself can
also be set by an I2C write. These features may be helpful
for software test.
Stuck Bus Reset
The LTC4283 has an SMBus-style stuck bus reset. If the
serial bus remains stuck for about 30ms, the I2C control-
ler block will reset itself. When the controller is reset, it
stops pulling down SDAO and searches for a new START
condition.
In the SMBus definition, the stuck bus timer is cleared by
SCL high. Many existing LTC chips including previous hot
swap controllers clear the timer when SCL and SDA are
both high. This is more thorough because it can detect
either SDA or SCL stuck low.
The method presents a problem with the LTC4283. With
read page or write page, very long transfers are possible.
For each byte of 0x00 transferred, SDA will be low for the
whole byte. A long sequence of 0x00 bytes may lead to
false stuck bus timeouts. The LTC4283 uses a modified
stuck bus mechanism to prevent false timeouts. The timer
is cleared If SCL is high and the LTC4283 is not pulling
down SDAO.
As with other stuck bus timers, SCL stuck low causes a
timeout. In addition, a timeout happens if the LTC4283
continuously pulls down SDAO for 30ms. This could hap-
pen if the bus stops with SCL high while the LTC4283 is
still pulling down on SDAO.
Data Synchronization and Arbitration
Several RAM locations and registers in the LTC4283 have
control shared between ADC logic and the I2C interface.
ADC logic writes data and the I
2
C interface reads from
them. The RAM locations are at addresses between 0x41
and 0x79. Registers for ENERGY and TICK_COUNTER are
at addresses between 0x7A and 0x83. These registers are
also written by ADC logic.
ADC writes to ENERGY, TICK_COUNTER and the ADC
RAM locations are always done while the I2C interface
is idle. That ensures none of the locations can change in
the middle of an I2C read. For example, when reading a
two-byte RAM location, the two bytes read will always be
consistent with each other.
The ENERGY and TICK_COUNTER registers are larger, but
the same technique can be used. To ensure consistency,
read all bytes of each register in a single I2C operation.
For energy calculations, you may also need ENERGY and
TICK_COUNTER to be consistent with each other. This
can be done by reading both registers together in a single
10-byte I
2
C read. The register locations are contiguous to
facilitate this approach. Read 10 bytes starting at register
location 0x7A.
LTC4283
52
Rev. A
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APPLICATIONS INFORMATION
There are some limits on the length of I
2
C transfers. If
any one transfer takes longer than an ADC conversion
time, some ADC data will be lost. This depends on the bus
speed, transfer length and ADC conversion time. See the
ADC[2:0] field in Table12.
As detailed above, the I
2
C interface operates in parallel
with ADC update logic. In some other cases, I2C access
will be disabled:
1. After a power-on reset or reboot, I2C access is dis-
abled while configuration registers are being loaded
from EEPROM.
2. While a fault log is being written to EEPROM
3. After a write to the REBOOT register which sets the
RBT_EN bit.
In these cases, the I
2
C controller ignores all inputs and
SDAO is not pulled down. As a result, slave address and
other bytes from the bus master will be NACK’ed. This
behavior is common in I2C systems. Be careful with this
when operating in an SMBus system. The SMBus specifi-
cation requires all slave address bytes to be ACK’ed but the
LTC4283 doesn’t ACK them in the three cases listed above.
While reading data from the LTC4283, the ACK for each
byte comes from the bus master. There’s no way for the
LTC4283 to indicate a problem during the read. If the I2C
controller is disabled during a read, bytes of 0xFF will be
returned by the LTC4283 in place of the expected data.
Single-Wire Broadcast
The LTC4283 can start itself up without any I
2
C activ
-
ity. The chip automatically loads configuration data from
EEPROM to working registers after a power up or reboot.
In this case, the user may not need a full I2C interface.
For many system applications, a full I2C interface would
require three isolators (see Figure2b). Use of the single-
wire broadcast mode can reduce this to one isolator.
When ADR1 is connected to INTVCC and ADR0 is con-
nected to V
EE
, single-wire broadcast mode is selected.
In this mode, I2C bus operation is disabled. In its place,
status and ADC information are continually transmitted
on SDAO. A packet of 20 bytes as shown in Table2 is
transmitted once for each ADC conversion cycle using
Manchester encoding.
The packet is in the following format:
Table2. Single-Wire Broadcast Data Format
DATA ADDRESS SIZE IN BITS
Preamble—0x2A N/A 8
SENSE 0x41 16
VPWR 0x44 16
POWER 0x47 16
VAUX Most recent ADC aux reading 16
SYSTEM_STATUS 0x00 8
ADC_STATUS 0x01 8
INPUT_STATUS 0x02 8
FAULT_STATUS 0x03 8
FAULT 0x04 8
ADC_ALARM_LOG 0x05–0x09 40
PEC N/A 8
Total 160
The preamble byte is a fixed pattern to allow hardware or
software to detect the packet start and bit rate as shown
in Figure28. V
AUX
is a selected auxiliary channel measure-
ment. In each ADC conversion cycle, one auxiliary channel
may be measured. Bits [7:4] of ADC_STATUS contain the
AUX_ADC_CH field to identify which ADC auxiliary input is
present in the VAUX field. See the Data Converters section
for an explanation of the channel select sequence.
Two different conventions are followed: G.E. Thomas and
IEEE 802.3 as shown in Figure27. For G.E. Thomas con-
vention, each data 1 bit is represented by a falling edge in
the middle of the bit cell. For IEEE 802.3 convention, data
1 bits are represented by a rising edge in the middle of the
bit cell. G.E. Thomas convention is used for the LTC4283.
This is the same as for the LTC4261 and LTC4284.
The final byte of the packet is an SMBus-compatible PEC
byte. PEC uses an 8-bit CRC with the polynomial X8 + X2
+ X + 1. PEC covers all bytes of the packet including the
preamble. The PEC accumulator is initialized to 0x00 at
the start of the packet.
LTC4283
53
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4283 F27
10100111001
CLOCK
DATA
MANCHESTER
(AS PER G.E. THOMAS)
MANCHESTER
(AS PER IEEE 802.3)
APPLICATIONS INFORMATION
The data rate of single-wire broadcast can be selected
using field BC in the CONFIG_3 register, see Table11.
In broadcast mode, there needs to be enough time to
transmit the entire 20-byte packet before another ADC
update. That limit means the slowest data rates (128k and
32k) can’t be used when the ADC is configured for 8-bit
samples. In those two cases, the LTC4283 automatically
switches to a minimum 512k data rate for single-wire
broadcast.
Figure27. An Example of Manchester Encoding, Showing Both Conventions
Figure28. Manchester Encoding for the Preamble Byte of 0x2A
4283 F28
00101010
SDAO
LTC4283
54
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Register Tables
APPLICATIONS INFORMATION
REGISTER NAME
REGISTER
ADDRESS* DESCRIPTION
READ/
WRITE
DATA
LENGTH
(BYTES) DEFAULT VALUE
SYSTEM_STATUS 0x00 System status information R 1 N/A
ADC_STATUS 0x01 ADC conversion status R 1 N/A
INPUT_STATUS 0x02 PGIO1–PGIO4, ADIO1–ADIO4 general purpose input status R 1 N/A
FAULT_STATUS 0x03 Fault status information R 1 N/A
FAULT 0x04 System fault R/W 1 0x00
ADC_ALARM_LOG 0x05-0x09 ADC measurement alarms R/W 5 0x0000_0000_00
CONTROL 0x0A-0x0B Controls the system on/off and auto-retry behaviors R/W 2 0xDB03
Reserved 0x0C Read only, always returns 0 R 1 N/A
CONFIG 0x0D-0x0F Configures current limit, foldback, delays, and other system parameters R/W 3 0x0CC0_00
PGIO_CONFIG 0x10-0x11 Configures I/O states and outputs of PGIO1–PGIO4 R/W 2 0x0004
ADIO_CONFIG 0x12 Configures I/O states and outputs of ADIO1–ADIO4, controls ADC R/W 1 0xF0
ADC_SELECT 0x13-0x14 Auxiliary ADC inputs selection R/W 2 0xFF0F
FAULT_ALERT 0x15 Controls whether ALERT# pulls low after a system fault is logged R/W 1 0x00
ADC_ALERT 0x16-0x1A Controls whether ALERT# pulls low after an ADC alarm is logged R/W 5 0x0000_0000_00
SENSE_MIN_TH 0x1B ADC alarm threshold for minimum SENSE+ − SENSE–R/W 1 0x00
SENSE_MAX_TH 0x1C ADC alarm threshold for maximum SENSE+ − SENSE–R/W 1 0xFF
VPWR_MIN_TH 0x1D ADC alarm threshold for minimum VPWR (RTNS/DRNS) voltage R/W 1 0x00
VPWR_MAX_TH 0x1E ADC alarm threshold for maximum VPWR (RTNS/DRNS) voltage R/W 1 0xFF
POWER_MIN_TH 0x1F ADC alarm threshold for minimum input power R/W 1 0x00
POWER_MAX_TH 0x20 ADC alarm threshold for maximum input power R/W 1 0xFF
ADIN1_MIN_TH 0x21 ADC alarm threshold for minimum ADIN1 voltage R/W 1 0x00
ADIN1_MAX_TH 0x22 ADC alarm threshold for maximum ADIN1 voltage R/W 1 0xFF
ADIN2_MIN_TH 0x23 ADC alarm threshold for minimum ADIN2 voltage R/W 1 0x00
ADIN2_MAX_TH 0x24 ADC alarm threshold for maximum ADIN2 voltage R/W 1 0xFF
ADIN3_MIN_TH 0x25 ADC alarm threshold for minimum ADIN3 voltage R/W 1 0x00
ADIN3_MAX_TH 0x26 ADC alarm threshold for maximum ADIN3 voltage R/W 1 0xFF
ADIN4_MIN_TH 0x27 ADC alarm threshold for minimum ADIN4 voltage R/W 1 0x00
ADIN4_MAX_TH 0x28 ADC alarm threshold for maximum ADIN4 voltage R/W 1 0xFF
ADIO1_MIN_TH 0x29 ADC alarm threshold for minimum ADIO1 voltage R/W 1 0x00
ADIO1_MAX_TH 0x2A ADC alarm threshold for maximum ADIO1 voltage R/W 1 0xFF
ADIO2_MIN_TH 0x2B ADC alarm threshold for minimum ADIO2 voltage R/W 1 0x00
ADIO2_MAX_TH 0x2C ADC alarm threshold for maximum ADIO2 voltage R/W 1 0xFF
ADIO3_MIN_TH 0x2D ADC alarm threshold for minimum ADIO3 voltage R/W 1 0x00
ADIO3_MAX_TH 0x2E ADC alarm threshold for maximum ADIO3 voltage R/W 1 0xFF
ADIO4_MIN_TH 0x2F ADC alarm threshold for minimum ADIO4 voltage R/W 1 0x00
ADIO4_MAX_TH 0x30 ADC alarm threshold for maximum ADIO4 voltage R/W 1 0xFF
DRNS_MIN_TH 0x31 ADC alarm threshold for minimum DRNS voltage R/W 1 0x00
DRNS_MAX_TH 0x32 ADC alarm threshold for maximum DRNS voltage R/W 1 0xFF
DRAIN_MIN_TH 0x33 ADC alarm threshold for minimum DRAIN voltage R/W 1 0x00
Table3. LTC4283 Register Address and Contents
LTC4283
55
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
REGISTER NAME
REGISTER
ADDRESS* DESCRIPTION
READ/
WRITE
DATA
LENGTH
(BYTES) DEFAULT VALUE
DRAIN_MAX_TH 0x34 ADC alarm threshold for maximum DRAIN voltage R/W 1 0xFF
Reserved 0x35 Undefined R/W 1 0x00
Reserved 0x36 Undefined R/W 1 0xFF
Reserved 0x37 Undefined R/W 1 0x00
Reserved 0x38 Undefined R/W 1 0xFF
ADIN12_MIN_TH 0x39 ADC alarm threshold for minimum ADIN2 – ADIN1 R/W 1 0x00
ADIN12_MAX_TH 0x3A ADC alarm threshold for maximum ADIN2 – ADIN1 R/W 1 0xFF
ADIN34_MIN_TH 0x3B ADC alarm threshold for minimum ADIN4 – ADIN3 R/W 1 0x00
ADIN34_MAX_TH 0x3C ADC alarm threshold for maximum ADIN4 – ADIN3 R/W 1 0xFF
ADIO12_MIN_TH 0x3D ADC alarm threshold for minimum ADIO2 – ADIO1 R/W 1 0x00
ADIO12_MAX_TH 0x3E ADC alarm threshold for maximum ADIO2 – ADIO1 R/W 1 0xFF
ADIO34_MIN_TH 0x3F ADC alarm threshold for minimum ADIO4 – ADIO3 R/W 1 0x00
ADIO34_MAX_TH 0x40 ADC alarm threshold for maximum ADIO4 – ADIO3 R/W 1 0xFF
SENSE 0x41 Most recent ADC output for SENSE+ − SENSE–R/W 2 0x0000
SENSE_MIN 0x42 Minimum ADC output for SENSE+ − SENSE–R/W 2 0x0000
SENSE_MAX 0x43 Maximum ADC output for SENSE+ − SENSE–R/W 2 0x0000
VPWR 0x44 Most recent ADC output for VPWR (RTNS/DRNS) R/W 2 0x0000
VPWR_MIN 0x45 Minimum ADC output for VPWR (RTNS/DRNS) R/W 2 0x0000
VPWR_MAX 0x46 Maximum ADC output for VPWR (RTNS/DRNS) R/W 2 0x0000
POWER 0x47 Most recent ADC output for power R/W 2 0x0000
POWER_MIN 0x48 Minimum ADC output for power R/W 2 0x0000
POWER_MAX 0x49 Maximum ADC output for power R/W 2 0x0000
ADIN1 0x4A Most recent ADC output for ADIN1 R/W 2 0x0000
ADIN1_MIN 0x4B Minimum ADC output for ADIN1 R/W 2 0x0000
ADIN1_MAX 0x4C Maximum ADC output for ADIN1 R/W 2 0x0000
ADIN2 0x4D Most recent ADC output for ADIN2 R/W 2 0x0000
ADIN2_MIN 0x4E Minimum ADC output for ADIN2 R/W 2 0x0000
ADIN2_MAX 0x4F Maximum ADC output for ADIN2 R/W 2 0x0000
ADIN3 0x50 Most recent ADC output for ADIN3 R/W 2 0x0000
ADIN3_MIN 0x51 Minimum ADC output for ADIN3 R/W 2 0x0000
ADIN3_MAX 0x52 Maximum ADC output for ADIN3 R/W 2 0x0000
ADIN4 0x53 Most recent ADC output for ADIN4 R/W 2 0x0000
ADIN4_MIN 0x54 Minimum ADC output for ADIN4 R/W 2 0x0000
ADIN4_MAX 0x55 Maximum ADC output for ADIN4 R/W 2 0x0000
ADIO1 0x56 Most recent ADC output for ADIO1 R/W 2 0x0000
ADIO1_MIN 0x57 Minimum ADC output for ADIO1 R/W 2 0x0000
ADIO1_MAX 0x58 Maximum ADC output for ADIO1 R/W 2 0x0000
ADIO2 0x59 Most recent ADC output for ADIO2 R/W 2 0x0000
ADIO2_MIN 0x5A Minimum ADC output for ADIO2 R/W 2 0x0000
Table 3. LTC4283 Register Address and Contents (Cont.)
LTC4283
56
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
REGISTER NAME
REGISTER
ADDRESS* DESCRIPTION
READ/
WRITE
DATA
LENGTH
(BYTES) DEFAULT VALUE
ADIO2_MAX 0x5B Maximum ADC output for ADIO2 R/W 2 0x0000
ADIO3 0x5C Most recent ADC output for ADIO3 R/W 2 0x0000
ADIO3_MIN 0x5D Minimum ADC output for ADIO3 R/W 2 0x0000
ADIO3_MAX 0x5E Maximum ADC output for ADIO3 R/W 2 0x0000
ADIO4 0x5F Most recent ADC output for ADIO4 R/W 2 0x0000
ADIO4_MIN 0x60 Minimum ADC output for ADIO4 R/W 2 0x0000
ADIO4_MAX 0x61 Maximum ADC output for ADIO4 R/W 2 0x0000
DRNS 0x62 Most recent ADC output for DRNS R/W 2 0x0000
DRNS_MIN 0x63 Minimum ADC output for DRNS R/W 2 0x0000
DRNS_MAX 0x64 Maximum ADC output for DRNS R/W 2 0x0000
DRAIN 0x65 Most recent ADC output for DRAIN R/W 2 0x0000
DRAIN_MIN 0x66 Minimum ADC output for DRAIN R/W 2 0x0000
DRAIN_MAX 0x67 Maximum ADC output for DRAIN R/W 2 0x0000
Reserved 0x68 Undefined R/W 2 N/A
Reserved 0x69 Undefined R/W 2 N/A
Reserved 0x6A Undefined R/W 2 N/A
Reserved 0x6B Undefined R/W 2 N/A
Reserved 0x6C Undefined R/W 2 N/A
Reserved 0x6D Undefined R/W 2 N/A
ADIN12 0x6E Most recent ADC output for ADIN2 – ADIN1 R/W 2 0x0000
ADIN12_MIN 0x6F Minimum ADC output for ADIN2 – ADIN1 R/W 2 0x0000
ADIN12_MAX 0x70 Maximum ADC output for ADIN2 – ADIN1 R/W 2 0x0000
ADIN34 0x71 Most recent ADC output for ADIN4 – ADIN3 R/W 2 0x0000
ADIN34_MIN 0x72 Minimum ADC output for ADIN4 – ADIN3 R/W 2 0x0000
ADIN34_MAX 0x73 Maximum ADC output for ADIN4 – ADIN3 R/W 2 0x0000
ADIO12 0x74 Most recent ADC output for ADIO2 – ADIO1 R/W 2 0x0000
ADIO12_MIN 0x75 Minimum ADC output for ADIO2 – ADIO1 R/W 2 0x0000
ADIO12_MAX 0x76 Maximum ADC output for ADIO2 – ADIO1 R/W 2 0x0000
ADIO34 0x77 Most recent ADC output for ADIO4 – ADIO3 R/W 2 0x0000
ADIO34_MIN 0x78 Minimum ADC output for ADIO4 – ADIO3 R/W 2 0x0000
ADIO34_MAX 0x79 Maximum ADC output for ADIO4 – ADIO3 R/W 2 0x0000
ENERGY 0x7A-0x7F Input energy meter R/W 6 0x0000_0000_0000
TICK_COUNTER 0x80-0x83 Tick counter for energy meter R/W 4 0x0000_0000
METER_CONTROL 0x84 Controls energy meter and tick counter R/W 1 0x00
ADC_SNAPSHOT 0x85 Controls ADC snapshot R/W 1 0x00
Reserved 0x86-0x8F Read only, always returns 0 R 10 N/A
FAULT_LOG_CONTROL 0x90 Enables logging fault and ADC data into EEPROM R/W 1 0x00
Reserved 0x91-0xA1 Read only, 0x91–0x9F return 0xFF, 0xA0 and 0xA1 return 0 R 17 N/A
REBOOT 0xA2 Enables reboot and configures reboot delay R/W 1 0x00
Table 3. LTC4283 Register Address and Contents (Cont.)
LTC4283
57
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
REGISTER NAME
REGISTER
ADDRESS* DESCRIPTION
READ/
WRITE
DATA
LENGTH
(BYTES) DEFAULT VALUE
Reserved 0xA3 Read only, always returns 0 R 1 N/A
EE_FAULT 0xA4 Records fault register in EEPROM upon a fault R/W 1 0x00
EE_ADC_ALARM_LOG 0xA5-0xA9 Records ADC_ALARM_LOG registers in EEPROM upon a fault R/W 5 0x0000_0000_00
EE_CONTROL
0xAA-0xAB
Stores default of CONTROL registers in EEPROM R/W 2 0xDB03
Reserved 0xAC Read only, returns 0xFF if EEPROM busy, otherwise returns 0 R 1 N/A
EE_CONFIG 0xAD-0xAF Stores default of CONFIG registers in EEPROM R/W 3 0x0CC0_00
EE_PGIO_CONFIG 0xB0-0xB1 Stores default of PGIO_CONFIG registers in EEPROM R/W 2 0x0004
EE_ADIO_CONFIG 0xB2 Stores default of ADIO_CONFIG register in EEPROM R/W 1 0xF0
EE_ADC_SELECT 0xB3-0xB4 Stores default of ADC_SELECT registers in EEPROM R/W 2 0xFF0F
EE_FAULT_ALERT 0xB5 Stores default of FAULT_ALERT register in EEPROM R/W 1 0x00
EE_ADC_ALERT 0xB6-0xBA Stores default of ADC_ALERT registers in EEPROM R/W 5 0x0000_0000_00
EE_SENSE_MIN_TH 0xBB Stores default of SENSE_MIN_TH register in EEPROM R/W 1 0x00
EE_SENSE_MAX_TH 0xBC Stores default of SENSE_MAX_TH register in EEPROM R/W 1 0xFF
EE_VPWR_MIN_TH 0xBD Stores default of VPWR_MIN_TH register in EEPROM R/W 1 0x00
EE_VPWR_MAX_TH 0xBE Stores default of VPWR_MAX_TH register in EEPROM R/W 1 0xFF
EE_POWER_MIN_TH 0xBF Stores default of POWER_MIN_TH register in EEPROM R/W 1 0x00
EE_POWER_MAX_TH 0xC0 Stores default of POWER_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIN1_MIN_TH 0xC1 Stores default of ADIN1_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIN1_MAX_TH 0xC2 Stores default of ADIN1_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIN2_MIN_TH 0xC3 Stores default of ADIN2_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIN2_MAX_TH 0xC4 Stores default of ADIN2_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIN3_MIN_TH 0xC5 Stores default of ADIN3_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIN3_MAX_TH 0xC6 Stores default of ADIN3_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIN4_MIN_TH 0xC7 Stores default of ADIN4_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIN4_MAX_TH 0xC8 Stores default of ADIN4_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIO1_MIN_TH 0xC9 Stores default of ADIO1_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIO1_MAX_TH 0xCA Stores default of ADIO1_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIO2_MIN_TH 0xCB Stores default of ADIO2_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIO2_MAX_TH 0xCC Stores default of ADIO2_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIO3_MIN_TH 0xCD Stores default of ADIO3_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIO3_MAX_TH 0xCE Stores default of ADIO3_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIO4_MIN_TH 0xCF Stores default of ADIO4_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIO4_MAX_TH 0xD0 Stores default of ADIO4_MAX_TH register in EEPROM R/W 1 0xFF
EE_DRNS_MIN_TH 0xD1 Stores default of DRNS_MIN_TH register in EEPROM R/W 1 0x00
EE_DRNS_MAX_TH 0xD2 Stores default of DRNS_MAX_TH register in EEPROM R/W 1 0xFF
EE_DRAIN_MIN_TH 0xD3 Stores default of DRAIN_MIN_TH register in EEPROM R/W 1 0x00
EE_DRAIN_MAX_TH 0xD4 Stores default of DRAIN_MAX_TH register in EEPROM R/W 1 0xFF
Reserved 0xD5 Undefined R/W 1 0x00
Reserved 0xD6 Undefined R/W 1 0xFF
Table 3. LTC4283 Register Address and Contents (Cont.)
LTC4283
58
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
REGISTER NAME
REGISTER
ADDRESS* DESCRIPTION
READ/
WRITE
DATA
LENGTH
(BYTES) DEFAULT VALUE
Reserved 0xD7 Undefined R/W 1 0x00
Reserved 0xD8 Undefined R/W 1 0xFF
EE_ADIN12_MIN_TH 0xD9 Stores default of ADIN12_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIN12_MAX_TH 0xDA Stores default of ADIN12_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIN34_MIN_TH 0xDB Stores default of ADIN34_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIN34_MAX_TH 0xDC Stores default of ADIN34_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIO12_MIN_TH 0xDD Stores default of ADIO12_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIO12_MAX_TH 0xDE Stores default of ADIO12_MAX_TH register in EEPROM R/W 1 0xFF
EE_ADIO34_MIN_TH 0xDF Stores default of ADIO34_MIN_TH register in EEPROM R/W 1 0x00
EE_ADIO34_MAX_TH 0xE0 Stores default of ADIO34_MAX_TH register in EEPROM R/W 1 0xFF
EE_SENSE 0xE1 Records MSB byte of SENSE registers in EEPROM upon a fault R/W 1 0x00
EE_SENSE_MIN 0xE2 Records MSB byte of SENSE_MIN registers in EEPROM upon a fault R/W 1 0x00
EE_SENSE_MAX 0xE3 Records MSB byte of SENSE_MAX registers in EEPROM upon a fault R/W 1 0x00
EE_RTNS 0xE4 Records MSB byte of RTNS registers in EEPROM upon a fault R/W 1 0x00
EE_RTNS_MIN 0xE5 Records MSB byte of RTNS_MIN registers in EEPROM upon a fault R/W 1 0x00
EE_RTNS_MAX 0xE6 Records MSB byte of RTNS_MAX registers in EEPROM upon a fault R/W 1 0x00
POWER_PLAY_ID 0xE7-0xE8 LTpowerPlay ID for LTC4283 R 2 0x0070
EE_SCRATCH 0xE9-0xEF Spare EEPROM bytes R/W 7 0x0000_0000_0000
EE_FAULT_LOG_
CONTROL
0xF0 EEPROM backup of FAULT_LOG_CONTROL register R/W 1 0x00
Reserved 0xF1-0xFF Read only, always returns 0xFF R 15 N/A
*For the two-byte ADC data registers from 0x41 to 0x79, the address points to the MSB byte and increments to the LSB byte when using a Write Word or
Read Word protocol.
Table 3. LTC4283 Register Address and Contents (Cont.)
LTC4283
59
Rev. A
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APPLICATIONS INFORMATION
Table4. SYSTEM_STATUS Registers (0x00) – Read Only
BIT NAME OPERATION
7 FET_ON_STATUS On/off status of GATE; 1 = GATE commanded on, 0 = GATE commanded off
6 EN# State of EN# pin; 1 = EN# high, 0 = EN# low
5 GATE_HIGH State of GATE pin; 1 = GATE high, 0 = GATE low
4 Reserved Undefined
3 TMR_LOW Status of TMR pin; 1 = TMR is lower than 0.1V, 0 = TMR is higher than 0.1V
2 EEPROM _BUSY Status of EEPROM writing; 1 = EEPROM is being written, 0 = EEPROM writing is completed
1 PG_STATUS Power good status; 1 = power good condition met, 0 = power good condition not met
0 Reserved Always returns 1
Table5. ADC_STATUS Register (0x01) – Read Only
BIT NAME OPERATION
7:4 AUX_ADC_CH Channel label of the auxiliary input that completed the latest ADC measurement in continuous or snapshot mode
AUX_ADC_CH [7:4] Auxiliary ADC Input Register Address
0000 ADIN1 0x4A
0001 ADIN2 0x4D
0010 ADIN3 0x50
0011 ADIN4 0x53
0100 ADIO1 0x56
0101 ADIO2 0x59
0110 ADIO3 0x5C
0111 ADIO4 0x5F
1000 DRNS 0x62
1001 DRAIN 0x65
1010 Reserved 0x68
1011 Reserved 0x6B
1100 ADIN2 – ADIN1 0x6E
1101 ADIN4 – ADIN3 0x71
1110 ADIO2 – ADIO1 0x74
1111 ADIO4 – ADIO3 0x77
3 ADC_IDLE Conversion status of ADC; 1 = ADC is idle in snapshot mode, 0 = ADC is in continuous mode or ADC is busy in snapshot mode
2 Reserved Always returns 0
1 Reserved Always returns 0
0 Reserved Always returns 0
LTC4283
60
Rev. A
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APPLICATIONS INFORMATION
Table6. INPUT_STATUS Register (0x02) – Read Only
BIT NAME OPERATION
7 PGIO1_INPUT State of PGIO1 pin; 1 = PGIO1 high, 0 = PGIO1 low
6 PGIO2_INPUT State of PGIO2 pin; 1 = PGIO2 high, 0 = PGIO2 low
5 PGIO3_INPUT State of PGIO3 pin; 1 = PGIO3 high, 0 = PGIO3 low
4 PGIO4_INPUT State of PGIO4 pin; 1 = PGIO4 high, 0 = PGIO4 low
3 ADIO1_INPUT State of ADIO1 pin; 1 = ADIO1 high, 0 = ADIO1 low
2 ADIO2_INPUT State of ADIO2 pin; 1 = ADIO2 high, 0 = ADIO2 low
1 ADIO3_INPUT State of ADIO3 pin; 1 = ADIO3 high, 0 = ADIO3 low
0 ADIO4_INPUT State of ADIO4 pin; 1 = ADIO4 high, 0 = ADIO4 low
Table8. FAULT Register (0x04) – Read/Write
BIT NAME OPERATION DEFAULT
7 EXT_FAULT External fault at PGIO4 pin; 1 = external fault detected, 0 = no external fault 0
6 FET_SHORT_FAULT FET short fault; 1 = FET short fault occurred, 0 = no FET short fault 0
5 POWER_FAILED VOUT was low after power good latched; 1 = VOUT low detected, 0 = VOUT has not been low 0
4 PGI_FAULT PGI fault at PGIO3 pin; 1 = PGI fault occurred, 0 = no PGI fault 0
3 FET_BAD_FAULT FET bad fault; 1 = FET bad fault occurred, 0 = no FET bad fault 0
2 OC_FAULT Overcurrent fault; 1 = overcurrent fault occurred, 0 = no overcurrent fault 0
1 UV_FAULT Undervoltage fault; 1 = undervoltage fault occurred, 0 = no undervoltage fault 0
0 OV_FAULT Overvoltage fault; 1 = overvoltage fault occurred, 0 = no overvoltage fault 0
Table7. FAULT_STATUS Register (0x03) – Read Only
BIT NAME OPERATION
7 EXT_FAULT_STATUS State of PGIO4 pin when configured to EXT_ FAULT#/EXT_FAULT; 1 = PGIO4 low/high, 0 = PGIO4 high/low
6 FET_SHORT_STATUS FET short status; 1 = FET shorted, 0 = FET not shorted
5 VOUT_LOW VOUT low status; 1 = VOUT < VOUTTH, 0 = VOUT ≥ VOUTTH
4 PGI_STATUS State of PGIO3 when configured to PGI#/PGI when PGI check timer expires; 1 = PGIO3 high/low, 0 = PGIO3 low/high
3 FET_BAD_STATUS FET bad status; 1 = FET bad condition present, 0 = FET bad condition not present
2 OC_STATUS Active current limit status; 1 = active current limit engaged, 0 = active current limit not engaged
1 UV_STATUS Input undervoltage status; 1 = UVH and UVL are low, 0 = UVH or UVL high
0 OV_STATUS Input overvoltage status; 1 = OV high, 0 = OV low
LTC4283
61
Rev. A
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APPLICATIONS INFORMATION
BIT NAME OPERATION DEFAULT
ADC_ALARM_LOG_1 (0x05) – Read/Write
7 EN#_CHANGED EN# pin changed state; 1 = EN# changed state, 0 = EN# unchanged 0
6 EEPROM_WRITTEN EEPROM was written through I2C; 1 = EEPROM was written, 0 = EEPROM write has not been written 0
5 SENSE_HIGH_ALARM SENSE+ – SENSE– was above SENSE_MAX_TH; 1 = SENSE+ – SENSE– was high, 0 = SENSE+ – SENSE–
has not been high
0
4 SENSE_LOW_ALARM SENSE+ – SENSE– was below SENSE_MIN_TH; 1 = SENSE+ – SENSE– was low, 0 = SENSE+ – SENSE– has
not been low
0
3 VPWR_HIGH_ALARM VPWR was above VPWR_MAX_TH; 1 = VPWR was high, 0 = VPWR has not been high 0
2 VPWR_LOW_ALARM VPWR was below VPWR_MIN_TH; 1 = VPWR was low, 0 = VPWR has not been low 0
1 POWER_HIGH_ALARM POWER was above POWER_MAX_TH; 1 = POWER was high, 0 = POWER has not been high 0
0 POWER_LOW_ALARM POWER was below POWER_MIN_TH; 1 = POWER was low, 0 = POWER has not been low 0
ADC_ALARM_LOG_2 (0x06) – Read/Write
7 ADIN1_HIGH_ALARM ADIN1 was above ADIN1_MAX_TH; 1 = ADIN1 was high, 0 = ADIN1 has not been high 0
6 ADIN1_LOW_ALARM ADIN1 was below ADIN1_MIN_TH; 1 = ADIN1 was low, 0 = ADIN1 has not been low 0
5 ADIN2_HIGH_ALARM ADIN2 was above ADIN2_MAX_TH; 1 = ADIN2 was high, 0 = ADIN2 has not been high 0
4 ADIN2_LOW_ALARM ADIN2 was below ADIN2_MIN_TH; 1 = ADIN2 was low, 0 = ADIN2 has not been low 0
3 ADIN3_HIGH_ALARM ADIN3 was above ADIN3_MAX_TH; 1 = ADIN3 was high, 0 = ADIN3 has not been high 0
2 ADIN3_LOW_ALARM ADIN3 was below ADIN3_MIN_TH; 1 = ADIN3 was low, 0 = ADIN3 has not been low 0
1 ADIN4_HIGH_ALARM ADIN4 was above ADIN4_MAX_TH; 1 = ADIN4 was high, 0 = ADIN4 has not been high 0
0 ADIN4_LOW_ALARM ADIN4 was below ADIN4_MIN_TH; 1 = ADIN4 was low, 0 = ADIN4 has not been low 0
ADC_ALARM_LOG_3 (0x07) – Read/Write
7 ADIO1_HIGH_ALARM ADIO1 was above ADIO1_MAX_TH; 1 = ADIO1 was high, 0 = ADIO1 has not been high 0
6 ADIO1_LOW_ALARM ADIO1 was below ADIO1_MIN_TH; 1 = ADIO1 was low, 0 = ADIO1 has not been low 0
5 ADIO2_HIGH_ALARM ADIO2 was above ADIO2_MAX_TH; 1 = ADIO2 was high, 0 = ADIO2 has not been high 0
4 ADIO2_LOW_ALARM ADIO2 was below ADIO2_MIN_TH; 1 = ADIO2 was low, 0 = ADIO2 has not been low 0
3 ADIO3_HIGH_ALARM ADIO3 was above ADIO3_MAX_TH; 1 = ADIO3 was high, 0 = ADIO3 has not been high 0
2 ADIO3_LOW_ALARM ADIO3 was below ADIO3_MIN_TH; 1 = ADIO3 was low, 0 = ADIO3 has not been low 0
1 ADIO4_HIGH_ALARM ADIO4 was above ADIO4_MAX_TH; 1 = ADIO4 was high, 0 = ADIO4 has not been high 0
0 ADIO4_LOW_ALARM ADIO4 was below ADIO4_MIN_TH; 1 = ADIO4 was low, 0 = ADIO4 has not been low 0
Table9. ADC_ALARM_LOG Registers (0x05–0x09) – Read/Write
LTC4283
62
Rev. A
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APPLICATIONS INFORMATION
BIT NAME OPERATION DEFAULT
ADC_ALARM_LOG_4 (0x08) – Read/Write
7 DRNS_HIGH_ALARM DRNS was above DRNS_MAX_TH; 1 = DRNS was high, 0 = DRNS has not been high 0
6 DRNS_LOW_ALARM DRNS was below DRNS_MIN_TH; 1 = DRNS was low, 0 = DRNS has not been low 0
5 DRAIN_HIGH_ALARM DRAIN was above DRAIN_MAX_TH; 1 = DRAIN was high, 0 = DRAIN has not been high 0
4 DRAIN_LOW_ALARM DRAIN was below DRAIN_MIN_TH; 1 = DRAIN was low, 0 = DRAIN has not been low 0
3 Reserved Undefined 0
2 Reserved Undefined 0
1 Reserved Undefined 0
0 Reserved Undefined 0
ADC_ALARM_LOG_5 (0x09) – Read/Write
7 ADIN12_HIGH_ALARM ADIN2 – ADIN1 was above ADIN12_MAX_TH; 1 = ADIN2 – ADIN1 was high, 0 = ADIN2 – ADIN1 has not
been high
0
6 ADIN12_LOW_ALARM ADIN2 – ADIN1 was below ADIN12_MIN_TH; 1 = ADIN2 – ADIN1 was low, 0 = ADIN2 – ADIN1 has not
been low
0
5 ADIN34_HIGH_ALARM ADIN4 – ADIN3 was above ADIN34_MAX_TH; 1 = ADIN4 – ADIN3 was high, 0 = ADIN4 – ADIN3 has not
been high
0
4 ADIN34_LOW_ALARM ADIN4 – ADIN3 was below ADIN34_MIN_TH; 1 = ADIN4 – ADIN3 was low, 0 = ADIN4 – ADIN3 has not
been low
0
3 ADIO12_HIGH_ALARM ADIO2 – ADIO1 was above ADIO12_MAX_TH; 1 = ADIO2 – ADIO1 was high, 0 = ADIO2 – ADIO1 has not
been high
0
2 ADIO12_LOW_ALARM ADIO2 – ADIO1 was below ADIO12_MIN_TH; 1 = ADIO2 – ADIO1 was low, 0 = ADIO2 – ADIO1 has not
been low
0
1 ADIO34_HIGH_ALARM ADIO4 – ADIO3 was above ADIO34_MAX_TH; 1 = ADIO4 – ADIO3 was high, 0 = ADIO4 – ADIO3 has not
been high
0
0 ADIO34_LOW_ALARM ADIO4 – ADIO3 was below ADIO34_MIN_TH; 1 = ADIO4 – ADIO3 was low, 0 = ADIO4 – ADIO3 has not
been low
0
LTC4283
63
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table10. CONTROL Registers (0x0A-0x0B) – Read/Write
BIT NAME OPERATION DEFAULT
CONTROL_1 (0x0A) – Read/Write
7 ON Turns MOSFET on and off; 1 = turn MOSFET on, 0 = turn MOSFET off 1
6 DVDT Enables dV/dt inrush control during startup; 1 = enabled, 0 = disabled 1
5 THERM_TMR Turns 2μa TMR pull-down off; 1 = TMR pull-down turned off, 0 = TMR pull-down turned on 0
4 FET_BAD_TURN_OFF Turns MOSFET off following a FET_BAD_FAULT; 1 = turn MOSFET off, 0 = keep MOSFET on 1
3 PWRGD_RESET_ CNTRL Configures power good reset; 1 = reset by VOUT low, 0 = reset by MOSFET off 1
2 PGIO2_ACLB Configures PGIO2; 1 = PGIO2 as inverted output for active current limit engagement after
startup; 0 = normal PGIO2 function configured by 0x10 bit[3:2]
0
1 MASS_WRITE_ ENABLE Enables mass write to all LTC4283S on the I2C bus; 1 = enabled, 0 = disabled 1
0 PAGE_READ_WRITE_ ENABLE Enables I2C page read/write protocols; 1 = enabled, 0 = disabled 1
CONTROL_2 (0x0B) – Read/Write
7 EXT_FAULT_RETRY Enables auto-retry following an EXT_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 0
6 PGI_RETRY Enables auto-retry following a PGI_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 0
5:4 FET_BAD_RETRY Configures auto-retry following a FET_BAD_FAULT and MOSFET turn off
FET_BAD_RETRY [5:4] Number of Retries
00 0 (Latch-Off)
01 1
10 7
11 Unlimited
00
3:2 OC_RETRY Configures auto-retry following an OC_FAULT
OC_RETRY [3:2] Number of Retries
00 0 (Latch-Off)
01 1
10 7
11 Unlimited
00
1 UV_RETRY Enables auto-retry following a UV_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 1
0 OV_RETRY Enables auto-retry following an OV_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 1
LTC4283
64
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table11. CONFIG Registers (0x0D-0x0F) – Read/Write
BIT NAME OPERATION DEFAULT
CONFIG_1 (0x0D) – Read/Write
7:4 ILIM Configures VILIM and VILIM(FAST)
ILIM [7:4] VILIM [mV] VILIM(FAST) [mV]
0000 15 30
0001 16 32
0010 17 34
0011 18 36
0100 19 38
0101 20 40
0110 21 42
0111 22 44
1000 23 46
1001 24 48
1010 25 50
1011 26 52
1100 27 54
1101 28 56
1110 29 58
1111 30 60
0000
3:2 FB Configures current limit foldback factor for startup and normal operation
FB [3:2] Foldback Factor, a [% VILIM]
00 100 (foldback disabled)
01 50
10 20
11 10
11
1 FB_DIS Disables foldback after startup; 1 = disabled, 0 = enabled. Foldback during startup is not affected 0
0 LPFB Enables load power foldback after startup; 1 = enabled, 0 = disabled 0
CONFIG_2 (0x0E) – Read/Write
7:6 VDTH Configures DRAIN voltage threshold for starting FET bad fault filtering timer, VD,FET(TH)
VDTH [7:6] VD,FET(TH) [mV]
00 72
01 102
10 143
11 203
11
LTC4283
65
Rev. A
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APPLICATIONS INFORMATION
BIT NAME OPERATION DEFAULT
5:4 FTBD_DL Configures FET_Bad fault filtering timer delay, tDL(FETBAD)
FTBD_DL [5:4] tDL(FETBAD) [s]
00 0.256
01 0.512
10 1.02
11 2.05
00
3:1 COOLING_DL Configures cooling delay preceding each auto-retry following OC_FAULT, FET_BAD_FAULT or
EXT_FAULT, tDL(RTRY)
COOLING_DL [3:1] tDL(RTRY) [s]
000 0.512
001 1.02
010 2.05
011 4.10
100 8.19
101 16.4
110 32.8
111 65.5
000
0 PORB Resets to 0 upon power-on reset. Write this bit to 1 to use it as power-on reset indicator: 1 =
power-on reset has not occurred, 0 = power-on reset occurred
0
CONFIG_3 (0x0F) – Read/Write
BIT NAME OPERATION DEFAULT
7 EXTFLT_TURN_OFF Turns MOSFET off following an external fault; 1 = turn MOSFET off, 0 = keep MOSFET on 0
6 VPWR_SELECT Selects voltage for ADC power multiplication; 1 = selects DRNS (attenuated drain voltage for
MOSFET power), 0 = selects RTNS (attenuated input voltage for input power)
0
5 FAST_I2C_EN Enables fast I2C mode; 1 = fast I2C enabled, 0 = fast I2C disabled 0
4:3 BC Configures bit rate of single-wire broadcast mode, fBC
BC [4:3] fBC [kbit/s]
00 2048
01 512
10 128 (Not available for 8-bit ADC)
11 32 (Not available for 8-bit ADC)
00
2 TICK_OVERFLOW_ ALERT Enables alert when tick counter overflows; 1 = alert enabled, 0 = alert disabled 0
1 METER_OVERFLOW_ ALERT Enables alert when energy meter overflows; 1 = alert enabled, 0 = alert disabled 0
0 INTEGRATE_I Enables integration of current; 1 = integrate current, 0 = integrate power 0
LTC4283
66
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table12. PGIO_CONFIG Registers (0x10:0x11) – Read/Write
BIT NAME OPERATION DEFAULT
PGIO_CONFIG_1 (0x10) – Read/Write
7:6 PGIO4_CONFIG Configures behavior of PGIO4 pin
PGIO4_CONFIG [7:6] PGIO4
00 EXT_ FAULT#
01 EXT_FAULT
10 General purpose output
11 General purpose input
00
5:4 PGIO3_CONFIG Configures behavior of PGIO3 pin
PGIO3_CONFIG [5:4] PGIO3
00 PGI#
01 PGI
10 General purpose output
11 General purpose input
00
3:2 PGIO2_CONFIG Configures behavior of PGIO2 pin
PGIO2_CONFIG [3:2] PGIO2
00 Power Good 2#
01 Power Good 2
10 General purpose output
11 General purpose input
00
1:0 PGIO1_CONFIG Configures behavior of PGIO1 pin
PGIO1_CONFIG [1:0] PGIO1
00 Power Good 1#
01 Power Good 1
10 General purpose output
11 General purpose input
00
PGIO_CONFIG_2 (0x11) – Read/Write
7 PGIO4_OUT Output data bit to PGIO4 pin when configured as general purpose output 0
6 PGIO3_OUT Output data bit to PGIO3 pin when configured as general purpose output 0
5 PGIO2_OUT Output data bit to PGIO2 pin when configured as general purpose output 0
4 PGIO1_OUT Output data bit to PGIO1 pin when configured as general purpose output 0
3 ADC_CONV_ALERT Enables alert when ADC finishes making a conversion; 1 = enable alert, 0 = disable alert 0
2:0 ADC Configures ADC resolution and conversion rate
ADC [2:0]
ADC Resolution
[Bits]
ADC Conversion Rate
fCONV [Hz]
Sampling Clock Frequency
fs [kHz]
000 8 996 512
010 10 125 256
100 12 15.6 128
110 14 3.91 128
xx1 16 0.977 128
100
LTC4283
67
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table13. ADIO_CONFIG Register (0x12) – Read/Write
BIT NAME OPERATION DEFAULT
7 ADIO4_CONFIG Configures behavior of ADIO4 pin; 1 = general purpose input, 0 = general purpose output 1
6 ADIO3_CONFIG Configures behavior of ADIO3 pin; 1 = general purpose input, 0 = general purpose output 1
5 ADIO2_CONFIG Configures behavior of ADIO2 pin; 1 = general purpose input, 0 = general purpose output 1
4 ADIO1_CONFIG Configures behavior of ADIO1 pin; 1 = general purpose input, 0 = general purpose output 1
3 ADIO4_OUT Output data bit to ADIO4 pin when configured as general purpose output 0
2 ADIO3_OUT Output data bit to ADIO3 pin when configured as general purpose output 0
1 ADIO2_OUT Output data bit to ADIO2 pin when configured as general purpose output 0
0 ADIO1_OUT Output data bit to ADIO1 pin when configured as general purpose output 0
Table14. ADC_SELECT Registers (0x13-0x14) – Read/Write
BIT NAME OPERATION DEFAULT
ADC_SELECT_1 (0x13) – Read/Write
7 ADIO4_SELECT Selects ADIO4 as input for ADC measurement; 1 = selected, 0 = not selected 1
6 ADIO3_SELECT Selects ADIO3 as input for ADC measurement; 1 = selected, 0 = not selected 1
5 ADIO2_SELECT Selects ADIO2 as input for ADC measurement; 1 = selected, 0 = not selected 1
4 ADIO1_SELECT Selects ADIO1 as input for ADC measurement; 1 = selected, 0 = not selected 1
3 ADIN4_SELECT Selects ADIN4 as input for ADC measurement; 1 = selected, 0 = not selected 1
2 ADIN3_SELECT Selects ADIN3 as input for ADC measurement; 1 = selected, 0 = not selected 1
1 ADIN2_SELECT Selects ADIN2 as input for ADC measurement; 1 = selected, 0 = not selected 1
0 ADIN1_SELECT Selects ADIN1 as input for ADC measurement; 1 = selected, 0 = not selected 1
ADC_SELECT_2 (0x14) – Read/Write
7 ADIO34_SELECT Selects ADIO4 – ADIO3 as input for ADC measurement; 1 = selected, 0 = not selected 0
6 ADIO12_SELECT Selects ADIO2 – ADIO1 as input for ADC measurement; 1 = selected, 0 = not selected 0
5 ADIN34_SELECT Selects ADIN4 – ADIN3 as input for ADC measurement; 1 = selected, 0 = not selected 0
4 ADIN12_SELECT Selects ADIN2 – ADIN1 as input for ADC measurement; 1 = selected, 0 = not selected 0
3 Reserved Undefined 1
2 Reserved Undefined 1
1 DRAIN_SELECT Selects DRAIN as input for ADC measurement; 1 = selected, 0 = not selected 1
0 DRNS_SELECT Selects DRNS as input for ADC measurement; 1 = selected, 0 = not selected 1
Table15. FAULT_ALERT Register (0x15) – Read/Write
BIT NAME OPERATION DEFAULT
7 EXT_FAULT_ALERT Enables alert for external fault; 1 = enable alert, 0 = disable alert 0
6 FET_SHORT_ALERT Enables alert for FET short fault; 1 = enable alert, 0 = disable alert 0
5 POWER_FAILED_ ALERT Enables alert for power failed fault; 1 = enable alert, 0 = disable alert 0
4 PGI_ALERT Enables alert for PGI fault; 1 = enable alert, 0 = disable alert 0
3 FET_BAD_ALERT Enables alert for FET bad fault; 1 = enable alert, 0 = disable alert 0
2 OC_ALERT Enables alert for overcurrent fault; 1 = enable alert, 0 = disable alert 0
1 UV_ALERT Enables alert for undervoltage fault; 1 = enable alert, 0 = disable alert 0
0 OV_ALERT Enables alert for overvoltage fault; 1 = enable alert, 0 = disable alert 0
LTC4283
68
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
BIT NAME OPERATION DEFAULT
ADC_ALERT_1 (0x16) – Read/Write
7 EN#_CHANGED_ALERT Enables alert when EN# pin changed state; 1 = enable alert, 0 = disable alert 0
6 EEPROM_WRITTEN_ALERT Enables alert when EEPROM is written through I2C; 1 = enable alert, 0 = disable alert 0
5 SENSE_HIGH_ALERT Enables alert when SENSE+ – SENSE– was above SENSE_MAX_TH; 1 = enable alert, 0 = disable alert 0
4 SENSE_LOW_ALERT Enables alert when SENSE+ – SENSE– was below SENSE_MIN_TH; 1 = enable alert, 0 = disable alert 0
3 VPWR_HIGH_ALERT Enables alert when VPWR was above VPWR_MAX_TH; 1 = enable alert, 0 = disable alert 0
2 VPWR_LOW_ALERT Enables alert when VPWR was below VPWR_MIN_TH; 1 = enable alert, 0 = disable alert 0
1 POWER_HIGH_ALERT Enables alert when POWER was above POWER_MAX_TH; 1 = enable alert, 0 = disable alert 0
0 POWER_LOW_ALERT Enables alert when POWER was below POWER_MIN_TH; 1 = enable alert, 0 = disable alert 0
ADC_ALERT_2 (0x17) – Read/Write
7 ADIN1_HIGH_ALERT Enables alert when ADIN1 was above ADIN1_MAX_TH; 1 = enable alert, 0 = disable alert 0
6 ADIN1_LOW_ALERT Enables alert when ADIN1 was below ADIN1_MIN_TH; 1 = enable alert, 0 = disable alert 0
5 ADIN2_HIGH_ALERT Enables alert when ADIN2 was above ADIN2_MAX_TH; 1 = enable alert, 0 = disable alert 0
4 ADIN2_LOW_ALERT Enables alert when ADIN2 was below ADIN2_MIN_TH; 1 = enable alert, 0 = disable alert 0
3 ADIN3_HIGH_ALERT Enables alert when ADIN3 was above ADIN3_MAX_TH; 1 = enable alert, 0 = disable alert 0
2 ADIN3_LOW_ALERT Enables alert when ADIN3 was below ADIN3_MIN_TH; 1 = enable alert, 0 = disable alert 0
1 ADIN4_HIGH_ALERT Enables alert when ADIN4 was above ADIN4_MAX_TH; 1 = enable alert, 0 = disable alert 0
0 ADIN4_LOW_ALERT Enables alert when ADIN4 was below ADIN4_MIN_TH; 1 = enable alert, 0 = disable alert 0
ADC_ALERT_3 (0x18) – Read/Write
7 ADIO1_HIGH_ALERT Enables alert when ADIO1 was above ADIO1_MAX_TH; 1 = enable alert, 0 = disable alert 0
6 ADIO1_LOW_ALERT Enables alert when ADIO1 was below ADIO1_MIN_TH; 1 = enable alert, 0 = disable alert 0
5 ADIO2_HIGH_ALERT Enables alert when ADIO2 was above ADIO2_MAX_TH; 1 = enable alert, 0 = disable alert 0
4 ADIO2_LOW_ALERT Enables alert when ADIO2 was below ADIO2_MIN_TH; 1 = enable alert, 0 = disable alert 0
3 ADIO3_HIGH_ALERT Enables alert when ADIO3 was above ADIO3_MAX_TH; 1 = enable alert, 0 = disable alert 0
2 ADIO3_LOW_ALERT Enables alert when ADIO3 was below ADIO3_MIN_TH; 1 = enable alert, 0 = disable alert 0
1 ADIO4_HIGH_ALERT Enables alert when ADIO4 was above ADIO4_MAX_TH; 1 = enable alert, 0 = disable alert 0
0 ADIO4_LOW_ALERT Enables alert when ADIO4 was below ADIO4_MIN_TH; 1 = enable alert, 0 = disable alert 0
ADC_ALERT_4 (0x19) – Read/Write
7 DRNS_HIGH_ALERT Enables alert when DRNS was above DRNS_MAX_TH; 1 = enable alert, 0 = disable alert 0
6 DRNS_LOW_ALERT Enables alert when DRNS was below DRNS_MIN_TH; 1 = enable alert, 0 = disable alert 0
5 DRAIN_HIGH_ALERT Enables alert when DRAIN was above DRAIN_MAX_TH; 1 = enable alert, 0 = disable alert 0
4 DRAIN_LOW_ALERT Enables alert when DRAIN was below DRAIN_MIN_TH; 1 = enable alert, 0 = disable alert 0
3 Reserved Undefined 0
2 Reserved Undefined 0
1 Reserved Undefined 0
0 Reserved Undefined 0
Table16. ADC_ALERT Registers (0x16-0x1A) – Read/Write
LTC4283
69
Rev. A
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APPLICATIONS INFORMATION
BIT NAME OPERATION DEFAULT
ADC_ALERT_5 (0x1A) – Read/Write
7 ADIN12_HIGH_ALERT Enables alert when ADIN2 – ADIN1 was above ADIN12_MAX_TH; 1 = enable alert, 0 = disable alert 0
6 ADIN12_LOW_ALERT Enables alert when ADIN2 – ADIN1 was below ADIN12_MIN_TH; 1 = enable alert, 0 = disable alert 0
5 ADIN34_HIGH_ALERT Enables alert when ADIN4 – ADIN3 was above ADIN34_MAX_TH; 1 = enable alert, 0 = disable alert 0
4 ADIN34_LOW_ALERT Enables alert when ADIN4 – ADIN3 was below ADIN34_MIN_TH; 1 = enable alert, 0 = disable alert 0
3 ADIO12_HIGH_ALERT Enables alert when ADIO2 – ADIO1 was above ADIO12_MAX_TH; 1 = enable alert, 0 = disable alert 0
2 ADIO12_LOW_ALERT Enables alert when ADIO2 – ADIO1 was below ADIO12_MIN_TH; 1 = enable alert, 0 = disable alert 0
1 ADIO34_HIGH_ALERT Enables alert when ADIO4 – ADIO3 was above ADIO34_MAX_TH; 1 = enable alert, 0 = disable alert 0
0 ADIO34_LOW_ALERT Enables alert when ADIO4 – ADIO3 was below ADIO34_MIN_TH; 1 = enable alert, 0 = disable alert 0
Table17. ENERGY Registers (0x7A-0x7F) – Read/Write
BIT NAME OPERATION DEFAULT
47:0 ENERGY Data of metered energy 0x0000_0000_0000
Table18. TICK_COUNTER Registers (0x80-0x83) – Read/Write
BIT NAME OPERATION DEFAULT
31:0 TICK_COUNTER Counts number of ADC conversion cycles that power measurements have been accumulated
in the energy meter
0x0000_0000
Table19. METER_CONTROL Register (0x84) – Read/Write
BIT NAME OPERATION DEFAULT
7 METER_RESET Resets energy meter and tick counter until cleared; 1 = reset, 0 = reset cleared 0
6 METER_HALT Halts energy meter and tick counter from accumulating; 1 = halted, 0 = not halted 0
5 TICK_OVERFLOW Tick counter has overflowed; 1 = overflowed, 0 = not overflowed 0
4 METER_OVERFLOW Energy meter accumulator has overflowed; 1 = overflowed, 0 = not overflowed 0
3 ALERT_GENERATED Latched to 1 when an alert is generated and can only be cleared via I2C; 1 = alert generated,
0 = alert has not been generated
0
2 EE_LOCK EEPROM lock status, read only; 1 = EEPROM is factory locked, 0 = EEPROM is not factory locked 0
1:0 Reserved Read only, always returns 0 00
LTC4283
70
Rev. A
For more information www.analog.com
APPLICATIONS INFORMATION
Table20. ADC_SNAPSHOT Register (0x85) — Read/Write
BIT NAME OPERATION DEFAULT
7:4 SNAPSHOT_SEL Selects one of the 16 ADC auxiliary inputs for snapshot measurement
SNAPSHOT_SEL [7:4] Auxiliary ADC Input
0000 ADIN1
0001 ADIN2
0010 ADIN3
0011 ADIN4
0100 ADIO1
0101 ADIO2
0110 ADIO3
0111 ADIO4
1000 DRNS
1001 DRAIN
1010 Reserved
1011 Reserved
1100 ADIN2 – ADIN1
1101 ADIN4 – ADIN3
1110 ADIO2 – ADIO1
1111 ADIO4 – ADIO3
0000
3 ADC_HALT Enables ADC snapshot mode; 1 = snapshot, 0 = continuous conversion 0
2:0 Reserved Read only, always returns 0 000
Table21. FAULT_LOG_CONTROL Register (0x90) – Read/Write
BIT NAME OPERATION DEFAULT
7 FAULT_LOG_ENABLE Enables logging fault registers and ADC data into EEPROM upon a fault; this bit can only be
cleared using I2C; 1 = fault log enabled, 0 = fault log disabled
0
6 FAULT_LOG_UNLOCK Allows clearing of FAULT_LOG_START and FAULT_LOG_DONE bits to re-enable fault log
following a previous fault log; 1 = clearing allowed, 0 = clearing not allowed
0
5 FAULT_LOG_START Indicates a fault log is started; I2C can not set this bit but can clear it; 1 = fault log started, 0 =
fault log has not been started
0
4 FAULT_LOG_DONE Indicates a fault log is completed; I2C can not set this bit but can clear it; 1 = fault log
completed, 0 = fault log has not been completed
0
3 FAULT_LOG_ALERT Enables alert when a fault log is completed; 1 = enable alert, 0 = disable alert 0
2:0 Reserved Read only, always returns 0 000
LTC4283
71
Rev. A
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Table22. Registers Recorded to EEPROM During Fault Log
REGISTER NAME
REGISTER
ADDRESS
EEPROM
ADDRESS
DATA LENGTH
(BYTES) DESCRIPTION
FAULT 0x04 0xA4 1 System fault
ADC_ALARM_LOG 0x05-0x09 0xA5-0xA9 5 ADC measurement alarms
SENSE 0x41 0xE1 1 MSB byte of most recent ADC output for SENSE+ – SENSE–
SENSE_MIN 0x42 0xE2 1 MSB byte of minimum ADC output for SENSE+ – SENSE–
SENSE_MAX 0x43 0xE3 1 MSB byte of maximum ADC output for SENSE+ – SENSE–
VPWR 0x44 0xE4 1 MSB byte of most recent ADC output for VPWR voltage
VPWR_MIN 0x45 0xE5 1 MSB byte of minimum ADC output for VPWR voltage
VPWR_MAX 0x46 0xE6 1 MSB byte of maximum ADC output for VPWR voltage
APPLICATIONS INFORMATION
Table23. REBOOT Register (0xA2) – Read/Write
BIT NAME OPERATION DEFAULT
7 RBT_EN Controls auto-reboot; 1 = reboot after delay tDL(RBT), 0 = no reboot. When set to 1, this bit remains
1 after reboot is done. Clear it before issuing the next reboot command
0
6:4 RBT_DL Configures delay for auto-reboot, tDL(RBT), after the REBOOT bit is set to 1
RBT_DL [6:4] tDL(RBT) [s]
000 0.512
001 1.02
010 2.05
011 4.10
100 8.19
101 16.4
110 32.8
111 65.5
000
3:2 Reserved Read only, always returns 0 00
1 DELAY_STATUS Reboot and cooling delay status; 1 = device is going through a reboot or cooling delay or in latch-
off, 0 = reboot or cooling delay has expired or has not been initiated
0
0 WP_STATUS WP pin status; 1 = WP is high, 0 = WP pin is low 0
Table24. Mapping between Faults/Alarms and Alert Masks
FAULT/ALARM ALERT MASK
FAULT 0x04 [7:0] FAULT_ALERT 0x15 [7:0]
ADC_ALARM_LOG_1 0x05 [7:0] ADC_ALERT_1 0x16 [7:0]
ADC_ALARM_LOG_2 0x06 [7:0] ADC_ALERT_2 0x17 [7:0]
ADC_ALARM_LOG_3 0x07 [7:0] ADC_ALERT_3 0x18 [7:0]
ADC_ALARM_LOG_4 0x08 [7:0] ADC_ALERT_4 0x19 [7:0]
ADC_ALARM_LOG_5 0x09 [7:0] ADC_ALERT_5 0x1A [7:0]
METER_CONTROL 0x84[4:3] CONFIG_3 0x0F [2:1]
ADC Conversion Completed PGIO_CONFIG_2 0x11 [3]
EEPROM Fault Log Completed FAULT_LOG_CONTROL 0x90 [3]
LTC4283
72
Rev. A
For more information www.analog.com
PACKAGE DESCRIPTION
5.00 ±0.10
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
PIN 1
TOP MARK
(SEE NOTE 6)
37
1
2
38
BOTTOM VIEW—EXPOSED PAD
5.50 REF
5.15 ±0.10
7.00
±0.10
0.75 ±0.05
R = 0.125
TYP
R = 0.10
TYP
0.25 ±0.05
(UH) QFN REF C 1107
0.50 BSC
0.200 REF
0.00 – 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
3.00 REF
3.15 ±0.10
0.40 ±0.10
0.70 ±0.05
0.50 BSC
5.5 REF
3.00 REF 3.15 ±0.05
4.10 ±0.05
5.50 ±0.05 5.15 ±0.05
6.10 ±0.05
7.50 ±0.05
0.25 ±0.05
PACKAGE
OUTLINE
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°
CHAMFER
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701 Rev C)
LTC4283
73
Rev. A
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
REV DATE DESCRIPTION PAGE NUMBER
A 07/20 Patent information added.
Typical Application: Changed 1W to 0.25W.
Applications Informations section: Figure 1 and Figure 13. Changed 1W to 0.25W.
Added Revision History.
Edits to Related Parts section.
1
1
19
73
74
LTC4283
74
Rev. A
For more information www.analog.com
ANALOG DEVICES, INC. 2020
07/20
www.analog.com
PART NUMBER DESCRIPTION COMMENTS
LTC4284 –48V High Power Hot Swap Controller with
Energy Monitor
Dual Gate Drives, SOA Timer, 8- to 16-Bit ADC Monitors Current, Voltage,
Power and Energy, Internal EEPROM, I2C or Single-Wire Broadcast
LTC4261/LT4261-2 –48V Hot Swap Controller with ADC and I2CdV/dt Startup Inrush, 10-Bit ADC Monitors Voltages and Current, I2C or Single-
Wire Broadcast, Two Sequenced Power Good Outputs, Supplies from –12V
ADM1075 –48V Hot Swap Controller with PMBus 12-Bit ADC Monitors Current, Voltage, Power and Energy
LTC4282/LTC4281 High Current Positive Voltage Hot Swap Controller
with I2C Compatible Monitoring
Dual/SINGLE Gate Drive, 12- or 16-Bit ADC Monitors Current, Voltage, Power
and Energy, Internal EEPROM, I2C, Supplies from 2.9V to 33V
LT4250L/LT4250H –48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from –18V to –80V
LTC4251/LTC4251-1 –48V Hot Swap Controller in SOT-23 Fast Active Current Limiting, supplies from –15V
LTC4252-1/LTC4252-2/
LTC4252A-1/LTC4252A-2
–48V Hot Swap Controller in MS8 Fast Active Current Limiting, Supplies from –15V, ±1% UV/OV (LTC4252A)
LTC4253 –48V Hot Swap Controller with Sequencer Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies
from –15V
LTC4260 Positive High Voltage Hot Swap Controller With I2C and 8-Bit ADC, Supplies from 8.5V to 80V
LTC4371 Negative Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 220ns Turn-Off
LTC4151 High Voltage Current and Voltage Monitor Operates from 7V to 80V, with I2C and 12-Bit ADC
RELATED PARTS
TYPICAL APPLICATION
R3
487k
1%
C
V
CC
1µF
0.5mΩ
R
S1
R
DB
5.11k
1%
M1
PSMN4R8-100BSE
×2
R
D
100k
R2
14.3k
1%
R1
10k
1%
R
RT
200k
1%
R
RB
5.11k
1%
R
DT
200k
1%
Q
IN
BCP56
R
Z
100k
C
IN
0.1µF
C
Z
0.1µF
R4
1k
3
4
4
R
TH4
2k
1%
R
TH3
2k
1%
R
TH2
20k
1%
R
TH1
10k AT
25°C
–48V RTN
UVH
UVL
OV
–48V INPUT
V
EE
INTV
CC
SENSE–
SENSE+
GATE
DRAIN
RTNS
SCL
SDAI
SDAO
LTC4283
–48V RTN
(SHORT PIN)
V
EE
DRNS
V
EE
V
EE
V
EE
V
Z
V
IN
V
EE
MICRO-
CONTROLLER
DIN
GND
ADuM1100
ADR1
VDD1
VDD2
3.3V
VDD
V
O
V
I
GND1
GND2
ADIN1-4
ADIO1-3
PGIO1-4
ADIO4
R
TH1
: TDK NTCG064BH103JTB
T(°C) = (55 • ADIO4 ADC READING • 31.25E-06) – 28
ADR0
V
EE
4283 F29
C
L
500µF
BATTERY OPERATED
(SUBJECT TO –36V
INPUT STEPS)
V
OUT
VLOAD
+
–
Figure29. –48V/600W Hot Swap Controller Monitoring System Status, Faults, Currents, Voltages,
Power and Temperature and Transmitting Data at 2MBit/s in Single-Wire Broadcast Mode
