W25Q32DW
Publication Release Date: September 18, 2012
- 1 - Revision D
1.8V 32M-BIT
SERIAL FLASH MEMORY WITH
DUAL/QUAD SPI & QPI
W25Q32DW
- 2 -
Table of Contents
1. GENERAL DESCRIPTION ............................................................................................................... 5
2. FEATURES ....................................................................................................................................... 5
3. PIN CONFIGURATION SOIC 208-MIL ............................................................................................. 6
4. PAD CONFIGURATION WSON 6X5-MM / 8X6-MM ........................................................................ 6
5. PIN DESCRIPTION SOIC 208-MIL, WSON 6X5/8X6-MM ............................................................... 6
6. PIN CONFIGURATION SOIC 300-MIL ............................................................................................. 7
7. PIN DESCRIPTION SOIC 300-MIL .................................................................................................. 7
7.1 Package Types ..................................................................................................................... 8
7.2 Chip Select (/CS) .................................................................................................................. 8
7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3) ..................................... 8
7.4 Write Protect (/WP) .............................................................................................................. 8
7.5 HOLD (/HOLD) ..................................................................................................................... 8
7.6 Serial Clock (CLK) ................................................................................................................ 8
8. BLOCK DIAGRAM ............................................................................................................................ 9
9. FUNCTIONAL DESCRIPTION ....................................................................................................... 10
9.1 SPI/QPI OPERATIONS ...................................................................................................... 10
9.1.1 Standard SPI Instructions ..................................................................................................... 10
9.1.2 Dual SPI Instructions ............................................................................................................ 10
9.1.3 Quad SPI Instructions ........................................................................................................... 11
9.1.4 QPI Instructions .................................................................................................................... 11
9.1.5 Hold Function ....................................................................................................................... 11
9.2 WRITE PROTECTION ....................................................................................................... 12
9.2.1 Write Protect Features ......................................................................................................... 12
10. CONTROL AND STATUS REGISTERS ......................................................................................... 13
10.1 STATUS REGISTER .......................................................................................................... 13
10.1.1 BUSY .................................................................................................................................. 13
10.1.2 Write Enable Latch (WEL) .................................................................................................. 13
10.1.3 Block Protect Bits (BP2, BP1, BP0) .................................................................................... 13
10.1.4 Top/Bottom Block Protect (TB) ........................................................................................... 13
10.1.5 Sector/Block Protect (SEC) ................................................................................................ 13
10.1.6 Complement Protect (CMP) ................................................................................................ 14
10.1.7 Status Register Protect (SRP1, SRP0) ............................................................................... 14
10.1.8 Erase/Program Suspend Status (SUS) .............................................................................. 14
10.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0) .............................................................. 14
10.1.10 Quad Enable (QE) ............................................................................................................ 15
10.1.11 W25Q32DW Status Register Memory Protection (CMP = 0) ........................................... 16
10.1.12 W25Q32DW Status Register Memory Protection (CMP = 1) ........................................... 17
W25Q32DW
10.2 INSTRUCTIONS ................................................................................................................. 18
Publication Release Date: September 18, 2012
- 3 - Revision D
10.2.1 Manufacturer and Device Identification .............................................................................. 18
10.2.2 Instruction Set Table 1 (Standard SPI Instructions) ........................................................... 19
10.2.3 Instruction Set Table 2 (Dual SPI Instructions) ................................................................... 20
10.2.4 Instruction Set Table 3 (Quad SPI Instructions) ................................................................. 20
10.2.5 Instruction Set Table 4 (QPI Instructions) ........................................................................... 21
10.2.6 Write Enable (06h) ............................................................................................................. 23
10.2.7 Write Enable for Volatile Status Register (50h) .................................................................. 23
10.2.8 Write Disable (04h) ............................................................................................................. 24
10.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h) ...................................... 24
10.2.10 Write Status Register (01h) .............................................................................................. 25
10.2.11 Read Data (03h) ............................................................................................................... 27
10.2.12 Fast Read (0Bh) ............................................................................................................... 28
10.2.13 Fast Read Dual Output (3Bh) ........................................................................................... 30
10.2.14 Fast Read Quad Output (6Bh) .......................................................................................... 31
10.2.15 Fast Read Dual I/O (BBh) ................................................................................................. 32
10.2.16 Fast Read Quad I/O (EBh) ............................................................................................... 34
10.2.17 Word Read Quad I/O (E7h) .............................................................................................. 37
10.2.18 Octal Word Read Quad I/O (E3h) ..................................................................................... 39
10.2.19 Set Burst with Wrap (77h) ................................................................................................ 41
10.2.20 Page Program (02h) ......................................................................................................... 42
10.2.21 Quad Input Page Program (32h) ...................................................................................... 44
10.2.22 Sector Erase (20h) ........................................................................................................... 44
10.2.23 32KB Block Erase (52h) ................................................................................................... 46
10.2.24 64KB Block Erase (D8h) ................................................................................................... 47
10.2.25 Chip Erase (C7h / 60h) ..................................................................................................... 48
10.2.26 Erase / Program Suspend (75h) ....................................................................................... 49
10.2.27 Erase / Program Resume (7Ah) ....................................................................................... 51
10.2.28 Power-down (B9h) ............................................................................................................ 52
10.2.29 Release Power-down / Device ID (ABh) ........................................................................... 53
10.2.30 Read Manufacturer / Device ID (90h) ............................................................................... 55
10.2.31 Read Manufacturer / Device ID Dual I/O (92h) ................................................................. 56
10.2.32 Read Manufacturer / Device ID Quad I/O (94h) ............................................................... 57
10.2.33 Read Unique ID Number (4Bh)......................................................................................... 58
10.2.34 Read JEDEC ID (9Fh) ...................................................................................................... 59
10.2.35 Erase Security Registers (44h) ......................................................................................... 60
10.2.36 Program Security Registers (42h) .................................................................................... 61
10.2.37 Read Security Registers (48h) ......................................................................................... 62
10.2.38 Set Read Parameters (C0h) ............................................................................................. 63
10.2.39 Burst Read with Wrap (0Ch) ............................................................................................. 64
10.2.40 Enable QPI (38h) .............................................................................................................. 65
W25Q32DW
10.2.41 Disable QPI (FFh) ............................................................................................................. 66
- 4 -
10.2.42 Enable Reset (66h) and Reset (99h) ................................................................................ 67
11. ELECTRICAL CHARACTERISTICS ............................................................................................... 68
11.1 Absolute Maximum Ratings ................................................................................................ 68
11.2 Operating Ranges............................................................................................................... 68
11.3 Power-Up Power-Down Timing and Requirements ............................................................ 69
11.4 DC Electrical Characteristics .............................................................................................. 70
11.5 AC Measurement Conditions .............................................................................................. 71
11.6 AC Electrical Characteristics .............................................................................................. 72
11.7 AC Electrical Characteristics (cont’d) ................................................................................. 73
11.8 Serial Output Timing ........................................................................................................... 74
11.9 Serial Input Timing .............................................................................................................. 74
11.10 Hold Timing ....................................................................................................................... 74
12. PACKAGE SPECIFICATION .......................................................................................................... 75
12.1 8-Pin SOIC 208-mil (Package Code SS) ............................................................................ 75
12.2 8-Contact 6x5mm WSON (Package Code ZP) .................................................................. 76
12.3 8-Contact 8x6mm WSON (Package Code ZE) .................................................................. 78
12.4 16-Pin SOIC 300-mil (Package Code SF) .......................................................................... 79
13. ORDERING INFORMATION .......................................................................................................... 80
13.1 Valid Part Numbers and Top Side Marking ........................................................................ 81
14. REVISION HISTORY ...................................................................................................................... 82
W25Q32DW
Publication Release Date: September 18, 2012
- 5 - Revision D
1. GENERAL DESCRIPTION
The W25Q32DW (32M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 1.7V to 1.95V power supply with current
consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving
packages.
The W25Q32DW array is organized into 16,384 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q32DW
has 1,024 erasable sectors and 64 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See figure 2.)
The W25Q32DW support the standard Serial Peripheral Interface (SPI), Dual/Quad I/O SPI as well as 2-
clocks instruction cycle Quad Peripheral Interface (QPI): Serial Clock, Chip Select, Serial Data I/O0 (DI),
I/O1 (DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 416MHz (104MHz x 4) for Quad I/O when
using the Fast Read Dual/Quad I/O and QPI instructions. These transfer rates can outperform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top or bottom array control,
provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and
device identification, a 64-bit Unique Serial Number and four 256-bytes Security Registers.
2. FEATURES
• Family of SpiFlash Memories
– W25Q32DW: 32M-bit / 4M-byte (4,194,304)
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– QPI: CLK, /CS, IO0, IO1, IO2, IO3
• Highest Performance Serial Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/s continuous data transfer rate
– More than 100,000 erase/program cycles
– More than 20-year data retention
• Efficient “Continuous Read” and QPI Mode
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Quad Peripheral Interface (QPI) reduces
instruction overhead
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
• Low Power, Wide Temperature Range
– Single 1.7 to 1.95V supply
– 4mA active current, <1µA Power-down (typ.)
– -40°C to +85°C operating range
• Flexible Architecture with 4KB sectors
– Uniform Sector Erase (4K-bytes)
– Uniform Block Erase (32K and 64K-bytes)
– Program 1 to 256 byte per programmable page
– Erase/Program Suspend & Resume
• Advanced Security Features
– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Power Supply Lock-Down and OTP protection
– 64-Bit Unique ID for each device
– 4X256-Bytes Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
• Space Efficient Packaging
– 8-pin SOIC 208-mil
– 8-pad WSON 6x5-mm/8x6-mm
– 16-pin SOIC 300-mil
– Contact Winbond for KGD and other options
W25Q32DW
- 6 -
3. PIN CONFIGURATION SOIC 208-MIL
1
2
3
4
8
7
6
5
/CS
DO (IO
1
)
/WP (IO
2
)
GND
VCC
/HOLD (IO
3
)
DI (IO
0
)
CLK
Top View
Figure 1a. W25Q32DW Pin Assignments, 8-pin SOIC 208-mil (Package Code SS)
4. PAD CONFIGURATION WSON 6X5-MM / 8X6-MM
1
2
3
4
/CS
DO (IO
1
)
/WP (IO
2
)
GND
VCC
/HOLD (IO
3
)
DI (IO
0
)
CLK
Top View
8
7
6
5
Figure 1b. W25Q32DW Pad Assignments, 8-pad WSON (Package Code ZP & ZE)
5. PIN DESCRIPTION SOIC 208-MIL, WSON 6X5/8X6-MM
PIN NO. PIN NAME I/O FUNCTION
1 /CS I Chip Select Input
2 DO (IO1) I/O Data Output (Data Input Output 1)*1
3 /WP (IO2) I/O Write Protect Input ( Data Input Output 2)*2
4 GND Ground
5 DI (IO0) I/O Data Input (Data Input Output 0)*1
6 CLK I Serial Clock Input
7 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2
8 VCC Power Supply
*1 IO0 and IO1 are used for Standard and Dual SPI instructions
*2 IO0 – IO3 are used for Quad SPI/QPI instructions
W25Q32DW
Publication Release Date: September 18, 2012
- 7 - Revision D
6. PIN CONFIGURATION SOIC 300-MIL
1
2
3
4
/CS
DO (IO
1
)/
2
)
GND
VCC
/HOLD (IO
3
)
DI (IO
0
)
CLK
Top View
NC
NC
NC
NC
NC
NC
NC
NC5
6
7
8
10
9
11
12
13
14
15
16
WP (IO
Figure 1c. W25Q32DW Pin Assignments, 16-pin SOIC 300-mil (Package Code SF)
7. PIN DESCRIPTION SOIC 300-MIL
PAD NO. PAD NAME I/O FUNCTION
1 /HOLD (IO3) I/O Hold Input (Data Input Output 3)*2
2 VCC Power Supply
3 N/C No Connect
4 N/C No Connect
5 N/C No Connect
6 N/C No Connect
7 /CS I Chip Select Input
8 DO (IO1) I/O Data Output (Data Input Output 1)*1
9 /WP (IO2) I/O Write Protect Input (Data Input Output 2)*2
10 GND Ground
11 N/C No Connect
12 N/C No Connect
13 N/C No Connect
14 N/C No Connect
15 DI (IO0) I/O Data Input (Data Input Output 0)*1
16 CLK I Serial Clock Input
*1 IO0 and IO1 are used for Standard and Dual SPI instructions
*2 IO0 – IO3 are used for Quad SPI/QPI instructions
W25Q32DW
- 8 -
7.1 Package Types
At the time this datasheet was published, not all package types had been finalized. Contact Winbond to
confirm availability of these packages before designing to this specification. W25Q32DW is offered in an
8-pin plastic 208-mil width SOIC (package code SS), a WSON 6x5-mm or 8X6-mm (package code ZP &
ZE) and a 16-pin plastic 300-mil width SOIC (package code SF) as shown in Figure 1a, 1b, 1c. Package
diagrams and dimensions are illustrated at the end of this datasheet.
7.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high, the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low, the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and figure 43).
If needed a pull-up resister on /CS can be used to accomplish this.
7.3 Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2, IO3)
The W25Q32DW supports standard SPI, Dual SPI, Quad SPI and QPI operation. Standard SPI
instructions use the unidirectional DI (input) pin to serially write instructions, addresses or data to the
device on the rising edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO
(output) to read data or status from the device on the falling edge of CLK.
Dual/Quad SPI and QPI instructions use the bidirectional IO pins to serially write instructions, addresses
or data to the device on the rising edge of CLK and read data or status from the device on the falling edge
of CLK. Quad SPI and QPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2
to be set. When QE=1, the /WP pin becomes IO2 and /HOLD pin becomes IO3.
7.4 Write Protect (/WP)
The Write Protect (/WP) pin can be used to prevent the Status Registers from being written. Used in
conjunction with the Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits and Status
Register Protect (SRP) bits, a portion as small as a 4KB sector or the entire memory array can be
hardware protected. The /WP pin is active low. However, when the QE bit of Status Register-2 is set for
Quad I/O, the /WP pin function is not available since this pin is used for IO2. See figure 1a, 1b and 1c for
the pin configuration of Quad I/O operation.
7.5 HOLD (/HOLD)
The /HOLD pin allows the device to be paused while it is actively selected. When /HOLD is brought low,
while /CS is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). When /HOLD is brought high, device operation can resume. The /HOLD function can be
useful when multiple devices are sharing the same SPI signals. The /HOLD pin is active low. When the
QE bit of Status Register-2 is set for Quad I/O, the /HOLD pin function is not available since this pin is
used for IO3. See figure 1a, 1b and 1c for the pin configuration of Quad I/O operation.
7.6 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Operations")
W25Q32DW
Publication Release Date: September 18, 2012
- 9 - Revision D
8. BLOCK DIAGRAM
Figure 2. W25Q32DW Serial Flash Memory Block Diagram
00FF00h 00FFFFh
• Block 0 (64KB) •
000000h 0000FFh
•
•
•
0FFF00h 0FFFFFh
• Block 15 (64KB) •
0F0000h 0F00FFh
10FF00h 10FFFFh
• Block 16 (64KB) •
100000h 1000FFh
•
•
•
1FFF00h 1FFFFFh
• Block 31 (64KB) •
1F0000h 1F00FFh
20FF00h 20FFFFh
• Block 32 (64KB) •
200000h 2000FFh
•
•
•
3FFF00h 3FFFFFh
• Block 63 (64KB) •
3F0000h 3F00FFh
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
000000h 0000FFh
Column Decode
And 256-Byte Page Buffer
Beginning
Page Address
Ending
Page Address
W25Q32DW
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
DO (IO
1
)
DI (IO
0
)
/CS
CLK
/HOLD (IO
3
)
/WP (IO
2
)
High Voltage
Generators
xx0F00h xx0FFFh
• Sector 0 (4KB) •
xx0000h xx00FFh
xx1F00h xx1FFFh
• Sector 1 (4KB) •
xx1000h xx10FFh
xx2F00h xx2FFFh
• Sector 2 (4KB) •
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
• Sector 13 (4KB) •
xxD000h xxD0FFh
xxEF00h xxEFFFh
• Sector 14 (4KB) •
xxE000h xxE0FFh
xxFF00h xxFFFFh
• Sector 15 (4KB) •
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 3 - 0
Write Protect Logic and Row Decode
00FF00h 00FFFFh
• Block 0 (64KB) •
000000h 0000FFh
•
•
•
0FFF00h 0FFFFFh
• Block 15 (64KB) •
0F0000h 0F00FFh
10FF00h 10FFFFh
• Block 16 (64KB) •
100000h 1000FFh
•
•
•
1FFF00h 1FFFFFh
• Block 31 (64KB) •
1F0000h 1F00FFh
20FF00h 20FFFFh
• Block 32 (64KB) •
200000h 2000FFh
•
•
•
3FFF00h 3FFFFFh
• Block 63 (64KB) •
3F0000h 3F00FFh
003000h 0030FFh
002000h 0020FFh
001000h 0010FFh
000000h 0000FFh
Column Decode
And 256-Byte Page Buffer
Beginning
Page Address
Ending
Page Address
W25Q32DW
SPI
Command &
Control Logic
Byte Address
Latch / Counter
Status
Register
Write Control
Logic
Page Address
Latch / Counter
DO (IO
1
)
DI (IO
0
)
/CS
CLK
/HOLD (IO
3
)
/WP (IO
2
)
High Voltage
Generators
xx0F00h xx0FFFh
• Sector 0 (4KB) •
xx0000h xx00FFh
xx1F00h xx1FFFh
• Sector 1 (4KB) •
xx1000h xx10FFh
xx2F00h xx2FFFh
• Sector 2 (4KB) •
xx2000h xx20FFh
•
•
•
xxDF00h xxDFFFh
• Sector 13 (4KB) •
xxD000h xxD0FFh
xxEF00h xxEFFFh
• Sector 14 (4KB) •
xxE000h xxE0FFh
xxFF00h xxFFFFh
• Sector 15 (4KB) •
xxF000h xxF0FFh
Block Segmentation
Data
Security Register 3 - 0
Write Protect Logic and Row Decode
W25Q32DW
- 10 -
9. FUNCTIONAL DESCRIPTION
9.1 SPI/QPI OPERATIONS
Power On
Standard SPI
Dual SPI
Quad SPI
operations
QPI
operations
Device
Initialization
Enable QPI (38h)
Disable QPI (FFh)
Reset (66h + 99h)Reset (66h + 99h)
Power On
Standard SPI
Dual SPI
Quad SPI
operations
QPI
operations
Device
Initialization
Enable QPI (38h)
Disable QPI (FFh)
Reset (66h + 99h)Reset (66h + 99h)
Figure 3. W25Q32DW Serial Flash Memory Operation Diagram
9.1.1 Standard SPI Instructions
The W25Q32DW is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions
use the DI input pin to serially write instructions, addresses or data to the device on the rising edge of
CLK. The DO output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is
not being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and
rising edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
9.1.2 Dual SPI Instructions
The W25Q32DW supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the
device at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are
ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-speed-
critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO pins
become bidirectional I/O pins: IO0 and IO1.
W25Q32DW
Publication Release Date: September 18, 2012
- 11 - Revision D
9.1.3 Quad SPI Instructions
The W25Q32DW supports Quad SPI operation when using instructions such as “Fast Read Quad Output
(6Bh)”, “Fast Read Quad I/O (EBh)”, “Word Read Quad I/O (E7h)” and “Octal Word Read Quad I/O
(E3h)”. These instructions allow data to be transferred to or from the device four to six times the rate of
ordinary Serial Flash. The Quad Read instructions offer a significant improvement in continuous and
random access transfer rates allowing fast code-shadowing to RAM or execution directly from the SPI bus
(XIP). When using Quad SPI instructions the DI and DO pins become bidirectional IO0 and IO1, and the
/WP and /HOLD pins become IO2 and IO3 respectively. Quad SPI instructions require the non-volatile
Quad Enable bit (QE) in Status Register-2 to be set.
9.1.4 QPI Instructions
The W25Q32DW supports Quad Peripheral Interface (QPI) operations only when the device is switched
from Standard/Dual/Quad SPI mode to QPI mode using the “Enable QPI (38h)” instruction. The typical
SPI protocol requires that the byte-long instruction code being shifted into the device only via DI pin in
eight serial clocks. The QPI mode utilizes all four IO pins to input the instruction code, thus only two serial
clocks are required. This can significantly reduce the SPI instruction overhead and improve system
performance in an XIP environment. Standard/Dual/Quad SPI mode and QPI mode are exclusive. Only
one mode can be active at any given time. “Enable QPI (38h)” and “Disable QPI (FFh)” instructions are
used to switch between these two modes. Upon power-up or after a software reset using “Reset (99h)”
instruction, the default state of the device is Standard/Dual/Quad SPI mode. To enable QPI mode, the
non-volatile Quad Enable bit (QE) in Status Register-2 is required to be set. When using QPI instructions,
the DI and DO pins become bidirectional IO0 and IO1, and the /WP and /HOLD pins become IO2 and IO3
respectively. See Figure 3 for the device operation modes.
9.1.5 Hold Function
For Standard SPI and Dual SPI operations, the /HOLD signal allows the W25Q32DW operation to be
paused while it is actively selected (when /CS is low). The /HOLD function may be useful in cases where
the SPI data and clock signals are shared with other devices. For example, consider if the page buffer
was only partially written when a priority interrupt requires use of the SPI bus. In this case the /HOLD
function can save the state of the instruction and the data in the buffer so programming can resume where
it left off once the bus is available again. The /HOLD function is only available for standard SPI and Dual
SPI operation, not during Quad SPI or QPI.
To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will activate on
the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the
/HOLD condition will activate after the next falling edge of CLK. The /HOLD condition will terminate on the
rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not already low the /HOLD
condition will terminate after the next falling edge of CLK. During a /HOLD condition, the Serial Data
Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are ignored. The Chip
Select (/CS) signal should be kept active (low) for the full duration of the /HOLD operation to avoid
resetting the internal logic state of the device.
W25Q32DW
- 12 -
9.2 WRITE PROTECTION
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, the W25Q32DW
provides several means to protect the data from inadvertent writes.
9.2.1 Write Protect Features
• Device resets when VCC is below threshold
• Time delay write disable after Power-up
• Write enable/disable instructions and automatic write disable after erase or program
• Software and Hardware (/WP pin) write protection using Status Register
• Write Protection using Power-down instruction
• Lock Down write protection for Status Register until the next power-up
• One Time Program (OTP) write protection for array and Security Registers using Status Register*
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, the W25Q32DW will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 43). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-
down to prevent adverse command sequence. If needed a pull-up resister on /CS can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-
disabled state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Protect (SRP0, SRP1) and Block Protect (CMP, SEC, TB, BP2, BP1 and BP0) bits. These
settings allow a portion as small as a 4KB sector or the entire memory array to be configured as read only.
Used in conjunction with the Write Protect (/WP) pin, changes to the Status Register can be enabled or
disabled under hardware control. See Status Register section for further information. Additionally, the
Power-down instruction offers an extra level of write protection as all instructions are ignored except for
the Release Power-down instruction.
W25Q32DW
Publication Release Date: September 18, 2012
- 13 - Revision D
10. CONTROL AND STATUS REGISTERS
The Read Status Register-1 and Status Register-2 instructions can be used to provide status on the
availability of the Flash memory array, if the device is write enabled or disabled, the state of write
protection, Quad SPI setting, Security Register lock status and Erase/Program Suspend status. The Write
Status Register instruction can be used to configure the device write protection features, Quad SPI setting
and Security Register OTP lock. Write access to the Status Register is controlled by the state of the non-
volatile Status Register Protect bits (SRP0, SRP1), the Write Enable instruction, and during Standard/Dual
SPI operations, the /WP pin.
10.1 STATUS REGISTER
10.1.1 BUSY
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and
tCE in AC Characteristics). When the program, erase or write status/security register instruction has
completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions.
10.1.2 Write Enable Latch (WEL)
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write
disable state occurs upon power-up or after any of the following instructions: Write Disable, Page
Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase
Security Register and Program Security Register.
10.1.3 Block Protect Bits (BP2, BP1, BP0)
The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and
S2) that provide Write Protection control and status. Block Protect bits can be set using the Write Status
Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be
protected from Program and Erase instructions (see Status Register Memory Protection table). The
factory default setting for the Block Protection Bits is 0, none of the array protected.
10.1.4 Top/Bottom Block Protect (TB)
The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the
Top (TB=0) or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table.
The factory default setting is TB=0. The TB bit can be set with the Write Status Register Instruction
depending on the state of the SRP0, SRP1 and WEL bits.
10.1.5 Sector/Block Protect (SEC)
The non-volatile Sector/Block Protect bit (SEC) controls if the Block Protect Bits (BP2, BP1, BP0) protect
either 4KB Sectors (SEC=1) or 64KB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array
as shown in the Status Register Memory Protection table. The default setting is SEC=0.
W25Q32DW
- 14 -
10.1.6 Complement Protect (CMP)
The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in
conjunction with SEC, TB, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once
CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1 and BP0 will be reversed. For
instance, when CMP=0, a top 4KB sector can be protected while the rest of the array is not; when CMP=1,
the top 4KB sector will become unprotected while the rest of the array become read-only. Please refer to
the Status Register Memory Protection table for details. The default setting is CMP=0.
10.1.7 Status Register Protect (SRP1, SRP0)
The Status Register Protect bits (SRP1 and SRP0) are non-volatile read/write bits in the status register
(S8 and S7). The SRP bits control the method of write protection: software protection, hardware
protection, power supply lock-down or one time programmable (OTP) protection.
SRP1 SRP0 /WP Status
Register Description
0 0 X Software
Protection
/WP pin has no control. The Status register can be written to
after a Write Enable instruction, WEL=1. [Factory Default]
0 1 0
Hardware
Protected
When /WP pin is low the Status Register locked and can not
be written to.
0 1 1
Hardware
Unprotected
When /WP pin is high the Status register is unlocked and can
be written to after a Write Enable instruction, WEL=1.
1 0 X
Power Supply
Lock-Down
Status Register is protected and can not be written to again
until the next power-down, power-up cycle.(1)
1 1 X
One Time
Program(2)
Status Register is permanently protected and can not be
written to.
Note:
1. When SRP1, SRP0 = (1, 0), a power-down, power-up cycle will change SRP1, SRP0 to (0, 0) state. 2.
This feature is available upon special order. Please contact Winbond for details.
10.1.8 Erase/Program Suspend Status (SUS)
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing a
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
10.1.9 Security Register Lock Bits (LB3, LB2, LB1, LB0)
The Security Register Lock Bits (LB3, LB2, LB1, LB0) are non-volatile One Time Program (OTP) bits in
Status Register (S13, S12, S11, S10) that provide the write protect control and status to the Security
Registers. The default state of LB3-0 is 0, Security Registers are unlocked. LB3-0 can be set to 1
individually using the Write Status Register instruction. LB3-0 are One Time Programmable (OTP), once
it’s set to 1, the corresponding 256-Byte Security Register will become read-only permanently.
W25Q32DW
Publication Release Date: September 18, 2012
- 15 - Revision D
10.1.10 Quad Enable (QE)
The Quad Enable (QE) bit is a non-volatile read/write bit in the status register (S9) that allows Quad SPI
and QPI operation. When the QE bit is set to a 0 state (factory default), the /WP pin and /HOLD are
enabled. When the QE bit is set to a 1, the Quad IO2 and IO3 pins are enabled, and /WP and /HOLD
functions are disabled.
QE bit is required to be set to a 1 before issuing an “Enable QPI (38h)” to switch the device from
Standard/Dual/Quad SPI to QPI, otherwise the command will be ignored. When the device is in QPI mode,
QE bit will remain to be 1. A “Write Status Register” command in QPI mode cannot change QE bit from a
“1” to a “0”.
WARNING: If the /WP or /HOLD pins are tied directly to the power supply or ground during
standard SPI or Dual SPI operation, the QE bit should never be set to a 1.
S7 S6 S5 S4 S3 S2 S1 S0
SRP0 SEC TB BP2 BP1 BP0 WEL BUSY
STATUS REGISTER PROTECT 0
(non-volatile)
SECTOR PROTECT
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
S7 S6 S5 S4 S3 S2 S1 S0
SRP0 SEC TB BP2 BP1 BP0 WEL BUSY
STATUS REGISTER PROTECT 0
(non-volatile)
SECTOR PROTECT
(non-volatile)
TOP/BOTTOM PROTECT
(non-volatile)
BLOCK PROTECT BITS
(non-volatile)
WRITE ENABLE LATCH
ERASE/WRITE IN PROGRESS
Figure 4a. Status Register-1
S15 S14 S13 S12 S11 S10 S9 S8
SUS CMP LB3 LB2 LB1 LB0 QE SRP1
SUSPEND STATUS
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BITS
(non-volatile OTP)
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
(
non-volatile
)
S15 S14 S13 S12 S11 S10 S9 S8
SUS CMP LB3 LB2 LB1 LB0 QE SRP1
SUSPEND STATUS
COMPLEMENT PROTECT
(non-volatile)
SECURITY REGISTER LOCK BITS
(non-volatile OTP)
QUAD ENABLE
(non-volatile)
STATUS REGISTER PROTECT 1
)
(
non-volatile
Figure 4b. Status Register-2
W25Q32DW
- 16 -
1
0.1.11 W25Q32DW Status Register Memory Protection (CMP = 0)
STATUS REGISTER(1) W25Q32DW (32M-BIT) MEMORY PROTECTION(3)
SEC TB BP2 BP1 BP0 PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X X 0 0 0 NONE NONE NONE NONE
0 0 0 0 1 63 3F0000h – 3FFFFFh 64KB Upper 1/64
0 0 0 1 0 62 and 63 3E0000h – 3FFFFFh 128KB Upper 1/32
0 0 0 1 1 60 thru 63 3C0000h – 3FFFFFh 256KB Upper 1/16
0 0 1 0 0 56 thru 63 380000h – 3FFFFFh 512KB Upper 1/8
0 0 1 0 1 48 thru 63 300000h – 3FFFFFh 1MB Upper 1/4
0 0 1 1 0 32 thru 63 200000h – 3FFFFFh 2MB Upper 1/2
0 1 0 0 1 0 000000h – 00FFFFh 64KB Lower 1/64
0 1 0 1 0 0 and 1 000000h – 01FFFFh 128KB Lower 1/32
0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256KB Lower 1/16
0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512KB Lower 1/8
0 1 1 0 1 0 thru 15 000000h – 0FFFFFh 1MB Lower 1/4
0 1 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2
X X 1 1 1 0 thru 63 000000h – 3FFFFFh 4MB ALL
1 0 0 0 1 63 3FF000h – 3FFFFFh 4KB U - 1/1024
1 0 0 1 0 63 3FE000h – 3FFFFFh 8KB U - 1/512
1 0 0 1 1 63 3FC000h – 3FFFFFh 16KB U - 1/256
1 0 1 0 X 63 3F8000h – 3FFFFFh 32KB U - 1/128
1 1 0 0 1 0 000000h – 000FFFh 4KB L - 1/1024
1 1 0 1 0 0 000000h – 001FFFh 8KB L - 1/512
1 1 0 1 1 0 000000h – 003FFFh 16KB L - 1/256
1 1 1 0 X 0 000000h – 007FFFh 32KB L - 1/128
Note:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.
W25Q32DW
Publication Release Date: September 18, 2012
- 17 - Revision D
1
0.1.12 W25Q32DW Status Register Memory Protection (CMP = 1)
STATUS REGISTER(1) W25Q32DW (32M-BIT) MEMORY PROTECTION(3)
SEC TB BP2 BP1 BP0 PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION(2)
X X 0 0 0 0 thru 63 000000h – 3FFFFFh 4MB ALL
0 0 0 0 1 0 thru 62 000000h – 3EFFFFh 4,032KB Lower 63/64
0 0 0 1 0 0 and 61 000000h – 3DFFFFh 3,968KB Lower 31/32
0 0 0 1 1 0 thru 59 000000h – 3BFFFFh 3,840KB Lower 15/16
0 0 1 0 0 0 thru 55 000000h – 37FFFFh 3,584KB Lower 7/8
0 0 1 0 1 0 thru 47 000000h – 2FFFFFh 3MB Lower 3/4
0 0 1 1 0 0 thru 31 000000h – 1FFFFFh 2MB Lower 1/2
0 1 0 0 1 1 thru 63 010000h – 3FFFFFh 4,032KB Upper 63/64
0 1 0 1 0 2 and 63 020000h – 3FFFFFh 3,968KB Upper 31/32
0 1 0 1 1 4 thru 63 040000h – 3FFFFFh 3,840KB Upper 15/16
0 1 1 0 0 8 thru 63 080000h – 3FFFFFh 3,584KB Upper 7/8
0 1 1 0 1 16 thru 63 100000h – 3FFFFFh 3MB Upper 3/4
0 1 1 1 0 32 thru 63 200000h – 3FFFFFh 2MB Upper 1/2
X X 1 1 1 NONE NONE NONE NONE
1 0 0 0 1 0 thru 63 000000h – 3FEFFFh 4,092KB L - 1023/1024
1 0 0 1 0 0 thru 63 000000h – 3FDFFFh 4,088KB L - 511/512
1 0 0 1 1 0 thru 63 000000h – 3FBFFFh 4,080KB L - 255/256
1 0 1 0 X 0 thru 63 000000h – 3F7FFFh 4,064KB L - 127/128
1 1 0 0 1 0 thru 63 001000h – 3FFFFFh 4,092KB U - 1023/1024
1 1 0 1 0 0 thru 63 002000h – 3FFFFFh 4,088KB U - 511/512
1 1 0 1 1 0 thru 63 004000h – 3FFFFFh 4,080KB U - 255/256
1 1 1 0 X 0 thru 63 008000h – 3FFFFFh 4,064KB U - 127/128
Note:
1. X = don’t care
2. L = Lower; U = Upper
3. If any Erase or Program command specifies a memory region that contains protected data portion, this
command will be ignored.
W25Q32DW
- 18 -
10.2 INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of the W25Q32DW consists of thirty six basic instructions
that are fully controlled through the SPI bus (see Instruction Set table1-3). Instructions are initiated with
the falling edge of Chip Select (/CS). The first byte of data clocked into the DI input provides the
instruction code. Data on the DI input is sampled on the rising edge of clock with most significant bit
(MSB) first.
The QPI instruction set of the W25Q32DW consists of twenty four basic instructions that are fully
controlled through the SPI bus (see Instruction Set table 4). Instructions are initiated with the falling edge
of Chip Select (/CS). The first byte of data clocked through IO[3:0] pins provides the instruction code. Data
on all four IO pins are sampled on the rising edge of clock with most significant bit (MSB) first. All QPI
instructions, addresses, data and dummy bytes are using all four IO pins to transfer every byte of data with
every two serial clocks (CLK).
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed with the
rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in figures 5
through 42. All read instructions can be completed after any clocked bit. However, all instructions that
Write, Program or Erase must complete on a byte boundary (/CS driven high after a full 8-bits have been
clocked) otherwise the instruction will be ignored. This feature further protects the device from inadvertent
writes. Additionally, while the memory is being programmed or erased, or when the Status Register is
being written, all instructions except for Read Status Register will be ignored until the program or erase
cycle has completed.
10.2.1 Manufacturer and Device Identification
MANUFACTURER ID (MF7 - MF0)
Winbond Serial Flash EFh
Device ID (ID7 - ID0) (ID15 - ID0)
Instruction ABh, 90h, 92h, 94h 9Fh
W25Q32DW 15h 6016h
W25Q32DW
Publication Release Date: September 18, 2012
- 19 - Revision D
10.2.2 Instruction Set Table 1 (Standard SPI Instructions)(1)
INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
CLOCK NUMBE R (0 – 7) (8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47)
Write Enable 06h
Volatile SR Write Enable 50h
Write Disable 04h
Read Status Register-1 05h (S7-S0)(2)
Read Status Register-2 35h (S15-S8)(2)
Write Status Register 01h (S7-S0) (S15-S8)
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)
Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0
Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0
Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0
Chip Erase C7h/60h
Erase / Program Suspend 75h
Erase / Program Resume 7Ah
Power-down B9h
Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0)
Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Release Powerdown / ID(4) ABh dummy dummy dummy (ID7-ID0)(2)
Manufacturer/Device ID(4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0)
JEDEC ID(4) 9Fh (MF7-MF0)
Manufacturer
(ID15-ID8)
Memory Type
(ID7-ID0)
Capacity
Read Unique ID 4Bh dummy dummy dummy dummy (UID63-UID0)
Erase
Security Registers(5) 44h A23-A16 A15-A8 A7-A0
Program
Security Registers(5) 42h A23-A16 A15-A8 A7-A0 D7-D0 D7-D0(3)
Read
Security Registers(5) 48h A23-A16 A15-A8 A7-A0 dummy (D7-D0)
Enable QPI 38h
Enable Reset 66h
Reset 99h
W25Q32DW
- 20 -
10.2.3 Instruction Set Table 2 (Dual SPI Instructions)
INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
CLOCK NUMBE R (0 – 7) (8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47)
Fast Read Dual Output 3Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(7)
Fast Read Dual I/O BBh A23-A8(6) A7-A0, M7-M0 (6) (D7-D0, …)(7)
Manufacturer/Device ID by
Dual I/O(4) 92h A23-A8(6) A7-A0, M7-M0 (6) (MF7-MF0,
ID7-ID0)
10.2.4 Instruction Set Table 3 (Quad SPI Instructions)
INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
CLOCK NUMBE R (0 – 7) (8 – 15) (16 – 23) (24 – 31) (32 – 39) (40 – 47)
Quad Page Program 32h A23-A16 A15-A8 A7-A0 D7-D0, …(9) D7-D0, …(3)
Fast Read Quad Output 6Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0, …)(9)
Fast Read Quad I/O EBh A23-A0,
M7-M0(8) (xxxx, D7-D0)(10) (D7-D0, …)(9)
Word Read Quad I/O(12) E7h A23-A0,
M7-M0(8) (xx, D7-D0)(11) (D7-D0, …)(9)
Octal Word Read
Quad I/O(13) E3h A23-A0,
M7-M0(8) (D7-D0, …)(9)
Set Burst with Wrap 77h xxxxxx,
W6-W4(8)
Manufacture/Device ID by
Quad I/O(4) 94h A23-A0,
M7-M0(8)
xxxx, (MF7-MF0,
ID7-ID0)
(MF7-MF0,
ID7-ID0, …)
W25Q32DW
Publication Release Date: September 18, 2012
- 21 - Revision D
10.2.5 Instruction Set Table 4 (QPI Instructions)(14)
INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE 6
CLOCK NUMBE R (0 , 1) (2 , 3) (4 , 5) (6 , 7) (8 , 9) (10 , 11)
Write Enable 06h
Volatile SR Write Enable 50h
Write Disable 04h
Read Status Register-1 05h (S7-S0)(2)
Read Status Register-2 35h (S15-S8)(2)
Write Status Register 01h (S7-S0) (S15-S8)
Page Program 02h A23-A16 A15-A8 A7-A0 D7-D0(9) D7-D0(3)
Sector Erase (4KB) 20h A23-A16 A15-A8 A7-A0
Block Erase (32KB) 52h A23-A16 A15-A8 A7-A0
Block Erase (64KB) D8h A23-A16 A15-A8 A7-A0
Chip Erase C7h/60h
Erase / Program Suspend 75h
Erase / Program Resume 7Ah
Power-down B9h
Set Read Parameters C0h P7-P0
Fast Read 0Bh A23-A16 A15-A8 A7-A0 dummy(15) (D7-D0)
Burst Read with Wrap(16) 0Ch A23-A16 A15-A8 A7-A0 dummy(15) (D7-D0)
Fast Read Quad I/O EBh A23-A16 A15-A8 A7-A0 M7-M0(15) (D7-D0)
Release Powerdown / ID(4) ABh dummy dummy dummy (ID7-ID0)(2)
Manufacturer/Device ID(4) 90h dummy dummy 00h (MF7-MF0) (ID7-ID0)
JEDEC ID(4) 9Fh (MF7-MF0)
Manufacturer
(ID15-ID8)
Memory Type
(ID7-ID0)
Capacity
Disable QPI FFh
Enable Reset 66h
Reset 99h
W25Q32DW
- 22 -
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
output from the device on either 1, 2 or 4 IO pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the
addressing will wrap to the beginning of the page and overwrite previously sent data.
4. See Manufacturer and Device Identification table for device ID information.
5. Security Register Address:
Security Register 0: A23-16 = 00h; A15-8 = 00h; A7-0 = byte address
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
Please note that Security Register 0 is Reserved by Winbond for future use. It is recommended to use
Security registers 1- 3 before using register 0.
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1
7. Dual SPI data output format:
IO0 = (D6, D4, D2, D0)
IO1 = (D7, D5, D3, D1)
8. Quad SPI address input format: Set Burst with Wrap input format:
IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO0 = x, x, x, x, x, x, W4, x
IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO1 = x, x, x, x, x, x, W5, x
IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO2 = x, x, x, x, x, x, W6, x
IO3 = A23, A19, A15, A11, A7, A3, M7, M3 IO3 = x, x, x, x, x, x, x, x
9. Quad SPI data input/output format:
IO0 = (D4, D0, …..)
IO1 = (D5, D1, …..)
IO2 = (D6, D2, …..)
IO3 = (D7, D3, …..)
10. Fast Read Quad I/O data output format:
IO0 = (x, x, x, x, D4, D0, D4, D0)
IO1 = (x, x, x, x, D5, D1, D5, D1)
IO2 = (x, x, x, x, D6, D2, D6, D2)
IO3 = (x, x, x, x, D7, D3, D7, D3)
11. Word Read Quad I/O data output format:
IO0 = (x, x, D4, D0, D4, D0, D4, D0)
IO1 = (x, x, D5, D1, D5, D1, D5, D1)
IO2 = (x, x, D6, D2, D6, D2, D6, D2)
IO3 = (x, x, D7, D3, D7, D3, D7, D3)
12. For Word Read Quad I/O, the lowest address bit must be 0. (A0 = 0)
13. For Octal Word Read Quad I/O, the lowest four address bits must be 0. (A3, A2, A1, A0 = 0)
14. QPI Command, Address, Data input/output format:
CLK # 0 1 2 3 4 5 6 7 8 9 10 11
IO0 = C4, C0, A20, A16, A12, A8, A4, A0, D4, D0, D4, D0
IO1 = C5, C1, A21, A17, A13, A9, A5, A1, D5, D1, D5, D1
IO2 = C6, C2, A22, A18, A14, A10, A6, A2, D6, D2, D6, D2
IO3 = C7, C3, A23, A19, A15, A11, A7, A3, D7, D3, D7, D3
15. The number of dummy clocks for QPI Fast Read, QPI Fast Read Quad I/O & QPI Burst Read with Wrap is
controlled by read parameter P7 – P4.
16. The wrap around length for QPI Burst Read with Wrap is controlled by read parameter P3 – P0.
W25Q32DW
Publication Release Date: September 18, 2012
- 23 - Revision D
DO
(IO
1
)
10.2.6 Write Enable (06h)
The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a
1. The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block
Erase, Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write
Enable instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI)
pin on the rising edge of CLK, and then driving /CS high.
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Mode 0
Mode 3
Instruction (06h)
High Impedance
/CS
CLK Mode 0
Mode 3 0 1
Mode 0
Mode 3
IO
0
IO
1
IO
2
IO
3
06h
Instruction
Figure 5. Write Enable Instruction for SPI Mode (left) or QPI Mode (right)
10.2.7 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 10.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-
volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable
for Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only
valid for the Write Status Register instruction to change the volatile Status Register bit values.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Mode 0
Mode 3
Instruction (50h)
High Impedance
/CS
CLK
Mode 0
Mode 3 0 1
Mode 0
Mode 3
IO
0
IO
1
IO
2
IO
3
50h
Instruction
Figure 6. Write Enable for Volatile Status Register Instruction for SPI Mode (left) or QPI Mode (right)
W25Q32DW
- 24 -
DO
(IO
1
)
10.2.8 Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to
a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the
DI pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Mode 0
Mode 3
Instruction (04h)
High Impedance
/CS
CLK
Mode 0
Mode 3 0 1
Mode 0
Mode 3
IO
0
IO
1
IO
2
IO
3
04h
Instruction
Figure 7. Write Disable Instruction for SPI Mode (left) or QPI Mode (right)
10.2.9 Read Status Register-1 (05h) and Read Status Register-2 (35h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is
entered by driving /CS low and shifting the instruction code “05h” for Status Register-1 or “35h” for
Status Register-2 into the DI pin on the rising edge of CLK. The status register bits are then shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure 8. The Status
Register bits are shown in Figure 4a and 4b and include the BUSY, WEL, BP2-BP0, TB, SEC, SRP0,
SRP1, QE, LB3-0, CMP and SUS bits (see Status Register section earlier in this datasheet).
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write
Status Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the
cycle is complete and if the device can accept another instruction. The Status Register can be read
continuously, as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (05h or 35h)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
76543210765432107
Status Register 1 or 2 out Status Register 1 or 2 out
**
= MSB
*
Figure 8a. Read Status Register Instruction (SPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 25 - Revision D
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
05h or 35h
2345
4040
5 1
6 2
7 3
5 1
6 2
7 3
4
5
6
7
SR1 or SR2
out
SR1 or SR2
out
Instruction
Figure 8b. Read Status Register Instruction (QPI Mode)
10.2.10 Write Status Register (01h)
The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status
Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2,
LB1, LB0, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written to. All other Status Register bit
locations are read-only and will not be affected by the Write Status Register instruction. LB3-0 are non-
volatile OTP bits, once it is set to 1, it can not be cleared to 0. The Status Register bits are shown in
Figure 4a and 4b, and described in 10.1.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL
must equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction
code “01h”, and then writing the status register data byte as illustrated in figure 9.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must
have been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0).
However, SRP1 and LB3, LB2, LB1, LB0 can not be changed from “1” to “0” because of the OTP
protection for these bits. Upon power off or the execution of a “Reset (99h)” instruction, the volatile Status
Register bit values will be lost, and the non-volatile Status Register bit values will be restored.
To complete the Write Status Register instruction, the /CS pin must be driven high after the eighth or
sixteenth bit of data that is clocked in. If this is not done the Write Status Register instruction will not be
executed. If /CS is driven high after the eighth clock (compatible with the 25X series) the CMP, QE and
SRP1 bits will be cleared to 0.
During non-volatile Status Register write operation (06h combined with 01h), after /CS is driven high, the
self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle
W25Q32DW
- 26 -
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
The Write Status Register instruction can be used in both SPI mode and QPI mode. However, the QE bit
cannot be written to when the device is in the QPI mode, because QE=1 is required for the device to enter
and operate in the QPI mode.
Please refer to 10.1 for detailed Status Register Bit descriptions. Factory default for all status Register bits
are 0.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (01h)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
7654321015 14 13 12 11 10 9 8
Status Register 1 in Status Register 2 in
Mode 0
Mode 3
**
= MSB
*
Figure 9a. Write Status Register Instruction (SPI Mode)
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
01h
2 3 4 5
4 0 12 8
5 1
6 2
7 3
13 9
14 10
15 11
SR1 in SR2 in
Mode 0
Mode 3
Instruction
Figure 9b. Write Status Register Instruction (QPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 27 - Revision D
10.2.11 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as
the clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in figure 10. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of fR
(see AC Electrical Characteristics).
The Read Data (03h) instruction is only supported in Standard SPI mode.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (03h)
High Impedance
8 9 10 28 29 30 31 32 33 34 35 36 37 38 39
765432107
24-Bit Address
23 22 21 3 2 1 0
Data Out 1
*
*
= MSB
*
Figure 10. Read Data Instruction (SPI Mode only)
W25Q32DW
- 28 -
10.2.12 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the devices
internal circuits additional time for setting up the initial address. During the dummy clocks the data value
on the DO pin is a “don’t care”.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (0Bh)
High Impedance
8 9 10 28 29 30 31
24-Bit Address
23 22 21 3210
Data Out 1
*
/CS
CLK
DI
(IO
0
)
DO
(IO )
32
1
33 34 35 36 37 38 39
Dummy Clocks
High Impedance
40 41 42 44 45 46 47 48 49 50 51 52 53 54 55
765432107
Data Out 2
7
*
6543210
*
4331
0
= MSB
*
Figure 11a. Fast Read Instruction (SPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 29 - Revision D
Fast Read (0Bh) in QPI Mode
The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of
dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide
range applications with different needs for either maximum Fast Read frequency or minimum data access
latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be
configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset
instruction is 2.
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
0Bh
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6789
4 0
5 1
6 2
7 3
A15-8 A7-0 Dummy
*
Byte 1 Byte 2
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13
4
5
6
7
IOs switch from
Input to Output
*
"Set Read Parameters" instruction (C0h) can set
the number of dummy clocks.
Instruction
Figure 11b. Fast Read Instruction (QPI Mode)
W25Q32DW
- 30 -
10.2.13 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred from the W25Q32DW at
twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal for quickly
downloading code from Flash to RAM upon power-up or for applications that cache code-segments to
RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight
“dummy” clocks after the 24-bit address as shown in Figure 12. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (3Bh)
High Impedance
8 9 10 28 29 30
32 33 34 35 36 37 38 39
6420
24-Bit Address
23 22 21 3 2 1 0
*
*
31
31
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Dummy Clocks
0
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
7531
High Impedance
6420
7531
6 4 2 0
7 5 3 1
6 4 2 0
7 5 3 1
IO
0
switches from
Input to Output
6
7
Data Out 1
*
Data Out 2
*
Data Out 3
*
Data Out 4
= MSB
*
Figure 12. Fast Read Dual Output Instruction (SPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 31 - Revision D
10.2.14 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. A Quad enable of Status Register-2 must be
executed before the device will accept the Fast Read Quad Output Instruction (Status Register bit QE
must equal 1). The Fast Read Quad Output Instruction allows data to be transferred from the W25Q32DW
at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24-bit address
as shown in Figure 13. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
/CS
CLK
Mode 0
Mode 3 01234567
Instruction (6Bh)
High Impedance
8 9 10 28 29 30
32 33 34 35 36 37 38 39
4 0
24-Bit Address
23 22 21 3210
*
31
31
/CS
CLK
Dummy Clocks
0
40 41 42 43 44 45 46 47
5 1
High Impedance
4
5
Byte 1
High Impedance
High Impedance
6 2
7 3
High Impedance
6
7
High Impedance
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Byte 2 Byte 3 Byte 4
IO
0
switches from
Input to Output
IO
0
IO
1
IO
2
IO
3
IO
0
IO
1
IO
2
IO
3
= MSB
*
Figure 13. Fast Read Quad Output Instruction (SPI Mode only)
W25Q32DW
- 32 -
10.2.15 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 14a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after /CS is
raised and then lowered) does not require the BBh instruction code, as shown in Figure 14b. This reduces
the instruction sequence by eight clocks and allows the Read address to be immediately entered after /CS
is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after
/CS is raised and then lowered) requires the first byte instruction code, thus returning to normal operation.
It is recommended to input FFFFh on IO0 for the next instruction (16 clocks), to ensure M4 = 1 and return
the device to normal operation.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (BBh)
8 9 10 12 13 14
24 25 26 27 28 29 30 31
6420
*
*
23
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
0
32 33 34 35 36 37 38 39
7531
*
6 4 2 0
7 5 3 1
6 4 2 0
7 5 3 1
6420
7531
**
IOs switch from
Input to Output
6
7
22 20 18 16
23 21 19 17
14 12 10 8
15 13 11 9
6 4 2 0
7 5 3 1
6 4 2 0
7 5 3 1
11 15 16 17 18 20 21 2219 23
1
A23-16 A15-8 A7-0 M7-0
Byte 1 Byte 2 Byte 3 Byte 4
= MSB
**
Figure 14a. Fast Read Dual I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 33 - Revision D
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 8 9 10 12 13 14
24 25 26 27 28 29 30 31
6420
*
*
15
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
0
7531
*
6420
7531
6420
7531
6 4 2 0
7 5 3 1
**
IOs switch from
Input to Output
6
7
22 20 18 16
23 21 19 17
14 12 10 8
15 13 11 9
6420
7531
6420
7531
11 15
1
A23-16 A15-8 A7-0 M7-0
Byte 1Byte 2Byte 3Byte 4
01234567
16 17 18 20 21 2219 23
*
= MSB
*
Figure 14b. Fast Read Dual I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)
W25Q32DW
- 34 -
10.2.16 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except
that address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and four Dummy
clocks are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction
overhead allowing faster random access for code execution (XIP) directly from the Quad SPI. The Quad
Enable bit (QE) of Status Register-2 must be set to enable the Fast Read Quad I/O Instruction.
Fast Read Quad I/O with “Continuous Read Mode”
The Fast Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 15a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the EBh instruction code, as shown in Figure 15b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
M7-0
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
2
IO
3
3 4 5
20 16 12 8
21 17
22 18
Figure 15a. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, SPI Mode)
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0
4
Byte 1 Byte 2
0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15 16 17 18 19 20 21 22 23
Dummy Dummy
Instruction (EBh)
W25Q32DW
Publication Release Date: September 18, 2012
- 35 - Revision D
M7-0
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6789
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15
Dummy Dummy
Figure 15b. Fast Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode)
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) command prior to EBh. The “Set Burst with Wrap” (77h) command can
either enable or disable the “Wrap Around” feature for the following EBh commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. See 10.2.19 for detail descriptions.
W25Q32DW
- 36 -
Fast Read Quad I/O (EBh) in QPI Mode
The Fast Read Quad I/O instruction is also supported in QPI mode, as shown in Figure 15c. When QPI
mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)”
instruction to accommodate a wide range applications with different needs for either maximum Fast Read
frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the
number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks
upon power up or after a Reset instruction is 2. In QPI mode, the “Continuous Read Mode” bits M7-0 are
also considered as dummy clocks. In the default setting, the data output will follow the Continuous Read
Mode bits immediately.
“Continuous Read Mode” feature is also available in QPI mode for Fast Read Quad I/O instruction. Please
refer to the description on previous pages.
“Wrap Around” feature is not available in QPI mode for Fast Read Quad I/O instruction. To perform a read
operation with fixed data length wrap around in QPI mode, a dedicated “Burst Read with Wrap” (0Ch)
instruction must be used. Please refer to 10.2.39 for details.
M7-0
*
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
EBh
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6789
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
*
"Set Read Parameters" instruction (C0h) can
set the number of dummy clocks.
Byte 3
Instruction
Figure 15c. Fast Read Quad I/O Instruction (Initial instruction or previous M5-4≠10, QPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 37 - Revision D
10.2.17 Word Read Quad I/O (E7h)
The Word Read Quad I/O (E7h) instruction is similar to the Fast Read Quad I/O (EBh) instruction except
that the lowest Address bit (A0) must equal 0 and only two Dummy clock are required prior to the data
output. The Quad I/O dramatically reduces instruction overhead allowing faster random access for code
execution (XIP) directly from the Quad SPI. The Quad Enable bit (QE) of Status Register-2 must be set to
enable the Word Read Quad I/O Instruction.
Word Read Quad I/O with “Continuous Read Mode”
The Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 16a. The
upper nibble of the (M7-4) controls the length of the next Fast Read Quad I/O instruction through the
inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t care
(“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the E7h instruction code, as shown in Figure 16b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
M7-0
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0
4
Byte 1 Byte 2
0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15 16 17 18 19 20 21
Dummy
Instruction (E7h)
Figure 16a. Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)
W25Q32DW
- 38 -
M7-0
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7
4 0
5 1
6 2
7 3
A15-8 A7-0
40
5 1
6 2
7 3
Byte 1 Byte 2
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4
5
6
7
IOs switch from
Input to Output
Byte 3
8 9 10 11 12 13
Dummy
Figure 16b. Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)
Word Read Quad I/O with “8/16/32/64-Byte Wrap Around” in Standard SPI mode
The Word Read Quad I/O instruction can also be used to access a specific portion within a page by
issuing a “Set Burst with Wrap” (77h) command prior to E7h. The “Set Burst with Wrap” (77h) command
can either enable or disable the “Wrap Around” feature for the following E7h commands. When “Wrap
Around” is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a
256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the
ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the command.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
commands.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to
enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap
around section within a page. See 10.2.19 for detail descriptions.
W25Q32DW
Publication Release Date: September 18, 2012
- 39 - Revision D
10.2.18 Octal Word Read Quad I/O (E3h)
The Octal Word Read Quad I/O (E3h) instruction is similar to the Fast Read Quad I/O (EBh) instruction
except that the lower four Address bits (A0, A1, A2, A3) must equal 0. As a result, the dummy clocks are
not required, which further reduces the instruction overhead allowing even faster random access for code
execution (XIP). The Quad Enable bit (QE) of Status Register-2 must be set to enable the Octal Word
Read Quad I/O Instruction.
Octal Word Read Quad I/O with “Continuous Read Mode”
The Octal Word Read Quad I/O instruction can further reduce instruction overhead through setting the
“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in Figure 17a. The
upper nibble of the (M7-4) controls the length of the next Octal Word Read Quad I/O instruction through
the inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t
care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out
clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Quad I/O instruction (after /CS
is raised and then lowered) does not require the E3h instruction code, as shown in Figure 17b. This
reduces the instruction sequence by eight clocks and allows the Read address to be immediately entered
after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next
instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus returning to
normal operation. It is recommended to input FFh on IO0 for the next instruction (8 clocks), to ensure M4
= 1 and return the device to normal operation.
M7-0
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7 8 9
4 0
5 1
6 2
7 3
A15-8 A7-0
4
Byte 1 Byte 2
0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
Byte 3
15 16 17 18 19 20 21
Instruction (E3h)
4 0
5 1
6 2
7 3
Byte 4
Figure 17a. Octal Word Read Quad I/O Instruction (Initial instruction or previous M5-4 ≠ 10, SPI Mode only)
W25Q32DW
- 40 -
M7-0
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7
4 0
5 1
6 2
7 3
A15-8 A7-0
40
5 1
6 2
7 3
Byte 1 Byte 2
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4
5
6
7
IOs switch from
Input to Output
Byte 3
8910 11 12 13
4 0
5 1
6 2
7 3
Byte 4
Figure 17b. Octal Word Read Quad I/O Instruction (Previous instruction set M5-4 = 10, SPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 41 - Revision D
10.2.19 Set Burst with Wrap (77h)
In Standard SPI mode, the Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read
Quad I/O” and “Word Read Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section
within a 256-byte page. Certain applications can benefit from this feature and improve the overall system
code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in Figure 18. Wrap bit W7 and the lower nibble W3-0 are not used.
W6, W5 W4 = 0 W4 =1 (DEFAULT)
Wrap Around Wrap Length Wrap Around Wrap Length
0 0 Yes 8-byte No N/A
0 1 Yes 16-byte No N/A
1 0 Yes 32-byte No N/A
1 1 Yes 64-byte No N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any
page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with
Wrap instruction should be issued to set W4 = 1. The default value of W4 upon power on is 1. In the case
of a system Reset while W4 = 0, it is recommended that the controller issues a Set Burst with Wrap
instruction to reset W4 = 1 prior to any normal Read instructions since W25Q32DW does not have a
hardware Reset Pin.
In QPI mode, the “Burst Read with Wrap (0Ch)” instruction should be used to perform the Read operation
with “Wrap Around” feature. The Wrap Length set by W5-4 in Standard SPI mode is still valid in QPI mode
and can also be re-configured by “Set Read Parameters (C0h)” instruction. Refer to 10.2.38 and 10.2.39
for details.
Wrap Bit
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
2 3 4 5
X X
X X
X X
X X
don't
care
6789
don't
care
don't
care
10 11 12 13 14 15
Instruction (77h)
Mode 0
Mode 3
X X
X X
X X
X X
X X
X X
X X
X X
w4 X
w5 X
w6 X
X X
Figure 18. Set Burst with Wrap Instruction (SPI Mode only)
W25Q32DW
- 42 -
10.2.20 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by
driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address (A23-A0) and
at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in Figure 19.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceed the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks can not exceed the remaining
page length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the
page and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions
again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register
is cleared to 0. The Page Program instruction will not be executed if the addressed page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits.
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Instruction (02h)
8 9 10 28 29 30 39
24-Bit Address
23 22 21 3 2 1
*
/CS
CLK
DI
(IO
0
)
40 41 42 43 44 45 46 47
Data Byte 2
48 49 50 52 53 54 55
2072
7 6 5 4 3 2 1 0
5139
0
31
0
32 33 34 35 36 37 38
Data Byte 1
7654321
*
Mode 0
Mode 3
Data Byte 3
2073
2074
2075
2076
2077
2078
2079
0
Data Byte 256
*
7 6 5 4 3 2 1 0
*
76543210
*
= MSB
*
Figure 19a. Page Program Instruction (SPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 43 - Revision D
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
02h
3
Instruction
2 3 4 5
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6789
4 0
5 1
6 2
7 3
A15-8 A7-0 Byte1 Byte 2 Byte 3
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13
Byte 255 Byte 256
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Mode 0
Mode 3
516
517
518
519
Figure 19b. Page Program Instruction (QPI Mode)
W25Q32DW
- 44 -
10.2.21 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously
erased (FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can
improve performance for PROM Programmer and applications that have slow clock speeds <5MHz.
Systems with faster clock speed will not realize much benefit for the Quad Page Program instruction since
the inherent page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program the Quad Enable in Status Register-2 must be set (QE=1). A Write Enable
instruction must be executed before the device will accept the Quad Page Program instruction (Status
Register-1, WEL=1). The instruction is initiated by driving the /CS pin low then shifting the instruction code
“32h” followed by a 24-bit address (A23-A0) and at least one data byte, into the IO pins. The /CS pin must
be held low for the entire length of the instruction while data is being sent to the device. All other functions
of Quad Page Program are identical to standard Page Program. The Quad Page Program instruction
sequence is shown in Figure 20.
/CS
CLK
Mode 0
Mode 3 01234567
Instruction (32h)
8 9 10 28 29 30
32 33 34 35 36 37
4 0
24-Bit Address
23 22 21 3210
*
31
31
/CS
CLK
5 1
Byte 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
Byte 2 Byte 3 Byte
256
040
5 1
6 2
7 3
4 0
5 1
6 2
7 3
4 0
5 1
6 2
7 3
536
537
538
539
540
541
542
543
Mode 0
Mode 3
Byte
253
Byte
254
Byte
255
IO
0
IO
1
IO
2
IO
3
IO
0
IO
1
IO
2
IO
3
*** ****
= MSB
*
Figure 20. Quad Input Page Program Instruction (SPI Mode only)
10.2.22 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
W25Q32DW
Publication Release Date: September 18, 2012
- 45 - Revision D
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2). The
Sector Erase instruction sequence is shown in Figure 21a & 21b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase
instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase
cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of
the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is
finished and the device is ready to accept other instructions again. After the Sector Erase cycle has
finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase
instruction will not be executed if the addressed page is protected by the Block Protect (CMP, SEC, TB,
BP2, BP1, and BP0) bits (see Status Register Memory Protection table).
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (20h)
High Impedance
8 9 29 30 31
24-Bit Address
23 22 210
*
Mode 0
Mode 3
= MSB
*
Figure 21a. Sector Erase Instruction (SPI Mode)
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
20h
Instruction
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6 7
40
5 1
6 2
7 3
A15-8 A7-0
Mode 0
Mode 3
Figure 21b. Sector Erase Instruction (QPI Mode)
W25Q32DW
- 46 -
10.2.23 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 22a & 22b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits (see Status Register Memory Protection table).
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (52h)
High Impedance
8 9 29 30 31
24-Bit Address
23 22 210
*
Mode 0
Mode 3
= MSB
*
Figure 22a. 32KB Block Erase Instruction (SPI Mode)
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
52h
Instruction
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
67
40
5 1
6 2
7 3
A15-8 A7-0
Mode 0
Mode 3
Figure 22b. 32KB Block Erase Instruction (QPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 47 - Revision D
10.2.24 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0). The Block Erase
instruction sequence is shown in Figure 23a & 23b.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write
Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be
executed if the addressed page is protected by the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0)
bits (see Status Register Memory Protection table).
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (D8h)
High Impedance
8 9 29 30 31
24-Bit Address
23 22 210
*
Mode 0
Mode 3
= MSB
*
Figure 23a. 64KB Block Erase Instruction (SPI Mode)
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
D8h
Instruction
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
67
40
5 1
6 2
7 3
A15-8 A7-0
Mode 0
Mode 3
Figure 23b. 64KB Block Erase Instruction (QPI Mode)
W25Q32DW
- 48 -
DO
(IO
1
)
10.2.25 Chip Erase (C7h / 60h)
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A Write
Enable instruction must be executed before the device will accept the Chip Erase Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in Figure 24.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction will
commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress,
the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY
bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any page is protected by
the Block Protect (CMP, SEC, TB, BP2, BP1, and BP0) bits (see Status Register Memory Protection
table).
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Instruction (C7h/60h)
High Impedance
Mode 0
Mode 3
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
C7h/60h
Instruction
Mode 0
Mode 3
Figure 24. Chip Erase Instruction for SPI Mode (left) or QPI Mode (right)
W25Q32DW
Publication Release Date: September 18, 2012
- 49 - Revision D
10.2.26 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from or program/erase data to, any other sectors or
blocks. The Erase/Program Suspend instruction sequence is shown in Figure 25a & 25b.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status
Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program
Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page
Program operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend
instruction will be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is required
to suspend the erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to
0 within “tSUS” and the SUS bit in the Status Register will be set from 0 to 1 immediately after
Erase/Program Suspend. For a previously resumed Erase/Program operation, it is also required that the
Suspend instruction “75h” is not issued earlier than a minimum of time of “tSUS” following the preceding
Resume instruction “7Ah”.
Unexpected power off during the Erase/Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block
that was being suspended may become corrupted. It is recommended for the user to implement system
design techniques against the accidental power interruption and preserve data integrity during
erase/program suspend state.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (75h)
High Impedance
Mode 0
Mode 3
tSUS
Accept instructions
Figure 25a. Erase/Program Suspend Instruction (SPI Mode)
W25Q32DW
- 50 -
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
75h
Instruction
Mode 0
Mode 3
tSUS
Accept instructions
Figure 25b. Erase/Program Suspend Instruction (QPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 51 - Revision D
10.2.27 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit
equals to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from
0 to 1 within 200ns and the Sector or Block will complete the erase operation or the page will complete the
program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah”
will be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 26a &
26b.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be
issued within a minimum of time of “tSUS” following a previous Resume instruction.
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Instruction (7Ah)
Mode 0
Mode 3
Resume previously
suspended Program or
Erase
Figure 26a. Erase/Program Resume Instruction (SPI Mode)
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
7Ah
Instruction
Mode 0
Mode 3
Resume previously
suspended Program or
Erase
Figure 26b. Erase/Program Resume Instruction (QPI Mode)
W25Q32DW
- 52 -
10.2.28 Power-down (B9h)
Although the standby current during normal operation is relatively low, standby current can be further
reduced with the Power-down instruction. The lower power consumption makes the Power-down
instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC Characteristics).
The instruction is initiated by driving the /CS pin low and shifting the instruction code “B9h” as shown in
Figure 27a & 27b.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-down
instruction will not be executed. After /CS is driven high, the power-down state will entered within the time
duration of tDP (See AC Characteristics). While in the power-down state only the Release from Power-
down / Device ID instruction, which restores the device to normal operation, will be recognized. All other
instructions are ignored. This includes the Read Status Register instruction, which is always available
during normal operation. Ignoring all but one instruction makes the Power Down state a useful condition
for securing maximum write protection. The device always powers-up in the normal operation with the
standby current of ICC1.
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Instruction (B9h)
Mode 0
Mode 3
tDP
Power-down current
Stand-by current
Figure 27a. Deep Power-down Instruction (SPI Mode)
/CS
CLK Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
B9h
Instruction
Mode 0
Mode 3
tDP
Power-down currentStand-by current
Figure 27b. Deep Power-down Instruction (QPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 53 - Revision D
10.2.29 Release Power-down / Device ID (ABh)
The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to
release the device from the power-down state, or obtain the devices electronic identification (ID) number.
To release the device from the power-down state, the instruction is issued by driving the /CS pin low,
shifting the instruction code “ABh” and driving /CS high as shown in Figure 28a & 28b. Release from
power-down will take the time duration of tRES1 (See AC Characteristics) before the device will resume
normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1 time
duration.
When used only to obtain the Device ID while not in the power-down state, the instruction is initiated by
driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device ID
bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in figure
28. The Device ID values for the W25Q32DW is listed in Manufacturer and Device Identification table. The
Device ID can be read continuously. The instruction is completed by driving /CS high.
When used to release the device from the power-down state and obtain the Device ID, the instruction is
the same as previously described, and shown in Figure 28c & 28d, except that after /CS is driven high it
must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the device
will resume normal operation and other instructions will be accepted. If the Release from Power-down /
Device ID instruction is issued while an Erase, Program or Write cycle is in process (when BUSY equals
1) the instruction is ignored and will not have any effects on the current cycle.
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Instruction (ABh)
Mode 0
Mode 3
tRES1
Power-down current Stand-by current
Figure 28a. Release Power-down Instruction (SPI Mode)
W25Q32DW
- 54 -
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
ABh
Instruction
Mode 0
Mode 3
tRES1
Power-down current Stand-by current
Figure 28b. Release Power-down Instruction (QPI Mode)
tRES2
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (ABh)
High Impedance
8 9 29 30 31
3 Dummy Bytes
23 22 2 1 0
*
Mode 0
Mode 3
76543210
*
32 33 34 35 36 37 38
Device ID
Power-down current Stand-by current
= MSB
*
Figure 28c. Release Power-down / Device ID Instruction (SPI Mode)
Power-down current Stand-by current
Device ID
/CS
CLK Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
ABh
2 3 4 5
X X
X X
X X
X X
6 7 8
4 0
5 1
6 2
7 3
IOs switch from
Input to Output
Instruction
tRES2
Mode 0
Mode 3
X X
X X
X X
X X
X X
X X
X X
X X
3 Dummy Bytes
Figure 28d. Release Power-down / Device ID Instruction (QPI Mode)
W25Q32DW
Publication Release Date: September 18, 2012
- 55 - Revision D
10.2.30 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device ID
instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code “90h”
followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh)
and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first as shown
in Figure 29. The Device ID values for the W25Q32DW is listed in Manufacturer and Device Identification
table. The instruction is completed by driving /CS high.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (90h)
High Impedance
8 9 10 28 29 30 31
Address (000000h)
23 22 21 3210
Device ID
*
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
32 33 34 35 36 37 38 39
Manufacturer ID (EFh)
40 41 42 44 45 46
76543210
*
4331
0
Mode 0
Mode 3
= MSB
*
Figure 29. Read Manufacturer / Device ID Instruction (SPI Mode)
W25Q32DW
- 56 -
10.2.31 Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 2x speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a
24-bit address (A23-A0) of 000000h, but with the capability to input the Address bits two bits per clock.
After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on
the falling edge of CLK with most significant bits (MSB) first as shown in Figure 30. The Device ID values
for the W25Q32DW is listed in Manufacturer and Device Identification table. If the 24-bit address is initially
set to 000001h the Device ID will be read first and then followed by the Manufacturer ID. The
Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction
is completed by driving /CS high.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (92h)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
7 5 3 1
**
6 4 2 0
7 5 3 1
6 4 2 0
7 5 3 1
6 4 2 0
7 5 3 1
6 4 2 0
23
**
A23-16 A15-8 A7-0 (00h) M7-0
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
24 25 26 27 28 29 30 31 32 33 34 36 37 383523
0
Mode 0
Mode 3
7 5 3 1
6 4 2 0
7531
6420
7 5 3 1
6 4 2 0
7 5 3
6 4 2
1
0
1
MFR ID Device ID MFR ID
(repeat)
Device ID
IOs switch from
Input to Output
(repeat)
****
= MSB
*
Figure 30. Read Manufacturer / Device ID Dual I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Dual I/O instruction.
W25Q32DW
Publication Release Date: September 18, 2012
- 57 - Revision D
10.2.32 Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer /
Device ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID
at 4x speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a
four clock dummy cycles and then a 24-bit address (A23-A0) of 000000h, but with the capability to input
the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the Device ID
are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first as shown
in Figure 31. The Device ID values for the W25Q32DW is listed in Manufacturer and Device Identification
table. If the 24-bit address is initially set to 000001h the Device ID will be read first and then followed by
the Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to
the other. The instruction is completed by driving /CS high.
Mode 0
Mode 3 01234567
Instruction (94h)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
5 1
4 0
23
Mode 0
Mode 3
IOs switch from
Input to Output
High Impedance
7 3
6 2
/CS
CLK
IO
0
IO
1
IO
2
IO
3
High Impedance
A23-16 A15-8 A7-0
(00h) M7-0
MFR ID Device ID
Dummy Dummy
/CS
CLK
IO
0
IO
1
IO
2
IO
3
23
0
1
2
3
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
5 1
4 0
7 3
6 2
24 25 26 27 28 29 30
MFR ID Device ID
(repeat) (repeat)
MFR ID Device ID
(repeat) (repeat)
Figure 31. Read Manufacturer / Device ID Quad I/O Instruction (SPI Mode only)
Note:
The “Continuous Read Mode” bits M(7-0) must be set to Fxh to be compatible with Fast Read Quad I/O instruction.
W25Q32DW
- 58 -
10.2.33 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each W25Q32DW device. The ID number can be used in conjunction with user software methods to help
prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the /CS pin
low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After which, the 64-
bit ID is shifted out on the falling edge of CLK as shown in Figure 32.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (4Bh)
High Impedance
8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
24 25 26 27 28 29 30 31 32 33 34 36 37 383523
Mode 0
Mode 3
*
Dummy Byte 1 Dummy Byte 2
39 40 41 42
Dummy Byte 3 Dummy Byte 4
63 62 61 210
64-bit Unique Serial Number
100
101
102
High Impedance
= MSB
*
Figure 32. Read Unique ID Number Instruction (SPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 59 - Revision D
10.2.34 Read JEDEC ID (9Fh)
For compatibility reasons, the W25Q32DW provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low
and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and
two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling
edge of CLK with most significant bit (MSB) first as shown in Figure 33a & 33b. For memory type and
capacity values refer to Manufacturer and Device Identification table.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (9Fh)
High Impedance
8 9 10 12 13 14 15
Capacity ID7-0
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
16 17 18 19 20 21 22 23
Manufacturer ID (EFh)
24 25 26 28 29 30
76543210
*
2715
Mode 0
Mode 3
11
76543210
*
Memory Type ID15-8
= MSB
*
Figure 33a. Read JEDEC ID Instruction (SPI Mode)
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
9Fh
2 3 4 5
12 8
13 9
14 10
15 11
EFh
6
4 0
5 1
6 2
7 3
ID15-8 ID7-0
IOs switch from
Input to Output
Instruction
Mode 0
Mode 3
Figure 33b. Read JEDEC ID Instruction (QPI Mode)
W25Q32DW
- 60 -
10.2.35 Erase Security Registers (44h)
The W25Q32DW offers four 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other
important information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable
instruction must be executed before the device will accept the Erase Security Register Instruction (Status
Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the
instruction code “44h” followed by a 24-bit address (A23-A0) to erase one of the four security registers.
ADDRESS A23-16 A15-12 A11-8 A7-0
Security Register #0* 00h 0 0 0 0 0 0 0 0 Don’t Care
Security Register #1 00h 0 0 0 1 0 0 0 0 Don’t Care
Security Register #2 00h 0 0 1 0 0 0 0 0 Don’t Care
Security Register #3 00h 0 0 1 1 0 0 0 0 Don’t Care
* Please note that Security Register 0 is Reserved by Winbond for future use. It is
recommended to use Security registers 1- 3 before using register 0.
The Erase Security Register instruction sequence is shown in Figure 34. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time
duration of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read
Status Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is
a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept
other instructions again. After the Erase Security Register cycle has finished the Write Enable Latch
(WEL) bit in the Status Register is cleared to 0. The Security Register Lock Bits (LB3-0) in the Status
Register-2 can be used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding
security register will be permanently locked, Erase Security Register instruction to that register will be
ignored (See 11.1.9 for detail descriptions).
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (44h)
High Impedance
8 9 29 30 31
24-Bit Address
23 22 210
*
Mode 0
Mode 3
= MSB
*
Figure 34. Erase Security Registers Instruction (SPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 61 - Revision D
10.2.36 Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one
byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations.
A Write Enable instruction must be executed before the device will accept the Program Security Register
Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting
the instruction code “42h” followed by a 24-bit address (A23-A0) and at least one data byte, into the DI pin.
The /CS pin must be held low for the entire length of the instruction while data is being sent to the device.
ADDRESS A23-16 A15-12 A11-8 A7-0
Security Register #0* 00h 0 0 0 0 0 0 0 0 Byte Address
Security Register #1 00h 0 0 0 1 0 0 0 0 Byte Address
Security Register #2 00h 0 0 1 0 0 0 0 0 Byte Address
Security Register #3 00h 0 0 1 1 0 0 0 0 Byte Address
* Please note that Security Register 0 is Reserved by Winbond for future use. It is
recommended to use Security registers 1- 3 before using register 0.
The Program Security Register instruction sequence is shown in Figure 35. The Security Register Lock
Bits (LB3-0) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is
set to 1, the corresponding security register will be permanently locked, Program Security Register
instruction to that register will be ignored (See 11.1.9, 11.2.21 for detail descriptions).
/CS
CLK
DI
(IO
0
)
Mode 0
Mode 3 01234567
Instruction (42h)
8 9 10 28 29 30 39
24-Bit Address
23 22 21 321
*
/CS
CLK
40
DI
(IO
0
)
41 42 43 44 45 46 47
Data Byte 2
48 49 50 52 53 54 55
2072
5139
765432100
31
0
32 33 34 35 36 37 38
Data Byte 1
7654321
*
= MSB
*
2073
2074
2075
2076
2077
2078
2079
0
Mode 0
Mode 3
Data Byte 3 Data Byte 256
*
76543210
*
76543210
*
Figure 35. Program Security Registers Instruction (SPI Mode only)
W25Q32DW
- 62 -
10.2.37 Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving
the /CS pin low and then shifting the instruction code “48h” followed by a 24-bit address (A23-A0) and
eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the CLK
pin. After the address is received, the data byte of the addressed memory location will be shifted out on
the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte
address reaches the last byte of the register (byte FFh), it will reset to 00h, the first byte of the register,
and continue to increment. The instruction is completed by driving /CS high. The Read Security Register
instruction sequence is shown in Figure 36. If a Read Security Register instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Security Register instruction allows clock rates from D.C. to a
maximum of FR (see AC Electrical Characteristics).
ADDRESS A23-16 A15-12 A11-8 A7-0
Security Register #0* 00h 0 0 0 0 0 0 0 0 Byte Address
Security Register #1 00h 0 0 0 1 0 0 0 0 Byte Address
Security Register #2 00h 0 0 1 0 0 0 0 0 Byte Address
Security Register #3 00h 0 0 1 1 0 0 0 0 Byte Address
* Please note that Security Register 0 is Reserved by Winbond for future use. It is
recommended to use Security registers 1- 3 before using register 0.
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (48h)
High Impedance
8 9 10 28 29 30 31
24-Bit Address
23 22 21 3210
Data Out 1
*
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
32 33 34 35 36 37 38 39
Dummy Byte
High Impedance
40 41 42 44 45 46 47 48 49 50 51 52 53 54 55
765432107
Data Out 2
*
76543210
*
76543210
4331
0
= MSB
*
Figure 36. Read Security Registers Instruction (SPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 63 - Revision D
10.2.38 Set Read Parameters (C0h)
In QPI mode, to accommodate a wide range of applications with different needs for either maximum read
frequency or minimum data access latency, “Set Read Parameters (C0h)” instruction can be used to
configure the number of dummy clocks for “Fast Read (0Bh)”, “Fast Read Quad I/O (EBh)” & “Burst Read
with Wrap (0Ch)” instructions, and to configure the number of bytes of “Wrap Length” for the “Burst Read
with Wrap (0Ch)” instruction.
In Standard SPI mode, the “Set Read Parameters (C0h)” instruction is not accepted. The dummy clocks
for various Fast Read instructions in Standard/Dual/Quad SPI mode are fixed, please refer to the
Instruction Table 10.2.2-10.2.4 for details. The “Wrap Length” is set by W5-4 bit in the “Set Burst with
Wrap (77h)” instruction. This setting will remain unchanged when the device is switched from Standard
SPI mode to QPI mode.
The default “Wrap Length” after a power up or a Reset instruction is 8 bytes, the default number of
dummy clocks is 2. The number of dummy clocks is only programmable for “Fast Read (0Bh)”, “Fast
Read Quad I/O (EBh)” & “Burst Read with Wrap (0Ch)” instructions in the QPI mode. Whenever the
device is switched from SPI mode to QPI mode, the number of dummy clocks should be set again, prior to
any 0Bh, EBh or 0Ch instructions.
P5 – P4 DUMMY
CLOCKS
MAXIMUM READ
FREQ.
MAXIMUM
READ FREQ.
(A[1:0]=0,0)
P1 – P0 WRAP
LENGTH
0 0 2 30MHz 30MHz 0 0 8-byte
0 1 4 50MHz 80MHz 0 1 16-byte
1 0 6 80MHz 104MHz 1 0 32-byte
1 1 8 104MHz 104MHz 1 1 64-byte
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
C0h
2 3
Read
Parameters
P4 P0
P5 P1
P6 P2
P7 P3
Instruction
Mode 0
Mode 3
Figure 37. Set Read Parameters Instruction (QPI Mode only)
W25Q32DW
- 64 -
10.2.39 Burst Read with Wrap (0Ch)
The “Burst Read with Wrap (0Ch)” instruction provides an alternative way to perform the read operation
with “Wrap Around” in QPI mode. The instruction is similar to the “Fast Read (0Bh)” instruction in QPI
mode, except the addressing of the read operation will “Wrap Around” to the beginning boundary of the
“Wrap Length” once the ending boundary is reached.
The “Wrap Length” and the number of dummy clocks can be configured by the “Set Read Parameters
(C0h)” instruction.
Dummy
*
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
0Ch
2345
20 16 12 8
21 17
22 18
23 19
13 9
14 10
15 11
A23-16
6789
4 0
5 1
6 2
7 3
A15-8 A7-0
Byte 1 Byte 2
40
5 1
6 2
7 3
4 0
5 1
6 2
7 3
10 11 12 13 14
4
5
6
7
IOs switch from
Input to Output
*
"Set Read Parameters" instruction (C0h) can
Byte 3
Instruction
set the number of dummy clocks.
Figure 38. Burst Read with Wrap Instruction (QPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 65 - Revision D
(IO
1
)
10.2.40 Enable QPI (38h)
The W25Q32DW support both Standard/Dual/Quad Serial Peripheral Interface (SPI) and Quad Peripheral
Interface (QPI). However, SPI mode and QPI mode can not be used at the same time. “Enable QPI (38h)”
instruction is the only way to switch the device from SPI mode to QPI mode.
Upon power-up, the default state of the device upon is Standard/Dual/Quad SPI mode. This provides full
backward compatibility with earlier generations of Winbond serial flash memories. See Intruction Set
Table 1-3 for all supported SPI commands. In order to switch the device to QPI mode, the Quad Enable
(QE) bit in Status Register 2 must be set to 1 first, and an “Enable QPI (38h)” instruction must be issued. If
the Quad Enable (QE) bit is 0, the “Enable QPI (38h)” instruction will be ignored and the device will remain
in SPI mode.
See Instruction Set Table 4 for all the commands supported in QPI mode.
When the device is switched from SPI mode to QPI mode, the exsiting Write Enable and Program/Erase
Suspend status, and the Wrap Length setting will remain unchanged.
/CS
CLK
DI
(IO
0
)
DO
Mode 0
Mode 3 01234567
Instruction (38h)
High Impedance
Mode 0
Mode 3
Figure 39. Enable QPI Instruction (SPI Mode only)
W25Q32DW
- 66 -
10.2.41 Disable QPI (FFh)
In order to exit the QPI mode and return to the Standard/Dual/Quad SPI mode, a “Disable QPI (FFh)”
instruction must be issued.
When the device is switched from QPI mode to SPI mode, the exsiting Write Enable Latch (WEL) and
Program/Erase Suspend status, and the Wrap Length setting will remain unchanged.
/CS
CLK Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
FFh
Instruction
Mode 0
Mode 3
Figure 40. Disable QPI Instruction (QPI Mode only)
W25Q32DW
Publication Release Date: September 18, 2012
- 67 - Revision D
10.2.42 Enable Reset (66h) and Reset (99h)
Because of the small package and the limitation on the number of pins, the W25Q32DW provide a
software Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any
on-going internal operations will be terminated and the device will return to its default power-on state and
lose all the current volatile settings, such as Volatile Status Register bits, Write Enable Latch (WEL)
status, Program/Erase Suspend status, Read parameter setting (P7-P0), Continuous Read Mode bit
setting (M7-M0) and Wrap Bit setting (W6-W4).
“Enable Reset (66h)” and “Reset (99h)” instructions can be issued in either SPI mode or QPI mode. To
avoid accidental reset, both instructions must be issued in sequence. Any other commands other than
“Reset (99h)” after the “Enable Reset (66h)” command will disable the “Reset Enable” state. A new
sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the device. Once the Reset
command is accepted by the device, the device will take approximately tRST=30us to reset. During this
period, no command will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation
when Reset command sequence is accepted by the device. It is recommended to check the BUSY bit and
the SUS bit in Status Register before issuing the Reset command sequence.
Mode 0
Mode 3 01234567
Instruction (99h)
Mode 0
Mode 3
/CS
CLK
DI
(IO
0
)
DO
(IO
1
)
Mode 0
Mode 3 01234567
Instruction (66h)
High Impedance
Figure 41a. Enable Reset and Reset Instruction Sequence (SPI Mode)
Mode 0
Mode 3 0 1
99h
Instruction
Mode 0
Mode 3
/CS
CLK
Mode 0
Mode 3 0 1
IO
0
IO
1
IO
2
IO
3
66h
Instruction
Figure 41b. Enable Reset and Reset Instruction Sequence (QPI Mode)
W25Q32DW
- 68 -
11. ELECTRICAL CHARACTERISTICS
11.1 Absolute Maximum Ratings (1)
PARAMETERS SYMBOL CONDITIONS RANGE UNIT
Supply Voltage VCC –0.6 to VCC+0.4 V
Voltage Applied to Any Pin VIO Relative to Ground –0.6 to VCC+0.4 V
Transient Voltage on any Pin VIOT <20nS Transient
Relative to Ground –1.0V to VCC+1.0V V
Storage Temperature TSTG –65 to +150 °C
Lead Temperature TLEAD See Note
(2) °C
Electrostatic Discharge Voltage VESD Human Body Model(3) –2000 to +2000 V
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the
European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
11.2 Operating Ranges
PARAMETER SYMBOL CONDITIONS SPEC UNIT
MIN MAX
Supply Voltage(1) VCC FR = 104MHz, fR = 50MHz 1.7 1.95 V
Ambient Temperature,
Operating TA Industrial –40 +85 °C
Note:
1. VCC voltage during Read can operate across the min and max range but should not exceed ±10% of
the programming (erase/write) voltage.
W25Q32DW
Publication Release Date: September 18, 2012
- 69 - Revision D
11.3 Power-Up Power-Down Timing and Requirements
PARAMETER SYMBOL
SPEC UNIT
MIN MAX
VCC (min) to /CS Low tVSL(1) 10 µs
Time Delay Before Write Instruction tPUW(1) 1 10 ms
Write Inhibit Threshold Voltage VWI(1) 1.0 1.4 V
Note:
1. These parameters are characterized only.
VCC
tVSL Read Instructions
Allowed
Device is fully
Accessible
tPUW
/CS must track VCC
Program, Erase and Write Instructions are ignored
Reset
State
VCC
(max)
VCC
(min)
V
WI
Time
Figure 43a. Power-up Timing and Voltage Levels
VCC
Time
/CS must track VCC
during VCC Ramp Up/Down
/CS
Figure 43b. Power-up, Power-Down Requirement
W25Q32DW
- 70 -
11.4 DC Electrical Characteristics
PARAMETER SYMBOL CONDITIONS SPEC UNIT
MIN TYP MAX
Input Capacitance CIN(1) VIN = 0V(1) 6 pF
Output Capacitance Cout(1) VOUT = 0V(1) 8 pF
Input Leakage ILI ±2 µA
I/O Leakage ILO ±2 µA
Standby Current ICC1 /CS = VCC,
VIN = GND or VCC 10 40 µA
Power-down Current ICC2 /CS = VCC,
VIN = GND or VCC 1 20 µA
Current Read Data /
Dual /Quad 1MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC
DO = Open 15 mA
Current Read Data /
Dual /Quad 50MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC
DO = Open 20 mA
Current Read Data /
Dual /Quad 80MHz(2) ICC3 C = 0.1 VCC / 0.9 VCC
DO = Open 30 mA
Current Read Data /
Dual Output Read/Quad
Output Read 104MHz(2)
ICC3 C = 0.1 VCC / 0.9 VCC
DO = Open 40 mA
Current Write Status
Register ICC4 /CS = VCC 8 12 mA
Current Page Program ICC5 /CS = VCC 20 25 mA
Current Sector/Block
Erase ICC6 /CS = VCC 20 25 mA
Current Chip Erase ICC7 /CS = VCC 20 25 mA
Input Low Voltage VIL –0.5 VCC x 0.3 V
Input High Voltage VIH VCC x 0.7 VCC + 0.4 V
Output Low Voltage VOL IOL = 100 µA 0.2 V
Output High Voltage VOH IOH = –100 µA VCC – 0.2 V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 1.8V.
2. Checker Board Pattern.
W25Q32DW
Publication Release Date: September 18, 2012
- 71 - Revision D
11.5 AC Measurement Conditions
PARAMETER SYMBOL
SPEC UNIT
MIN MAX
Load Capacitance CL 30 pF
Input Rise and Fall Times TR, TF 5 ns
Input Pulse Voltages VIN 0.1 VCC to 0.9 VCC V
Input Timing Reference Voltages IN 0.3 VCC to 0.7 VCC V
Output Timing Reference Voltages OUT 0.5 VCC to 0.5 VCC V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
Input and Output
Timing Reference Levels
Input Levels
0.9 VCC
0.1 VCC
0.5 VCC
Figure 39. AC Measurement I/O Waveform
W25Q32DW
- 72 -
11.6 AC Electrical Characteristics
DESCRIPTION SYMBOL ALT
SPEC UNIT
MIN TYP MAX
Clock frequency for SPI Read data instructions
(03h) fR D.C. 50 MHz
Clock frequency for SPI Quad Read instructions
(6Bh,EBh,E7h,E3h) FR f
C1 D.C. 80 MHz
Clock frequency for QPI Read instructions(0Bh,
EBh,0Ch) with 2/4/6/8 dummy clocks
FR f
C1 D.C. 30/50/80/104 MHz
Clock frequency for QPI Read instructions(0Bh,
EBh,0Ch) with 2/4/6/8 dummy clocks, A<1:0>=0,0
FR f
C1 D.C. 30/80/104/104 MHz
Clock frequency for all other SPI/QPI instructions FR f
C1 D.C. 104 MHz
Clock High, Low Time
for all instructions except for Read Data (03h)
tCLH,
tCLL(1)
4 ns
Clock High, Low Time
for Read Data (03h) instruction
tCRLH,
tCRLL(1)
8
8
ns
Clock Rise Time peak to peak tCLCH(2) 0.1 V/ns
Clock Fall Time peak to peak tCHCL(2) 0.1 V/ns
/CS Active Setup Time relative to CLK tSLCH tCSS 5 ns
/CS Not Active Hold Time relative to CLK tCHSL 5 ns
Data In Setup Time tDVCH tDSU 2 ns
Data In Hold Time tCHDX tDH 3 ns
/CS Active Hold Time relative to CLK tCHSH 5 ns
/CS Not Active Setup Time relative to CLK tSHCH 5 ns
/CS Deselect Time (for Array Read Æ Array
Read)
tSHSL1 tCSH 10 ns
/CS Deselect Time (for Erase or Program Æ Read
Status Registers)
Volatile Status Register Write Time
tSHSL2 tCSH 50
50
ns
Output Disable Time tSHQZ(2) tDIS 7 ns
Clock Low to Output Valid tCLQV1 tV1 7 ns
Clock Low to Output Valid (for Read ID
instructions) tCLQV2 tV2 7.5 ns
Output Hold Time tCLQX tHO 0 ns
/HOLD Active Setup Time relative to CLK tHLCH 5 ns
Continued – next page
W25Q32DW
Publication Release Date: September 18, 2012
- 73 - Revision D
11.7 AC Electrical Characteristics (cont’d)
DESCRIPTION SYMBOL ALT
SPEC
UNIT
MIN TYP MAX
/HOLD Active Hold Time relative to CLK tCHHH 5 ns
/HOLD Not Active Setup Time relative to CLK tHHCH 5 ns
/HOLD Not Active Hold Time relative to CLK tCHHL 5 ns
/HOLD to Output Low-Z tHHQX(2) tLZ 7 ns
/HOLD to Output High-Z tHLQZ(2) tHZ 12 ns
Write Protect Setup Time Before /CS Low tWHSL(3) 20 ns
Write Protect Hold Time After /CS High tSHWL(3) 100 ns
/CS High to Power-down Mode tDP(2) 3 µs
/CS High to Standby Mode without Electronic
Signature Read
tRES1(2) 30 µs
/CS High to Standby Mode with Electronic Signature
Read
tRES2(2) 30 µs
/CS High to next Instruction after Suspend tSUS(2) 20 µs
/CS High to next Instruction after Reset tRST(2) 30 µs
Write Status Register Time tW 10 15 ms
Byte Program Time (First Byte) (4) t
BP1 20 50 µs
Additional Byte Program Time (After First Byte) (4) t
BP2 2.5 10 µs
Page Program Time tPP 0.7 3 ms
Sector Erase Time (4KB) tSE 30 200/400(5) ms
Block Erase Time (32KB) tBE1 120 800 ms
Block Erase Time (64KB) tBE2 150 1,000 ms
Chip Erase Time tCE 7.5 30 s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. Only applicable as a constraint for a Write Status Register instruction when Sector Protect Bit is set to 1.
4. For multiple bytes after first byte within a page, tBPN = tBP1 + tBP2 * N (typical) and tBPN = tBP1 + tBP2 * N (max), where N =
number of bytes programmed.
5. Max Value tSE with <50K cycles is 200ms and >50K & <100K cycles is 400ms.
W25Q32DW
- 74 -
11.8 Serial Output Timing
11.9 Serial Input Timing
11.10 Hold Timing
W25Q32DW
Publication Release Date: September 18, 2012
- 75 - Revision D
12. PACKAGE SPECIFICATION
12.1 8-Pin SOIC 208-mil (Package Code SS)
θ
GAUGE PLANE
θ
GAUGE PLANE
SYMBOL MILLIMETERS INCHES
Min Nom Max Min Nom Max
A 1.75 1.95 2.16 0.069 0.077 0.085
A1 0.05 0.15 0.25 0.002 0.006 0.010
A2 1.70 1.80 1.91 0.067 0.071 0.075
b 0.35 0.42 0.48 0.014 0.017 0.019
C 0.19 0.20 0.25 0.007 0.008 0.010
D 5.18 5.28 5.38 0.204 0.208 0.212
D1 5.13 5.23 5.33 0.202 0.206 0.210
E 5.18 5.28 5.38 0.204 0.208 0.212
E1 5.13 5.23 5.33 0.202 0.206 0.210
e
(2)
1.27 BSC. 0.050 BSC.
H 7.70 7.90 8.10 0.303 0.311 0.319
L 0.50 0.65 0.80 0.020 0.026 0.031
y --- --- 0.10 --- --- 0.004
θ 0° --- 8° 0° --- 8°
Notes:
1. Controlling dimensions: millimeters, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package.
4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.
W25Q32DW
- 76 -
12.2 8-Contact 6x5mm WSON (Package Code ZP)
SYMBOL MILLIMETERS INCHES
Min Nom Max Min Nom Max
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.35 0.40 0.48 0.014 0.016 0.019
C --- 0.20 REF. --- --- 0.008 REF. ---
D 5.90 6.00 6.10 0.232 0.236 0.240
D2 3.35 3.40 3.45 0.132 0.134 0.136
E 4.90 5.00 5.10 0.193 0.197 0.201
E2 4.25 4.30 4.35 0.167 0.169 0.171
e
(2)
1.27 BSC. 0.050 BSC.
L 0.55 0.60 0.65 0.022 0.024 0.026
y 0.00 --- 0.075 0.000 --- 0.003
W25Q32DW
Publication Release Date: September 18, 2012
- 77 - Revision D
8-Contact 6x5mm WSON Cont’d.
SYMBOL MILLIMETERS INCHES
Min Nom Max Min Nom Max
SOLDER PATTERN
M 3.40 0.134
N 4.30 0.169
P 6.00 0.236
Q 0.50 0.020
R 0.75 0.026
Notes:
1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.
4. The metal pad area on the bottom center of the package is connected to the device ground (GND pin). Avoid placement of
exposed PCB vias under the pad.
W25Q32DW
- 78 -
12.3 8-Contact 8x6mm WSON (Package Code ZE)
SYMBOL MILLIMETERS INCHES
Min Nom Max Min Nom Max
A 0.70 0.75 0.80 0.028 0.030 0.031
A1 0.00 0.02 0.05 0.000 0.001 0.002
b 0.35 0.40 0.48 0.014 0.016 0.019
C 0.19 0.20 0.25 0.007 0.008 0.010
D 7.90 8.00 8.10 0.311 0.315 0.319
D2 4.60 4.65 4.70 0.181 0.183 0.185
E 5.90 6.00 6.10 0.232 0.236 0.240
E2 5.15 5.20 5.25 0.203 0.205 0.207
e 1.27 BSC 0.050 BSC
L 0.45 0.50 0.55 0.018 0.020 0.022
y 0.00 --- 0.050 0.000 --- 0.002
W25Q32DW
Publication Release Date: September 18, 2012
- 79 - Revision D
12.4 16-Pin SOIC 300-mil (Package Code SF)
GAUGE PLANE
DETAIL A
GAUGE PLANE
DETAIL A
SYMBOL MILLIMETERS INCHES
Min Nom Max Min Nom Max
A 2.36 2.49 2.64 0.093 0.098 0.104
A1 0.10 --- 0.30 0.004 --- 0.012
A2 --- 2.31 --- --- 0.091 ---
b 0.33 0.41 0.51 0.013 0.016 0.020
C 0.18 0.23 0.28 0.007 0.009 0.011
D 10.08 10.31 10.49 0.397 0.406 0.413
E 10.01 10.31 10.64 0.394 0.406 0.419
E1 7.39 7.49 7.59 0.291 0.295 0.299
e(2) 1.27 BSC. 0.050 BSC.
L 0.38 0.81 1.27 0.015 0.032 0.050
y --- --- 0.076 --- --- 0.003
θ 0° --- 8° 0° --- 8°
Notes:
1. Controlling dimensions: inches, unless otherwise specified.
2. BSC = Basic lead spacing between centers.
3. Dimensions D and E1 do not include mold flash protrusions and should be measured from the bottom of the package.
W25Q32DW
- 80 -
13. ORDERING INFORMATION
W(1) 25Q 32D W x
x
(2)
(3,4)
G = Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
P = Green Package with Status Register Power-Down & OTP enabled
I = Industrial (-40°C to +85°C)
SS = 8-pin SOIC 208-mil ZP = 8-pad WSON 6x5mm
SF = 16-pin SOIC 300-mil ZE = 8-pad WSON 8x6mm
W = 1.7V to 1.95V
32D = 32M-bit
25Q = SpiFlash Serial Flash Memory with 4KB sectors, Dual/Quad I/O
W = Winbond
Notes:
1. The “W” prefix is not included on the part marking.
2. Only the 2nd letter is used for the part marking; WSON package type ZP and ZE are not used for the part
marking.
3. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and
Reel (shape T) or Tray (shape S), when placing orders.
4. For shipments with OTP feature enabled, please specify when placing orders.
W25Q32DW
Publication Release Date: September 18, 2012
- 81 - Revision D
13.1 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25Q32DW SpiFlash Memory. Please contact
Winbond for specific availability by density and package type. Winbond SpiFlash memories use an 12-digit
Product Number for ordering. However, due to limited space, the Top Side Marking on all packages use
an abbreviated 10-digit number.
PACKAGE TYPE DENSITY PRODUCT NUMBER TOP SIDE MARKING
SS
SOIC-8 208mil 32M-bit W25Q32DWSSIG
W25Q32DWSSIP
25Q32DWSIG
25Q32DWSIP
SF
SOIC-16 300mil 32M-bit W25Q32DWSFIG
W25Q32DWSFIP
25Q32DWFIG
25Q32DWFIP
ZP(1)
WSON-8 6x5mm 32M-bit W25Q32DWZPIG
W25Q32DWZPIP
25Q32DWIG
25Q32DWIP
ZE(1)(2)
WSON-8 8x6mm 32M-bit W25Q32DWZEIG
W25Q32DWZEIP
25Q32DWIG
25Q32DWIP
Notes:
1. For WSON packages, the package type ZP and ZE are not used in the top side marking.
2. Package type ZE (WSON-8 8x6mm) is a special order package, please contact Winbond for ordering
information.
W25Q32DW
- 82 -
14. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A 11/11/09 New Create Preliminary
B 08/03/10 All Updated QPI instruction diagrams
C 01/14/11
55
63
70-71
72
na
63
72-73
Updated instruction 90h description
Updated dummy clocks description & frequency
Updated ICC1, ICC2, Vin, Vin Waveform
Updated maximum frequency
Update VCC Range
Update Set Read Parameter (C0h)
Update parameters tCE & tCHDX
D 09/18/12 All
69
Removed preliminary designator
Added power-down requirement
Trademarks
Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems
or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Further more, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur. Winbond customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document
and the products and services described herein at any time, without notice.
