PRELIMINARY DATA SHEET • AAT1110 FAST TRANSIENT 800 MA STEP-DOWN CONVERTER
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com
10 September 11, 2013 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 201971D
S
OUT
PP
)MIN(IN f4ESR
I
V
1
C
Where, fS is the switching frequency.
Always examine the ceramic capacitor DC voltage coefficient
characteristics when selecting the proper value. For example,
the capacitance of a 10 F, 6.3 V, X5R ceramic capacitor with
5.0 V DC applied is actually about 6 F.
The maximum input capacitor RMS current is:
IN
OUT
IN
OUT
OUTRMS V
V
1
V
V
II
The input capacitor RMS ripple current varies with the input and
output voltage and always is less than or equal to half of the
total DC load current.
2
1
5.0D1D
V
V
1
V
V2
IN
OUT
IN
OUT
for VIN = 2 VOUT
2
I
IOUT
MAXRMS
)(
The term
IN
OUT
IN
OUT V
V
1
V
V appears in both the input voltage
ripple and input capacitor RMS current equations and is a
maximum when VOUT is twice VIN. This is why the input voltage
ripple and the input capacitor RMS current ripple are a
maximum at 50% duty cycle.
The input capacitor provides a low impedance loop for the
edges of pulsed current drawn by the AAT1110. Low ESR/ESL
X7R and X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high frequency
content of the input current localized, minimizing EMI and input
voltage ripple.
The proper placement of the input capacitor (C2) can be seen in
the evaluation board layout in Figure 28.
A laboratory test setup typically consists of two long wires
running from the bench power supply to the evaluation board
input voltage pins. The inductance of these wires, along with
the low-ESR ceramic input capacitor, can create a high-Q
network that may affect converter performance. This problem
often becomes apparent in the form of excessive ringing in the
output voltage during load transients. Errors in the loop phase
and gain measurements can also result.
Because the inductance of a short PCB trace feeding the input
voltage is significantly lower than the power leads from the
bench power supply, most applications do not exhibit this
problem.
In applications where the input power source lead inductance
cannot be reduced to a level that does not affect the converter
performance, a high ESR tantalum or aluminum electrolytic
should be placed in parallel with the low ESR, ESL bypass
ceramic. This dampens the high-Q network and stabilizes the
system.
Output Capacitor
The output capacitor limits the output ripple and provides
holdup during large load transitions. A 4.7 F to 10 F X5R or
X7R ceramic capacitor typically provides sufficient bulk
capacitance to stabilize the output during large load transitions
and has the ESR and ESL characteristics necessary for low
output ripple.
The output voltage droop due to a load transient (ILOAD) is
dominated by the capacitance of the ceramic output capacitor.
During a step increase in load current, the ceramic output
capacitor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match the load
current demand. The relationship of the output voltage droop
during the three switching cycles to the output capacitance can
be estimated by:
SDROOP
LOAD
OUT fV I3
C
Once the average inductor current increases to the DC load
level, the output voltage recovers. The above equation
establishes a limit on the minimum value for the output
capacitor with respect to load transients.
The internal voltage loop compensation also limits the minimum
output capacitor value to 4.7 F. This is due to its effect on the
loop crossover frequency (bandwidth), phase margin, and gain
margin. Increased output capacitance reduces the crossover
frequency with greater phase margin.
The maximum output capacitor RMS ripple current is given by:
)MAX(INS
OUT)MAX(INOUT
MAXRMS VfL
VVV
32
1
I
)(
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than a few
degrees rise in hot-spot temperature.