LTC2391HLX-16#PBF - ANALOG DEVICES

LTC2391-16

239116fa

TYPICAL APPLICATION

DESCRIPTION

16-Bit, 250ksps SAR ADC

with 94dB SNR

The LTC

2391-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC. Operating

from a single 5V supply, the LTC2391-16 supports a large

±4.096V fully differential input range, making it ideal for

high performance applications which require maximum

dynamic range. The LTC2391-16 achieves ±2LSB INL

max, no missing codes at 16-bits and 94dB SNR (typ).

The LTC2391-16 includes a precision internal reference

with a guaranteed 0.5% initial accuracy and a ±20ppm/°C

(max) temperature coefﬁ cient. Fast 250ksps throughput

with no cycle latency in both parallel and serial interface

modes makes the LTC2391-16 ideally suited for a wide

variety of high speed applications. An internal oscillator

sets the conversion time, easing external timing con-

siderations. The LTC2391-16 dissipates only 95mW at

250ksps, while both nap and sleep power-down modes are

provided to further reduce power during inactive periods.

FEATURES

APPLICATIONS

n 250ksps Throughput Rate

n ±2LSB INL (Max)

n Guaranteed 16-Bit No Missing Codes

n 94dB SNR (Typ) at fIN = 20kHz

n Guaranteed Operation to 125°C

n Single 5V Supply

n 1.8V to 5V I/O Voltages

n 95mW Power Dissipation

n ±4.096V Differential Input Range

n Internal Reference (20ppm/°C Max)

n No Pipeline Delay, No Cycle Latency

n Parallel and Serial Interface

n Internal Conversion Clock

n 48-Lead 7mm × 7mm LQFP and QFN Packages

n Medical Imaging

n High Speed Data Acquisition

n Digital Signal Processing

n Industrial Process Control

n Instrumentation

n ATE

16k Point FFT fS = 250ksps,

fIN = 20kHz

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

0.1μF10μF

SER/PAR

BYTESWAP

OB/2C

BUSY

PARALLEL

SERIAL

INTERFACE

OGND

239116 TA01

IN–

IN+

2200pF

249Ω

ANALOG INPUT

0V TO 4.096V

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER GNDRESETCNVST PD

SAMPLE CLOCK

REFOUTREFIN

AVP DVP

LTC2391-16

OVP

1.8V TO 5V

16 BIT

VCM

1μF10μF

4.7μF

LT6350

FREQUENCY (kHz)

–180

AMPLITUDE (dBFS)

–160

–120

–100

–80

50 100 125

239116 G08

–140

25 75

–60

–40

–20 SNR = 94dB

THD  –103dB

SINAD = 93.5dB

SFDR = 104dB

LTC2391-16

239116fa

Supply Voltage (VAVP

, VDVP , VOVP) ..........................6.0V

Analog Input Voltage (Note 3)

IN+, IN–, REFIN, CNVST .. (GND – 0.3V) to (VAVP + 0.3V)

Digital Input Voltage ........(GND – 0.3V) to (VOVP + 0.3V)

Digital Output Voltage .....(GND – 0.3V) to (VOVP + 0.3V)

Power Dissipation ...............................................500mW

(Notes 1, 2)

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2391CUK-16#PBF LTC2391CUK-16#TRPBF LTC2391UK-16 48-Lead 7mm × 7mm Plastic QFN 0°C to 70°C

LTC2391IUK-16#PBF LTC2391IUK-16#TRPBF LTC2391UK-16 48-Lead 7mm × 7mm Plastic QFN –40°C to 85°C

LEAD FREE FINISH TRAY PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC2391CLX-16#PBF LTC2391CLX-16#PBF LTC2391LX-16 48-Lead 7mm × 7mm Plastic LQFP 0°C to 70°C

LTC2391ILX-16#PBF LTC2391ILX-16#PBF LTC2391LX-16 48-Lead 7mm × 7mm Plastic LQFP –40°C to 85°C

LTC2391HLX-16#PBF LTC2391HLX-16#PBF LTC2391LX-16 48-Lead 7mm × 7mm Plastic LQFP –40°C to 125°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁ nish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁ cations, go to: http://www.linear.com/tapeandreel/

ABSOLUTE MAXIMUM RATINGS

TOP VIEW

GND

UK PACKAGE

48-LEAD (7mm s 7mm) PLASTIC QFN

GND 1

AVP 2

DVP 3

SER/PAR 4

GND 5

OB/2C 6

GND 7

BYTESWAP 8

D0 9

D1 10

D2 11

D3 12

36 VCM

35 GND

34 CNVST

33 PD

32 RESET

31 CS

30 RD

29 BUSY

28 D15

27 D14

26 D13

25 D12

48 GND

47 AVP

46 AVP

45 AVP

44 GND

43 IN+

42 IN–

41 GND

40 AVP

39 REFSENSE

38 REFIN

37 REFOUT

D4 13

D5 14

D6 15

D7 16

OGND 17

OVP 18

DVP 19

GND 20

D8 21

D9/SDIN 22

D10/SDOUT 23

D11/SCLK 24

TJMAX = 125°C, θJA = 29°C/W

EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB

GND

AVP

DVP

SER/PAR

GND

OB/2C

GND

BYTESWAP

OGND

OVP

DVP

GND

D9/SDIN

D10/SDOUT

D11/SCLK

GND

AVP

GND

IN+

IN–

GND

AVP

REFSENSE

REFIN

REFOUT

VCM

GND

CNVST

RESET

BUSY

D15

D14

D13

D12

TOP VIEW

LX PACKAGE

48-LEAD (7mm s 7mm) PLASTIC LQFP

TJMAX = 150°C, θJA = 55°C/W

PIN CONFIGURATION

Operating Temperature Range

LTC2391C ................................................ 0°C to 70°C

LTC2391I.............................................. –40°C to 85°C

LTC2391H .......................................... –40°C to 125°C

Storage Temperature Range ................... –65°C to 150°C

LTC2391-16

239116fa

ANALOG INPUT

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise

speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIN+Absolute Input Range (IN+) (Note 5) l–0.05 AVP V

VIN–Absolute Input Range (IN–) (Note 5) l–0.05 AVP V

VIN+ – VIN–Input Differential Voltage Range VIN = VIN+ – VIN– l–VREF VREF V

VCM Common Mode Input Range lVREF/2 – 0.05 VREF/2 VREF/2 + 0.05 V

IIN Analog Input Leakage Current l±1 μA

CIN Analog Input Capacitance Sample Mode

Hold Mode

CMRR Input Common Mode Rejection Ratio 70 dB

CONVERTER CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating

temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Resolution l16 Bits

No Missing Codes l16 Bits

Transition Noise 0.3 LSBRMS

INL Integral Linearity Error (Note 6) l–2 ±1 2 LSB

DNL Differential Linearity Error l–1 1 LSB

BZE Bipolar Zero Error (Note 7) l–7 7 LSB

Bipolar Zero Error Drift 1 ppm/°C

FSE Bipolar Full-Scale Error External Reference

Internal Reference (Note 7)

l0.14

0.1

Bipolar Full-Scale Error Drift ±10 ppm/°C

DYNAMIC ACCURACY

The l denotes the speciﬁ cations which apply over the full operating temperature range,

otherwise speciﬁ cations are at TA = 25°C. AIN = –1dBFS (Notes 4, 8)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SINAD Signal-to-(Noise + Distortion) Ratio fIN = 20kHz l90.5 93.5 dB

SNR Signal-to-Noise Ratio fIN = 20kHz l91 94 dB

THD Total Harmonic Distortion fIN = 20kHz, First 5 Harmonics l–103 –94 dB

SFDR Spurious-Free Dynamic Range fIN = 20kHz 104 dB

–3dB Input Bandwidth 50 MHz

Aperture Delay 0.5 ns

Aperture Jitter 7ps

RMS

Transient Response Full-Scale Step 60 ns

LTC2391-16

239116fa

PARAMETER CONDITIONS MIN TYP MAX UNITS

VREF Output Voltage IOUT = 0 4.076 4.096 4.116 V

VREF Output Tempco IOUT = 0 (I-, H-Grades) (Note 11) l±10 ±20 ppm/°C

VREF Output Impedance –0.1mA ≤ IOUT ≤ 0.1mA 2.6 kΩ

External Reference Voltage 2.5 4.096 AVP – 0.5 V

REFIN Input Impedance 85 kΩ

VREF Line Regulation AVP = 4.75V to 5.25V 0.3 mV/V

VCM Output Voltage IOUT = 0 2.08 V

DIGITAL INPUTS AND DIGITAL OUTPUTS

The l denotes the speciﬁ cations which apply over the full

operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage l0.8 • OVP V

VIL Low Level Input Voltage l0.5 V

IIN Digital Input Current VIN = 0V to OVP l–10 10 μA

CIN Digital Input Capacitance 5pF

VOH High Level Output Voltage IO = –500μA lOVP – 0.2 V

VOL Low Level Output Voltage IO = 500μA l0.2 V

IOZ Hi-Z Output Leakage Current VOUT = 0V to OVP l–10 10 μA

ISOURCE Output Source Current VOUT = 0V –10 mA

ISINK Output Sink Current VOUT = OVP 10 mA

POWER REQUIREMENTS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VAVP

, VDVP Supply Voltage l4.75 5 5.25 V

VOVP Supply Voltage 1.71 5.25 V

IDD Supply Current

Power Down Mode

250ksps Sample Rate with Nap Mode

Conversion Done and All Digital Inputs Tied to OVP

250

μA

PDPower Dissipation

Power Down Mode

250ksps Sample Rate with Nap Mode

Conversion Done and All Digital Inputs Tied to OVP

175

125

1250

μW

INTERNAL REFERENCE CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full

operating temperature range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

LTC2391-16

239116fa

TIMING CHARACTERISTICS

The l denotes the speciﬁ cations which apply over the full operating temperature

range, otherwise speciﬁ cations are at TA = 25°C. (Note 4)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

fSMPL Sampling Frequency l250 ksps

tCONV Conversion Time l2500 ns

tACQ Acquisition Time l1485 ns

t4CNVST Low Time l20 ns

t5CNVST High Time l250 ns

t6CNVST↓ to BUSY Delay CL = 15pF l15 ns

t7RESET Pulse Width l5ns

t8SCLK Period (Note 9) l12.5 ns

t9SCLK High Time l4ns

t10 SCLK Low Time l4ns

, tfSCLK Rise and Fall Times (Note 10) 1 μs

t11 SDIN Setup Time l2ns

t12 SDIN Hold Time l1ns

t13 SDOUT Delay After SCLK↑ C

L = 15pF l28ns

t14 SDOUT Delay After CS↓l8ns

t15 CS↓ to SCLK Setup Time l20 ns

t16 Data Valid to BUSY↓l1ns

t17 Data Access Time after RD↓ or BYTESWAP↑l10 ns

t18 Bus Relinquish Time l10 ns

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to ground.

Note 3: When these pin voltages are taken below ground or above

AVP, DVP or OVP, they will be clamped by internal diodes. This product can

handle input currents up to 100mA below ground or above AVP, DVP or

OVP without latchup.

Note 4: AVP = DVP = OVP = 5V, fSMPL = 250ksps, external reference equal

to 4.096V unless otherwise noted.

Note 5: Recommended operating conditions.

Note 6: Integral nonlinearity is deﬁ ned as the deviation of a code from a

straight line passing through the actual endpoints of the transfer curve.

The deviation is measured from the center of the quantization band.

Note 7: Bipolar zero error is the offset voltage measured from –0.5LSB

when the output code ﬂ ickers between 0000 0000 0000 0000 and 1111

1111 1111 1111. Bipolar full-scale error is the worst-case of –FS or +FS

untrimmed deviation from ideal ﬁ rst and last code transitions and includes

the effect of offset error.

Note 8: All speciﬁ cations in dB are referred to a full-scale ±4.096V input

with a 4.096V reference voltage.

Note 9: t13 of 8ns maximum allows a shift clock frequency up to

2 • (t13 + tSETUP) for falling edge capture with 50% duty cycle and up to

80MHz for rising capture. tSETUP is the set-up time of the receiving logic.

Note 10: Guaranteed by design.

Note 11: Temperature coefﬁ cient is calculated by dividing the maximum

change in output voltage by the speciﬁ ed temperature range.

0.5V

50% 50%

239116F01

0.5V

tDELAY

tWIDTH

tDELAY

Figure 1. Voltage Levels for Timing Speciﬁ cations

LTC2391-16

239116fa

TYPICAL PERFORMANCE CHARACTERISTICS

DC Histogram

(Internal Reference)

Internal Reference Output

vs Temperature Offset Error vs Temperature

Full-Scale Error vs Temperature

Integral Nonlinearity

vs Output Code

Differential Nonlinearity

vs Output Code

DC Histogram

(External Reference)

16k Point FFT fS = 250ksps,

fIN = 20kHz

OUTPUT CODE

INL ERROR (LSB)

0.5

1.0

65536

239116 G01

–0.5

–1.0

–2.0 16384 32768 49152

–1.5

2.0

1.5

OUTPUT CODE

–1.5

DNL ERROR (LSB)

–1.0

–0.5

0.5

1.0

1.5

16384 32768 49152 65536

239116 G02

TA = 25°C, fSMPL = 250ksps, unless otherwise noted.

CODE

32764

COUNTS

1200000

1600000

2000000

239116 G03

800000

400000

1000000

1400000

1800000

600000

200000

032766 32768 32770 32772

CODE

32764

COUNTS

1200000

1600000

2000000

239116 G04

800000

400000

1000000

1400000

1800000

600000

200000

032766 32768 32770 32772

TEMPERATURE (°C)

–55

REFERENCE OUTPUT (V)

4.0975

–15 25 45 125

239116 G05

4.0970

4.0965

4.0960

4.0955

4.0950

4.0945

4.0940

4.0935

4.0930

4.0925 –35 5 65 85 105

TC = 4ppm/°C

TEMPERATURE (°C)

–55

OFFSET ERROR (LSB)

0.2

0.6

0.8

1.0

–15 25 45 125

239116 G06

0.4

–35 5 65 85 105

TEMPERATURE (°C)

–55

–10

FULL-SCALE ERROR (LSB)

–8

–4

–2

–15 25 45 125

239116 G07

–6

–35 5 65 85 105

FREQUENCY (kHz)

–180

AMPLITUDE (dBFS)

–160

–120

–100

–80

50 100 125

239116 G08

–140

25 75

–60

–40

–20 SNR = 94dB

THD  –103dB

SINAD = 93.5dB

SFDR = 104dB

16k Point FFT fS = 250ksps,

fIN = 100kHz

FREQUENCY (kHz)

–180

AMPLITUDE (dBFS)

–160

–120

–100

–80

50 100 125

239116 G09

–140

25 75

–60

–40

–20 SNR = 93.4dB

THD  –98.7dB

SINAD = 92.3dB

SFDR = 106.6dB

LTC2391-16

239116fa

SNR, SINAD vs Input Level

THD, Harmonics

vs Input Frequency

THD, Harmonics at fIN = 20kHz

vs Temperature

Supply Current vs Sampling

Frequency

Supply Current vs Temperature

Power-Down Current

vs Temperature

SNR, SINAD vs Input Frequency

TYPICAL PERFORMANCE CHARACTERISTICS

TA = 25°C, fSMPL = 250ksps, unless otherwise noted.

SNR, SINAD at fIN = 20kHz

vs Temperature

INPUT FREQUENCY (kHz)

SNR, SINAD (dBFS)

100

239116 G10

80 50

25 75

96 SNR

SINAD

INPUT FREQUENCY (kHz)

THD, HARMONICS (dBFS)

–90

–85

–80

100

THD

3RD

2ND

239116 G11

–95

–100

–120

–115

25 50 75

–105

–110

–70

–75

TEMPERATURE (°C)

–55

SNR, SINAD (dBFS)

SNR

–15 25 45 125

239116 G12

–35 5 65 85 105

SINAD

INPUT LEVEL (dB)

–40

SNR, SINAD (dBFS)

94.0

94.5

239116 G14

93.5

93.0 –30 –20 –10

95.0

SNR

SINAD

SAMPLING FREQUENCY (kHz)

POWER SUPPLY CURRENT (mA)

0.1 10 100 1000

239116 G15

TEMPERATURE (°C)

–55

POWER SUPPLY CURRENT (mA)

–15 25 45 125

239116 G16

–35 5 65 85 105

AVP

DVP

0VP

TEMPERATURE (°C)

–55

POWER-DOWN CURRENT (μA)

–15 25 45 125

239116 G17

–35 5 65 85 105

AVP

DVP

0VP

TEMPERATURE (°C)

–55

–120

THD, HARMONICS (dBFS)

–115

–105

–100

3RD

–15 25 45 125

239116 G13

–110

–35 5 65 85 105

–95

THD

2ND

LTC2391-16

239116fa

PIN FUNCTIONS

GND (Pins 1, 5, 7, 20, 35, 41, 44, 48, Exposed Pad Pin

49): Ground. All GND pins must be connected to a solid

ground plane.

AVP (Pins 2, 40, 45, 46, 47): 5V Analog Power Supply.

The range of AVP is 4.75V to 5.25V. Bypass AVP to GND

with a good quality 0.1μF and a 10μF ceramic capacitor

in parallel.

DVP (Pins 3, 19): 5V Digital Power Supply. The range of

DVP is 4.75V to 5.25V. Bypass DVP to GND with a good

quality 0.1μF and a 10μF ceramic capacitor in parallel.

SER/PAR (Pin 4): Serial/Parallel Selection Input. This pin

controls the digital interface. A logic high on this pin se-

lects the serial interface and a logic low selects the parallel

interface. In the serial mode the non-active digital outputs

are high impedance.

OB/2C (Pin 6): Offset Binary/Two’s Complement Input.

When OB/2C is high, the digital output is offset binary.

When low, the MSB is inverted resulting in two’s comple-

ment output.

BYTESWAP (Pin 8): BYTESWAP Input. With BYTESWAP

low, data will be output with Pin 28 (D15) being the MSB

and Pin 9 (D0) being the LSB. With BYTESWAP high, the

upper eight bits and the lower eight bits will be switched.

The MSB is output on Pin 16 and Bit 8 is output on Pin 9.

Bit 7 is output on Pin 28 and the LSB is output on Pin 21.

D0 (Pin 9): Data Bit 0. When SER/PAR = 0 this pin is Bit 0

of the parallel port data output bus.

D1 (Pin 10): Data Bit 1. When SER/PAR = 0 this pin is

Bit 1 of the parallel port data output bus.

D2 (Pin 11): Data Bit 2. When SER/PAR = 0 this pin is

Bit 2 of the parallel port data output bus.

D3 (Pin 12): Data Bit 3. When SER/PAR = 0 this pin is

Bit 3 of the parallel port data output bus.

D4 (Pin 13): Data Bit 4. When SER/PAR = 0 this pin is

Bit 4 of the parallel port data output bus.

D5 (Pin 14): Data Bit 5. When SER/PAR = 0 this pin is

Bit 5 of the parallel port data output bus.

D6 (Pin 15): Data Bit 6. When SER/PAR = 0 this pin is

Bit 6 of the parallel port data output bus.

D7 (Pin 16): Data Bit 7. When SER/PAR = 0 this pin is

Bit 7 of the parallel port data output bus.

OGND (Pin 17): Digital Ground for the Input/Output

Interface.

OVP (Pin 18): Digital Power Supply for the Input/Output

Interface. The range for OVP is 1.8V to 5V. Bypass OVP

to OGND with a good quality 4.7μF ceramic capacitor

close to the pin.

D8 (Pin 21): Data Bit 8. When SER/PAR = 0 this pin is

Bit 8 of the parallel port data output bus.

D9/SDIN (Pin 22): Data Bit 9/Serial Data Input. When SER/

PAR = 0 this pin is Bit 9 of the parallel port data output bus.

When SER/PAR = 1, (serial mode) this is the serial data

input. SDIN can be used as a data input to daisy chain two

or more conversion results into a single SDOUT line. The

digital data level on SDIN is output on SDOUT with a delay

of 16 SCLK periods after the start of the read sequence.

D10/SDOUT (Pin 23): Data Bit 10/Serial Data Output. When

SER/PAR = 0 this pin is Bit 10 of the parallel port data

output bus. When SER/PAR = 1, (serial mode) this is the

serial data output. The conversion result can be clocked

out serially on this pin synchronized to SCLK. The data

is clocked out MSB ﬁ rst on the rising edge of SCLK and

is valid on the falling edge of SCLK. The data format is

determined by the logic level of OB/2C.

D11/SCLK (Pin 24): Data Bit 11/Serial Clock Input. When

SER/PAR = 0 this pin is Bit 11 of the parallel port data

output bus. When SER/PAR = 1, (serial mode) this is the

serial clock input.

D12 (Pin 25): Data Bit 12. When SER/PAR = 0 this pin is

Bit 12 of the parallel port data output bus.

D13 (Pin 26): Data Bit 13. When SER/PAR = 0 this pin is

Bit 13 of the parallel port data output bus.

D14 (Pin 27): Data Bit 14. When SER/PAR = 0 this pin is

Bit 14 of the parallel port data output bus.

D15 (Pin 28): Data Bit 15. When SER/PAR = 0 this pin is

Bit 15 of the parallel port data output bus. The data format

is determined by the logic level of OB/2C.

LTC2391-16

239116fa

BUSY (Pin 29): Busy Output. A low-to-high transition oc-

curs when a conversion is started. It stays high until the

conversion is complete. The falling edge of BUSY can be

used as the data-ready clock signal.

RD (Pin 30): Read Data Input. When CS and RD are both

low, the parallel and serial output bus is enabled.

CS (Pin 31): Chip Select. When CS and RD are both low,

the parallel and serial output bus is enabled. CS is also

used to gate the external shift clock.

RESET (Pin 32): Reset Input. When high the LTC2391-16

is reset, and if this occurs during a conversion, the con-

version is halted and the data bus is put into Hi-Z mode.

PD (Pin 33): Power-Down Input. When high, the

LTC2391-16 is powered down and subsequent conversion

requests are ignored. Before entering power shutdown,

the digital output data should be read.

CNVST (Pin 34): Conversion Start Input. A falling edge

on CNVST puts the internal sample-and-hold into the hold

mode and starts a conversion. CNVST is independent of CS.

VCM (Pin 36): Common Mode Analog Output. Typically

the output voltage is 2.048V. Bypass to GND with a 10μF

capacitor.

REFOUT (Pin 37): Internal Reference Output. Nominal

output voltage is 4.096V. Connect this pin to REFIN if us-

ing the internal reference. If an external reference is used

connect REFOUT to ground.

REFIN (Pin 38): Reference Input. An external reference

can be applied to REFIN if a more accurate reference is

required. If an external reference is used tie REFOUT to

ground.

REFSENSE (Pin 39): Reference Input Sense. Leave

REFSENSE open when using the internal reference. If

an external reference is used connect REFSENSE to the

ground pin of the external reference.

IN–, IN+ (Pin 42, Pin 43): Differential Analog Inputs.

IN+ – (IN–) can range up to ±VREF

PIN FUNCTIONS

LTC2391-16

239116fa

FUNCTIONAL BLOCK DIAGRAM

16-BIT SAMPLING ADC

PARALLEL/

SERIAL

INTERFACE

SDIN

SDOUT

SCLK

SER/PAR

BYTESWAP

OB/2C

BUSY

239116BD

16-BIT

1x BUFFER

REFOUT

REFIN

IN–

IN+

AVP

LTC2391-16 DVP OVP

VCM

REFSENSE

CONTROL LOGIC

4.096V

REFERENCE

CNVST PD RESET GND OGND

16-BIT OR

TWO BYTE

TIMING DIAGRAMS

Conversion Timing Using the Parallel Interface

CONVERT

PREVIOUS CONVERSION CURRENT CONVERSION

CNVST

CS, RD = 0

BUSY

D[15:0]

ACQUIRE

239116 TD01

Conversion Timing Using the Serial Interface

D14

D15 D13 D11 D9 D7 D5 D3

CONVERT

CNVST

CS, RD = 0

BUSY

SCLK

SDOUT

ACQUIRE

239116 TD02

D12 D10 D8 D6 D4 D2 D0

LTC2391-16

239116fa

APPLICATIONS INFORMATION

OVERVIEW

The LTC2391-16 is a low noise, high speed 16-bit suc-

cessive approximation register (SAR) ADC. Operating

from a single 5V supply, the LTC2391-16 supports a large

±4.096V fully differential input range, making it ideal

for high performance applications which require a wide

dynamic range. The LTC2391-16 achieves ±2LSB INL max,

no missing codes at 16 bits and 94dB SNR (typ).

The LTC2391-16 includes a precision internal reference with

a guaranteed 0.5% initial accuracy and a ±20ppm/°C (max)

temperature coefﬁ cient. Fast 250ksps throughput with no

cycle latency in both parallel and serial interface modes

makes the LTC2391-16 ideally suited for a wide variety

of high speed applications. An internal oscillator sets the

conversion time, easing external timing considerations.

The LTC2391-16 dissipates only 95mW at 250ksps, while

both nap and sleep power-down modes are provided to

further reduce power during inactive periods.

CONVERTER OPERATION

The LTC2391-16 operates in two phases. During the ac-

quisition phase, the charge redistribution capacitor D/A

converter (CDAC) is connected to the IN+ and IN– pins

to sample the differential analog input voltage. A falling

edge on the CNVST pin initiates a conversion. During the

conversion phase, the 16-bit CDAC is sequenced through

a successive approximation algorithm, effectively compar-

ing the sampled input with binary-weighted fractions of

the reference voltage (e.g., VREF/2, VREF/4 … VREF/65536)

using the differential comparator. At the end of conversion,

the CDAC output approximates the sampled analog input.

The ADC control logic then prepares the 16-bit digital

output code for parallel or serial transfer.

TRANSFER FUNCTION

The LTC2391-16 digitizes the full-scale voltage of 2 • VREF

into 216 levels, resulting in an LSB size of 125μV when VREF

= 4.096V. The ideal transfer function for two’s complement

is shown in Figure 2. The OB/2C pin selects either offset

binary or two’s complement format.

ANALOG INPUT

The analog inputs of the LTC2391-16 are fully differential

in order to maximize the signal swing that can be digitized.

The analog inputs can be modeled by the equivalent circuit

shown in Figure 3. The diodes at the input provide ESD pro-

tection. The analog inputs should not exceed the supply or

go below ground. In the acquisition phase, each input sees

approximately 40pF (CIN) from the sampling CDAC in series

with 50Ω (RIN) from the on-resistance of the sampling

switch. Any unwanted signal that is common to both

inputs will be reduced by the common mode rejection of

the ADC. The inputs draw only one small current spike

while charging the CIN capacitors during acquisition.

During conversion, the analog inputs draw only a small

leakage current.

Figure 2. LTC2391-16 Two’s Complement Transfer Function

Figure 3. The Equivalent Circuit for the

Differential Analog Input of the LTC2391-16

INPUT VOLTAGE (V)

OUTPUT CODE (TWO’S COMPLEMENT)

–1

LSB

239116 F02

011...111

011...110

000...001

000...000

100...000

100...001

111...110

LSB

BIPOLAR

ZERO

111...111

FSR/2 – 1LSB–FSR/2

FSR = +FS – –FS

1LSB = FSR/65536

IN+RIN

CIN

AVP

AVP BIAS

VOLTAGE

IN–RIN

239116 F03

CIN

LTC2391-16

239116fa

APPLICATIONS INFORMATION

INPUT DRIVE CIRCUITS

A low impedance source can directly drive the high imped-

ance inputs of the LTC2391-16 without gain error. A high

impedance source should be buffered to minimize settling

time during acquisition and to optimize the distortion

performance of the ADC.

For best performance, a buffer ampliﬁ er should be used to

drive the analog inputs of the LTC2391-16. The ampliﬁ er

provides low output impedance to allow for fast settling

of the analog signal during the acquisition phase. It also

provides isolation between the signal source and the ADC

inputs which draw a small current spike during acquisition.

Input Filtering

The noise and distortion of the buffer ampliﬁ er and other

circuitry must be considered since they add to the ADC

noise and distortion. Noisy input circuitry should be ﬁ ltered

prior to the analog inputs to minimize noise. A simple

1-pole RC ﬁ lter is sufﬁ cient for many applications.

Large ﬁ lter RC time constants slow down the settling at

the analog inputs. It is important that the overall RC time

constants be short enough to allow the analog inputs to

completely settle to 16-bit resolution within the acquisi-

tion time (tACQ).

High quality capacitors and resistors should be used in the

RC ﬁ lter since these components can add distortion. NPO

and silver mica type dielectric capacitors have excellent

linearity. Carbon surface mount resistors can generate

distortion from self heating and from damage that may

occur during soldering. Metal ﬁ lm surface mount resistors

are much less susceptible to both problems.

Single-to-Differential Conversion

For single-ended input signals, a single-ended-to-differ-

ential conversion circuit must be used to produce a dif-

ferential signal at the ADC inputs. The LT6350 ADC driver is

recommended for performing a single-ended-to-differential

conversion, as shown in Figure 4a. Its low noise and good

DC linearity allows the LTC2391-16 to meet full data sheet

speciﬁ cations. An alternative solution using two op amps

is shown in Figure 4b. Using two LT

1806 op amps, the

circuit achieves 94dB signal-to-noise ratio (SNR). For a

20kHz input signal, the input of the LTC2391-16 has been

bandwidth limited to about 25kHz.

ADC REFERENCE

A low noise, low temperature drift reference is critical to

achieving the full data sheet performance of the ADC. The

LTC2391-16 provides an excellent internal reference with

a ±20ppm/°C (max) temperature coefﬁ cient. For better

accuracy, an external reference can be used.

The high speed, low noise internal reference buffer is used

for both internal and external reference applications. It

cannot be bypassed.

Figure 4a. Recommended Single-Ended-to-Differential

Conversion Circuit Using the LT6350 ADC Driver

Figure 4b. Alternative Single-Ended-to-Differential

Conversion Circuit Using Two LT1806 Op Amps

249Ω

ANALOG INPUT

0V TO 4.096V

SINGLE-ENDED-

TO-DIFFERENTIAL

DRIVER

249Ω

2200pF LTC2391-16

239116 F04a

IN+

IN–

LT6350

249Ω

301Ω

ANALOG

INPUT

0V TO 4.096V

COMMON

MODE

VOLTAGE

301Ω 0.013μF LTC2391-16

239116 F04b

IN+

IN–

–

LT1806

–

LT1806

LTC2391-16

239116fa

APPLICATIONS INFORMATION

Internal Reference

To use the internal reference, simply tie the REFOUT and

REFIN pins together. This connects the 4.096V output of

the internal reference to the input of the internal reference

buffer. The output impedance of the internal reference is

approximately 2.6kΩ and the input impedance of the in-

ternal reference buffer is about 85kΩ. It is recommended

that this node be bypassed to ground with a 1μF or larger

capacitor to ﬁ lter the output noise of the internal reference.

The REFSENSE pin should be left ﬂ oating when using the

internal reference.

External Reference

An external reference can be used with the LTC2391-16

when even higher performance is required. The

LT1790-4.096 offers 0.05% (max) initial accuracy and

10ppm/°C (max) temperature coefﬁ cient. When using an

external reference, connect the reference output to the

REFIN pin and connect the REFOUT pin to ground. The

REFSENSE pin should be connected to the ground of the

external reference.

DYNAMIC PERFORMANCE

Fast fourier transform (FFT) techniques are used to test

the ADC’s frequency response, distortion and noise at the

rated throughput. By applying a low distortion sine wave

and analyzing the digital output using an FFT algorithm,

the ADC’s spectral content can be examined for frequen-

cies outside the fundamental. The LTC2391-16 provides

guaranteed tested limits for both AC distortion and noise

measurements.

Signal-to-Noise and Distortion Ratio (SINAD)

The signal-to-noise and distortion ratio (SINAD) is the

ratio between the RMS amplitude of the fundamental input

frequency and the RMS amplitude of all other frequency

components at the A/D output. The output is band-limited

to frequencies from above DC and below half the sampling

frequency. Figure 5 shows that the LTC2391-16 achieves

a typical SINAD of 93.5dB at a 250ksps sampling rate

with a 20kHz input.

Figure 5. 16k Point FFT of the LTC2391-16, fS = 250ksps, fIN = 20kHz

FREQUENCY (kHz)

–180

AMPLITUDE (dBFS)

–160

–120

–100

–80

50 100 125

239116 G08

–140

25 75

–60

–40

–20 SNR = 94dB

THD  –103dB

SINAD = 93.5dB

SFDR = 104dB

LTC2391-16

239116fa

APPLICATIONS INFORMATION

Signal-to-Noise Ratio (SNR)

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency and

the RMS amplitude of all other frequency components

except the ﬁ rst ﬁ ve harmonics and DC. Figure 5 shows

that the LTC2391-16 achieves a typical SNR of 94dB at a

250kHz sampling rate with a 20kHz input.

Total Harmonic Distortion (THD)

Total harmonic distortion (THD) is the ratio of the RMS sum

of all harmonics of the input signal to the fundamental itself.

The out-of-band harmonics alias into the frequency band

between DC and half the sampling frequency (fSMPL/2).

THD is expressed as:

THD =20log V22+V32+V42...V

where V1 is the RMS amplitude of the fundamental fre-

quency and V2 through VN are the amplitudes of the second

through Nth harmonics.

POWER CONSIDERATIONS

The LTC2391-16 provides three sets of power supply

pins: the analog 5V power supply (AVP), the digital 5V

power supply (DVP) and the digital input/output interface

power supply (OVP). The ﬂ exible OVP supply allows the

LTC2391-16 to communicate with any digital logic operating

between 1.8V and 5V, including 2.5V and 3.3V systems.

Power Supply Sequencing

The LTC2391-16 does not have any speciﬁ c power supply

sequencing requirements. Care should be taken to observe

the maximum voltage relationships described in the Ab-

solute Maximum Ratings section. The LTC2391-16 has a

power-on reset (POR) circuit. With the POR, the result of

the ﬁ rst conversion is valid after power has been applied

to the ADC. The LTC2391-16 will reset itself if the power

supply voltage drops below 2.5V. Once the supply voltage

is brought back to its nominal value, the POR will reinitial-

ize the ADC and it will be ready to start a new conversion.

Nap Mode

The LTC2391-16 can be put into the nap mode after a

conversion has been completed to reduce the power

consumption between conversions. In this mode some

of the circuitry on the device is turned off. Nap mode is

enabled by keeping CNVST low between conversions. When

the next conversion is requested, bring CNVST high and

hold for at least 250ns, then start the next conversion by

bringing CNVST low. See Figure 6.

Power Shutdown Mode

When PD is tied high, the LTC2391-16 enters power

shutdown and subsequent requests for conversion are

ignored. Before entering power shutdown, the digital

output data needs to be read. However, if a request for

power shutdown (PD = high) occurs during a conversion,

the conversion will ﬁ nish and then the device will power

down. The data from that conversion can be read after PD

Figure 6. Nap Mode Timing for the LTC2391-16

CNVST

BUSY

NAP

tCONV tACQ

NAP MODE

239116 F06

LTC2391-16

239116fa

APPLICATIONS INFORMATION

= low is applied. In this mode, power consumption drops

to a typical value of 175μW from 95mW. This mode can

be used if the LTC2391-16 is inactive for a long period of

time and the user wants to minimize the power dissipation.

Recovery from Power Shutdown Mode

Once the PD pin is returned to a low level, ending the

power shutdown request, the internal circuitry will begin

to power up. If the internal reference is used, the 2.6kΩ

output impedance with the 1μF bypass capacitor on the

REFIN/REFOUT pins will be the main time constant for

the power-on recovery time. If an external reference is

used, typically allow 5ms for recovery before initiating a

new conversion.

Power Dissipation vs Sampling Frequency

The power dissipation of the LTC2391-16 will decrease

as the sampling frequency is reduced when nap mode

is activated. See Figure 7. In nap mode, a portion of the

circuitry on the LTC2391-16 is turned off after a conversion

has been completed. Increasing the time allowed between

conversions lowers the average power.

TIMING AND CONTROL

The LTC2391-16 conversion is controlled by CNVST. A

falling edge on CNVST will start a conversion. CS and RD

control the digital interface on the LTC2391-16. When

either CS or RD is high, the digital outputs are high

impedance.

CNVST Timing

The LTC2391-16 conversion is controlled by CNVST. A

falling edge on CNVST will start a conversion. Once a

conversion has been initiated, it cannot be restarted until

the conversion is complete. For optimum performance

CNVST should be a clean low jitter signal. Converter status

is indicated by the BUSY output which remains high while

the conversion is in progress. To ensure no errors occur

in the digitized results return the rising edge either within

40ns from the start of the conversion or wait until after

the conversion has been completed. The CNVST timing

needed to take advantage of the reduced power mode of

operation is described in the Nap Mode section.

Internal Conversion Clock

The LTC2391-16 has an internal clock that is trimmed

to achieve a maximum conversion time of 2500ns. No

external adjustments are required and with a maximum

acquisition time of 1485ns, a throughput performance of

250ksps is guaranteed.

DIGITAL INTERFACE

The LTC2391-16 allows both parallel and serial digital

interfaces. The ﬂ exible OVP supply allows the LTC2391-16

to communicate with any digital logic operating between

1.8V and 5V, including 2.5V and 3.3V systems.

Figure 7. Power Dissipation of the LTC2391-16

Decreases with Decreasing Sampling Frequency

SAMPLING FREQUENCY (kHz)

POWER SUPPLY CURRENT (mA)

0.1 10 100 1000

239116 G15

LTC2391-16

239116fa

APPLICATIONS INFORMATION

Parallel Modes

The parallel output data interface is active when the

SER/PAR pin is tied low and when both CS and RD are low.

The output data can be read as a 16-bit word as shown

in Figures 8, 9 and 10 or it can be read as two 8-bit bytes

by using the BYTESWAP pin. As shown in Figure 11, with

the BYTESWAP pin low, the ﬁ rst eight MSBs are output on

the D15 to D8 pins and the eight LSBs are output on the

D7 to DO pins. When BYTESWAP is taken high, the eight

LSBs now are output on the D15 to D8 pins and the eight

MSBs are output on the D7 to D0 pins.

Serial Modes

The serial output data interface is active when the

SER/PAR pin is tied high and when both CS and RD are

low. The serial output data will be clocked out on the

SDOUT pin when an external clock is applied to the SCLK

pin. Clocking out the data after the conversion will yield

the best performance. With a shift clock frequency of at

least 15MHz, a 250ksps throughput is achieved. The serial

output data changes state on the rising edge of SCLK and

can be captured on the falling edge of SCLK. D15 remains

valid till the ﬁ rst rising edge of shift clock after the ﬁ rst

falling edge of shift clock. The non-active digital outputs

are high impedance when operating in the serial mode.

If CS and RD are used to gate the serial output data, the

full conversion result should be read before CS and RD

are returned to a high level.

The SDIN input pin is used to daisy chain multiple con-

verters. This is useful for applications where hardware

constraints may limit the number of lines needed to

interface to a large number of converters. For example,

if two devices are cascaded, the MSB of the ﬁ rst device

will appear at the output after 17 SCLK cycles. The ﬁ rst

MSB is clocked in on the falling edge of the ﬁ rst SCLK.

See Figure 12.

Data Format

When OB/2C is high, the digital output is offset binary.

When low, the MSB is inverted resulting in two’s comple-

ment output. This pin is active in both the parallel and

serial modes of operation.

Reset

When the RESET pin is high, the LTC2391-16 is reset, and

if this occurs during a conversion, the conversion is halted

and the data bus is put into Hi-Z mode. In reset, requests

for new conversions are ignored. Once RESET returns low,

the LTC2391-16 is ready to start a new conversion after

the acquisition time plus 2μs has been met. See Figure 13.

Figure 8. Read the Parallel Data Continuously.

The Data Bus is Always Driven and Can’t Be Shared

CS = RD = 0

t6t16

tCONV

CNVST

BUSY

DATA BUS D[15:0] PREVIOUS CONVERSION NEW

239116 F08

LTC2391-16

239116fa

APPLICATIONS INFORMATION

Figure 9. Read the Parallel Data After the Conversion

Figure 10. Read the Parallel Data During the Conversion

Figure 11. 8-Bit Parallel Interface Using the BYTESWAP Pin

BUSY

DATA BUS D[15:0] Hi-Z CURRENT

CONVERSION

t17 t18

239116 F09

Hi-Z

CS = 0

CNVST, RD

BUSY

DATA BUS D[15:0] Hi-Z

t17 t18

tCONV

CONVERSION

Hi-Z

239116 F09

CS, RD

BYTESWAP

D[15:8] HIGH BYTE LOW BYTE

8-BIT INTERFACE

Hi-Z Hi-Z

239116 F11

t17 t17 t18

LTC2391-16

239116fa

APPLICATIONS INFORMATION

Figure 12. Serial Interface with External Clock. Read After the Conversion. Daisy Chain Multiple Converters

Figure 13. RESET Pin Timing

RD = 0

BUSY

t15

t10

t13

123

D152

D151

SCLK STARTS HIGH

SCLK STARTS LOW

D141D131D11D01

239116 F12

D142D132D12D02D151D141

415161718

SCLK

SDOUT

(ADC 2)

Hi-Z

SDIN

(ADC 2)

t12

t14

t11

RD = 0

BUSY

t10

t13

123

D152

D151D141D131D11D01

D142D132D12D02D151D141

415161718

SCLK

SDOUT

(ADC 2)

Hi-Z

SDIN

(ADC 2)

t12

t14

t11

LTC2391-16

ADC 1 ADC 2

SDOUT

CNVST IN

CS IN

RD IN

SCLK IN

CNVST

SCLK

SDIN

LTC2391-16

SDOUT DATA OUT

CNVST

SCLK

SDIN

RESET

DATA BUS D[15:0] Hi-Z

CVNST

tACQ + 2μs

239116 F13

LTC2391-16

239116fa

APPLICATIONS INFORMATION

BOARD LAYOUT

To obtain the best performance from the LTC2391-16, a

printed circuit board (PCB) is recommended. Layout for

the printed circuit board should ensure the digital and

analog signal lines are separated as much as possible.

In particular, care should be taken not to run any digital

clocks or signals alongside analog signals or underneath

the ADC.

Recommended Layout

The following is an example of a recommended PCB layout.

A single solid ground plane is used. Bypass capacitors to

the supplies are placed as close as possible to the supply

pins. Low impedance common returns for these bypass

capacitors are essential to the low noise operation of the

ADC. The analog input traces are screened by ground.

For more details and information refer to DC1500A, the

evaluation kit for the LTC2391-16

Partial Schematic of Demoboard

BUSY

D15

D14

D13

D12

D11/SCLK

D10/SDOUT

D9/SDIN

BYTESWAP

GND

BUSY

D15

D14

D13

D12

D11/SCLK

D10/SDOUT

D9/SDIN

RESET

REFOUT

3738

C36

1μF

3934

REFINREFSENSE

LTC2391-16

IN+

IN–

CNVST

SER/PAR

GND

VCM

AVP/AVL AVP AVP AVP AVP

GND GND GND GND GND GND OGND

LTC2391-16

DVP OVP

3.3V

319

R24

1.0Ω

48 44 41 35 20 1 17

239116 TA02

40454647

DVP/DVL

249Ω

1% 44

C53

10μF

C55

OPT

OB/2C

C40

4.7μF

C29

0.1μF C28

10μF

C30

10μF

C31

0.1μF

C54

OPT

2200pF

1206 NPO

LTC2391-16

239116fa

APPLICATIONS INFORMATION

Partial Top Silkscreen

Partial Layer 1 Component Side Partial Layer 2 Ground Plane

LTC2391-16

239116fa

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

7.00 ±0.10

(4 SIDES)

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 TOP MARK

(SEE NOTE 6)

PIN 1

CHAMFER

C = 0.35

0.40 ±0.10

4847

BOTTOM VIEW—EXPOSED PAD

5.50 REF

(4-SIDES)

0.75 ±0.05 R = 0.115

TYP

0.25 ±0.05

0.50 BSC

0.200 REF

0.00 – 0.05

(UK48) QFN 0406 REV C

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.70 ±0.05

5.50 REF

(4 SIDES) 6.10 ±0.05 7.50 ±0.05

0.25 ±0.05

0.50 BSC

PACKAGE OUTLINE

5.15 ±0.10

5.15 ±0.05

R = 0.10

TYP

UK Package

48-Lead Plastic QFN (7mm w 7mm)

(Reference LTC DWG # 05-08-1704 Rev C)

LTC2391-16

239116fa

LX Package

48-Lead Plastic LQFP (7mm × 7mm)

(Reference LTC DWG # 05-08-1760 Rev Ø)

LX48 LQFP 0907 REVØ

0° – 7°

11° – 13°

0.45 – 0.75

1.00 REF

11° – 13°

9.00 BSC

7.00 BSC

9.00 BSC

1.60

MAX

1.35 – 1.45

0.05 – 0.150.09 – 0.20 0.50

BSC 0.17 – 0.27

GAUGE PLANE

0.25

NOTE:

1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE

2. DIMENSIONS ARE IN MILLIMETERS

3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT

4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER

5. DRAWING IS NOT TO SCALE

SEE NOTE: 4

C0.30 – 0.50

R0.08 – 0.20

7.15 – 7.25

5.50 REF

7.15 – 7.25

PACKAGE OUTLINE

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

SECTION A – A

0.50 BSC

0.20 – 0.30

1.30 MIN

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC2391-16

239116fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

REVISION HISTORY

REV DATE DESCRIPTION PAGE NUMBER

A 7/12 Increased TJMAX to 150°C on LQFP package

Added condition for reading conversion result under Serial Modes

Added plus 2μs to acquisition time in Reset section and Fig 13

Updated data bit numbering on Figure 12

16, 18

LTC2391-16

239116fa

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0712 REV A • PRINTED IN USA

TYPICAL APPLICATION

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, Settling Time: 900ns

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LT6350 Low Noise Single-Ended-to-Differential ADC Driver Rail-to-Rail Input and Outputs, 240ns 0.01% Settling Time

ADC Driver: Single-Ended Input to Differential Output

–+IN1

–IN1

V+

V–

OUT2

OUT1

SHDN

+IN2

VIN

0V to 4V

0.1μF

0.1μF 0.1μF

499Ω

2V –5V

LT6350

239116 TA03

–

249Ω

2200pF

–AIN–

AIN+

LTC2391-16