ICS1893BF, Rev. F, 5/13/10 May, 2010

IDT reserves the right to make changes in the device data identified in

this publication without further notice. IDT advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

– Auto-Negotiation with Parallel detection

– Node applications, managed or unmanaged

– 10M or 100M full and half-duplex modes

– Loopback mode for Diagnostic Functions

– Auto-MDI/MDIX crossover correction

that supports the ISO/IEC 10Base-T and 100Base-TX

Carrier-Sense Multiple Access/Collision Detection

(CSMA/CD) Ethernet standards, ISO/IEC 8802-3.

The ICS1893BF is intended for MII, Node applications that

require the Auto-MDIX feature that automatically corrects

Station-Management (STA) entity. The ICS1893BF

Media-Dependent Interface (MDI) can be configured to

provide either half- or full-duplex operation at data rates of 10

Mb/s or 100Mb/s.

The ICS1893BF is available in a 300-mil 48-lead SSOP

package. The ICS1893BF shares the same proven

MII

MII

Interface

Chapter 4 Operating Modes Overview.............................................................................................16

4.1.2 Specific Reset Operations ..................................................................................... 18

4.2 Power-Down Operations ........................................................................................ 19

4.3 Automatic Power-Saving Operations .....................................................................20

4.6 10Base-T Operations .............................................................................................21

4.7 Half-Duplex and Full-Duplex Operations ...............................................................21

6.1 Functional Block: Media Independent Interface ..................................................... 32

6.2.1 Auto-Negotiation General Process ........................................................................33

6.2.2 Auto-Negotiation: Parallel Detection ...................................................................... 34

6.2.3 Auto-Negotiation: Remote Fault Signaling ............................................................. 35

6.2.4 Auto-Negotiation: Reset and Restart ..................................................................... 35

6.3.6 4B/5B Encoding/Decoding .....................................................................................39

6.4 Functional Block: 100Base-TX TP-PMD Operations ............................................. 39

6.4.1 100Base-TX Operation: Stream Cipher Scrambler/Descrambler .......................... 39

6.4.2 100Base-TX Operation: MLT-3 Encoder/Decoder .................................................40

6.4.5 100Base-TX Operation: Twisted-Pair Transmitter .................................................40

7.11.6 NRZ/NRZI Encoding (bit 16.3) ............................................................................... 77

7.14.4 ICS Reserved (bits 19.12:10) .................................................................................88

9.1 Absolute Maximum Ratings .................................................................................106

9.5.4 100M MII: Synchronous Transmit Timing ............................................................. 113

9.5.6 100M/MII Media Independent Interface: Synchronous Receive Timing ...............115

9.5.7 MII Management Interface Timing .......................................................................116

9.5.12 10M MII: Carrier Assertion/De-Assertion (Half-Duplex Transmission)..................121

either half-duplex or full-duplex modes.

3. Tri-states the signals on its Twisted-Pair Transmit pins (TP_TXP and TP_TXN)

5. Enters the power-down state

4. Sets all Management Register bits to their default values

listed in Section 4.1.1.1, “Entering Reset”.

receive clock (RXCLK) are available, which is typically 53 ms after the RESETn pin goes high. [For details

After entering reset from a power-on condition, the ICS1893BF remains in reset for approximately 20 µs.

their default values. This action automatically clears (that is, sets equal to logic zero) Control Register bit

see Section 7.11.3, “PHY Address (bits 16.10:6)”.]

3. The Control Register bit 0.15 does not represent the status of a hardware reset. It is a self-clearing bit

internal functions and drives all MAC Interface output pins to logic zero except for those that support the MII

Serial Management Port. In addition, the ICS1893BF tri-states its Twisted-Pair Transmit pins (TP_TXP and

but its link partner supports 100Base-TX and 100Base-T4 modes – the two devices automatically select

bit 19.0 to logic:

equalization, and baseline wander correction. In addition, in 100Base-TX mode, the ICS1893BF provides a

c. A Media Status or Control interface that consists of a Carrier Sense signal (CRS) and a Collision

of the following:

– Status Register (register 1), which reports basic device capabilities and status

well as new connections that have multiple technology options for the link. For example, when the

Auto-Negotiation sublayer performs the following steps:

During a reset, the ICS1893BF initializes its Auto-Negotiation sublayer modules to their default states.

the link partner's ability to perform the auto-negotiation process. Typically, an STA polls both the

Auto-Negotiation Complete bit (bit 1.5) and the Link Status bit (bit 1.2) to determine when a link is

– Serial-to-parallel conversion

then processes the data to detect the presence of a carrier.

it forces the assertion of the RX_ER signal, sets the Premature End bit (bit 17.5) to logic one, and

transitions to the IDLE State.

Clock PLL cannot acquire ‘lock’ on the serial data stream, it asserts an error signal. The status of this

error signal can be read in the QuickPoll Detailed Status Register’s PLL Lock Error bit (bit 17.9). This

a PLL Lock Error occurs. These errors, in turn, generate a link fault and force the link monitor

the CRS signal.

a. Cannot confirm either the /I/J/ (IDLE, J) symbols or the /J/K/ symbols, the receive error signal

The COL control signal is generated by the transmit modules. For details, see Section 6.3.3.1, “PCS

– One of the 10 undefined symbols, it sets its QuickPoll Detailed Status Register’s Invalid Symbol bit

– A Halt symbol, it sets the Halt Symbol Detected bit in its QuickPoll Detailed Status Register (bit 17.6)

scrambler/descrambler that complies with the ANSI Standard X3.263: 199X FDDI TP-PMD. The purpose of

the stream cipher scrambler is to spread the transmission spectrum to minimize electromagnetic

MHz to 100 MHz. The TP-PMD MLT-3 decoder converts the received three-level signal back to an NRZI bit

of the data stream.

attenuation and phase shift. The high-frequency loss occurs primarily because of the cable skin effect that

The ICS1893BF uses the same Twisted-Pair Receive pins (TP_RXP and TP_RXN) for both 10Base-T and