CY23S09, CY23S05
Low Cost 3.3 V Spread Aware
Zero Delay Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 38-07296 Rev. *G Revised October 04, 2011
Features
■10 MHz to 100 MHz and 133 MHz operating range, compatible
with CPU and PCI bus frequencies
■Zero input-output propagation delay
■Multiple low skew outputs
❐Output-output skew less than 250 ps
❐Device-device skew less than 700 ps
❐One input drives five outputs (CY23S05)
❐One input drives nine outputs, grouped as 4 + 4 + 1
(CY23S09)
■Less than 200 ps Cycle-to-cycle jitter is compatible with
Pentium based systems
■Test mode to bypass PLL (CY23S09 only, see Select Input
Decoding for CY23S09 on page 2)
■Available in space saving 16-pin, 150-mil SOIC, 4.4 mm
TSSOP, and 150-mil SSOP (CY23S09) or 8-pin, 150-mil
SOIC package (CY23S05)
■3.3 V operation, advanced 0.65 CMOS technology
■Spread Aware
Functional Description
The CY23S09 is a low cost 3.3 V zero delay buffer designed to
distribute high speed clocks and is available in a 16-pin SOIC
package. The CY23S05 is an 8-pin version of the CY23S09. It
accepts one reference input, and drives out five low skew clocks.
The -1H versions of each device operate at up to 100 and
133 MHz frequencies and have higher drive than the -1 devices.
All parts have on-chip PLLs that lock to an input clock on the REF
pin. The PLL feedback is on-chip and is obtained from the
CLKOUT pad.
The CY23S09 has two banks of four outputs each, which can be
controlled by the select inputs as shown in the Select Input
Decoding table on Select Input Decoding for CY23S09 on page
2. If all output clocks are not required, Bank B can be
three-stated. The select inputs also allow the input clock to be
directly applied to the outputs for chip and system testing
purposes.
The CY23S09 and CY23S05 PLLs enter a power down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0 A of current draw (for commercial temperature
devices) and 25.0 A (for industrial temperature devices). The
CY23S09 PLL shuts down in one additional case, as shown in
the Select Input Decoding for CY23S09 on page 2.
Multiple CY23S09 an d CY23S05 devices can accept the same
input clock and distrib ute it. In this case, th e skew between the
outputs of two devices is guaranteed to be less than 700 ps.
All outputs have less than 200 ps of cycle-to-cycle jitter . The input
to output propagation delay on both devices is guaranteed to be
less than 350 ps; the output to o utput skew is gua ranteed to be
less than 250 ps.
The CY23S05 and CY23S09 is available in two different config-
urations, as shown in the Ordering Information on page 7. The
CY23S05-1 and CY23S09-1 is the base part. The CY23S05-1H
and CY23S09-1H is the high drive version of the -1, and its rise
and fall times are much faster than -1.
Logic Block Diagram
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 2 of 12
Figure 1. REF. Input to CLKA/CLKB Delay vs. Loading Differen ce between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs must be uniformly loaded to achieve Zero Delay
between the input and output. Be cause the CLKOUT pin is the
internal feedback to the PLL, its relative loadin g can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT is
not used, it must have a capacitive load equal to that on other
outputs, to obtain zero input-output delay. If input to output delay
adjustments are required, use the above graph to calculate
loading differences between the CLKOUT pin and other outputs.
For zero output-output skew, be sure to load all outputs equally.
For further information, see applicat ion note “AN1234 - CY2308:
Zero Delay Buffer.”
Spread Aware
Many systems being designed now use a technology called
S pread S pectrum Frequency Timing Generation. Cypress is one
of the pioneers of SSFTG development and designed this
product so as not to filter off the Spread Spectrum feature of the
Reference input, assuming it exists. When a zero delay buffer is
not designed to pass the SS feature through, the result is a signif-
icant amount of tracking skew, which may cause problems in
systems requiring synchronization.
For more details on Spread Spectrum timing technology, please
see the Cypress Whitepaper EMI and Spread Spectrum
Technology.
Select Input Decoding for CY23S09
S2 S1 CLOCK A1–A4 CLOCK B1–B4 CLKOUT[1] Output Source PLL Shutdown
0 0 Three-state Three-state Driven PLL N
0 1 Driven Three-state Driven PLL N
1 0 Driven Driven Driven Reference Y
1 1 Driven Driven Driven PLL N
Note
1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 3 of 12
Pinouts
Figure 2. Pin Configuration – CY23S09 Figure 3. Pin Configuration – CY23S05
Table 1. Pin Description for CY23S09
Pin Signal Description
1REF
[2] Input reference frequency, 5 V tol erant inp ut
2 CLKA1[3] Buffered clock output, bank A
3 CLKA2[3] Buffered clock output, bank A
4V
DD 3.3 V supply
5 GND Ground
6 CLKB1[3] Buffered clock output, bank B
7 CLKB2[3] Buffered clock output, bank B
8S2
[4] Select input, bit 2
9S1
[4] Select input, bit 1
10 CLKB3[3] Buffered clock output, bank B
11 CLKB4[3] Buffered clock output, bank B
12 GND Ground
13 VDD 3.3 V supply
14 CLKA3[3] Buffered clock output, bank A
15 CLKA4[3] Buffered clock output, bank A
16 CLKOUT[3] Buffered output, internal feedba ck on this pin
Table 2. Pin Description for CY23S05
Pin Signal Description
1REF
[2] Input reference frequency, 5 V tolerant input
2CLK2
[3] Buffered clock output
3CLK1
[3] Buffered clock output
4 GND Ground
5CLK3
[3] Buffered clock output
6V
DD 3.3 V supply
7CLK4
[3] Buffered clock output
8 CLKOUT[3] Buffered clock output, internal feedback on this pin
Notes
2. Weak pull down.
3. Weak pull down on all outputs.
4. Weak pull up on these inputs.
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 4 of 12
Maximum Ratings
Supply voltage to ground potential ...............–0.5 V to +7.0 V
DC input voltage (Except REF) ..........–0.5 V to VDD + 0.5 V
DC input voltage REF 0.5 V to 7 V
Storage temperature .............. ... ...............–65 C to +150 C
Maximum soldering temperature (10 seconds)......... 260 C
Junction temperature................................................. 150 C
Static discharge voltage
(per MIL-STD-883, Method 3015) ..........................> 2,000 V
Operating Conditions for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices[5]
Parameter Description Min Max Unit
VDD Supply voltage 3.0 3.6 V
TAOperating temperature (Ambient temperature) 0 70 C
CLLoad capacitance, below 100 MHz 30 pF
CLLoad capacitance, from 100 MHz to 133 MHz 10 pF
CIN Input capacitance 7 pF
Electrical Characteristics for CY23S05SC-XX and CY23S09SC-XX Commercial Temperature Devices
Parameter Description Test Conditions Min Max Unit
VIL Input LOW voltage[6] 0.8 V
VIH Input HIGH voltage[6] 2.0 V
IIL Input LOW current VIN = 0 V 50.0 A
IIH Input HIGH current VIN = VDD 100.0 A
VOL Output LOW voltage[7] IOL = 8 mA (–1)
IOH = 12 mA (–1H) 0.4 V
VOH Output HIGH voltage[7] IOH = –8 mA (–1)
IOL = –12 mA (–1H) 2.4 V
IDD (PD mode) Power-down supply current REF = 0 MHz 12.0 A
IDD Supply current Unloaded outputs at 66.67 MHz,
SEL inputs at VDD 32.0 mA
Switching Characteristics for CY23S05SC-1 and CY23S09SC-1 Commercial Temperature Devices [8]
Parameter Description Test Cond itions Min Typ Max Unit
t1 Output frequency 30 pF loa d
10 pF load 10
10 100
133.33 MHz
MHz
Duty cycle[7] = t2 t1Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 %
t3 Rise time[7] Measured between 0.8 V and 2.0 V 2.50 ns
t4Fall time[7] Measured between 0.8 V and 2.0 V 2.50 ns
t5Output-to-output skew[7] All outputs equally loaded 250 ps
t6Delay, REF Rising Edge to
CLKOUT Rising Edge[7] Measured at VDD/2 0 ±350 ps
t7Device-to-device skew[7] Measured at VDD/2 on the CLKOUT pins
of devices 0700ps
tJCycle-to-cycle jitter[7] Measured at 66.67 MHz, loaded outputs 200 ps
tLOCK PLL lock time[7] Stable power supply, valid clock
presented on REF pin 1.0 ms
Notes
5. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
6. REF input has a threshold voltage of VDD/2.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters specified with loaded outputs.
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 5 of 12
Switching Characteristics for CY23S05SI-1H and CY23S09SI-1H Industrial Temperature Devices[8]
Parameter Description Test Cond itions Min Typ Max Unit
t1 Output frequency 30 pF loa d
10 pF load 10
10 100
133.33 MHz
MHz
Duty cycle[7] = t2 t1Measured at 1.4 V, Fout = 66.67 MHz 40.0 50.0 60.0 %
Duty cycle[7] = t2 t1Measured at 1.4 V, Fout <50.0 MHz 45.0 50.0 55.0 %
t3 Rise time[7] Measured between 0.8 V and 2.0 V 1.50 ns
t4Fall time[7] Measured between 0.8 V and 2.0 V 1.50 ns
t5Output-to-output skew[7] All outputs equally loaded 250 ps
t6Delay, REF Rising Edge to
CLKOUT Rising Edge[7] Measured at VDD/2 0±350ps
t7Device-to-Device Skew[7] Measured at VDD/2 on the CLKOUT pins
of devices 0700ps
t8Output slew rate[7] Measured between 0.8 V and 2.0 V using
Test Circuit #2 1V/ns
tJCycle-to-cycle jitter[7] Measured at 66.67 MHz, loaded outputs 200 ps
tLOCK PLL lock time[7] Stable power supply, valid clock
presented on REF pin 1.0 ms
Switching Waveforms Figure 4. Duty Cycle Timing
Figure 5. All Outputs Rise/Fall Time
Figure 6. Output-Output Skew
Figure 7. Input-Output Propagation Delay
t1
t2
1.4 V 1.4 V 1.4 V
OUTPUT
t3
3.3 V
0 V
0.8 V
2.0 V 2.0 V
0.8 V
t4
1.4 V
1.4 V
t5
OUTPUT
OUTPUT
VDD/2
t6
INPUT
OUTPUT
VDD/2
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 6 of 12
Figure 8. Device-Device Skew
Test Circuits
Switching Waveforms continued
2309–8
VDD/2
VDD/2
t7
CLKOUT, Device 1
CLKOUT, Device 2
0.1 F
VDD
0.1 F
VDD
CLK out
CLOAD
OUTPUTS
GND
GND
0.1 F
VDD
0.1 F
VDD
10 pF
OUTPUTS
GND
GND
1 kW
1 kW
Test Circuit # 1 Test Circuit # 2
For parameter t8 (output slew rate) on –1H devi c es
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 7 of 12
Ordering Code Definitions
Ordering Information
Ordering Code Package Name Package Type Operating Range
Pb-Free
CY23S05SXC-1 SZ08 8-pin 150-mil SOIC Commercial (0 to 7 0 C)
CY23S05SXC-1T SZ08 8-pin 150-mil SOIC – Tape and Reel Commercial (0 to 70 C)
CY23S05SXC-1H SZ08 8-pin 150-mil SOIC Commercial (0 to 7 0 C)
CY23S05SXC-1HT SZ08 8-pin 150-mil SOIC – Tape and Reel Commercial (0 to 70 C)
CY23S05SXI-1 SZ08 8-pin 150-mil SOIC Industrial (–40 to 85 C)
CY23S05SXI-1T SZ08 8-pin 150-mil SOIC – Tape and Reel Industrial (–40 to 85 C)
CY23S09SXC-1 SZ16 16-pin 150-mil SOIC Commercial (0 to 70 C)
CY23S09SXC-1T SZ16 16-pin 150-mil SOIC – Tape and Reel Commercial (0 to 70 C)
CY23S09SXC-1H SZ16 16-pin 150-mil SOIC Commercial (0 to 7 0 C)
CY23S09SXC-1HT SZ16 16-pin 150-mil SOIC – Tape and Reel Commercial (0 to 70 C)
CY23S09ZXC-1H ZZ16 16-pin 4.4 mm TSSOP Commercial (0 to 70 C)
CY23S09ZXC-1HT ZZ16 16-pin 4.4 mm TSSOP – Tape and Reel Commercial (0 to 70 C)
Tape and Reel
Output Drive:
1 = standard drive
1H = high drive
Temperature Range:
C = Commercial
I = Industrial
Package:
Base device part number (S = Spread aware)
Company ID: CY = Cypress
23S05
CY S(X) C1(H) (T)
05 = 5-output zero delay buffer
09 = 9-output zero delay buffer
S = SOIC, leaded
Z = TSSOP, leaded
SX = SOIC, Pb-free
ZX = TSSOP, Pb-free
-
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 8 of 12
Package Diagrams
Figure 9. 8-Pin (150-Mil) SOIC S08 and SZ08
Figure 10. 16-Pin (150-Mil) SOIC S16 and SZ16
51-85066 *E
51-85068 *D
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 9 of 12
Figure 11. 16-Pin TSSOP 4.40 mm Body Z16 and ZZ16
Package Diagrams continued
51-85091 *D
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 10 of 12
Acronym
Document Conventions
Units of Measure
Acronym Description
CMOS complementary metal oxide semiconductor
EMI electromagnetic interference
PLL phase-locked loop
SOIC small outline integrated circuit
SS spread spectrum
SSFTG spread spectrum frequency timing generator
SSOP sh ru nk sma l l ou tl i n e package
TSSOP thin shrunk small outline package
Symbol Unit of Measure
C degree Celsius
MHZ megahertz
uA microamperes
mA milliamperes
ms milliseconds
ns nanoseconds
%percent
pF picofarads
ps picoseconds
Vvolt
CY23S09, CY23S05
Document Number: 38-0729 6 Rev. *G Page 11 of 12
Document History Page
Document Title: CY23S09/CY23S05 Low Cost 3.3 V Spread Aware Zero Delay Buffer
Document Number: 38-07296
Rev. ECN No. Submission
Date Orig. of
Change Description of Change
** 111147 11/14/01 DSG Changed from spec number 38-01094 to 38-0729 6
*A 111773 02/20/02 C TK Added 150-mil SSOP option
*B 122885 12/22/02 RBI A dded power-up requirements to Operating Conditions
*C 267849 See ECN RGL Added Lead-Free devices
*D 2595524 10/23/08 CXQ/PYRS Added device “Status” to Ordering Information
*E 2761988 09/10/09 KVM Removed obsolete parts from Ordering Information table: CY23S09ZC-1,
CY23S09OC-1, CY23S09OC-1H, CY23S09ZXC-1, CY23S09OXC-1,
CY23S09OXC-1H.
Added CY23S05SXC-1T, CY23S05SXC-1HT, CY23S09SXC-1T,
CY23S09SXC-1HT, CY23S09ZXC-1HT.
Removed Status column from Ordering Information table; added footnote.
Updated package names and added numerical temperature range to
Ordering Information table.
Removed QSOP package drawing.
*F 2897373 03/22/10 CXQ Removed part numbers CY23S05SC-1, CY23 S05SC-1H, CY23S09SC-1,
CY23S09SC-1H, and CY23S09ZC-1H from Ordering Information table.
Added CY23S05SXI-1 and CY23S05SXI-1T to Ordering Information table.
Updated package diagrams.
Updated copyright section.
*G 3394655 10/04/11 PURU Added Figure 1
Updated Hyper links
Updated Package Diagrams
Added Ordering Code Definitions, Acronym, and Units of Measure.
Document Number: 38-07296 Rev. *G Revised October 04, 2011 Page 12 of 12
All product and company names mentioned in this document may be the trademarks of their respective holders.
CY23S09, CY23S05
© Cypress Semico nducto r Co rpor ation , 20 01-2 011. The information cont ai ned he rein is subj ect to chang e with out no tice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products a re n ot war ran t ed nor int e nd ed to be used fo r
medical, life supp or t, l if e savin g, cr it ical control or safety applic at io ns, unless pursuant to an express wr i tte n ag reement with Cypress. Further mor e, Cypre ss does not author iz e it s pr o ducts for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protect ion (United States an d foreign),
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used on ly in conjunction with a C ypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, mod ification, translati on, compilatio n, or represent ation of this Sour ce Code except a s specified abo ve is prohibit ed without
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