CMOS Static RAM 256K (32K x 8-Bit) IDT71256S IDT71256L Features Description The IDT 71256 is a 262,144-bit high-speed static RAM organized as 32K x 8. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Address access times as fast as 20ns are available with power consumption of only 350mW (typ.). The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to and remain in, a low-power standby mode as long as CS remains HIGH. In the full standby mode, the low-power device consumes less than 15W, typically. This capability provides significant system level power and cooling savings. The low-power (L) version also offers a battery backup data retention capability where the circuit typically consumes only 5W when operating off a 2V battery. The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP, a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC providing high board level packing densities. The IDT71256 military RAM is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. High-speed address/chip select time - Military: 25/35/45/55/70/85/100ns (max.) - Industrial: 25/35ns (max.) - Commercial: 20/25/35ns (max.) low power only Low-power operation Battery Backup operation - 2V data retention Produced with advanced high-performance CMOS technology Input and output directly TTL-compatible Available in standard 28-pin (300 or 600 mil) ceramic DIP, 28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and 32-pin LCC Military product compliant to MIL-STD-883, Class B Functional Block Diagram A0 VCC 262,144 BIT MEMORY ARRAY ADDRESS DECODER GND A14 I/O0 I/O CONTROL INPUT DATA CIRCUIT I/O7 CS OE WE , CONTROL CIRCUIT 2946 drw 01 NOVEMBER 2008 1 (c)2008 Integrated Device Technology, Inc. DSC-2946/11 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Pin Configurations A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND Truth Table(1) 1 28 2 27 3 26 4 25 24 5 6 7 8 9 D28-3 P28-1 D28-1 SO28-5 10 VCC WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3 23 22 21 20 11 19 18 12 17 13 16 14 15 2 1 32 31 30 29 28 6 7 27 8 26 9 10 L32-1 I/O Function X H X High-Z Standby (ISB) X VHC X High-Z Standby (ISB1) H L H High-Z Output Disabled H L L DOUT Read Data L L X DIN Write Data Symbol A7 A12 A 1 A14 NC V VCC A WE A13 4 3 5 OE 25 24 11 23 12 22 13 21 A8 A9 A11 NC OE A10 CS I/O7 I/O6 Rating Com'l. Ind. Mil. VTERM Terminal Voltage with Respect to GND TA Operating Temperature TBIAS Temperature Under Bias TSTG Storage Temperature PT Power Dissipation 1.0 1.0 1.0 IOUT DC Output Current 50 50 50 Unit -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 V -55 to +125 o C -55 to +125 -55 to +125 -65 to +135 o C -55 to +125 -55 to +125 -65 to +150 o C 0 to +70 -40 to +85 W mA 2946 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. , , 2946 drw 03 I/O1 I/O2 GND NC I/O3 I/O4 I/O5 14 15 16 17 18 19 20 2946 tbl 02 Absolute Maximum Ratings(1) DIP/SOJ Top View A6 A5 A4 A3 A2 A1 A0 NC I/O0 CS NOTE: 1. H = VIH, L = VIL, X = Don't care. 2946 drw 02 INDEX WE 32-Pin LCC Top View Capacitance (TA = +25C, f = 1.0MHz) Pin Descriptions Symbol Name Description A0 - A14 Address Inputs I/O0 - I/O7 Data Input/Output CS Chip Select WE Write Enable OE Output Enable GND Ground VCC Power Parameter(1) CIN Input Capacitance CI/O I/O Capacitance Conditions Max. Unit VIN = 0V 11 pF VOUT = 0V 11 pF 2946 tbl 04 NOTE: 1. This parameter is determined by device characterization, but is not production tested. 2946 tbl 01 2 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Recommended DC Operating Conditions Recommended Operating Temperature and Supply Voltage Temperature GND Vcc Symbol Military -55OC to +125OC 0V 5V 10% V CC Supply Voltage Industrial -40OC to +85OC 0V 5V 10% GND Ground 0V 5V 10% Grade Commercial O O 0 C to +70 C 2946 tbl 05 Parameter Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 6.0 V 0.8 V V IH Input High Voltage 2.2 ____ V IL Input Low Voltage -0.5(1) ____ NOTE: 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle. 2946 tbl 06 DC Electrical Characteristics(1,2) (VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71256S/L20 Power Symbol ICC ISB ISB1 Com'l. & Ind Mil. Com'l & Ind Mil. S ____ ____ ____ L 135 ____ 125 S ____ ____ Standby Power Supply Current (TTL Level), CS > VIH, VCC = Max., Outputs Open, f = fMAX(2) L 3 Full Standby Power Supply Current (CMOS Level), CS > V HC, VCC = Max., f = 0 S Parameter Dynamic Operating Current CS < V IL, Outputs Open VCC = Max., fMAX(2) 71256S/L25 L 71256S/L35 71256S/L45 Com'l. & Ind Mil. 150 ____ 140 ____ 135 130 115 120 ____ 115 ____ 20 ____ 20 ____ 20 ____ 3 3 3 3 ____ 3 ____ ____ ____ 20 ____ 20 ____ 20 0.6 ____ 1.5 ____ 1.5 0.6 1.5 Com'l. Mil. Unit 0.6 mA mA mA 2946 tbl 07 Symbol ICC ISB ISB1 71256S/L55 71256S/L70 71256S/L85 71256S/L100 Power Mil. Mil. Mil. Mil. Unit Dynamic Operating Current CS < VIL, Outputs Open VCC = Max., fMAX(2) S 135 135 135 135 mA L 115 115 115 115 Standby Power Supply Current (TTL Level), CS > VIH, VCC = Max., Outputs Open, f = fMAX(2) S 20 20 20 20 L 3 3 3 3 Full Standby Power Supply Current (CMOS Level), CS > VHC, VCC = Max., f = 0 S 20 20 20 20 L 1.5 1.5 1.5 1.5 Parameter mA mA 2946 tbl 08 NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling. 6.42 3 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2946 tbl 09 5V 5V 480 480 DATA OUT DATA OUT 30pF* 255 5pF* 255 , , 2946 drw 04 2946 drw 05 Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) *Includes scope and jig capacitances DC Electrical Characteristics (VCC = 5.0V 10%) IDT71256S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions Min. Typ. ____ IDT71256L Max. Min. Typ. Max. Unit 10 5 ____ ____ ____ 5 2 A ____ V CC = Max., V IN = GND to VCC MIL. COM"L & IND. ____ ____ ____ V CC = Max., CS = VIH, V OUT = GND to V CC MIL. COM"L & IND. ____ ____ ____ ____ ____ 5 2 A ____ 10 5 ____ ____ IOL = 8mA, VCC = Min. ____ ____ 0.4 ____ ____ 0.4 V IOL = 10mA, VCC = Min. ____ ____ 0.5 ____ ____ 0.5 2.4 ____ ____ 2.4 ____ ____ IOH = -4mA, VCC = Min. V 2946 tbl 10 Data Retention Characteristics Over All Temperature Ranges (L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V) Typ.(1) VCC @ Symbol Parameter V DR VCC for Data Retention ICCDR Data Retention Current tCDR Chip Deselect to Data Retention Time tR(3) Operation Recovery Time Max. VCC @ Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit ____ 2.0 ____ ____ ____ ____ V ____ ____ ____ ____ ____ ____ 500 120 800 200 0 ____ ____ ____ ____ ns tRC(2) ____ ____ ____ ____ ns MIL. COM'L. & IND. CS > VHC A 2946 tbl 11 NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed by device characterization, but is not production tested. 4 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Low VCC Data Retention Waveform DATA RETENTION MODE VCC 4.5V VDR 2V tCDR CS 4.5V VIH tR VIH VDR 2946 drw 06 AC Electrical Characteristics (VCC = 5.0V 10%, All Temperature Ranges) 71256L20(1) Symbol Parameter 71256S25 71256L25 71256S35 71256L35 71256S45(3) 71256L45(3) Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 20 ____ 25 ____ 35 ____ 45 ____ ns tAA Address Access Time ____ 20 ____ 25 ____ 35 ____ 45 ns tACS Chip Select Access Time ____ 20 ____ 25 ____ 35 ____ 45 ns tCLZ(2) Chip Select to Output in Low-Z 5 ____ 5 ____ 5 ____ 5 ____ ns tCHZ(2) Chip Desele ct to Output in High-Z ____ 10 ____ 11 ____ 15 ____ 20 ns tOE Output Enable to Output Valid ____ 10 ____ 11 ____ 15 ____ 20 ns tOLZ(2) Output Enab le to Output in Low-Z 2 ____ 2 ____ 2 ____ 0 ____ ns tOHZ(2) Output Disab le to Output in High-Z 2 8 2 10 2 15 ____ 20 ns tOH Output Hold from Address Change 5 ____ 5 ____ 5 ____ 5 ____ ns 20 ____ 25 ____ 35 ____ 45 ____ ns 20 ____ 30 ____ 40 ____ ns Write Cycle tWC Write Cycle Time tCW Chip Select to End-of-Write 15 ____ tAW Address Valid to End-of-Write 15 ____ 20 ____ 30 ____ 40 ____ ns tAS Address Set-up Time 0 ____ 0 ____ 0 ____ 0 ____ ns 20 ____ 30 ____ 35 ____ ns tWP Write Pulse Width 15 ____ tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ ns tDW Data to Write Time Overlap 11 ____ 13 ____ 15 ____ 20 ____ ns ____ 10 ____ 11 ____ 15 ____ 20 ns (2) tWHZ Write Enab le to Output in High-Z tDH Data Hold from Write Time 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(2) Output Active from End-of-Write 5 ____ 5 ____ 5 ____ 5 ____ ns NOTES: 1. 0 to +70C temperature range only. 2. This parameter is guaranteed by device characterization, but is not production tested. 3. -55C to +125C temperature range only. 6.42 5 2946 tbl 12 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges AC Electrical Characteristics (VCC = 5.0V 10%, Military Temperature Ranges) 71256S55(1) 71256L55(1) Symbol Parameter 71256S70(1) 71256L70(1) 71256S85(1) 71256L85(1) 71256S100(1) 71256L100(1) Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 55 ____ 70 ____ 85 ____ 100 ____ ns tAA Address Access Time ____ 55 ____ 70 ____ 85 ____ 100 ns tACS Chip Select Access Time ____ 55 ____ 70 ____ 85 ____ 100 ns tCLZ(2) Chip Select to Output in Low-Z 5 ____ 5 ____ 5 ____ 5 ____ ns tCHZ(2) Chip Desele ct to Output in High-Z ____ 25 ____ 30 ____ 35 ____ 40 ns tOE Output Enable to Output Valid ____ 25 ____ 30 ____ 35 ____ 40 ns tOLZ(2) Output Enab le to Output in Low-Z 0 ____ 0 ____ 0 ____ 0 ____ ns tOHZ(2) Output Disab le to Output in High-Z 0 25 0 30 ____ 35 ____ 40 ns tOH Output Hold from Address Change 5 ____ 5 ____ 5 ____ 5 ____ ns Write Cycle tWC Write Cycle Time 55 ____ 70 ____ 85 ____ 100 ____ ns tCW Chip Select to End-of-Write 50 ____ 60 ____ 70 ____ 80 ____ ns tAW Address Valid to End-of-Write 50 ____ 60 ____ 70 ____ 80 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns 45 ____ 50 ____ 55 ____ ns 0 ____ 0 ____ 0 ____ ns 35 ____ 40 ____ ns tAS Address Set-up Time tWP Write Pulse Width 40 ____ tWR Write Recovery Time 0 ____ 30 ____ tDW Data to Write Time Overlap 25 ____ tWHZ(2) Write Enab le to Output in High-Z ____ 25 ____ 30 ____ 35 ____ 40 ns tDH Data Hold from Write Time (WE) 0 ____ 0 ____ 0 ____ 0 ____ ns tOW(2) Output Active from End-of-Write 5 ____ 5 ____ 5 ____ 5 ____ NOTES: 1. -55 to +125C temperature range only. 2. This parameter is guaranteed by device characterization, but is not production tested. 6 ns 2946 tbl 13 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Read Cycle No. 1(1) tRC ADDRESS tOH tAA OE tOE tOLZ (5) tOHZ(5) CS tACS tCHZ(5) tCLZ (5) DATAOUT 2946 drw 07 Timing Waveform of Read Cycle No. 2(1,2,4) tRC ADDRESS tAA tOH tOH DATAOUT , 2946 drw 08 Timing Waveform of Read Cycle No. 2(1,3,4) CS tACS tCHZ(5) tCLZ (5) DATAOUT 2946 drw 09 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS is LOW. 3. Address valid prior to or coincident with CS transition LOW. 4. OE is LOW. 5. Transition is measured 200mV from steady state. 6.42 7 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4,6) t WC ADDRESS t OHZ (5) OE tAW CS (6) t WR t WP t AS WE tWZ (5) t OW (3) DATAOUT (3) tDW tDH DATAIN 2946 drw 10 Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4) tWC ADDRESS tAW CS t AS tCW(6) tt WR WE t DW tDH2 DATA IN 2946 drw 11 NOTES: 1. A write occurs during the overlap of a LOW CS and a LOW WE. 2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 3. During this period, I/O pins are in the output state so that the input signals must not be applied. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state. 5. Transition is measured 200mV from steady state. 6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short as the specified tWP . For a CS controlled write cycle, OE may be LOW with no degradation to tCW. 8 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Ordering Information -- Commercial & Industrial Ordering Information -- Military 6.42 9 IDT71256S/L CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges Datasheet Document History 11/4/99 Pp. 1-5, 9 Pg. 1 Pg. 2 Pg. 3 Pg. 5 Pg. 6 Pg. 8 Pg. 9 Pg. 10 08/09/00 02/01/01 Updated to new format Added Industrial Temperature Range offerings Removed 30, 120, and 150ns military and 45ns commercial speed grade offerings. Removed P28-2 package from DIP/SOJ Top View Removed 30ns and 45ns (Commercial only) speed grade offerings from DC Electrical table Revised notes and footnotes Removed 30ns speed grade offering from AC Electrical table Revised notes and footnotes Expressed Military Temperature range on AC Electrical table Revised notes and footnotes Removed Note 1 and renumbered notes and footnotes Revised Ordering Information and presented by temperature range offering Added Datasheet Document History Not recommended for new designs Remove "Not recommended for new designs" 11/15/06 Pg.3 Changed power limits for commercial and industrial. Refer to PCN SR-0602-03. Added Restricted hazardous substance devce to ordering information. 11/01/08 Pg.2,9 Corrected typo on pin 21 in 32-Pin LCC diagram. Updated the ordering information by removing the "IDT" notation. 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