NOVEMBER 2008
1
©2008 Integrated Device Technology, Inc. DSC-2946/11
Features
◆◆
◆◆
◆High-speed address/chip select time
– Military: 25/35/45/55/70/85/100ns (max.)
– Industrial: 25/35ns (max.)
– Commercial: 20/25/35ns (max.) low power only
◆◆
◆◆
◆Low-power operation
◆◆
◆◆
◆Battery Backup operation – 2V data retention
◆◆
◆◆
◆Produced with advanced high-performance CMOS
technology
◆◆
◆◆
◆Input and output directly TTL-compatible
◆◆
◆◆
◆Available in standard 28-pin (300 or 600 mil) ceramic DIP,
28-pin (600 mil) plastic DIP, 28-pin (300 mil) SOJ and
32-pin LCC
◆◆
◆◆
◆Military product compliant to MIL-STD-883, Class B
Functional Block Diagram
Description
The IDT 71256 is a 262,144-bit high-speed static RAM organized as
32K x 8. It is fabricated using IDT's high-performance, high-reliability
CMOS technology.
Address access times as fast as 20ns are available with power
consumption of only 350mW (typ.). The circuit also offers a reduced power
standby mode. When CS goes HIGH, the circuit will automatically go to and
remain in, a low-power standby mode as long as CS remains HIGH. In
the full standby mode, the low-power device consumes less than 15µW,
typically. This capability provides significant system level power and
cooling savings. The low-power (L) version also offers a battery backup
data retention capability where the circuit typically consumes only 5µW
when operating off a 2V battery.
The IDT71256 is packaged in a 28-pin (300 or 600 mil) ceramic DIP,
a 28-pin 300 mil SOJ, a 28-pin (600 mil) plastic DIP, and a 32-pin LCC
providing high board level packing densities.
The IDT71256 military RAM is manufactured in compliance with the
latest revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance and
reliability.
CMOS Static RAM
256K (32K x 8-Bit)
IDT71256S
IDT71256L
A
0
ADDRESS
DECODER 262,144 BIT
MEMORY ARRAY
I/O CONTROL
2946 drw 01
INPUT
DATA
CIRCUIT
WE
CS
V
CC
GND
A
14
I/O
0
I/O
7
CONTROL
CIRCUIT
OE
,
2
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configurations
DIP/SOJ
Top View
Truth Table(1)
32-Pin LCC
Top View
2946 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
424
23
22
21
20
19
18
17
D28-3
P28-1
D28-1
SO28-5
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
A
14
WE
A
13
A
8
A
10
A
11
OE
A
12
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
9
16
15
5
6
7
8
9L32-1
201918
17
10
11
12
13
1
V
1615
2946 drw 03
14
4
A
3
A
1
,
1
INDEX
2
21
22
23
24
25
26
27
28
29
32 31 30
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
A8
A9
A11
NC
OE
A10
CS
I/O7
I/O6
A
7
A
12
A
14
NC
V
CC
WE
A
13
I/O
1
I/O
2
GND
NC
I/O
3
I/O
4
I/O
5
,
Pin Descriptions
Name Description
A
0
- A
14
Address Inputs
I/O
0
- I/O
7
Data Inp ut/ Outp ut
CS Chip Se lect
WE Write Enable
OE Output Enable
GND Ground
V
CC
Power
2946 tbl 01
Capacitance (TA = +25°C, f = 1.0MHz)
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
NOTE:
1 . H = VIH, L = VIL, X = Don't care.
WE CS OE I/O Function
X H X High-Z Standby (I
SB
)
XV
HC
X High-Z Standby (I
SB1
)
H L H High-Z Output Disabled
HLLD
OUT
Re ad Da ta
LLXD
IN
Write Data
29 46 t b l 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol Rating Com'l. Ind. Mil. Unit
V
TERM
Terminal Vo ltage
wi th Re s p e c t
to GND
-0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 V
T
A
Operating
Temperature 0 to +70 -40 to +85 -55 to +125
o
C
T
BIAS
Temperature
Und er Bias -55 to + 125 -55 to + 125 -65 to +135
o
C
T
STG
Storage
Temperature -55 to + 125 -55 to + 125 -65 to + 150
o
C
P
T
Power
Dissipation 1.0 1.0 1.0 W
I
OUT
DC Output Current505050mA
2 9 46 tb l 03
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itanc e V
IN
= 0V 11 pF
C
I/O
I/O Cap acitance V
OUT
= 0V 11 pF
2946 tbl 04
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
3
Recommended Operating
Temperature and Supply Voltage Recommended DC Operating
Conditions
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
Grade Temperature GND Vcc
Military -55
O
C to + 125
O
C 0V 5V ± 10%
Industrial -40
O
C to + 85
O
C 0V 5V ± 10%
Commercial 0
O
C to + 70
O
C 0V 5V ± 10%
29 46 t b l 05
Symbol Parameter Min. Typ. Max. Unit
V
CC
Sup ply Voltage 4.5 5.0 5.5 V
GND Ground 0 0 0 V
V
IH
Inp ut High Vo ltag e 2. 2
____
6.0 V
V
IL
Input Low Voltage -0.5
(1)
____
0.8 V
2946 tbl 06
DC Electrical Characteristics(1,2) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
71256S/L20 71256S/L25 71256S/L35 71256S/L45
Symbol Parameter Power Com'l.
& I nd Mil. Com'l
& I nd Mil. Com'l.
& I nd Mil. Com'l. Mil. Unit
I
CC
Dynamic Ope rating Current
CS < V
IL
, Outputs Open
V
CC
= Max., f
MAX
(2)
S
____ ____ ____
150
____
140
____
135 mA
L135
____
125 130 115 120
____
115
I
SB
Standby Po wer Supply Current
(TTL Lev e l), CS > V
IH
, V
CC
= Max.,
Outp uts Op e n, f = f
MAX
(2)
S
____ ____ ____
20
____
20
____
20 mA
L3
____
3333
____
3
I
SB1
Full Standby Power Supply Current
(CMOS Le ve l), CS > V
HC
,
V
CC
= Max., f = 0
S
____ ____ ____
20
____
20
____
20 mA
L0.6
____
0.6 1.5 0.6 1.5
____
1.5
2946 tb l 07
71256S/L55 71256S/L70 71256S/L85 71256S/L100
Symbol Parameter Power Mil. Mil. Mil. Mil. Unit
I
CC
Dynamic Operating Current
CS < V
IL
, Outputs Open
V
CC
= Max., f
MAX
(2)
S 135 135 135 135 mA
L 115 115 115 115
I
SB
Standby Powe r Supply Current
(TTL Lev e l), CS > V
IH
, V
CC
= Max.,
Ou tputs Open, f = f
MAX
(2)
S20202020
mA
L3 3 3 3
I
SB1
Full Standby Power Supply Current
(CMOS Lev e l), CS > V
HC
,
V
CC
= Max. , f = 0
S20202020
mA
L 1.5 1.5 1.5 1.5
2946 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC, all address inputs are cycling at fMAX; f = 0 means no address pins are cycling.
4
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Test Conditions
*Includes scope and jig capacitances
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and t WHZ)
Figure 1. AC Test Load
Inp ut P ul se Le v e ls
Inp ut Ris e / Fal l Tim e s
Inp ut Timing Re fe re n ce Le v e l s
Outp ut Re ference Le ve ls
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
29 46 t b l 09
2946drw 04
480Ω
255Ω30pF*
DATA
OUT
5V
,
2946drw 05
480Ω
255Ω5pF*
DATA
OUT
5V
,
DC Electrical Characteristics (VCC = 5.0V ± 10%)
Data Retention Characteristics Over All Temperature Ranges
(L Version Only) (VLC = 0.2V, VHC = VCC - 0.2V)
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter Test Conditions
IDT71256S IDT71256L
UnitMin. Typ. Max. Min. Typ. Max.
|I
LI
|Inp ut Le akage Current V
CC
= Max.,
V
IN
=
GND to V
CC
MIL.
COM "L & IND.
____
____
____
____
10
5
____
____
____
____
5
2µA
|I
LO
| Outp ut Le akag e Curre nt V
CC
= Max., CS = V
IH
,
V
OUT
= GND to V
CC
MIL.
COM "L & IND.
____
____
____
____
10
5
____
____
____
____
5
2µA
V
OL
Output Low Voltage I
OL
= 8mA, V
CC
= Min.
____ ____
0.4
____ ____
0.4 V
I
OL
= 10mA, V
CC
= Min.
____ ____
0.5
____ ____
0.5
V
OH
Output High Voltage I
OH
= -4mA, V
CC
= Min. 2.4
____ ____
2.4
____ ____
V
2946 tbl 10
Typ.
(1)
V
CC
@ Max.
V
CC
@
Symbol Parameter Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit
V
DR
V
CC
for Data Rete ntion
____
2.0
____ ____ ____ ____
V
I
CCDR
Data Re tenti o n Curre nt MIL.
COM 'L. & IND.
____
____
____
____
____
____
500
120 800
200 µA
t
CDR
Chip Des e l e ct to Data
Rete ntion Time CS > V
HC
0
____ ____ ____ ____
ns
t
R
(3)
Operation Recovery Time t
RC
(2)
____ ____ ____ ____
ns
2946 tbl 11
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
Low VCC Data Retention Waveform
2946 drw 06
DATA
RETENTION
MODE
4.5V 4.5V
V
DR
≥2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS V
DR
NOTES:
1. 0° to +70°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.
Symbol Parameter
71256L20
(1)
71256S25
71256L25 71256S35
71256L35 71256S45
(3)
71256L45
(3)
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cy cle Time 20
____
25
____
35
____
45
____
ns
t
AA
Address Access Time
____
20
____
25
____
35
____
45 ns
t
ACS
Chip Select Ac cess Time
____
20
____
25
____
35
____
45 ns
t
CLZ
(2)
Chip S ele c t to Output in Lo w-Z 5
____
5
____
5
____
5
____
ns
t
CHZ
(2)
Chip De selec t to Outp ut in High-Z
____
10
____
11
____
15
____
20 ns
t
OE
Output Enable to Output Valid
____
10
____
11
____
15
____
20 ns
t
OLZ
(2)
O utpu t En able to O u tput in Low- Z 2
____
2
____
2
____
0
____
ns
t
OHZ
(2)
Outp ut Di sabl e to Outp ut i n Hi g h-Z 2 8 2 10 2 15
____
20 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
ns
Wri te Cycl e
t
WC
Write Cycle Time 20
____
25
____
35
____
45
____
ns
t
CW
Chip Select to End-o f-Write 15
____
20
____
30
____
40
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 15
____
20
____
30
____
35
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data to Write Time Overlap 11
____
13
____
15
____
20
____
ns
t
WHZ
(2)
Write Enable to Outp ut in High-Z
____
10
____
11
____
15
____
20 ns
t
DH
Data Hold from Write Time 0
____
0
____
0
____
0
____
ns
t
OW
(2)
Output Active from End-of-Write 5
____
5
____
5
____
5
____
ns
2946 tbl 12
6
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%, Military Temperature Ranges)
NOTES:
1. -55° to +125°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
Symbol Parameter
71256S55
(1)
71256L55
(1)
71256S70
(1)
71256L70
(1)
71256S85
(1)
71256L85
(1)
71256S100
(1)
71256L100
(1)
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cy cle Time 55
____
70
____
85
____
100
____
ns
t
AA
Address Access Time
____
55
____
70
____
85
____
100 ns
t
ACS
Chip Select Ac cess Time
____
55
____
70
____
85
____
100 ns
t
CLZ
(2)
Chip S ele c t to Output in Lo w-Z 5
____
5
____
5
____
5
____
ns
t
CHZ
(2)
Chip De selec t to Outp ut in High-Z
____
25
____
30
____
35
____
40 ns
t
OE
Output Enable to Output Valid
____
25
____
30
____
35
____
40 ns
t
OLZ
(2)
O utpu t En able to O u tput in Low- Z 0
____
0
____
0
____
0
____
ns
t
OHZ
(2)
Outp ut Di sabl e to Outp ut i n Hi g h-Z 0 25 0 30
____
35
____
40 ns
t
OH
Output Ho ld from Address Change 5
____
5
____
5
____
5
____
ns
Wri te Cycl e
t
WC
Write Cycle Time 55
____
70
____
85
____
100
____
ns
t
CW
Chip Select to End-o f-Write 50
____
60
____
70
____
80
____
ns
t
AW
Address Valid to End-of-Write 50
____
60
____
70
____
80
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 40
____
45
____
50
____
55
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data to Write Time Overlap 25
____
30
____
35
____
40
____
ns
t
WHZ
(2)
Write Enable to Outp ut in High-Z
____
25
____
30
____
35
____
40 ns
t
DH
Data Hold from Write Time ( WE)0
____
0
____
0
____
0
____
ns
t
OW
(2)
Output Active from End-of-Write 5
____
5
____
5
____
5
____
ns
2946 tbl 13
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
7
Timing Waveform of Read Cycle No. 2(1,2,4)
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address valid prior to or coincident with CS transition LOW.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
Timing Wav eform of Read Cycle No. 1(1)
ADDRESS
CS
OE
DATA
OUT
t
RC
t
AA
t
OH
t
OE
t
ACS
t
CLZ(5)
t
OLZ(5)
2946 drw 07
t
CHZ(5)
t
OHZ(5)
2946 drw 08
ADDRESS
DATA
OUT
t
RC
t
AA
t
OH
t
OH
,
Timing Waveform of Read Cycle No. 2(1,3,4)
CS
DATA
OUT
t
ACS
t
CLZ(5)
2946 drw 09
t
CHZ(5)
8
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Timing W ave form of Write Cy cle No . 1 (WE Controlled Timing)(1,2,4,6)
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3 . During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of tWP or (tWHZ +tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse width can be as short
as the specified tWP. For a CS controlled write cycle, OE may be LOW with no degradation to tCW.
Timing Wa vef orm of Write Cyc le No. 2 (CS Controlled Timing)(1,2,4)
CS
2946 drw 10
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WZ
t
t
AS
(5)
(3)
OE
(3)
(6)
OW
t
OHZ(5)
t
WR
CS
2946 drw 11
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH2
AS
tt
(6)
6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
9
Ordering Information — Commercial & Industrial
Ordering Information — Military
10
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
Datasheet Document History
11/4/99 Updated to new format
Pp. 1–5, 9 Added Industrial Temperature Range offerings
Pg. 1 Removed 30, 120, and 150ns military and 45ns commercial speed grade offerings.
Pg. 2 Removed P28-2 package from DIP/SOJ Top View
Pg. 3 Removed 30ns and 45ns (Commercial only) speed grade offerings from DC Electrical table
Revised notes and footnotes
Pg. 5 Removed 30ns speed grade offering from AC Electrical table
Revised notes and footnotes
Pg. 6 Expressed Military Temperature range on AC Electrical table
Revised notes and footnotes
Pg. 8 Removed Note 1 and renumbered notes and footnotes
Pg. 9 Revised Ordering Information and presented by temperature range offering
Pg. 10 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Remove "Not recommended for new designs"
11/15/06 Pg.3 Changed power limits for commercial and industrial. Refer to PCN SR-0602-03. Added Restricted hazardous
substance devce to ordering information.
11/01/08 Pg.2,9 Corrected typo on pin 21 in 32-Pin LCC diagram. Updated the ordering information by removing the
"IDT" notation.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com
