Standard Products RadHard Eclipse FPGA Family (6250 and 6325) Advanced Data Sheet December, 2004 www.aeroflex.com/RadHardFPGA FEATURES Comprehensive design tools include high quality Verilog/ VHDL synthesis and simulation QuickLogic IP available for microcontrollers, DRAM controllers, USART and PCI Packaged in a 208-pin CQFP, 288 CQFP, 484 CCGA, and 484 CLGA Standard Microcircuit Drawing 5962-04229 - QML Q and V compliant part 0.25m, five-layer metal, ViaLinkTM epitaxial CMOS process for smallest die sizes One-time programmable, ViaLink technology for personalization 150 MHz 16-bit counters, 150 MHz datapaths, 60+ MHz FIFOs 2.5V core supply voltage, 3.3V I/O supply voltage Up to 320,000 usable system gates (non-volatile) I/Os - Interfaces with 3.3 volt - PCI compliant with 3.3 volt - Full JTAG 1149.1 compliant - Registered I/O cells with individually controlled enables Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Test Method 1019 - Total-dose: 300 krad(Si) - SEL Immune: >120MeV-cm2/mg INTRODUCTION The RadHard Eclipse Field Programmable Gate Array Family (FPGA) offers up to 320,000 usable system gates including Dual-Port RadHard SRAM modules. It is fabricated on 0.25m five-layer metal ViaLink CMOS process and contains a maximum of 1,536 logic cells and 24 dual-port RadHard SRAM modules (see Figure 1 Block Diagram). Each RAM module has 2,304 RAM bits, for a maximum total of 55,300 bits. Please reference product family comparison chart on page 2. - LETTH (0.25) MeV-cm2/mg: >42 logic cell flip flops >64 for embedded SRAM RAM modules are Dual Port (one asynchronous/synchronous read port, one write port) and can be configured into one of four modes (see Figure 2). The RadHard Eclipse FPGA is available in a 208-pin Cerquad Flatpack, allowing access to 99 bidirectional signal I/O, 1 dedicated clock, 8 programmable clocks and 16 high drive inputs. Other package options include a 288 CQFP, 484 CCGA and a 484 CLGA. - Saturated Cross Section (cm2) per bit 5.0E-7 logic cell flip flops 2.0E-7 embedded SRAM Up to 24 dual-port RadHard SRAM modules, organized in user-configurable 2,304 bit blocks - 5ns access times, each port independently accessible - Fast and efficient for FIFO, RAM, and initialized RAM functions 100% routable with 100% utilization and 100% user fixed I/O Variable-grain logic cells provide high performance and 100% utilization Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 3). This approach allows a variety of address depths and word widths to be tailored to a specific application. Aeroflex uses QuickLogic Corporation's licensed ESP (Embedded Standard Products) technology. QuickLogic is a pioneer in the FPGA semiconductor and software tools field. 1 Product Family Comparison The RadHard Eclipse Field Programmable Gate Array Family consists of the UT6250 and UT6325. The similarities and differences are summarized in the chart below. Features Maximum Logic Flip Flops Cell Flip Flops Device System Gates Logic Cells UT6325 320,640 1,536 3,692 UT6250 248,160 960 2,670 RAM Modules RAM Bits I/O Standards Clocks High Drive Inputs 3072 24 55,300 LVTTL, LVCMOS3, PCI, GTL+, SSTL2, SSTL3 9 16 1920 20 46,100 LVTTL, LVCMOS3, PCI, GTL+, SSTL2, SSTL3 9 16 Radiation Device RadHard Total Dose LETTH (0.25) MeV-cm2/mg Saturated Cross Section Latch-up Immune UT6325 3E5 >42 logic cell flip flops >64 embedded SRAM 5.0E-7 logic cell flip flops 2.0E-7 embedded SRAM >120 UT6250 3E5 >42 logic cell flip flops >64 embedded SRAM 5.0E-7 logic cell flip flops 2.0E-7 embedded SRAM >120 Packages Device 208 PQFP 208 CQFP 280PBGA 288 CQFP 484 PBGA 484 CLGA 484 CCGA UT6235 99 99 163 163 310 310 310 UT6250 99 99 163 163 250 250 250 2 Embedded RAM Blocks Maximum of 24 RadHard SRAM Blocks Fabric Embedded RAM Blocks Bidirectional I//O and High-Drive Inputs Figure 1. RadHard Eclipse FPGA Block Diagram 3 IP Maximum of 1,536 High Speed Variable Grain Logic Cells PRODUCT DESCRIPTION I/O Pins (9:0) (17:0) WA WD RCLK RD WCLK MODE * Each bidirectional I/O contains RadHard flip-flops for input, output, and output enable lines (9:0) RA WE (1:0) * Up to 310 bi-directional input/output pins, PCI-compliant for 3.3V buses (see Table 4) RE Distributed Networks (17:0) * One, dedicated clock network, hardwired to each logic cell flip-flop clock pin to minimize skew ASYNCRD * Eight programmable clock networks, accessible from clock pins or internal logic Figure 2. RadHard Eclipse FPGA RAM * 20 pre-defined Quad-clock networds, five per quadrant. Accessed by the 8 programmable global clock networks Software support for the product is available from QuickLogic. The turnkey QuickWorksTM package provides the most complete software solution from design entry to logic synthesis, place and route, simulation, static timing, and power analysis. The QuickToolsTM for Workstations package provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest or other third-party tools for design entry, synthesis, simulation. Please visit Quick Logic's website at www.quicklogic.com for more information. * Sixteen high drive inputs. Two inputs located in each of the eight I/O banks. Used as clock or enable signals for the I/O RadHard flip-flops, or as high drive inputs for internal logic Performance * Input + logic cell + output total delays under 12ns * Data path speeds over 200 MHz The variable grain logic cell features up to 17 simultaneous inputs and 6 outputs within a cell that can be fragmented into 6 independent sections. Each cell has a fan-in of 30 including register and control lines (see Figure 5). WDATA RAM Module (2,304 bits) WADDR * Counter speeds over 150 MHz * FIFO speeds over 60+ MHz RDATA RADDR RAM Module (2,304 bits) WDATA RDATA Figure 3. RadHard Eclipse FPGA Module Bits 4 + - INPUT REGISTER Q E D R PAD Q OUTPUT REGISTER D R E OUTPUT ENABLE REGISTER Q D R Figure 4. RadHard Eclipse FPGA I/O Cell 5 QS A1 A2 A3 A4 A5 A6 OS OP B1 B2 C1 C2 MP MS AZ OZ S D Q QZ R D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 S D Q R PS PP QC DCLK CLKSEL QR GRST Figure 5. RadHard Eclipse FPGA Logic Cell 6 NZ Q2Z FZ Table 1: 208-pin Ceramic Quad Flatpack Pinout Table Pin Function Pin Function Pin Function Pin Function Pin Function Pin Function 1 GND 36 IO(B) 71 IO(C) 106 GND 141 IO(F) 176 IO(G) 2 GND 37 IO(B) 72 VCCIO(C) 107 IO(E) 142 IO(F) 177 VCCIO(G) 3 GND 38 IO(B) 73 IO(C) 108 GND 143 IO(F) 178 GND 4 GND 39 IOCTRL(B) 74 IO(C) 109 IO(E) 144 IOCTRL(F) 179 IO(G) 5 IO(A) 40 INREF(B) 75 GND 110 IO(E) 145 INREF(F) 180 IO(G) 6 IO(A) 41 IOCTRL(B) 76 VCC 111 VCCIO(E) 146 VCC 181 IO(G) 7 IO(A) 42 IO(B) 77 IO(C) 112 IO(E) 147 IOCTRL(F) 182 VCC 8 VCCIO(A) 43 IO(B) 78 TRSTB 113 VCC 148 IO(F) 183 TCK 9 IO(A) 44 VCCIO(B) 79 VCC 114 IO(E) 149 IO(F) 184 VCC 10 IO(A) 45 IO(B) 80 IO(D) 115 IO(E) 150 VCCIO(F) 185 IO(H) 11 IOCTRL(A) 46 VCC 81 IO(D) 116 IO(E) 151 IO(F) 186 IO(H) 12 VCC 47 IO(B) 82 IO(D) 117 IOCTRL(E) 152 IO(F) 187 IO(H) 13 INREF(A) 48 IO(B) 83 GND 118 INREF(E) 153 GND 188 GND 14 IOCTRL(A) 49 GND 84 VCCIO(D) 119 IOCTRL(E) 154 IO(F) 189 VCCIO(H) 15 IO(A) 50 TDO 85 IO(D) 120 IO(E) 155 NU 190 IO(H) 16 IO(A) 51 NU 86 VCC 121 IO(E) 156 GND 191 IO(H) 17 IO(A) 52 GND 87 IO(D) 122 VCCIO(E) 157 GND 192 IOCTRL(H) 18 IO(A) 53 GND 88 IO(D) 123 GND 158 GND 193 IO(H) 19 VCCIO(A) 54 GND 89 VCC 124 IO(E) 159 GND 194 INREF(H) 20 IO(A) 55 GND 90 IO(D) 125 IO(E) 160 GND 195 VCC 21 GND 56 VCC 91 IO(D) 126 IO(E) 161 IO(G) 196 IOCTRL(H) 22 IO(A) 57 IO(C) 92 IOCTRL(D) 127 CLK(5) 162 VCCIO(G) 197 IO(H) 23 TDI 58 GND 93 INREF(D) 128 CLK(6) 163 IO(G) 198 IO(H) 24 CLK(0) 59 IO(C) 94 IOCTRL(D) 129 VCC 164 IO(G) 199 IO(H) 25 CLK(1) 60 VCCIO(C) 95 IO(D) 130 CLK(7) 165 VCC 200 IO(H) 26 VCC 61 IO(C) 96 IO(D) 131 VCC 166 IO(G) 201 IO(H) 27 CLK(2) 62 IO(C) 97 IO(D) 132 CLK(8) 167 IO(G) 202 IO(H) 28 CLK(3) 63 IO(C) 98 VCCIO(D) 133 TMS 168 IO(G) 203 VCCIO(H) 29 VCC 64 IO(C) 99 IO(D) 134 IO(F) 169 IOCTRL(G) 204 GND 30 CLK(4), DEDCLK 65 IO(C) 100 IO(D) 135 IO(F) 170 INREF(G) 205 IO(H) 31 IO(B) 66 IO(C) 101 GND 136 IO(F) 171 IOCTRL(G) 206 NU 32 IO(B) 67 IOCTRL(C) 102 NU 137 GND 172 IO(G) 207 GND 33 GND 68 INREF(C) 103 GND 138 VCCIO(F) 173 IO(G) 208 GND 34 VCCIO(B) 69 IOCTRL(C) 104 GND 139 IO(F) 174 IO(G) 35 IO(B) 70 IO(C) 105 GND 140 IO(F) 175 VCC 7 Table 2: RadHard Eclipse Pin Description PIN FUNCTION DESCRIPTION TDI/RSI Test data in for JTAG/RAM initialization Serial Data In Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. TRSTB/RRO Active low reset for JTAG/ RAM initialization reset out Hold LOW during normal operation. Connects to serial PROM reset for RAM initialization. Connect to GND if unused. TMS Test mode select for JTAG Hold HIGH during normal operation. Connect to VCC if not used for JTAG. TCK Test clock for JTAG Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG. TDO/RCO Test data out for JTAG/RAM initialization clock out Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. STM Special Test Mode Must be grounded during normal operation. I/ACLK High-drive input and/or array Can be configured as either or both. network driver I/GCLK High-drive input and/or global Can be configured as either or both network driver I High-drive input Use for input signals with high fanout I/O Input/Output pin Can be configured as an input and/or output VCC Power supply pin Connect to 2.5V supply VCCIO Input voltage tolerance pin Connect to 3.3V supply GND Ground pin Connect to ground 8 ABSOLUTE MAXIMUM RATINGS1 (Referenced to VSS) SYMBOL PARAMETER LIMITS VCC Core supply voltage -0.5 to 3.6V VCCIO I/O supply voltage -0.5 to 4.6V INREF I/O reference voltage 2.7V VIO Voltage on any pin -0.5V to VCCIO +0.5V ILU Electrical Latchup Immunity +/-100mA PD Power Dissipation .5 - 2.5W JC Thermal resistance, junction-to-case2 5oC/W TJ Maximum junction temperature2 +150C ESDS ESD pad protection +/-2000V II DC input current 20 mA TLS Lead Temperature 300C Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Test per MIL-STD-883; Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VCCIO PARAMETER LIMITS Core supply voltage 2.3 to 2.7V I/O Input Tolerance Voltage 3.0 to 3.6V TA Ambient Temperature K1 Delay factor for RadHard FPGA -55C to +125C 0.42 to 2.3 Notes: 1. To conclude best and worst case delays, multiply the RadHard K factor from the operating conditions with the delay values defined in the following AC delay tables. 9 DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* (-55C to +125C) (VCC = 2.5V + 10%) SYMBOL PARAMETER CONDITION MIN MAX UNIT IIN Input or I/O leakage current VIN = VCCIO or Gnd -10 10 A IOZ Three-state output leakage current VIN= VCCIO or Gnd -10 10 A CI1 Input capacitance -- - 8 pF CI/O1 Bi-directional capacitance -- - 12 pF IOS2 Short-circuit output current VO = GND VO = VCCIO -15 40 -180 210 mA mA VIN, VO = VCCIO or GND .50 5 mA -10 10 A - 150 A ICC Quiescent current IREF DC supply current on INREF IPD Pad Pull-down (programmable) VCCIO = 3.6V Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Capacitance is sample tested for initial qualification or design changes only. Clock pins are 12pF maximum. 2. Input only or I/O. Duration should not exceed 30 seconds. Table 3: DC Input and Output Levels VIL INREF VIH VOL VOH IOL IOH VMIN VMAX VMIN VMAX VMIN VMAX VMAX VMIN mA mA LVTTL n/a n/a -0.3 0.8 2.0 VCCIO + 0.3 0.4 2.4 2.0 -2.0 LVCMOS3 n/a n/a -0.3 0.7 1.7 VCCIO + 0.3 0.7 1.7 2.0 -2.0 PCI n/a n/a -0.3 0.3 x VCCIO 0.5 x VCCIO 1.5 -0.5 VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO Notes: 1. The data provided in Table 1 are JEDEC and PCI specifications. See preceding AC Delay Data for information specific to RadHard Eclipse FPGA I/Os. Table 4: Max Bidirectional I/O per Device/Package Combination Device 208 CQFP 288 CQFP 484 CCGA RadHard Eclipse FPGA 6250 99 163 250 RadHard Eclipse FPGA 6325 99 163 310 Notes: 1. Excludes input only signals such as DEDCLK. PROGCLK and IOCTRL. 10 AC CHARACTERISTICS LOGIC CELLS (Pre/Post-Radiation)* (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) Min Max TPD Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output 0.205 1.01 TSU Setup Time: time the synchronous input of the flip flop must be stable before the active clock edge 0.231 -- THL Hold Time: time the synchronous input of the flip flop must be stable after the active clock edge 0 -- TCO Clock to Out Delay: the amount of time taken by the flip flop to output after the active clock edge - 0.43 TCWHI Clock High Time: required minimum time the clock stays high 0.46 -- TCWLO Clock Low Time: required minimum that the clock stays low 0.46 -- TSET Set Delay: time between when the flip flop is "set" (high) and when the output is consequently "set" (high) -- 0.59 TRESET Reset Delay: time between when the flip flop is "reset" (low) and when the output is consequently "reset" (low) -- 0.66 TSW Set Width: time that the SET signal remains high/low 0.3 -- TRW Reset Width: time that the RESET signal remains high/low 0.3 Notes: * Post-radiation performance guaranteed at 25C per MIL-STD-883 Method 1019. 1. Stated timing for typical case propagation delay over process variation at VCC=2.5V and TA=25oC. Multiply by the appropriate delay factor, K, for voltage and temperature settings as specified in operating range. 2. These limits are derived from a representative selection of the slowest paths through the logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design. 11 SET D Q CLK RESET Figure 6: Logic Cell Flip Flop CLK tCWHI (MIN) tCWLO (MIN) SET RESET Q tRESET tSET tRW tSW Figure 7: Logic Cell Flip Flop Timings - First Waveform CLK D tSU tHL D tCO Figure 8: Logic Cell Flip Flop Timings - Second Waveform 12 Quad Net Figure 9: Global Clock Structure GLOBAL CLOCK TREE DELAY (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) Min Max tPGCK Global clock pin delay to quad net 0.990 1.386 tBGCK Global clock buffer delay (quad net to flip flop) 0.534 1.865 Programmable Clock Global Clock Buffer External Clock Global Clock Clock Select tPGCK tBGCK Figure 10: Global Clock Structure Schematic 13 RAM CELL SYNCHRONOUS and ASYNCHRONOUS READ TIMING (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) RAM Cell Synchronous Read Timing Min Max tSRA RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK 0.686ns -- tHRA RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK 0ns -- tSRE RE setup time to RCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK 0.243ns -- tHRE RE hold time to RCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK 0ns -- tRCRD RCLK to RD: time between the active READ CLOCK edge and the time when the data is delivered to RD -- 2.3ns -- 2.4ns RAM Cell Asynchronous Read Timing tPDRD RA to RD: time between when the READ ADDRESS is input and when the DATA is output RCLK RA tSRA tHRA tSRE tHRE RE RD old data new data tRCRD tPDRD Figure 11: RAM Cell Synchronous and Asynchronous Read Timing 14 RAM CELL SYNCHRONOUS WRITE TIMING (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) Min Max tSWA WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK 0.675ns -- tHWA WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK 0ns -- tSWD WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK 0.654ns -- tHWD WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK 0ns -- tSWE WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK 0.276ns tHWE WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK 0ns tWCRD WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD -- 2.8 WCLK WA tSWA tHWA tSWD tHWD tSWE tHWE WD WE RD old data new data tWCRD Figure 12: RAM Cell Synchronous Write Timing 15 tICLK tIN - tINI tISU + - tSID Q E D R PAD Figure 13. Input Register Cell 16 INPUT REGISTER CELL (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) Min Max tISU Input register setup time: time the synchronous input of the pin must be stable before the active clock edge 3.308ns 3.526ns tIHL Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0ns -- tICO Input register clock to out: time taken by the flip-flop to output after the active clock edge -- 0.494ns tIRST Input register reset delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) -- 0.464ns tIESU Input register clock enable setup time: time "enable" must be stable before the active clock edge 0.830ns - tIEH Input register clock enable hold time: time "enable" must be stable after the active clock edge 0ns -- STANDARD INPUT DELAYS (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) Min tSID (LVTTL) tSID (LVCMOS3) LVTTL input delay: Low voltage TTL for 3.3V applications Max - 0.34 LVCMOS2 input delay: Low voltage CMOS for 3.3V applications - 0.42 R CLK D tISU tIHL tICO Q tIRST E tIESU tIEH Figure 14. Input Register Timing 17 PAD Q D Figure 15. Output Register Cell 18 OUTPUT REGISTER CELL (VCC = 2.5V, TA = 25oC, K=1.00) SYMBOL PARAMETER Value (ns) Min Max tOUTLH Output Delay low to high (90% of H) - 2.59 tOUTHL Output Delay high to low (10% of L) - 2.16 tPZH Output Delay tri-state to high (90% of H) - 3.06 tPZL Output Delay tri-state to low (10% of L) -- 2.71 tPHZ Output Delay high to tri-state -- 3.44 tPLZ Output Delay low to tri-state -- 3.32 tCOP Clock to out delay (does not include clock tree delays) -- 2.67 (fast skew) 9.0 (slow skew) OUTPUT SLEW RATES (VCC = 2.5V, TA = 25oC, K=1.00, VCCIO = 3.3V) Fast Slew Slow Slew Rising Edge 2.8V/ns 1.0V/ns Falling Edge 2.86V/ns 1.0V/ns L tOUTHL L H H Z Z L tPZH Z Z tPZL L H H L tOUTHL H H L tPLZ Figure 16. Output Register Cell Timing 19 tPHZ Power vs Operating Frequency The basic power equation which best models power consumption is shown below. PTOTAL = 0.350 + f(0.0031 NLC + 0.0948 NCKBF +0.01 NCLBF + 0.0263 NCKLD + 0.543 NRAM + 0.0035 NINP + 0.0257 NOUTP) (mW) Where * NLC is the total number of logic cells in the design * NCKBF = # of clock buffers * NCLBF = # of column clock buffers * NCKLD = # of loads connected to the column clock buffers * NRAM = # of RAM blocks * NINP is the number of input pins * NOUTP is the number of output pins Figure 17 exhibits the power consumption in the device. The chip was filled with (300) 8-bit counters, approximately 76% logic cell utilization. Power vs Frequency (Counter_300) 2.5 Power (W) 2 1.5 1 .5 0 0 20 40 60 80 100 Frequency (Mhz) Figure 17: Power Consumption 20 120 140 Power-Up Sequencing VCCIO VCC Voltage (VCCIO - VCC) MAX VCC 400 us Figure 18. Power-Up Requirements/Recommendations When powering up the device, the VCC/VCCIO rails must take 400s or longer to reach the maximum value. Note: Ramping VCC/VCCIO to the maximum voltage faster than 400s can cause the device to initialize improperly (i.e. prevents the device from resetting completely during initialization). For users with a limited power budget, keep (VCCIO - VCC) MAX < 500 mV when ramping up the power supply. 21 Joint Test Access Group (JTAG) TCK TMS TAp Controller State Machine (16 States) Instruction Decode & Control Logic TRSTB Instruction Register RDI Mux Mux TDO Boundary-Scan Register (Data Register) Bypass Register Internal Register I/O Registers User Defined Data Register Figure 19. JTAG Block Diagram Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not in the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. The 1149.1 standard requires the following three tests: * Extest Instruction: The Extest instruction performs a PCB interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patters (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction: This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. 22 * Bypass Instruction: The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device. Table 5: JTAG Pin Descriptions Pin Function Description TDI/RSI Test Data In for JTAG/RAM init. Serial Data In Hold HIGH during normal operation. Connects to serial PROM data in for RAM initialization. Connect to VCC if unused. TRSTB/RRO Active low Reset for JTAG/RAM init. reset out Hold LOW during normal operation. Connects to serial PROM data in for RAM initialization. Connect to GND if unused. TMS Test Mode Select for JTAG Hold HIGH during normal operation. Connect to VCC if not used for JTAG. TCK Test Clock for JTAG Hold HIGH or LOW during normal operation. Connect to VCC or GND if not used for JTAG. Test data out for JTAG/RAM init. clock out Connect to serial PROM clock for RAM initialization. Must be left unconnected if not used for JTAG or RAM initialization. TDO/RCO Recommended Unused Pin Terminations for the RadHard Eclipse FPGA Devices All unused, general purpose I/O pins can be tied to VCC, GND, or HIZ (high impedance) internally using the Configuration editor. This option is given in the bottom-right corner of the placement window. To use the Placement Editor, choose Constraint ->Fix Placement in the Option pull-down menu of SpDE. The rest of the pins should be terminated at the board level in the manner presented in Table 5. Table 6: Recommended Unused Pin Terminations Signal Name IOCTRL <y> CLK <x> INREF <y> Recommended Termination Any unused pins of this type must be connected to either VCC or GND. Any unused clock pins should be connected to either VCC or GND. If an I/O bank does not require the use of INREF signal, the pin should be connected to GND. Note: X---> number, Y ---> alphabetical character 23 Table 7: RadHard Eclipse Device Pins Description Pin Direction Function CLK I I/O(A) I/O VCC I Core power supply pin VCCIO(A) I Input voltage tolerance pin GND I Ground pin DEDCLK I Dedicated clock pin INREF(A) I Differential reference voltage IOCTRL(A) I High drive input Global clock network driver Input/Output Pin Low skew global clock. This pin provides access to the dedicated, distributed network capable of driving the CLOCK, SET, RESET, F1 and A2 inputs to the Logic Cell; READ and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks; and Output Enables of the I/O. The I/O pin is a bi-directional pin, configurable to either an input only, output-only, or bi-directional pin. The A inside the parenthesis means that the I/O is located in Bank A. If an I/O is not used, SpDE (QuickWorks Tool) provides the option of tying that pin to GND, VCC, or TriState during programming. Connect to 2.5 V supply This pin connects to the 3.3V supply. The A inside the parenthesis means that VCCIO is located in BANK A. Every I/O pin in Bank A will be tolerant of VCCIO input signals and will output VCCIO level signals. Connect to ground. Low skew global clock. This pin provides access to the dedicated, distributed clock network capable of driving the CLOCK inputs of all sequential elements of the device (e.g. RAM and flipflops). The A inside the parenthesis means that INREF is located in BANK A. This pin should be tied to GND for LVCMOS3 and LVTTL2 inputs. This pin provides fast RESET, SET, CLOCK, and ENABLE access to the I/O cell flip-flops, providing fast clock-to-out and fast I/O response times. This pin can also double as a high-drive pin to the internal logic cells. The A inside the parenthesis means that IOCTRL is located in BANK A. This pin should be tied to GND or VCC if it is not used. 24 PACKAGING 1. All exposed metalized areas are gold plated over nickel plating per MIL-PRF-38535. 2. Lead finishes are in accordance with MIL-PRF-38535. 3. Letter designations are to cross-reference to MIL-STD-1835. 4. Packages may be shipped with repaired leads as shown. Figure 20. 208-pin Ceramic FLATPACK 25 Figure 21. 288-pin Ceramic Quad FLATPACK 1. All exposed metalized areas are gold plated over nickel plating per MIL-PRF-38535. 2. App note: Capacitor monitoring pads are dimensioned for a MIL-C-55581 CDR33 chip capacitor. 3. Lead finishes are in accordance with MIL-PRF-38535. 4. Letter designations are to cross-reference to MIL-STD-1835. 5. Packages may be shipped with repaired leads as shown. Coplanarity requirements do not apply in repaired area. 6. Seal ring is connected to VSS. 7. Drawing units are in millimeters. 26 1. Seal ring is connected to VSS. 2. Units are in millimeters (inches). 3. All top sides exposed metalized areas must be gold plated 100 to 225 micro-inches thick and all bottom side exposed metalized areas must be gold plated to 60 micro-inches thick nominal. Both sides shall be over electroplated nickel undercoating 100 to 350 micro-inches per MIL-PRF-38535. The bottom side plating is not subject to the salt atmosphere requirements of 40-7150-xx. 4. Camber: 0.08MM max. 5. Geometry is vendor optional. Cannot be alphanumeric and must be isolated within the shaded area. Must be electrically isolated. Plating is optional. Figure 22. 484-pin Ceramic Column Grid Array 27 1. Seal ring is connected to VSS. 2. Units are in millimeters (inches). 3. All top sides exposed metalized areas must be gold plated 100 to 225 micro-inches thick and all bottom side exposed metalized areas must be gold plated to 60 micro-inches thick nominal. Both sides shall be over electroplated nickel undercoating 100 to 350 micro-inches per MIL-PRF-38535. The bottom side plating is not subject to the salt atmosphere requirements of 40-7150-xx. 4. Camber: 0.08MM max. 5. Geometry is vendor optional. Cannot be alphanumeric and must be isolated within the shaded area. Must be electrically isolated. Plating is optional. Figure 23. 484-pin Ceramic Land Grid Array 28 ORDERING INFORMATION UT6325 RadHard FPGA: UT ***** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40oC to +125oC) (X) (W) (P) (V) (R) (M) (S) = 208-pin PQFP Plastic Quad Flatpack = 208-pin CQFP Ceramic Quad Flatpack = 280-pin PBGA Plastic Ball Grid Array = 288-pin CQFP Ceramic Quad Flatpack = 484-pin PBGA Plastic Ball Grid Array = 484-pin CLGA Ceramic Land Grid Array = 484-pin CCGA Ceramic Column Grid Array Device Type: (6325) = FPGA Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed. 29 UT6325 FPGA: SMD 5962 - 04229 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (W) = 208-pin CQFP Ceramic Quad Flatpack (V) = 288-pin CQFP Ceramic Quad Flatpack (M) = 484-pin CLGA Ceramic Land Grid Array (S) = 484-pin CCGA Ceramic Column Grid Array Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 02 = UT6325 Military Temperature Range 04 = UT6325 Extended Industrial Temperature Range Flow (-40oC to +125oC) Drawing Number: 04229 Total Dose: (R) = 1E5 (100 krad)(Si)) (F) = 3E5 (300 krad)(Si)) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 30 ORDERING INFORMATION UT6250 RadHard FPGA: UT ***** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40oC to +125oC) (X) (W) (P) (V) (R) (M) (S) = 208-pin PQFP Plastic Quad Flatpack = 208-pin CQFP Ceramic Column Grid Array = 280-pin PBGA Plastic Ball Grid Array = 288-pin CQFP Ceramic Quad Flatpack = 484-pin PBGA Plastic Ball Grid Array = 484-pin CLGA Ceramic Land Grid Array = 484-pin CCGA Ceramic Column Grid Array Device Type: (6250) = FPGA Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3. Prototype flow per Aeroflex Manufacturing Flows Document. Tested at 25C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per Aeroflex Manufacturing Flows Document. Devices are tested at -55C, room temp, and 125C. Radiation neither tested nor guaranteed. 31 UT6250 FPGA: SMD 5962 - 04229 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (W) = 208-pin CQFP CeramicQuad Flatpack (V) = 288-pin CQFP Ceramic Quad Flatpack (M) = 484-pin CLGA Ceramic Land Grid Array (S) = 484-pin CCGA Ceramic Column Grid Array Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 01 = UT6250 Military Temperature Range 03 = UT6250 Extended Industrial Temperature Range Flow (-40oC to +125oC) Drawing Number: 04229 Total Dose: (R) = 1E5 (100 krad)(Si)) (F) = 3E5 (300 krad)(Si)) Federal Stock Class Designator: No options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an "X" is specified when ordering, part marking will match the lead finish and will be either "A" (solder) or "C" (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 32 COLORADO Toll Free: 800-645-8862 Fax: 719-594-8468 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com Aeroflex Colorado Springs, Inc. reserves the right to make changes to any products and services herein at any time without notice. Consult Aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. Aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by Aeroflex; nor does the purchase, lease, or use of a product or service from Aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of Aeroflex or of third parties. Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 33