1
FEATURES
APPLICATIONS
DESCRIPTION
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
12-Bit, 125 MSPSAnalog-To-Digital Converter
THS9001, OPA695, OPA847
2
•12-Bit Resolution
•125 MSPS Sample Rate
•Wireless Communication•High SNR: 69.7 dBFS at 100 MHz f
IN
– Communication Receivers•High SFDR: 82 dBc at 100 MHz f
IN
– Base Station Infrastructure•2.3-V
PP
Differential Input Voltage
•Test and Measurement Instrumentation•Internal Voltage Reference
•Single and Multichannel Digital Receivers•3.3-V Single-Supply Voltage
•Communication Instrumentation•Analog Power Dissipation: 578 mW
– Radar•Serial Programming Interface
– Infrared•TQFP-64 PowerPAD™ Package
•Video and Imaging•Medical Equipment•Recommended Op Amps:THS3201, THS3202, THS4503, THS4509,
The ADS5520 is a high-performance, 12-Bit, 125 MSPS analog-to-digital converter (ADC). To provide a completeconverter solution, it includes a high-bandwidth linear sample-and-hold stage (S & H) and internal reference.Designed for applications demanding the highest speed and highest dynamic performance in little space, theADS5520 has excellent power consumption of 578 mW at 3.3-V single-supply voltage. This allows an evenhigher system integration density. The provided internal reference simplifies system design requirements. ParallelCMOS-compatible output ensures seamless interfacing with common logic.
The ADS5520 is available in a 64-pin TQFP PowerPAD package over the industrial temperature range.
Table 1. ADS5500 Product Family
80 MSPS 105 MSPS 125 MSPS
12 Bit ADS5522 ADS5521 ADS552014 Bit ADS5542 ADS5541 ADS5500
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004 – 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
.
.
.
ADS5520
Serial Programming Register
Control Logic
Timing Circuitry
Internal
Reference
Output
Control
CLKOUT
CLK+
CLK−
VIN+
VIN−
CM
AVDD DRVDD
OVR
DFS
Digital
Error
Correction
12-Bit
Pipeline
ADC Core
S&H
AGND DRGND
SCLKSDATASEN
D0
D11
ADS5520
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORTPRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY
ADS5520IPAP Tray, 160HTQFP-64
(2)ADS5520 PAP – 40 ° C to 85 ° C ADS5520IPowerPAD
ADS5520IPAPR Tape and Reel, 1000
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet.(2) Thermal pad size: 3,5 mm x 3,5 mm (min), 4 mm x 4 mm (max). θ
JA
= 21.47 ° C/W and θ
JC
= 2.99 ° C/W, when used with 2 oz. coppertrace and pad soldered directly to a JEDEC standard, four-layer, 3 in x 3 in PCB.
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ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
over operating free-air temperature range (unless otherwise noted)
(1)
ADS5520 UNIT
AV
DD
to A
GND
, DRV
DD
to DR
GND
– 0.3 to 3.7 VSupply Voltage
A
GND
to DR
GND
± 0.1 VAnalog input to A
GND
(2) (3)
– 0.3 to minimum (AVDD + 0.3, 3.6) VLogic input to DR
GND
– 0.3 to DRV
DD
VDigital data output to DR
GND
– 0.3 to DRV
DD
VOperating temperature range – 40 to 85 ° CJunction temperature 105 ° CStorage temperature range – 65 to 150 ° C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyondthose specified is not implied.(2) If the input signal can exceed 3.6 V, then a resistor greater than or equal to 25 Ωshould be added in series with each of the analoginput pins to support input voltages up to 3.8 V. For input voltages above 3.8 V, the device can only handle transients and the duty cycleof the overshoot should be limited to less than 5% for inputs up to 3.9 V.(3) The overshoot duty cycle can be defined as the ratio of the total time of overshoot to the total intended device lifetime, expressed as apercentage. The total time of overshoot is the integrated time of all overshoot occurrences over the lifetime of the device.
PARAMETER MIN TYP MAX UNIT
Supplies
Analog supply voltage, AV
DD
3 3.3 3.6 V
Output driver supply voltage, DRV
DD
3 3.3 3.6 V
Analog input
Differential input range 2.3 V
PP
Input common-mode voltage, V
CM
(1)
1.45 1.55 1.65 V
Digital Output
Maximum output load 10 pF
Clock Input
DLL ON 60 125ADCLK input sample rate (sine wave) 1/t
C
MSPSDLL OFF 2 80
Clock amplitude, sine wave, differential
(2)
1 3 V
PP
Clock duty cycle
(3)
50%
Open free-air temperature range ADS5520I – 40 85 ° C
(1) Input common-mode should be connected to CM.(2) See Figure 49 for more information.(3) See Figure 48 for more information.
Typical values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-V
PP
differential clock, and – 1dBFS differentialinput, unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
Resolution 12 Bits
Analog Inputs
Differential input range 2.3 V
PP
Differential input impedance See Figure 39 6.6 k Ω
Differential input capacitance See Figure 39 4 pFAnalog input common-mode current
300 µA(per input)
Analog input bandwidth Source impedance = 50 Ω750 MHz
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ELECTRICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-V
PP
differential clock, and – 1dBFS differentialinput, unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
ClockVoltage overload recovery time 4
cycles
Internal Reference Voltages
Reference bottom voltage, V
REFM
0.95 VReference top voltage, V
REFP
2.1 VReference error – 4% ± 0.9% 4%1.55Common-mode voltage output, V
CM
V± 0.05
Dynamic DC Characteristics and Accuracy
No missing codes TestedDifferential nonlinearity error, DNL f
IN
= 10 MHz -0.5 ± 0.25 0.5 LSBIntegral nonlinearity error, INL f
IN
= 10 MHz -1.5 ± 0.8 1.5 LSBOffset error – 11 ± 1.5 11 mVOffset temperature coefficient 0.01 mV/ ° C
Δoffset error/ ΔAV
DD
from AV
DD
= 3 V toDC power-supply rejection ratio, DC PSRR 0.25 mV/VAV
DD
= 3.6 VGain error
(1)
– 2 ± 0.45 2 %FSGain temperature coefficient 0.01 Δ%/ ° C
Dynamic AC Characteristics
25 ° C 68 70.2f
IN
= 10 MHz
Full temp range 66 69.3f
IN
= 55 MHz 70.125 ° C 68 70.1Signal-to-noise ratio. SNR f
IN
= 70 MHz dBFSFull temp range 66 68.8f
IN
= 100 MHz 69.7f
IN
= 150 MHz 69.3f
IN
= 220 MHz 68.4RMS idle channel noise Inputs tied to common-mode 0.32 LSB25 ° C 79 85f
IN
= 10 MHz
Full temp range 76 84f
IN
= 55 MHz 7925 ° C 78 83Spurious-free dynamic range, SFDR f
IN
= 70 MHz dBcFull temp range 75 82f
IN
= 100 MHz 82f
IN
= 150 MHz 78f
IN
= 220 MHz 7425 ° C 79 91f
IN
= 10 MHz
Full temp range 76 86f
IN
= 55 MHz 8425 ° C 78 87Second-harmonic, HD2 f
IN
= 70 MHz dBcFull temp range 75 83f
IN
= 100 MHz 84f
IN
= 150 MHz 78f
IN
= 220 MHz 74
(1) Gain error is specified by design and characterization; it is not tested in production.
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DIGITAL CHARACTERISTICS
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
ELECTRICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, DLL On, 3-V
PP
differential clock, and – 1dBFS differentialinput, unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
25 ° C 79 89f
IN
= 10 MHz
Full temp range 76 88f
IN
= 55 MHz 7925 ° C 78 85Third-harmonic, HD3 f
IN
= 70 MHz dBcFull temp range 75 82f
IN
= 100 MHz 82f
IN
= 150 MHz 80f
IN
= 220 MHz 78f
IN
= 10 MHz 25 ° C 88Worst-harmonic/spur (other than HD2 and
dBcHD3)
f
IN
= 70 MHz 25 ° C 8625 ° C 67.5 69.8f
IN
= 10 MHz
Full temp range 65.5 69f
IN
= 55 MHz 69.525 ° C 67.5 69.9Signal-to-noise + distortion, SINAD f
IN
= 70 MHz dBFSFull temp range 65.5 68.6f
IN
= 100 MHz 69.5f
IN
= 150 MHz 68.5f
IN
= 220 MHz 66.725 ° C 78 85f
IN
= 10 MHz
Full temp range 75 83f
IN
= 55 MHz 7725 ° C 77 81Total harmonic distortion, THD f
IN
= 70 MHz dBcFull temp range 74 79.5f
IN
= 100 MHz 79f
IN
= 150 MHz 75f
IN
= 220 MHz 72Effective number of bits, ENOB f
IN
= 70 MHz 11.3 Bitsf = 10.1 MHz, 15.1 MHz (-7dBFS each tone) 95Two-tone intermodulation distortion, IMD f = 50.1 MHz, 55.1 MHz (-7dBFS each tone) 92 dBFSf = 148.1 MHz, 153.1 MHz (-7dBFS each tone) 93.5AC power supply rejection ratio, ACPSRR Supply noise frequency ≤100 MHz 35 dB
Power Supply
Total supply current, ICC f
IN
= 70 MHz 236 260 mAAnalog supply current, IAVDD f
IN
= 70 MHz 175 190 mAOutput buffer supply current, IDRVDD f
IN
= 70 MHz 61 70 mAAnalog only 578 627Power dissipation mWOutput buffer power with 10-pF load on digital
202 231output to groundStandby power With Clocks running 180 250 mW
Valid over full recommended operating temperature range, AV
DD
= DRV
DD
= 3.3 V, unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
Digital Inputs
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ADS5520
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DIGITAL CHARACTERISTICS (continued)Valid over full recommended operating temperature range, AV
DD
= DRV
DD
= 3.3 V, unless otherwise noted
PARAMETER CONDITIONS MIN TYP MAX UNIT
High-level input voltage, V
IH
2.4 VLow-level input voltage, V
IL
0.8 VHigh-level input current, I
IH
10 µALow-level input current, I
IL
– 10 µAInput current for RESET – 20 µAInput capacitance 4 pF
Digital Outputs
Low-level output voltage, V
OL
C
LOAD
= 10 pF 0.3 0.4 VHigh-level output voltage, V
OH
C
LOAD
= 10 pF 2.8 3 VOutput capacitance 3 pF
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TIMING CHARACTERISTICS
(1) (2)
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
Typical values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, sampling rate = 125 MSPS, 50% clock duty cycle, 3-V
PP
differential clock, and C
LOAD
= 10 pF, unlessotherwise noted
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
Aperture delay, t
A
Input CLK falling edge to data sampling point 1 nsAperture jitter (uncertainty) Uncertainty in sampling instant 300 fsData setup time, t
SU
Data valid
(3)
to 50% of CLKOUT rising edge 2.3 2.7 nsData hold time, t
H
50% of CLKOUT rising edge to data becoming 1.7 2 nsinvalid
(3)
Input clock to output data valid start, Input clock rising edge to data valid start delay 2 2.6 nst
START
(4) (5)
Input clock to output data valid end, Input clock rising edge to data valid end delay 5.8 6.9 nst
END
(4) (5)
Output clock jitter, t
JIT
Uncertainty in CLKOUT rising edge, peak-to-peak 150 210 ps
PP
Output clock rise time, t
r
Rise time of CLKOUT from 20% to 80% of DRV
DD
1.7 1.9 nsOutput clock fall time, t
f
Fall time of CLKOUT from 80% to 20% of DRV
DD
1.5 1.7 nsInput clock to output clock delay, t
PDI
Input clock rising edge, zero crossing, to output 4.2 4.8 5.5 nsclock rising edge 50%Data rise time, t
r
Data rise time measured from 20% to 80% of 3.6 4.6 nsDRV
DD
Data fall time, t
f
Data fall time measured from 80% to 20% of 2.8 3.7 nsDRV
DD
Output enable(OE) to data output delay Time required for outputs to have stable timings 1000 Clockwith regard to input clock
(6)
after OE is activated cyclesTime to valid data after coming out of software 1000power down
ClockWake-up time
cyclesTime to valid data after stopping and restarting the 1000clockLatency Time for a sample to propagate to the ADC outputs 17.5 Clock
cycles
(1) Timing parameters are ensured by design and characterization, and not tested in production.(2) See Table 6 through Table 9 in the Application Information section for timing information at additional sampling frequencies.(3) Data valid refers to 2 V for LOGIC HIGH and 0.8 V for LOGIC LOW.(4) See the Output Information section for details on using the input clock for data capture.(5) These specifications apply when the CLKOUT polarity is set to rising edge (according to Table 3 ). Add 1/2 clock period for the validnumber for a falling edge CLKOUT polarity.(6) Data outputs are available within a clock from assertion of OE; however, it takes 1000 clock cycles to ensure stable timing with respectto input clock.
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Input Clock
Analog
Input
Signal
Sample
NN + 1 N + 2 N + 3 N + 4
N + 14 N + 16 N + 17
N + 15
N − 17 N − 16 N − 15 N − 14 N − 13 N − 3 N − 2 N − 1 N
tsu
th
tSTART
tA
tEND
tPDI
Data Out
(D0−D11)
17.5 Clock Cycles
Data Invalid
Output Clock
RESET TIMING CHARACTERISTICS
RESET (Pin 35)
t1 10 ms
t2 2 ms t3 2 msSEN Active
Power Supply
(AVDD, DRVDD)
ADS5520
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A. It is recommended that the loading at CLKOUT and all data lines are accurately matched to ensure that the abovetiming matches closely with the specified values.
Figure 1. Timing Diagram
Typical values given at T
A
= 25 ° C, min and max specified over the full recommended operating temperature range, AV
DD
=DRV
DD
= 3.3 V, and 3-V
PP
differential clock, unless otherwise noted
PARAMETER DESCRIPTION MIN TYP MAX UNIT
Switching Specification
Power-on delay, t
1
Delay from power-on of AVDD and 10 msDRVDD to RESET pulse activeReset pulse width, t
2
Pulse width of active RESET signal 2 µsRegister write delay, t
3
Delay from RESET disable to SEN 2 µsactivePower-up time Delay from power-up of AV
DD
and 40 msDRV
DD
to output stable
Figure 2. Reset Timing Diagram
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SERIAL PROGRAMMING INTERFACE CHARACTERISTICS
A3
ADDRESS
SDATA
MSB
DATA
A2 A1 A0 D11 D10 D9 D0
16 x M
MSB LSB LSBMSB
SCLK
SEN
SDATA
tSLOADS tSLOADH
tSCLK
tWSCLK
tWSCLK
tsu(D) th(D)
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
The ADS5520 has a three-wire serial interface. The ADS5520 latches serial data SDATA on the falling edge ofserial clock SCLK when SEN is active.•Serial shift of bits is enabled when SEN is low. SCLK shifts serial data at the falling edge.•Minimum width of data stream for a valid loading is 16 clocks.•Data is loaded at every 16th SCLK falling edge while SEN is low.•In case the word length exceeds a multiple of 16 bits, the excess bits are ignored.•Data can be loaded in multiples of 16-bit words within a single active SEN pulse.•The first 4-bit nibble is the address of the register while the last 12 bits are the register contents.
Figure 3. DATA Communication is 2-Byte, MSB First
Figure 4. Serial Programming Interface Timing Diagram
Table 2. Serial Programming Interface Timing Characteristics
SYMBOL PARAMETER MIN
(1)
TYP
(1)
MAX
(1)
UNIT
t
SCLK
SCLK period 50 nst
WSCLK
SCLK duty cycle 25% 50% 75%t
SLOADS
SEN to SCLK setup time 8 nst
SLOADH
SCLK to SEN hold time 6 nst
DS
Data setup time 8 nst
DH
Data hold time 6 ns
(1) Typ, min, and max values are characterized, but not production tested.
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VDFS t2
12 AVDD
4
12 AVDD tVDFS t5
12 AVDD
7
12 AVDD tVDFS t8
12 AVDD
VDFS u10
12 AVDD
ADS5520
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Table 3. Serial Register Table
(1)
A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DESCRIPTION
DLL
Clock DLLCTRL
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 Internal DLL is on; recommended for 60 MSPS to 125 MSPSclock speeds.
1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Internal DLL is off; recommended for 2 MSPS to 80 MSPSclock speeds.
TP < 1 > TP < 0 > Test Mode
1 1 1 0 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation
1 1 1 0 0 0 1 0 0 0 0 0 0 0 X 0 All outputs forced to 0
1 1 1 0 0 1 0 0 0 0 0 0 0 0 X 0 All outputs forced to 1
1 1 1 0 0 1 1 0 0 0 0 0 0 0 X 0 Each output bit toggles between 0 and 1.
(2) (3)
PDN Power Down
1 1 1 1 0 0 0 0 0 0 0 0 0 0 X 0 Normal mode of operation
1 1 1 1 1 0 0 0 0 0 0 0 0 0 X 0 Device is put in power-down (low-current) mode.
(1) The register contents default to the appropriate setting for normal operation up on RESET.(2) The patterns given are applicable to the straight offset binary output format. If 2 ' s complement output format is selected, the test modeoutputs will be the binary two ' s complement equivalent of these patterns as described in the Output Information section.(3) While each bit toggles between 1 and 0 in this mode, there is no assured phase relationship between the data bits D0 through D13. Forexample, when D0 is a 1, D1 in not assured to be a 0, and vice versa.
Table 4. Data Format Select (DFS) Table
DFS-PIN VOLTAGE (V
DFS
) DATA FORMAT CLOCK OUTPUT POLARITY
Straight Binary Data valid on rising edge
2's complement Data valid on rising edge
Straight Binary Data valid on falling edge
2's complement Data valid on falling edge
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PIN CONFIGURATION
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
PAP PACKAGE
HTQFP-64
(TOP VIEW)
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ADS5520
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PIN ASSIGNMENTS
(1)
TERMINAL
NO. OFNAME NO. PINS I/O DESCRIPTION
5, 7, 9, 15, 22,AV
DD
24, 26, 28, 33, 12 I Analog power supply34, 37, 396, 8, 12, 13,14, 16, 18, 21,A
GND
14 I Analog ground23, 25, 27, 32,36, 38DRV
DD
49, 58 2 I Output driver power supply1, 42, 48, 50,DR
GND
6 I Output driver ground57, 59NC 44, 45 2 — Not connectedINP 19 1 I Differential analog input (positive)INM 20 1 I Differential analog input (negative)REFP 29 1 O Reference voltage (positive); 1- µ F capacitor in series with a 1- Ωresistor to GNDREFM 30 1 O Reference voltage (negative); 1- µ F capacitor in series with a 1- Ωresistor to GNDIREF 31 1 I Current set; 56-k Ωresistor to GND; do not connect capacitorsCM 17 1 O Common-mode output voltageRESET 35 1 I Reset (active high), Internal 200-k Ωresistor to AV
DD
(2)
OE 41 1 I Output enable (active high)
(3)
DFS 40 1 I Data format and clock out polarity select
(4) (3)
CLKP 10 1 I Data converter differential input clock (positive)CLKM 11 1 I Data converter differential input clock (negative)SEN 4 1 I Serial interface chip select
(3)
SDATA 3 1 I Serial interface data
(3)
SCLK 2 1 I Serial interface clock
(3)
D0 (LSB) to 46, 47, 51-56,
14 O Parallel data outputD11 (MSB) 60-63OVR 64 1 O Over-range indicator bitCLKOUT 43 1 O CMOS clock out in sync with data
(1) PowerPAD is connected to analog ground.(2) If RESET pin is unused, it must be tied to AGND and serial interface should be used to reset the device. See the serial programminginterface section for details.(3) Pins OE, DFS, SEN, SDATA, and SCLK have internal clamping diodes to the DRVDD supply. Any external circuit driving these pinsmust also run off the same supply voltage as DRVDD.(4) Table 4 defines the voltage levels for each mode selectable via the DFS pin.
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DEFINITION OF SPECIFICATIONS
SNR +10Log10 PS
PN
SINAD +10Log10 PS
PN)PD
ENOB +SINAD *1.76
6.02
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
Offset ErrorAnalog Bandwidth
The offset error is the difference, given in number ofThe analog input frequency at which the power of the
LSBs, between the ADC's actual average idlefundamental is reduced by 3 dB with respect to the
channel output code and the ideal average idlelow frequency value.
channel output code. This quantity is often mappedinto mV.Aperture Delay
Temperature DriftThe delay in time between the falling edge of theinput sampling clock and the actual time at which the
The temperature drift coefficient (with respect to gainsampling occurs.
error and offset error) specifies the change perdegree Celsius of the parameter from T
MIN
to T
MAX
. ItAperture Uncertainty (Jitter)
is calculated by dividing the maximum deviation ofThe sample-to-sample variation in aperture delay.
the parameter across the T
MIN
to T
MAX
range by thedifference (T
MAX
– T
MIN
).Clock Pulse Width/Duty Cycle
Signal-to-Noise Ratio (SNR)The duty cycle of a clock signal is the ratio of the timethe clock signal remains at a logic high (clock pulse
SNR is the ratio of the power of the fundamental (P
S
)width) to the period of the clock signal. Duty cycle is
to the noise floor power (P
N
), excluding the power attypically expressed as a percentage. A perfect
dc and the first eight harmonics.differential sine wave clock results in a 50% dutycycle.
Maximum Conversion Rate
SNR is either given in units of dBc (dB to carrier)The maximum sampling rate at which certified
when the absolute power of the fundamental is usedoperation is given. All parametric testing is performed
as the reference or dBFS (dB to Full-Scale) when theat this sampling rate unless otherwise noted.
power of the fundamental is extrapolated to theMinimum Conversion Rate converter's full-scale range.
The minimum sampling rate at which the ADC Signal-to-Noise and Distortion (SINAD)functions.
SINAD is the ratio of the power of the fundamentalDifferential Nonlinearity (DNL) (P
S
) to the power of all the other spectral componentsincluding noise (P
N
) and distortion (P
D
), but excludingAn ideal ADC exhibits code transitions at analog input
dc.values spaced exactly 1LSB apart. The DNL is thedeviation of any single step from this ideal value,measured in units of LSBs.
Integral Nonlinearity (INL)
SINAD is either given in units of dBc (dB to carrier)when the absolute power of the fundamental is usedThe INL is the deviation of the ADC's transfer
as the reference or dBFS (dB to full-scale) when thefunction from a best fit line determined by a least
power of the fundamental is extrapolated to thesquares curve fit of that transfer function, measured
converter's full-scale range.in units of LSBs.
Effective Number of Bits (ENOB)Gain Error
The ENOB is a measure of a converter's performanceThe gain error is the deviation of the ADC's actual
as compared to the theoretical limit based oninput full-scale range from its ideal value. The gain
quantization noise.error is given as a percentage of the ideal inputfull-scale range. Gain error does not account forvariations in the internal reference voltages (see theElectrical Specifications section for limits on thevariation of V
REFP
and V
REFM
).
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PD
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Total Harmonic Distortion (THD) Two-Tone Intermodulation Distortion (IMD3)
THD is the ratio of the power of the fundamental (P
S
) IMD3 is the ratio of the power of the fundamental (atto the power of the first eight harmonics (P
D
). frequencies f
1
and f
2
) to the power of the worstspectral component at either frequency 2f
1
– f
2
or2f
2
– f
1
. IMD3 is either given in units of dBc (dB tocarrier) when the absolute power of the fundamentalis used as the reference, or dBFS (dB to Full-Scale)THD is typically given in units of dBc (dB to carrier).
when the power of the fundamental is extrapolated toSpurious-Free Dynamic Range (SFDR)
the converter's full-scale range.The ratio of the power of the fundamental to the
DC Power Supply Rejection Ration (DC PSRR)highest other spectral component (either spur or
The DC PSSR is the ratio of the change in offsetharmonic). SFDR is typically given in units of dBc (dB
error to a change in analog supply voltage. The DCto carrier).
PSRR is typically given in units of mV/V.
Reference Error
The reference error is the variation of the actualreference voltage (VREFP - VREFM) from its idealvalue. The reference error is typically given as apercentage.
Voltage Overload Recovery Time
The voltage overload recovery time is defined as thetime required for the ADC to recover to within 1% ofthe full-scale range in response to an input voltageoverload of 10% beyond the full-scale range.
14 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5520
TYPICAL CHARACTERISTICS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50
20 40 62.5
SFDR =85.1dBc
THD=82.2dBc
SNR=70.5dBFS
SINAD=70.3dBFS
60
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50 62.5
20 40 60
SFDR =86.0dBc
THD=83.1dBc
SNR=70.8dBFS
SINAD=70.5dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50
20 40 60 62.5
SFDR =85.6dBc
THD=83.0dBc
SNR=70.4dBFS
SINAD=70.2dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50
20 40 60 62.5
SFDR =78.8dBc
THD=78.0dBc
SNR=70.5dBFS
SINAD=69.9dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50
20 40 60 62.5
SFDR =83.7dBc
THD=79.8dBc
SNR=70.2dBFS
SINAD=69.8dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
0 10 30 50
20 40 60 62.5
SFDR =80.6dBc
THD=79.3dBc
SNR=70.4dBFS
SINAD=70.0dBFS
−120
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, sampling rate = 125 MSPS,DLL On, and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 4 MHz Input Signal) (FFT for 16 MHz Input Signal)
Figure 5. Figure 6.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 55 MHz Input Signal) (FFT for 70 MHz Input Signal)
Figure 7. Figure 8.
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 80 MHz Input Signal) (FFT for 100 MHz Input Signal)
Figure 9. Figure 10.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): ADS5520
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50
20 40 60 62.5
SFDR =72.3dBc
THD=70.4dBc
SNR=68.7dBFS
SINAD=66.9dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 50
20 40 62.5
SFDR =75.5dBc
THD=75.0dBc
SNR=69.7dBFS
SINAD=68.8dBFS
60
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 5020 40 60 62.5
SFDR =68.31dBc
THD=66.15dBc
SNR=67.11dBFS
SINAD=64.08dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 5020 40 60 62.5
f1= 10MHz, −7dBFS
f2= 15MHz, −7dBFS
IMD3= −87.5dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 5020 40 60 62.5
f1= 50MHz, −7dBFS
f2= 55MHz, −7dBFS
IMD3= −84.3dBFS
f − Frequency − MHz
Amplitude − dB
0
−20
−40
−60
−80
−100
−120
0 10 30 5020 40 60 62.5
f1= 148MHz, −7dBFS
f2= 153MHz, −7dBFS
IMD3= −86.5dBFS
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, sampling rate = 125 MSPS,DLL On, and 3-V differential clock, unless otherwise noted
SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE(FFT for 150 MHz Input Signal) (FFT for 220 MHz Input Signal)
Figure 11. Figure 12.
SPECTRAL PERFORMANCE TWO-TONE(FFT for 300 MHz Input Signal) INTERMODULATION
Figure 13. Figure 14.
TWO-TONE TWO-TONEINTERMODULATION INTERMODULATION
Figure 15. Figure 16.
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Product Folder Link(s): ADS5520
Code
LSB
0.05
0
−0.05
−0.10
−0.15
−0.20
−0.25
0 512 1024 1536 2048
0.10
0.15
0.20
0.25
2560 3072 3584 4096
fIN =10.1MHz, AIN = −0.5dBFS
Code
LSB
0.25
0
−0.25
−0.50
0 512 1024 1536 2048
0.50
0.75
2560 3072 3584 4096
fIN =10.1MHz
AIN = −0.5dBFS
InputFrequency − MHz
Signal-to-NoiseRatio − dBFS
72
71
70
69
68
67
66
0 50 150 250200100 300
InputFrequency − MHz
SFDR − dBc
90
75
70
65
60
55
50
0 50 150 250
200100
85
80
300
AVDD − AnalogSupplyVoltage − V
SNR − dBFSSFDR − dBc
86
78
76
74
72
70
68
3.00 3.15 3.30 3.60
3.45
82
80
84
SFDR
SNR
fIN =70MHz
AVDD − AnalogSupplyVoltage − V
SNR − dBFSSFDR − dBc
78
74
73
72
71
70
69
3.00 3.15 3.30 3.60
3.45
76
75
77
SFDR
SNR
fIN =150MHz
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, sampling rate = 125 MSPS,DLL On, and 3-V differential clock, unless otherwise noted
DIFFERENTIAL INTEGRALNONLINEARITY NONLINEARITY
Figure 17. Figure 18.
SPURIOUS-FREE DYNAMIC RANGE SIGNAL-TO-NOISE RATIOvs INPUT FREQUENCY vs INPUT FREQUENCY
Figure 19. Figure 20.
AC PERFORMANCE AC PERFORMANCEvs ANALOG SUPPLY VOLTAGE vs ANALOG SUPPLY VOLTAGE
Figure 21. Figure 22.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): ADS5520
DVDD − DigitalSupplyVoltage − V
SNR − dBFSSFDR − dBc
74
73
72
71
70
69
3.00 3.15 3.30 3.60
3.45
76
75
77
SFDR
SNR
fIN =150MHz
DVDD − DigitalSupplyVoltage − V
SNR − dBFSSFDR − dBc
78
76
74
72
70
68
3.00 3.15 3.30 3.60
3.45
82
80
84
SFDR
SNR
fIN =70MHz
SampleRate − MSPS
PowerDissipation − W
0.75
0.7
0.65
0.6
0.55
0.5
10 20 30 12040
0.8
60
fIN =150.1MHz
50 70 80 90 100 110
DLL OFF
DLL ON
SampleRate − MSPS
PowerDissipation − W
0.75
0.7
0.65
0.6
0.55
0.5
10 20 30 12040
0.8
60
fIN =70.1MHz
50 70 80 90 100 110
DLL OFF
DLL ON
Temperature − C
SNR − dBFSSFDR − dBc
85
80
75
70
65
60
−40 −15 10 8535
90
SFDR
SNR
60
fIN =70.1MHz
Input Amplitude − dBFS
ACPerformance − dB
70
50
30
10
−10
−30
−100 −90 −60 0−40
90
−20−80 −70 −50 −30 −10
SNR (dBc)
SNR(dBFS)
SFDR(dBc)
fIN =70.1MHz
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, sampling rate = 125 MSPS,DLL On, and 3-V differential clock, unless otherwise noted
AC PERFORMANCE AC PERFORMANCEvs DIGITAL SUPPLY VOLTAGE vs DIGITAL SUPPLY VOLTAGE
Figure 23. Figure 24.
POWER DISSIPATION POWER DISSIPATIONvs SAMPLE RATE vs SAMPLE RATE
Figure 25. Figure 26.
AC PERFORMANCE AC PERFORMANCEvs TEMPERATURE vs INPUT AMPLITUDE
Figure 27. Figure 28.
18 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5520
Input Amplitude − dBFS
ACPerformance − dB
70
50
30
10
−10
−30
−100 −90 −60 0−40
90
−20−80 −70 −50 −30 −10
SNR (dBFS)
SNR(dBc)
SFDR(dBc)
fIN =150.1MHz
Input Amplitude − dBFS
ACPerformance − dB
70
50
30
10
−10
−30
−100 −90 −60 0−40
90
−20−80 −70 −50 −30 −10
SNR (dBFS)
SFDR(dBc)
SNR(dBc)
fIN =220.1MHz
Code
Percentage − %
60
50
40
30
20
10
0
2052 2053 2054 2055
70
80
90
100
2556 2057 2058
0.179100037
11.01570129
88.80519867
0 0 0 0
DifferentialClock Amplitude − V
SNR − dBFSSFDR − dBc
85
80
75
70
65
60
0 0.5 1 31.5
90
SFDR
SNR
2 2.5
fIN =70.1MHz
f − Frequency − MHz
Amplitude − dB
−40
−60
−80
−100
−120
−140
0 10 20 7030
0
40 60
−20
50
fS=125MSPS
fIN =170MHz
ClockDutyCycle − %
SNR − dBFSSFDR − dBc
85
80
75
70
65
60
40 45 50 55
90
SFDR
SNR
60
fIN =20.1MHz
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, sampling rate = 125 MSPS,DLL On, and 3-V differential clock, unless otherwise noted
AC PERFORMANCE AC PERFORMANCEvs INPUT AMPLITUDE vs INPUT AMPLITUDE
Figure 29. Figure 30.
OUTPUT AC PERFORMANCENOISE HISTOGRAM vs CLOCK AMPLITUDE
Figure 31. Figure 32.
WCDMA AC PERFORMANCECARRIER vs CLOCK DUTY CYCLE
Figure 33. Figure 34.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): ADS5520
TYPICAL CHARACTERISTICS
Input Frequency − MHz
SampleFrequency − MSPS
20 40 60 80 100 120 140 160 180 200 220
60
65
70
75
80
85
90
95
100
105
110
115
120
125
66
66
66
67
67
67
68
69
69
70
70
70
70
69
68
SNR − dBFS
66
67
68
69
70
Input Frequency − MHz
SampleFrequency − MSPS
20 40 60 80 100 120 140 160 180 200 220
60
65
70
75
80
85
90
95
100
105
110
115
120
125
SNR −dBFS
65
66
66
66
67 67
67
67
67
68
68 68
68
68
69 69
69
69
70
70
70
65
66
67
69
64
64
68
70
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,unless otherwise noted
SIGNAL-TO-NOISE RATIO (SNR)(DLL On)
Figure 35.
SIGNAL-TO-NOISE RATIO (SNR)(DLL Off)
Figure 36.
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Product Folder Link(s): ADS5520
Input Frequency − MHz
SampleFrequency − MSPS
20 40 60 80 100 120 140 160 180 200 220
60
65
70
75
80
85
90
95
100
105
110
115
120
125
SFDR − dBc
72
74
76
78
80
82
84
86
88
74
74
47
76
76
76
76
78
78
78
78
80
80
80
80
82
82
82
82
82
82
82
84
84
84
84
84
84
84
84
8
84
6
86
86
88
86
86
82 82
84
84
86
84
84
88
86
Input Frequency − MHz
SampleFrequency − MSPS
20 40 60 80 100 120 140 160 180 200 220
60
65
70
75
80
85
90
95
100
105
110
115
120
125
SFDR − dBc
70
80
90
100
110
120
74
74
74
76 76
76
76
76
78
78
78
78
80
80
80
80
82
82
82
82
82
84
84
84
84
84
84
86
86 86
86
84
88
78
84
72
72
74
76
78
80
82
84
86
88
88
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
TYPICAL CHARACTERISTICS (continued)Typical values given at T
A
= 25 ° C, AV
DD
= DRV
DD
= 3.3 V, differential input amplitude = -1dBFS, and 3-V differential clock,unless otherwise noted
SPURIOUS-FREE DYNAMIC RANGE (SFDR)(DLL On)
Figure 37.
SPURIOUS-FREE DYNAMIC RANGE (SFDR)(DLL Off)
Figure 38.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): ADS5520
APPLICATION INFORMATION
THEORY OF OPERATION
INPUT CONFIGURATION
R3
R1a
L1
L2R1b
C1a
C1b
CA
CP1CP3
VINCM
1V
CP4
CP2
INP
INM
S3a
S3b
S2
S1a
S1b
L1, L2: 6 nH − 10 nH effective
R1a, R1b: 5W − 8W
C1a, C1b: 2.2 pF − 2.6 pF
CP1, CP2: 2.5 pF − 3.5 pF
CP3, CP4: 1.2 pF − 1.8 pF
CA: 0.8 pF − 1.2 pF
R3: 80 W − 120 W
Swithches: S1a, S1b: On Resistance: 35 W − 50 W
S2: On Resistance: 7.5 W − 15 W
S3a, S3b: On Resistance: 40 W − 60 W
All switches OFF Resistance: 10 GW
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
The ADS5520 is a low-power, 12-Bit, 125 MSPS, CMOS, switched capacitor, pipeline ADC that operates from asingle 3.3-V supply. The conversion process is initiated by a falling edge of the external input clock. Once thesignal is captured by the input S & H, the input sample is sequentially converted by a series of small resolutionstages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock edgesare used to propagate the sample through the pipeline every half clock cycle. This process results in a datalatency of 17.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in eitherstraight offset binary or binary 2's complement format.
The analog input for the ADS5520 consists of a differential sample-and-hold architecture implemented using theswitched capacitor technique shown in Figure 39 .
A. All Switches are ON in sampling phase which is approximately one half of a clock period.
Figure 39. Analog Input Stage
22 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5520
R0
50ΩZ0
50Ω
1:1 INP
INM CM
ADT1−1WT
R
50Ω
1nF 0.1µF
AC Signal
Source
10Ω
25Ω
25Ω
ADS5520
600mA fS(in MSPS)
125 MSPS
(1)
ADS5520
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....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
This differential input topology produces a high level of ac-performance for high sampling rates. It also results ina very high usable input bandwidth, especially important for high intermediate-frequency (IF) or undersamplingapplications. The ADS5520 requires each of the analog inputs (INP, INM) to be externally biased around thecommon-mode level of the internal circuitry (CM, pin 17). For a full-scale differential input, each of the differentiallines of the input signal (pins 19 and 20) swings symmetrically between CM + 0.575 V and CM – 0.575 V. Thismeans that each input is driven with a signal of up to CM ± 0.575 V, so that each input has a maximumdifferential signal of 1.15 V
PP
for a total differential input signal swing of 2.3 V
PP
. The maximum swing isdetermined by the two reference voltages, the top reference (REFP, pin 29), and the bottom reference (REFM,pin 30).
The ADS5520 obtains optimum performance when the analog inputs are driven differentially. The circuit shownin Figure 40 illustrates one possible configuration using an RF transformer.
Figure 40. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Placing a 25- Ωresistor in series withINP and INM is recommended to dampen ringing due to ADC kickback.
Since the input signal must be biased around the common-mode voltage of the internal circuitry, thecommon-mode voltage (V
CM
) from the ADS5520 is connected to the center-tap of the secondary winding.
To ensure a steady low-noise V
CM
reference, best performance is attained when the CM output (pin 17) is filteredto ground with a 10- Ωseries resistor and parallel 0.1- µF and 0.001- µF low-inductance capacitors, as illustrated inFigure 39 .
Output V
CM
(pin 17) is designed to directly drive the ADC input. When providing a custom CM level, be awarethat the input structure of the ADC sinks a common-mode current in the order of 600 µA (300 µA per input).Equation 1 describes the dependency of the common-mode current and the sampling frequency:
Where:
f
S
> 2MSPS.
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combinesingle-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier without atransformer, to drive the input of the ADS5520. Texas Instruments offers a wide selection of single-endedoperational amplifiers (including the THS3201, THS3202, OPA695, and OPA847) that can be selecteddepending on the application. An RF gain block amplifier, such as Texas Instruments THS9001, can also beused with an RF transformer for high input frequency applications. The THS4503 is a recommended differentialinput/output amplifier. Table 5 lists the recommended amplifiers.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): ADS5520
RIN
RIN CIN
0.1µF
RT
100Ω
0.1µF
1000pF
1:1
RS
100Ω
OPA695
R1
400Ω
AV= 8V/V
(18dB)
R2
57.5Ω
VIN INP
INM CM
−5V+5V
10Ω
ADS5520
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
Table 5. Recommended Amplifiers to Drive the Input of the ADS5520
INPUT SIGNAL FREQUENCY RECOMMENDED AMPLIFIER TYPE OF AMPLIFIER USE WITH TRANSFORMER?
DC to 20 MHz THS4503 Differential In/Out Amp NoDC to 50 MHz OPA847 Operational Amp YesDC to 100 MHz THS4509 Differential In/Out Amp NoOPA695 Operational Amp Yes10 MHz to 120 MHz THS3201 Operational Amp YesTHS3202 Operational Amp YesOver 100 MHz THS9001 RF Gain Block Yes
When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA695, or OPA847) toprovide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF transformerand one amplifier in each of the legs of the secondary driving the two differential inputs of the ADS5520. Thesethree amplifier circuits minimize even-order harmonics. For high frequency inputs, an RF gain block amplifier canbe used to drive a transformer primary; in this case, the transformer secondary connections can drive the input ofthe ADS5520 directly, as shown in Figure 40 , or with the addition of the filter circuit shown in Figure 41 .
Figure 41 illustrates how R
IN
and C
IN
can be placed to isolate the signal source from the switching inputs of theADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended that thesecomponents be included in the ADS5520 circuit layout when any of the amplifier circuits discussed previously areused. The components allow fine-tuning of the circuit performance. Any mismatch between the differential linesof the ADS5520 input produces a degradation in performance at high input frequencies, mainly characterized byan increase in the even-order harmonics. In this case, special care should be taken to keep as much electricalsymmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers thatcan simplify the driver circuit for applications requiring dc-coupling of the input. Flexible in their configurations(see Figure 42 ), such amplifiers can be used for single-ended-to-differential conversion signal amplification.
Figure 41. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
24 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5520
RF
RG
VOCM INP
INM CM
RF
RG
RS
0.1mF
0.1mF
10mF
1mF
RT
+3.3V
+5V
0.1mF10mF
-5V
THS4503
RIN
RIN
10 W
ADS5520
12-Bit / 125MSPS
POWER-SUPPLY SEQUENCE
AVDD
REFP
29
28
2 kW
1 W
1 mF
POWER-DOWN
REFERENCE CIRCUIT
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
Figure 42. Using the THS4503 with the ADS5520
The preferred power-up sequence is to ramp AV
DD
first, followed by DRV
DD
, including a simultaneous ramp ofAV
DD
and DRV
DD
. In the event that DRV
DD
ramps up first in the system, care must be taken to ensure that AV
DDramps up within 10 ms. Optionally, it is recommended to put a 2-k Ωresistor from REFP (pin 29) to AVDD asshown in Figure 43 . This helps to make the device more robust to power supply ramp-up timings.
Figure 43.
The device enters power-down in one of two ways: either by reducing the clock speed or by setting the PDN bitthrough the serial programming interface. Using the reduced clock speed, power-down may be initiated for clockfrequency below 2 MSPS. The exact frequency at which the power down occurs varies from device to device.
Using the serial interface PDN bit to power down the device places the outputs in a high-impedance state andonly the internal reference remains on to reduce the power-up time. The power-down mode reduces powerdissipation to approximately 180 mW.
The ADS5520 has built-in internal reference generation, requiring no external circuitry on the printed circuit board(PCB). For optimum performance, it is best to connect both REFP and REFM to ground with a 1- µF decouplingcapacitor (the 1- Ωresistor shown in Figure 44 is optional). In addition, an external 56.2-k Ωresistor should beconnected from IREF (pin 31) to AGND to set the proper current for the operation of the ADC, as shown inFigure 44 . No capacitor should be connected between pin 31 and ground; only the 56.2-k Ωresistor should beused.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Link(s): ADS5520
29
30
31
REFP
REFM
IREF
1 W
1 W
56.2 kW
1 mF
1 mF
CLOCK INPUT
5 kW5 kW
3 pF 3 pF
6 pF
CLKP CLKM
CM CM
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
Figure 44. REFP, REFM, and IREF Connections for Optimum Performance
The ADS5520 clock input can be driven with either a differential clock signal or a single-ended clock input, withlittle or no difference in performance between both configurations. The common-mode voltage of the clock inputsis set internally to CM (pin 17) using internal 5-k Ωresistors that connect CLKP (pin 10) and CLKM (pin 11) to CM(pin 17), as shown in Figure 45 .
Figure 45. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect CLKM (pin 11) to ground with a 0.01- µFcapacitor, while CLKP is ac-coupled with a 0.01- µF capacitor to the clock source, as shown in Figure 46 .
26 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5520
0.01µF
0.01µF
CLKP
CLKM
Square Wave
or Sine Wave
(3VPP)
ADS5520
0.01µFCLKP
CLKM
0.01µF
Differential Square Wave
or Sine Wave
(3VPP)ADS5520
100
95
90
85
80
75
70
65
60
Clock Duty Cycle −%
35 40 5045 55 6560
SFDR
SNR
SFDR −dBcSNR −dBFS
fIN = 20MHz
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
Figure 46. AC-Coupled, Single-Ended Clock Input
The ADS5520 clock input can also be driven differentially, reducing susceptibility to common-mode noise. In thiscase, it is best to connect both clock inputs to the differential input clock signal with 0.01- µF capacitors, as shownin Figure 47 .
Figure 47. AC-Coupled, Differential Clock Input
For high input frequency sampling, it is recommended to use a clock source with low jitter. Additionally, theinternal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a 50% dutycycle should be provided. Figure 48 shows the performance variation of the ADC versus clock duty cycle.
Figure 48. AC Performance vs Clock Duty Cycle
Bandpass filtering of the source can help produce a 50% duty cycle clock and reduce the effect of jitter. Whenusing a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that sense, using adifferential clock allows for the use of larger amplitudes without exceeding the supply rails and absolutemaximum ratings of the ADC clock input. Figure 49 shows the performance variation of the device versus inputclock amplitude. For detailed clocking schemes based on transformer or PECL-level clocks, see theADS55xxEVM User's Guide (SLWU010 ), available for download from www.ti.com.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): ADS5520
95
90
85
80
75
70
65
60
Differential Clock Amplitude −V
0 0.5 1.0 1.5 2.0 2.5 3.0
fIN = 70MHz
SFDR
SNR
SFDR −dBcSNR −dBFS
INTERNAL DLL
OUTPUT INFORMATION
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
Figure 49. AC Performance vs Clock Amplitude
In order to obtain the fastest sampling rates achievable with the ADS5520, the device uses an internal digitaldelay lock loop (DLL). Nevertheless, the limited frequency range of operation of DLL degrades the performanceat clock frequencies below 60 MSPS. In order to operate the device below 60 MSPS, the internal DLL must beshut off using the DLL OFF mode described in the Serial Interface Programming section. The TypicalPerformance Curves show the performance obtained in both modes of operation: DLL ON (default) and DLLOFF. In either of the two modes, the device enters power-down mode if no clock or slow clock is provided. Thelimit of the clock frequency where the device functions properly with default settings is ensured to be over 2 MHz.
The ADC provides 12 data outputs (D11 to D0, with D11 being the MSB and D0 the LSB), a data-ready signal(CLKOUT, pin 43), and an out-of-range indicator (OVR, pin 64) that equals 1 when the output reaches thefull-scale limits.
Two different output formats (straight offset binary or 2's complement) and two different output clock polarities(latching output data on rising or falling edge of the output clock) can be selected by setting DFS (pin 40) to oneof four different voltages. Table 4 details the four modes. In addition, output enable control (OE, pin 41, activehigh) is provided to put the outputs into a high-impedance state.
In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level. For a positiveoverdrive, the output code is 0xFFF in straight offset binary output format and 0x7FF in 2's complement outputformat. For a negative input overdrive, the output code is 0x000 in straight offset binary output format and 0x800in 2's complement output format. These outputs to an overdrive signal are ensured through design andcharacterization.
The output circuitry of the ADS5520, by design, minimizes the noise produced by the data switching transients,and, in particular, its coupling to the ADC analog circuitry. Output D4 (pin 51) senses the load capacitance andadjusts the drive capability of all the output pins of the ADC to maintain the same output slew rate described inthe timing diagram of Figure 1 . Care should be taken to ensure that all output lines (including CLKOUT) havenearly the same load as D4 (pin 51). This circuit also reduces the sensitivity of the output timing versus supplyvoltage or temperature. Placing external resistors in series with the outputs is not recommended.
The timing characteristics of the digital outputs change for sampling rates below the 125 MSPS maximumsampling frequency. Table 6 and Table 7 show the setup, hold, input clock to output data delays, and rise andfall times for different sampling frequencies with the DLL on and off, respectively.
Table 8 and Table 9 show the rise and fall times at additional sampling frequencies with DLL on and off,respectively.
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Product Folder Link(s): ADS5520
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
To use the input clock as the data capture clock, it is necessary to delay the input clock by a delay, t
d
, thatresults in the desired setup or hold time. Use either of the following equations to calculate the value of t
d
.
Desired setup time = t
d
– t
START
Desired hold time = t
END
– t
d
Table 6. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
Data Rise time t
r
Data Fall time t
ft
SETUP
(ns) t
HOLD
(ns) t
START
(ns) t
END
(ns)f
S
(ns) (ns)(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
105 2.4 3.1 2.2 2.6 1.7 2.6 5.8 7.3 4.4 5.1 3.3 3.880 3.3 4.1 3 3.4 0.3 1.5 5.3 8 5.8 6.6 4.4 5.365 4.1 5 3.7 4.2 -0.8 0.4 5.3 8.7 6.7 7.2 5.5 6.4
Table 7. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
Data Rise time t
r
Data Fall time t
ft
SETUP
(ns) t
HOLD
(ns) t
START
(ns) t
END
(ns)f
S
(ns) (ns)(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80 3.6 4.7 1.8 3.1 3.3 4.7 8.2 11.1 5.6 6.1 4.4 5.165 4.7 6 2.1 3.1 2.4 4.2 8.3 12 6.6 7.2 5.5 6.440 8.5 11 2.8 3.5 -1 1.5 8.9 14.5 7.5 8 7.3 7.820 17 25.7 2.5 4.7 -9.8 2 9.5 21.6 7.5 8 7.6 810 27 51 4 6.5 -30 -3 11.5 312 284 370 4 13 185 320 515 576 50 82 75 150
Table 8. Timing Characteristics at Additional Sampling Frequencies (DLL ON)
CLKOUT Jitter,CLKOUT Rise Time CLKOUT Fall Time Input-to-Output Clock DelayPeak-to-Peakf
S
t
r
(ns) t
f
(ns) t
PDI
(ns)t
JIT
(ps)(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
105 2 2.2 1.7 1.8 175 250 4 4.7 5.580 2.5 2.8 2.1 2.3 210 315 3.7 4.3 5.165 3.1 3.5 2.6 2.9 260 380 3.5 4.1 4.8
Table 9. Timing Characteristics at Additional Sampling Frequencies (DLL OFF)
CLKOUT Jitter,CLKOUT Rise Time CLKOUT Fall Time Input-to-Output Clock DelayPeak-to-Peakf
S
t
r
(ns) t
f
(ns) t
PDI
(ns)t
JIT
(ps)(MSPS)
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX
80 2.5 2.8 2.1 2.3 210 315 7.1 8 8.965 3.1 3.5 2.6 2.9 260 380 7.8 8.5 9.440 4.8 5.3 4 4.4 445 650 9.5 10.4 11.420 8.3 9.5 7.6 8.2 800 1200 13 15.5 1810 16 20.7 25.52 31 52 36 65 2610 4400 537 551 567
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): ADS5520
SERIAL PROGRAMMING INTERFACE
PowerPAD PACKAGE
Assembly Process
ADS5520
SBAS310F – MAY 2004 – REVISED OCTOBER 2008 .......................................................................................................................................................
www.ti.com
The ADS5520 has internal registers for the programming of some of the modes described in the previoussections. The registers should be reset after power-up by applying a 2 µs (minimum) high pulse on RESET (pin35); this also resets the entire ADC and sets the data outputs to low. This pin has a 200-k Ωinternal pullupresistor to AVDD. The programming is done through a three-wire interface. The timing diagram and serialregister setting in the Serial Programing Interface section describe the programming of this register.
Table 3 shows the different modes and the bit values to be written to the register to enable them.
Note that some of these modes may modify the standard operation of the device and possibly vary theperformance with respect to the typical data shown in this data sheet.
Applying a RESET signal is absolutely essential to set the internal registers to their default states for normaloperation. If the hardware RESET function is not used in the system, the RESET pin must be tied to ground andit is necessary to write the default values to the internal registers through the serial programming interface. Theregisters must be written in the following order.Write 9000h (Address 9, Data 000)Write A000h (Address A, Data 000)Write B000h (Address B, Data 000)Write C000h (Address C, Data 000)Write D000h (Address D, Data 000)Write E000h (Address E, Data 804)Write 0000h (Address 0, Data 000)Write 1000h (Address 1, Data 000)Write F000h (Address F, Data 000)
NOTE:
This procedure is only required if a RESET pulse is not provided to the device.
The PowerPAD package is a thermally enhanced standard size IC package designed to eliminate the use ofbulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted usingstandard printed circuit board (PCB) assembly techniques and can be removed and replaced using standardrepair procedures.
The PowerPAD package is designed so that the lead frame die pad (or thermal pad) is exposed on the bottom ofthe IC. This provides a low thermal resistance path between the die and the exterior of the package. The thermalpad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using the PCB as aheatsink.
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated inthe Mechanical Data section. The recommended thermal pad dimension is 8 mm x 8 mm.2. Place a 5-by-5 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. Thesmall size prevents wicking of the solder through the holes.3. It is recommended to place a small number of 25 mil diameter holes under the package, but outside thethermal pad area to provide an additional heat path.4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as aground plane).5. Do not use the typical web or spoke via connection pattern when connecting the thermal vias to the groundplane. The spoke pattern increases the thermal resistance to the ground plane.6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
30 Submit Documentation Feedback Copyright © 2004 – 2008, Texas Instruments Incorporated
Product Folder Link(s): ADS5520
ADS5520
www.ti.com
....................................................................................................................................................... SBAS310F – MAY 2004 – REVISED OCTOBER 2008
For more detailed information regarding the PowerPAD package and its thermal properties, see either theapplication brief SLMA004B (PowerPAD Made Easy) or technical brief SLMA002 (PowerPAD ThermallyEnhanced Package).
Table 10. Revision History
Added notes regarding the input voltage overstress requirements.Changed minimum recommended sampling rate to 2 MSPS.Clarified the Electrical Characteristics measurement conditions.Changed power dissipation reporting to separate analog and digital power dissipation.Clarified the Digital Characteristics measurement conditions.Added timing parameters - output clock jitter, wakeup time, output clock rise and fall time, T
pdi
and timings across Fs.Clarified the Timing Characteristics measurement conditions.Clarified output capture test modes.Pin table info added - RESET pin, note on OE, SEN, SDATA and SCLK pinsUpdated the definitions section.Clarified measurement conditions for the specifications plots.Updated Equation 1 to match the new definition of common −mode input current and minimum sample rate.Removed the input voltage stress section - notes added in absolute max tableUpdated the Power Down section to reflect the newly specified 2 MSPS minimum sampling rate.Text in internal DLL section added about 2 MSPSNote on mandatory RESET added
Rev D
Added min/max spec for Offset error and Gain error
Rev F
Output Information Section, p. 28.Changed - From: binary output format and 0x4FFF To: binary output format and 0x7FF.Changed From: binary output format and 0x2000 To: binary output format and 0x800.
Copyright © 2004 – 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): ADS5520
PACKAGE OPTION ADDENDUM
www.ti.com 21-May-2010
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
ADS5520IPAP ACTIVE HTQFP PAP 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5520IPAPG4 ACTIVE HTQFP PAP 64 160 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5520IPAPR ACTIVE HTQFP PAP 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
ADS5520IPAPRG4 ACTIVE HTQFP PAP 64 1000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ADS5520IPAPR HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ADS5520IPAPR HTQFP PAP 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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