www.fairchildsemi.com LMV321, LMV358, LMV324 General Purpose, Low Voltage, Rail-to-Rail Output Amplifiers Features at +2.7V Description * * * * * * The LMV321 (single), LMV358 (dual), and LMV324 (quad) are a low cost, voltage feedback amplifiers that consume only 80A of supply current per amplifier. The LMV3XX family is designed to operate from 2.7V (1.35V) to 5.5V (2.75V) supplies. The common mode voltage range extends below the negative rail and the output provides rail-to-rail performance. * * * * 80A supply current per channel 1.2MHz gain bandwidth product Output voltage range: 0.01V to 2.69V Input voltage range: -0.25V to +1.5V 1.5V/s slew rate LMV321 directly replaces other industry standard LMV321 amplifiers; available in SC70-5 and SOT23-5 packages LMV358 directly replaces other industry standard LMV358 amplifiers; available in MSOP-8 and SOIC-8 packages LMV324 directly replaces other industry standard LMV324 amplifiers; available in TSSOP-14 and SOIC-14 packages Fully specified at +2.7V and +5V supplies Operating temperature range: -40C to +125C The LMV3XX family is designed on a CMOS process and provides 1.2MHz of bandwidth and 1.5V/s of slew rate at a low supply voltage of 2.7V. The combination of low power, rail-to-rail performance, low voltage operation, and tiny package options make the LMV3XX family well suited for use in personal electronics equipment such as cellular handsets, pagers, PDAs, and other battery powered applications. Applications Low cost general purpose applications Cellular phones Personal data assistants A/D buffer DSP interface Smart card readers Portable test instruments Keyless entry Infrared receivers for remote controls Telephone systems Audio applications Digital still cameras Hard disk drives MP3 players CL = 200pF Rs = 0 Magnitude (1dB/div) * * * * * * * * * * * * * * Frequency Response vs. CL CL = 50pF Rs = 0 + CL = 200pF Rs = 225 CL = 100pF Rs = 0 CL = 10pF Rs = 0 CL = 20pF Rs = 0 CL = 2pF Rs = 0 Rs - CL 10k 2k 10k 0.01 0.1 1 10 Frequency (MHz) Typical Application +Vs 6.8F + +In + 0.01F Out LMV3XX - Rf Rg REV. 1B. March. 2009 DATA SHEET LMV321/LMV358/LMV324 Pin Assignments LMV321 SC70-5 SOT23-5 +In 1 -Vs 2 -In 3 5 +Vs +In 1 -Vs 2 -In 3 + 5 +Vs 4 Out 8 +Vs 7 Out2 6 -In2 5 +In2 + - 4 Out - LMV358 MSOP-8 SOIC-8 Out1 1 -In1 2 +In1 3 -Vs 4 + + 8 +Vs Out1 1 7 Out2 -In1 2 6 -In2 +In1 3 5 +In2 -Vs 4 + + LMV324 TSSOP-14 +In1 3 +Vs 4 +In2 5 - - + + + - 2 -In2 6 Out2 7 - 2 + -In1 14 Out4 Out1 1 13 -In4 -In1 2 12 +In4 +In1 3 11 -Vs +Vs 4 10 +In3 +In2 5 14 Out4 - - + + + - 9 -In3 -In2 6 8 Out3 Out2 7 13 -In4 12 +In4 11 -Vs - 1 + Out1 SOIC-14 10 +In3 9 -In3 8 Out3 REV.1B. March. 2009 LMV321/LMV358/LMV324 DATA SHEET Absolute Maximum Ratings Parameter Supply Voltages Maximum Junction Temperature Storage Temperature Range Lead Temperature, 10 seconds Input Voltage Range Min. 0 - -65 - -Vs -0.5 Max. +6 +175 +150 +260 +Vs +0.5 Unit V C C C V Min. -40 2.5 Max. +125 5.5 Unit C V Recommended Operating Conditions Parameter Operating Temperature Range Power Supply Operating Range Electrical Specifications (Tc = 25C, Vs = +2.7V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted) Parameter AC Performance Gain Bandwidth Product Phase Margin Gain Margin Slew Rate Input Voltage Noise Crosstalk: LMV358 LMV324 DC Performance Input Offset Voltage1 Average Drift Input Bias Current2 Input Offset Current2 Power Supply Rejection Ratio1 Supply Current (Per Channel)1 Input Characteristics Input Common Mode Voltage Range1 Common Mode Rejection Ratio1 Output Characteristics Output Voltage Swing Conditions Min. CL = 50pF, RL = 2k to Vs/2 LO HI 50 0 50 RL = 10k to Vs/2; LO1 RL = 10k to Vs/2; HI1 Max. 1.2 52 17 1.5 36 91 80 Vo = 1Vpp >50kHz 100kHz 100kHz DC Typ. 0.1 1.7 8 <1 <1 65 80 -0.25 1.5 70 0.01 2.69 Unit MHz deg dB V/s nV/Hz dB dB 7 120 1.3 2.6 mV V/C nA nA dB A V V dB V V Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes: 1. Guaranteed by testing or statistical analysis at +25C. 2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure. REV.1B. March. 2009 3 DATA SHEET LMV321/LMV358/LMV324 Electrical Specifications (Tc = 25C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted) Parameter AC Performance Gain Bandwidth Product Phase Margin Gain Margin Slew Rate Input Voltage Noise Crosstalk: LMV358 LMV324 DC Performance Input Offset Voltage1 Average Drift Input Bias Current2 Input Offset Current2 Power Supply Rejection Ratio1 Open Loop Gain1 Supply Current (Per Channel)1 Input Characteristics Input Common Mode Voltage Range1 Common Mode Rejection Ratio1 Output Characteristics Output Voltage Swing Short Circuit Output Current1 Conditions Min. CL = 50pF, RL = 2k to Vs/2 LO HI 50 50 0 50 RL = 2k to Vs/2; LO/HI RL = 10k to Vs/2; LO1 RL = 10k to Vs/2; HI1 sourcing; Vo = 0V sinking; Vo = 5V Max. Unit 1.4 73 12 1.5 33 91 80 >50kHz 100kHz 100kHz DC Typ. 0.1 5 10 1 6 <1 <1 65 70 100 -0.4 3.8 75 0.036 to 4.95 0.013 4.98 +34 -23 MHz deg dB V/s nV/Hz dB dB 7 mV V/C nA nA dB dB A 150 3.6 V V dB 4.9 V V V mA mA Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes: 1. Guaranteed by testing or statistical analysis at +25C. 2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure. Package Thermal Resistance Package 5 lead SC70 5 lead SOT23 8 lead SOIC 8 lead MSOP 14 lead TSSOP 14 lead SOIC 4 JA 331.4C/W 256C/W 152C/W 206C/W 100C/W 88C/W REV.1B. March. 2009 LMV321/LMV358/LMV324 DATA SHEET Typical Operating Characteristics (Tc = 25C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted) G=2 Inverting Frequency Response Vs = +5V Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) Non-Inverting Freq. Response Vs = +5V G=1 G = 10 G=5 0.01 0.1 1 10 G = -2 G = -1 G = -10 G = -5 0.01 0.1 Frequency (MHz) Normalized Magnitude (1dB/div) Normalized Magnitude (1dB/div) G=1 G=2 G = 10 G=5 0.1 1 G = -1 G = -2 G = -10 G = -5 0.01 10 0.1 1 Frequency (MHz) Frequency (MHz) Frequency Response vs. CL Frequency Response vs. RL CL = 50pF Rs = 0 + CL = 200pF Rs = 225 CL = 100pF Rs = 0 CL = 10pF Rs = 0 CL = 20pF Rs = 0 CL = 2pF Rs = 0 Rs - CL 10k Magnitude (1dB/div) Magnitude (1dB/div) CL = 200pF Rs = 0 10 Inverting Freq. Response Vs = +2.7V Non-Inverting Freq. Response Vs = +2.7V 0.01 1 Frequency (MHz) 2k 10 RL = 100k RL = 1k RL = 10k RL = 2k 10k 0.01 0.1 1 10 0.01 0.1 Frequency (MHz) 2.5 0.2 2 0.15 1.5 Output (V) Output (V) 10 Large Signal Pulse Response Small Signal Pulse Response 0.25 0.1 0.05 0.1 0.5 0 0 -0.5 -0.05 0 2 4 6 8 10 12 Time (s) REV. 1B. March. 2009 1 Frequency (MHz) 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 Time (s) 5 DATA SHEET LMV321/LMV358/LMV324 Typical Operating Characteristics (Tc = 25C, Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 10k, Vo (DC) = Vcc/2; unless otherwise noted) Input Voltage Noise Total Harmonic Distortion 100 0.6 80 0.5 Vo = 1Vpp 0.4 THD (%) nV/Hz 70 60 50 0.3 0.2 40 0.1 30 20 0 1 10 100 0.1 1000 Frequency (kHz) 1 10 100 Frequency (kHz) Open Loop Gain & Phase vs. Frequency 100 RL = 2k CL = 50pF -45 80 Phase -90 60 -135 40 |Gain| -180 20 -225 0 -270 Open Loop Gain (dB) Open Loop Phase (deg) 0 -20 10 100 1k 10k 100k 1M 10M Frequency (Hz) 6 REV.1B. March. 2009 LMV321/LMV358/LMV324 DATA SHEET Application Information + General Description The LMV3XX family are single supply, general purpose, voltage-feedback amplifiers that are pin-for-pin compatible and drop in replacements with other industry standard LMV321, LMV358, and LMV324 amplifiers. The LMV3XX family is fabricated on a CMOS process, features a rail-to-rail output, and is unity gain stable. The typical non-inverting circuit schematic is shown in Figure +Vs - Figure 2: Typical Topology for driving a capacitive load Out LMV3XX - Rf Rg Magnitude (dB) + 2k 10k + 0.01F CL 10k 6.8F +In Rs LMV3XX 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 CL = 50pF Rs = 0 CL = 100pF Rs = 400 CL = 200pF Rs = 450 0.01 0.1 1 10 Frequency (MHz ) 1. Figure 1: Typical Non-inverting configuration Power Dissipation The maximum internal power dissipation allowed is directly related to the maximum junction temperature. If the maximum junction temperature exceeds 150C, some performance degradation will occur. If the maximum junction temperature exceeds 175C for an extended time, device failure may occur. Driving Capacitive Loads The Frequency Response vs CL plot on page 4, illustrates the response of the LMV3XX family. A small series resistance (Rs) at the output of the amplifier, illustrated in Figure 2, will improve stability and settling performance. Rs values in the Frequency Response vs CL plot were chosen to achieve maximum bandwidth with less than 1dB of peaking. For maximum flatness, use a larger Rs. As the plot indicates, the LMV3XX family can easily drive a 200pF capacitive load without a series resistance. For comparison, the plot also shows the LMV321 driving a 200pF load with a 225 series resistance. Figure 3: Frequency Response vs CL for unity gain configuration Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.01F ceramic capacitors * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.01F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts shown in Figure 5 on page 8 for more information. Driving a capacitive load introduces phase-lag into the output signal, which reduces phase margin in the amplifier. The unity gain follower is the most sensitive configuration. In a unity gain follower configuration, the LMV3XX family requires a 450 series resistor to drive a 200pF load. The response is illustrated in Figure 3. REV.1B. March. 2009 7 DATA SHEET LMV321/LMV358/LMV324 Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Eval Bd Description KEB013 Single Channel, Dual Supply, SOT23-5 for buffer-style pinout LMV321AS5X KEB014 Single Channel, Dual Supply, SC70-5 for buffer-style pinout LMV321AP5X KEB006 Dual Channel, Dual Supply, 8 lead SOIC LMV358AM8X KEB010 Dual Channel, Dual Supply, 8 lead MSOP LMV358AMU8X KEB012 Quad Channel, Dual Supply, 14 lead TSSOP LMV324AMTC14X KEB018 Quad Channel, Dual Supply, 14 lead SOIC LMV324AM14X Evaluation board schematics and layouts are shown in Figures 4 and 5. Products Evaluation Board Schematic Diagrams Figure 4a: LMV321 KEB013 schematic 8 Figure 4b: LMV321 KEB014 schematic REV.1B. March. 2009 LMV321/LMV358/LMV324 DATA SHEET Evaluation Board Schematic Diagrams (Continued) Figure 4c: LMV358 KEB006/KEB010 schematic Figure 4d: LMV324 KEB012/KEB018 schematic REV.1B. March. 2009 9 DATA SHEET LMV321/LMV358/LMV324 LMV321 Evaluation Board Layout 10 Figure 5a: KEB013 (top side) Figure 5b: KEB013 (bottom side) Figure 5c: KEB014 (top side) Figure 5d: KEB014 (bottom side) REV.1B. March. 2009 LMV321/LMV358/LMV324 DATA SHEET LMV358 Evaluation Board Layout Figure 5e: KEB006 (top side) Figure 5f: KEB006 (bottom side) Figure 5g: KEB010 (top side) Figure 5h: KEB010 (bottom side) REV.1B. March. 2009 11 DATA SHEET LMV321/LMV358/LMV324 LMV324 Evaluation Board Layout 12 Figure 5i: KEB012 (top side) Figure 5j: KEB012 (bottom side) Figure 5k: KEB018 (top side) Figure 5l: KEB018 (bottom side) REV.1B. March. 2009 LMV321/LMV358/LMV324 DATA SHEET b SOT23-5 CL DATUM 'A' LMV321 Package Dimensions e 2 CL CL E e1 C D CL A CL e L CL CL HE E Q1 CL REV.1B. March. 2009 A2 SYMBOL e D b E HE Q1 A2 A1 A c L MIN MAX 0.65 BSC 1.80 2.20 0.15 0.30 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 1.10 0.30 C D A MAX 1.45 0.15 1.30 0.50 0.20 3.10 3.00 1.75 0.55 0.95 ref 1.90 ref 0 10 1. All dimensions are in millimeters. 2 Foot length measured reference to flat foot surface parallel to DATUM 'A' and lead surface. 3. Package outline exclusive of mold flash & metal burr. 4. Package outline inclusive of solder plating. 5. Comply to EIAJ SC74A. 6. Package ST 0003 REV A supercedes SOT-D-2005 REV C. A1 b MIN 0.90 0.00 0.90 0.25 0.09 2.80 2.60 1.50 0.35 NOTE: A2 SC70 E1 SYMBOL A A1 A2 b C D E E1 L e e1 NOTE: A1 1. 2. 3. 4. All dimensions are in millimeters. Dimensions are inclusive of plating. Dimensions are exclusive of mold flashing and metal burr. All speccifications comply to EIAJ SC70. 13 LMV321/LMV358/LMV324 DATA SHEET LMV324 Package Dimensions TSSOP 6 e 7 -B- N 5 (b) 2X E/2 TSSOP-14 8 1.0 DIA E1 E c SYMBOL A A1 A2 L R R1 b b1 c c1 01 L1 aaa bbb ccc ddd e 02 03 D E1 E e N c1 1.0 b1 ddd C B A 1 2 3 6 2X N/2 TIPS SECTION AA e /2 9 1.0 ccc A2 D 8 3 7 -A- aaa C A -C- b NX A1 (02) (0.20) bbb M C B A R1 -H- R GAGE PLANE 10 A (03) 0.25 L A 01 (L1) MIN - 0.05 0.85 0.50 0.09 0.09 0.19 0.19 0.09 0.09 0 NOM - - 0.90 0.60 - - - 0.22 - - - 1.0 REF 0.10 0.10 0.05 0.20 0.65 BSC 12 REF 12 REF 5.00 4.40 6.4 BSC 0.65 BSC 14 4.90 4.30 MAX 1.10 0.15 0.95 0.75 - - 0.30 0.25 0.20 0.16 8 5.10 4.50 NOTES: 1 All dimensions are in millimeters (angle in degrees). 2 Dimensioning and tolerancing per ASME Y14.5-1994. 3 Dimensions "D" does not include mold flash, protusions or gate burrs. Mold flash protusions or gate burrs shall not exceed 0.15 per side . 4 Dimension "E1" does not include interlead flash or protusion. Interlead flash or protusion shall not exceed 0.25 per side. 5 Dimension "b" does not include dambar protusion. Allowable dambar protusion shall be 0.08mm total in excess of the "b" dimension at maximum material condition. Dambar connot be located on the lower radius of the foot. Minimum space between protusion and adjacent lead is 0.07mm for 0.5mm pitch packages. 6 Terminal numbers are shown for reference only. 7 Datums - A - and - B - to be determined at datum plane - H - . 8 Dimensions "D" and "E1" to be determined at datum plane - H - . 9 This dimensions applies only to variations with an even number of leads per side. For variation with an odd number of leads per side, the "center" lead must be coincident with the package centerline, Datum A. 10 Cross sections A - A to be determined at 0.10 to 0.25mm from the leadtip. 8 Lead SYMBOL D E1 E e N MIN 2.90 4.30 SYMBOL D E1 E e N Pin No. 1 MIN 6.50 4.30 SOIC e NOM 3.0 4.40 D 6.4 BSC 0.65 BSC 8 CL 14 Lead MAX 3.10 4.50 ZD SYMBOL D E1 E e N MIN 4.90 4.30 SYMBOL D E1 E e N MIN 7.70 4.30 20 Lead NOM 6.50 4.40 6.4 BSC 0.65 BSC 20 B A1 16 Lead SYMBOL D E1 E e N MAX 7.90 4.50 SYMBOL D E1 E e N 7 4.50 A2 NOM 7.80 4.40 6.4 BSC 0.65 BSC 24 DETAIL-A MIN NOM MAX SOIC-14 4.90 5.00 5.10 SYMBOL MIN MAX 4.30 4.40 4.50 A1 .0098 6.4 .0040 BSC B .018 0.65 .014 BSC C .0075 .0098 16 D .337 .344 E .150 .157 e Lead .050 BSC 28 .2284 .2440 MINH NOM MAX .0099 .0196 9.50h 9.70 9.80 .016 .050 4.30L 4.40 4.50 A .060 .068 6.4 BSC 8 0 0.65 BSC ZD 0.20 ref 28 A2 .054 .062 L NOTE: DETAIL-A C REV.1B. March. 2009 MAX 5.10 4.50 24 Lead MAX CL6.60E H h x 45 A NOM 5.00 4.40 6.4 BSC 0.65 BSC 14 1. All dimensions are in inches. 2. Lead coplanarity should be 0 to 0.10mm (.004") max. 3. Package surface finishing: (2.1) Top: matte (charmilles #18~30). (2.2) All sides: matte (charmilles #18~30). (2.3) Bottom: smooth or matte (charmilles #18~30). 4. All dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side (d). 15 DATA SHEET LMV321/LMV358/LMV324 Ordering Information Model Part Number LMV321 Lead Free Package Container Pack Qty LMV321AP5X SC70-5 Reel 3000 LMV321 LMV321AP5X_NL SC70-5 Reel 3000 LMV321 LMV321AS5X SOT23-5 Reel 3000 LMV358 LMV358AM8X SOIC-8 (Narrow) Reel 2500 LMV358 LMV358AMU8X MSOP-8 Reel 3000 LMV324 LMV324AMTC14X TSSOP-14 Reel 2500 LMV324 LMV324AM14X SOIC-14 Reel 2500 Temperature range for all parts: -40C to +125C. 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Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Advance Information Formative / In Design Preliminary First Production No Identification Needed Full Production Obsolete Not In Production Definition Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I40 (c) 2008 Fairchild Semiconductor Corporation www.fairchildsemi.com