(1/18) *This document summarizes major features of the device. The contents of this document are preliminary. A formal specification is separately provided by "DATA SHEET". FUJITSU ASSP PRODUCTS Power Management ICs Version 1.0 March ,2002 DC/DC Converter IC for Charging Li-ion battery with Synchronous Rectification MB39A107 * DESCRIPTION The MB39A107 is a DC/DC converter IC for charging suitable for down-conversion, using pulse-width modulation (PWM) type and enabling output voltage to be set to any desired level from one cell to four cells. The output for the Nch MOS drive of the synchronous rectification type is adopted. The current amp which can set the offset voltage is built-in. As a result, it can be used for the current watch of the AC adapter and the battery. Moreover, this IC can also dynamically control the secondary battery's charge current by detecting a voltage drop in an AC adapter in order to keep its power constant (dynamically-controlled charging). The MB39A107 provides a broad power supply voltage range and low standby current as well as high efficiency, making it ideal for use as a built-in charging device in products such as notebook PC. * FEATURES * * Built-in current detection amplifier by which offset voltage can be adjusted * Output voltage setting accuracy : 4.2V0.74%(Ta=-10C to +85C) * Output voltage setting using external resistor : 1 cell to 4 cells * Power supply voltage range : 7 V to 25 V * Oscillation frequency range : 100kHz to (1MHz) * In standby mode, leave output voltage setting resistor open to prevent inefficient current loss * Built-in standby current function : 0A(Typ) * Built-in circuit for load-independent soft-start * Built-in output off function at low input voltage * Totem-pole type output for Nch MOS FET (2/18) * PIN DISCRIPTIONS Pin No. Pin Name I/O Description 1 VCC - Power supply terminal for reference voltage and control circuit. 2 +INUV I Under voltage detection comparator (UV Comp.) input terminal. 3 OUTC1 O Current detection amplifier (Current Amp1) output terminal. 4 -INC1 I Current detection amplifier (Current Amp1) input terminal. 5 +INC1 I Current detection amplifier (Current Amp1) input terminal. 6 IOFA1 I Current detection amplifier (Current Amp1) offset voltage input terminal. 7 +INE1 I Error amplifier (Error Amp1) non-inverted input terminal. 8 -INE1 I Error amplifier (Error Amp1) inverted input terminal. 9 FB1 O Error amplifier (Error Amp1) output terminal. 10 OUTC2 O Current detection amplifier (Current Amp2) output terminal. 11 -INC2 I Current detection amplifier (Current Amp2) input terminal. 12 +INC2 I Current detection amplifier (Current Amp2) input terminal. 13 +INE2 I Error amplifier (Error Amp2) non-inverted input terminal. 14 -INE2 I Error amplifier (Error Amp2) inverted input terminal. 15 FB2 O Error amplifier (Error Amp2) output terminal. 16 -INE3 I Error amplifier (Error Amp3) inverted input terminal. 17 FB3 O Error amplifier (Error Amp3) output terminal. 18 OUTD O With IC in standby mode, this terminal is set to "Hi-Z" to prevent loss of current through output voltage setting resistance. Set CTL terminal to "H" level to output "L" level. 19 CS - Soft-start setting capacitor terminal. 20 RT - Triangular wave oscillation frequency setting resistor connection terminal. 21 VREF O Reference voltage output terminal. 22 GND - Ground terminal. 23 CTL-1 I DC/DC converter block power supply control terminal. 24 CTL-2 I Current detection amplifier (Current Amp2) power supply control terminal. 25 PGND - Ground terminal. 26 OUT-2 O External synchronous rectification side FET gate drive terminal. 27 VS - External main side FET source connection terminal. 28 OUT-1 O External main side FET gate drive terminal. 29 CB - Boot capacitor connection terminal. Connect a capacitor between the CB and VS terminals. 30 VB O Output circuit bias output terminal. (3/18) * BLOCKDIAGRAM RS2 To Microprocessor OUTC1 +INUV 3 VCC 2 1 <CurrentAmp1> <UVComp> +INC1 -INC1 5 x25 4 IOFA1 4.05V Offset adjustment 6 <ErrorAmp1> VREF -INE1 +INE1 (6.0V) 8 30 VB Reg. VB 7 Chg_ctr 4.2V CB 29 A B Ichg VO FB1 <PWMComp> 9 OUT-1 Drv-1 Dead Time Modulation -INE2 14 OUTC2 10 +INC2 A -INC2 B <CurrentAmp2> <ErrorAmp2> VREF RS1 28 VS 27 Battery OUT-2 Drv-2 12 26 PGND x25 25 11 +INE2 7V to 25V 13 Output voltage (Battery voltage) is adjustable. H:UVLO release 2.5V FB2 1.5V 15 UVLO Vcc UVLO <ErrorAmp3> VREF -INE3 16 VREF UVLO OUTD 18 4.2V CurrentAmp1 ON/OFF FB3 17 CTL-2 24 < SOFT> VREF Vcc 10uA <OSC> CS 19 Cs CT 45pF 4.2V bias <REF> <CTL> VREF 5.0V 20 RT RT 21 VREF 22 GND CTL-1 DC/DC ON/OFF 23 (4/18) * PIN ASSIGNMENT (TOP VIEW) VCC 1 30 VB +INUV 2 29 CB OUTC1 3 28 OUT-1 -INC1 4 27 VS +INC1 5 26 OUT-2 IOFA1 6 25 PGND +INE1 7 24 CTL-2 -INE1 8 23 CTL-1 FB1 9 22 GND OUTC2 10 21 VREF -INC2 11 20 RT +INC2 12 19 CS +INE2 13 18 OUTD -INE2 14 17 FB3 FB2 15 16 -INE3 (FPT-30P-M04) (5/18) * ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit Power supply voltage VCC - 27 V Boot voltage VCB CB terminal 32 V Control input voltage VCTL CTL-1,CTL-2 terminal 27 V Output current IOUT 60 mA 1390* mW -55 to 125 C Power dissipation Storage temperature PD TSTG - Ta<25C - * When mounted on a 10cm square epoxy double-sided. (6/18) * RECOMMENDED OPERATION CONDITIONS Parameter Symbol Condition MIN TYP MAX Unit Power supply voltage VCC - 7 - 25 V Boot voltage VCB - - 30 V Reference voltage Output current IREF - -1 - 0 mA Bias output current IVB - -1 - 0 mA VINE +INE1 to +INE3, -INE1,-INE2 terminal 0 - VCC-1.8 V VINC +INC1,+INC2, -INC1,-INC2 terminal 0 - VCC V VINUV +INUV terminal 0 - VCC V VIOFA1 - 0 - 5 V VOUTD - 0 - 17 V IOUTD - 0 - 2 mA VCTL - 0 - 25 V IOUT - -45 - 45 mA -600 - 600 mA -1200 - 1200 mA Input voltage IOFA1 terminal input voltage OUTD terminal output voltage OUTD terminal output current CTL terminal input voltage Output current IOUT Peak output current IOUT CB terminal Main side, Duty5%(t=1/foscxDuty) Synchronous rectification side, Duty5%(t=1/foscxDuty) fOSC - 100 (500) (1000) kHz Timing resistor RT - (22) (47) (200) k Soft-start capacitor Cs - - 0.022 1.0 F Boot capacitor CB - - 0.1 1.0 F Bias output capacitor CVB - (0.47) (1.0) (10) F Reference voltage output capacitor CREF - - 0.1 1.0 F Operating ambient Temperature Ta - -30 25 85 C Oscillation frequency Please be advised that this specification might be changed for some reasons such as improvement of performance without any pre-notice. (7/18) * ELECTRICAL CHARACTERISTICS (Ta = 25C, VCC =19V, VB=0mA, VREF=0mA) Parameter Symbol Pin No. Condition Min. 1. Reference Voltage Output voltage Typ. Max. Unit [REF] VREF1 Ta=+25C (4.967) 5.000 (5.041) VREF2 Ta=-10C to +85C V (4.95 5.00 (5.05) V Input stability Line VCC=7V to 25V - 3 10 mV Load stability Short-circuit output current Load VREF=0mA to -1mA - 1 10 mV -50 -25 -12 mA IOS VREF=1V 2. Under Voltage Lockout Protection Circuit Block Threshold voltage Hysteresis width [UVLO] VTLH VCC = 6.2 6.4 6.6 V VTHL VCC = 5.2 5.4 5.6 V 0.7 1.0 1.3 V - VH VTLH VREF = 2.6 2.8 3.0 V VTHL VREF = 2.4 2.6 2.8 V 0.05 0.20 0.35 V -10 -6 A (450) 500 (550) kHz - 1* - % Threshold voltage Hysteresis width - VH 3. Soft-Start Block Charge Current [SOFT] - ICS 4. Triangular Wave Oscillator Block -14 [OSC] Oscillation frequency fosc (RT=47k) Frequency temperature stability f/fdt Ta=-30C to +85C 5-1. Error Amplifier Block [Error Amp1] VTH1 FB1=2V, Ta=+25C VTH2 FB1=2V, Ta=-10C to +85C Threshold voltage V 4.169 4.200 4.231 V - 1 5 mV -100 -30 - nA Input offset voltage VIO Input bias voltage IB Voltage gain AV DC - 100* - dB Frequency band width BW AV=0dB - 2* - MHz Output voltage *Standard design value FB1=2V (4.179) 4.200 (4.221) - VFBH - 4.7 4.9 - V VFBL - - 20 200 mV (8/18) (Ta = 25C, VCC =19V, VB=0mA, VREF=0mA) Parameter Symbol Pin No. Condition Min. Typ. Max. Unit Output source current ISOURCE FB1=2V - -2 -1 mA Output sink current FB1=2V 150 300 - A ISINK 5-2. Error Amplifier Block Input offset voltage VIO Input bias voltage IB Voltage gain AV Frequency band width BW Output voltage [Error Amp2] - 1 5 mV -100 -30 - nA DC - 100* - dB AV=0dB - 2* - MHz FB2=2V - VFBH - 4.7 4.9 - V VFBL - - 20 200 mV Output source current ISOURCE FB2=2V - -2 -1 mA Output sink current FB2=2V 150 300 - A ISINK 5-3. Error Amplifier Block [Error Amp3] VTH1 FB1=2V, Ta=+25C VTH2 FB1=2V, Ta=-10C to +85C Threshold voltage (4.179) 4.200 (4.221) V 4.169 4.200 4.231 V Voltage gain AV DC - 100* - dB Frequency band width BW AV=0dB - 2* - MHz VFBH - 4.7 4.9 - V VFBL - - 20 200 mV Output voltage Output source current ISOURCE FB1=FB2=2V - -2 -1 mA Output sink current ISINK FB1=FB2=2V 150 300 - A ILEAK OUTD=17V - 0 1 A RON OUTD=1mA - 35 50 OUTD terminal output leak current OUTD terminal output ON resistance 6-1. Current Amplifier Block [Current Amp1] Input offset voltage VIO +INC=-INC= 3V to Vcc, IOFA1=2.5V Voltage gain AV +INC=3V to Vcc Vin=-100mV, IOFA1=2.5V *: Standard design value (-1) - (1) mV (24.25) 25 (27.25) V/V (9/18) (Ta = 25C, VCC =19V, VB=0mA, VREF=0mA) Parameter Symbol Pin No. Condition Min. Typ. Max. Unit IINC1 +INC=-INC=19V - (50) - A IINC2 CTL-2=0V, +INC=-INC=19V - (0) - A Frequency band width BW AV=0dB - (2)* - MHz IOFA1 terminal Input current I-INCL IOFA1=2.5V -100 -30 - nA Input current VOUTCH - (5.3) 5.6 - V VOUTCL - - (0) (50) mV Output source current ISOURCE OUTC=2V - -2 -1 mA Output sink current OUTC=2V 150 300 - A Output voltage ISINK 6-2. Current Amplifier Block Input offset voltage VIO Voltage gain AV +INC=-INC= 3V to Vcc +INC=3V to Vcc Vin=-100mV (-2) - (2) mV (24.25) 25 (27.25) V/V IINC1 +INC=-INC=19V - (50) - A IINC2 CTL-1=0V, +INC=-INC=19V - (0) - A BW AV=0dB - (2)* - MHz Input current Frequency band width [Current Amp2] VOUTCH - (5.3) 5.6 - V VOUTCL - - (0) (50) mV Output source current ISOURCE OUTC=2V - -2 -1 mA Output sink current OUTC=2V 150 300 - A Output voltage ISINK 7. PWM Comp. Block [PWM Comp.1] VTL Duty cycle = 0% VTH Duty cycle = 100% Dtr (RT=47k) 1.4 1.5 - V - 2.5 2.6 V (95) (97) (99) % Threshold voltage Maximum duty cycle *: Standard design value (10/18) (Ta = 25C, VCC =19V, VB=0mA, VREF=0mA) Parameter Symbol Pin No. Condition 8. Output block Typ. Max. Unit - -400* - mA - -800* - mA - -400* - mA - -800* - mA [OUT] ISOURCE Output source current ISOURCE ISINK Output sink current ISINK Output ON resistance Dead time Main side, Duty5%, (t=1/foscxDuty) Synchronous side, Duty5%, (t=1/foscxDuty) Main side, Duty5%, (t=1/foscxDuty) Synchronous side, Duty5%, (t=1/foscxDuty) ROH OUT=-45mA - 6.5 9.8 ROL OUT=45mA - 5 7.5 tD1 - - (50)* - ns tD2 - - (50)* - ns 9. Under Voltage Detection Comparator Block [UV Comp.] VTLH +INUV1= - (4.2) - V VTHL +INUV1= (3.97) (4.05) (4.13) V - - (0.15) - V +INUV=0V - (-100) - nA Threshold Voltage Hysteresis width VH Input bias current IINUV 10. Bias Voltage Block Threshold Voltage Min. [VB] VB - 11. Control Block 5.9 6 6.1 V 2 - 25 V 0 - 0.8 V [CTL] ON condition VON OFF condition VOFF CTL-1, CTL-2 terminal CTL-1, CTL-2 terminal ICTLH CTL -1=CTL-2=5V - 100 150 A ICTLL CTL -1=CTL-2=0V - 0 1 A ICCS CTL-1=CTL-2=0V - 0 10 A ICC1 CTL-1=CTL-2=5V - (5.5) (8.3) mA CTL-1=5V, CTL-2=0V CTL-1=0V, CTL-2=5V - (4.0) (6.0) mA - (1.5) (2.3) mA Input current 12. General Standby current Power supply current ICC2 ICC3 *: Standard design value (11/18) * FUNCTIONAL DESCRIPTION 1. DC/DC Converter Unit (1) Reference voltage block (REF) The reference voltage generator uses the voltage supplied from the VCC terminal (pin 1) to generate a temperature compensated, stable voltage (5.0V Typ) used as the reference supply voltage for the IC's internal circuitry. This terminal can also be used to obtain a load current to a maximum of 1 mA from the reference voltage VREF terminal (pin 21) . (2) Triangular wave oscillator block (OSC) The triangular wave oscillator builds the capacitor for frequency setting into, and generates the triangular wave oscillation waveform by connecting the frequency setting resistor with the RT terminal (pin 20) . The triangular wave is input to the PWM comparator on the IC. (3) Error amplifier block (Error Amp1) This amplifier detects the output signal from the current detection amplifier (Current Amp2) , compares this to the +INE1 terminal (pin 7) , and outputs a PWM control signal to be used in controlling the charging current. A double constant current value can be set together with the charging current control with error amplifier (Error Amp.2). Therefore, the fail safe control with high safety or more can be achieved. In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the FB1 terminal (pin 9) and -INE1 terminal (pin 8) , providing stable phase compensation to the system. Connecting a soft-start capacitor to the CS terminal (pin 19) prevents rush currents when the IC is turned on. Using an error amplifier for soft-start detection makes the soft-start time constant, independent of the output load. It is possible to correspond also to dynamic control charge (Dynamically-controlled charging) by which the constant current control and the voltage drop of AC adaptor is detected by combining with current detection amplifier (Current Amp1). (4) Error amplifier block (Error Amp2) This amplifier detects the output signal from the current detection amplifier (Current Amp2) , compares this to the +INE2 terminal (pin 13) , and outputs a PWM control signal to be used in controlling the charging current. In addition, an arbitrary loop gain can be set up by connecting a feedback resistor and capacitor between the FB2 terminal (pin 15) and -INE2 terminal (pin 14) , providing stable phase compensation to the system. Connecting a soft-start capacitor to the CS terminal (pin 19) prevents rush currents when the IC is turned on. Using an error amplifier for soft-start detection makes the soft-start time constant, independent of the output load. (5) Error amplifier block (Error Amp3) This error amplifier (Error Amp3) detects the output voltage from the DC/DC converter and outputs the PWM control signal. External output voltage setting resistors can be connected to the error amplifier inverted input terminal to set the desired level of output voltage from 1 cell to 4 cells. In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the FB3 terminal (pin 17) to the -INE3 terminal (pin 16) of the error amplifier, enabling stable phase compensation to the system. Connecting a soft-start capacitor to the CS terminal (pin 19) prevents rush currents when the IC is turned on. Using an error amplifier for soft-start detection makes the soft-start time constant, independent of the output load. (6) Current detection amplifier block (Current Amp1) The current detection amplifier (Current Amp1) detects a voltage drop which occurs between both ends of the output sense resistor (RS2 ) due to the flow of the AC adapter current, using the +INC1 terminal (pin 5) and -INC1 terminal (pin 4) . Then it outputs the signal amplified by 25 times to the OUTC1 terminal (pin 3). Moreover, an equal offset voltage to the voltage impressed to the IOFA1 terminal (pin 6) can be set. (7) Current detection amplifier block (Current Amp2) The current detection amplifier (Current Amp2) detects a voltage drop which occurs between both ends of the output sense resistor (RS1) due to the flow of the AC adapter current, using the +INC2 terminal (pin 12) and -INC2 terminal (pin 11) . Then it outputs the signal amplified by 25 times to the OUTC2 terminal (pin 10). (12/18) (8) PWM comparator block (PWM Comp.) The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty of the error amplifiers (Error Amp1 to Error Amp3) depending on their output voltage. The PWM comparator circuit compares the triangular wave voltage the lowest generated by the triangular wave oscillator to the error amplifier output voltage and turns on the external main side output transistor, turns off the external synchronous rectification side output transistor during the interval (13/18) * SETTING THE CHARGING VOLTAGE The charging voltage (DC/DC output voltage) can be set by connecting external voltage setting resistors (R1, R2) to the -INE3 terminal (pin 16). Be sure to select a resistor value that allows you to ignore the on-resistor (35 , 1mA) of the internal FET connected to the OUTD terminal (pin 18). Battery charging voltage : Vo Vo(V) = (R1 + R2) / R2 x -INE3 (V) B R1 Vo -INE3 <Error Amp.3> 16 R2 18 4.2V OUTD 19 CS * METHOD OF SETTING THE CHARGING CURRENT The charge current (output limit current) value can be set with the voltage at the +INE2 terminal (pin 13). If a current exceeding the set value attempts to flow, the charge voltage drops according to the set current value. Battery charge current setting voltage : +INE2 +INE2(V) = 25 x Ichg (A) x RS () * METHOD OF SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY The triangular wave oscillation frequency can be set by the timing resistor (RT) connected the RT terminal (pin 20) . Triangular wave oscillation frequency : fosc fosc(kHz) 13500 / RT (k) (14/18) * METHOD OF SETTING THE SOFT-START TIME (1) Setting constant voltage mode soft-start For preventing rush current upon activation of IC, the IC allows soft-start using the capacitor (CS) connected to the CS terminal (pin 19) . When CTL-1 terminal (pin 23) is placed under "H" level and IC is activated (VCC UVLO threshold voltage) , Q2 is turned off and the external soft-start capacitor (CS) connected to the CS terminal is charged at 10 A. Error Amp3 output (FB3 terminal (pin 17) ) is determined by comparison between the lower voltage of the two non-inverted input terminals 4.2V and CS terminal voltage) and inverted input terminal voltage (-INE3 terminal (pin 16) voltage). Within the soft-start period (CS terminal voltage < 4.2V), FB3 is determined by comparison between -INE3 terminal voltage and CS terminal voltage, and DC/DC converter output voltage goes up proportionately with the increase of CS terminal voltage caused by charging on the soft-start capacitor. Soft-start time is obtained from the following formula : Soft-start time : ts (time to output 100 %) ts (s) 0.42 x CS (F) 4.9V 4.2V CS terminal voltage Error Amp block comparison voltage to -INE3 voltage 0V Soft-start time ts VREF 10uA 10uA -INE3 <Error Amp.3> 16 CS 19 4.2V Cs Q2 Soft-start circuit UVLO (15/18) (2) Setting constant current mode soft-start For preventing rush current upon activation of IC, the IC allows soft start using the capacitor (CS) connected to the CS terminal (pin 19) . When CTL-1 terminal (pin 23) is placed under "H" level and IC is activated (VCC UVLO threshold voltage), Q2 is turned off and the external soft-start capacitor (CS) connected to the CS terminal is charged at 10 A. Error Amp2 output (FB2 terminal (pin 15) ) is determined by comparison between the lower voltage of the two non-inverted input terminals (+INE2 terminal (pin 13) and CS terminal voltage) and inverted input terminal voltage (-INE2 terminal (pin 14) voltage) . Within the soft start period (CS terminal voltage < +INE2), FB2 is determined by comparison between -INE2 terminal voltage and CS terminal voltage, and DC/DC converter output voltage goes up proportionately with the increase of CS terminal voltage caused by charging on the soft-start capacitor. Soft-start time is obtained from the following formula. Soft-start time : ts (time to output 100 %) ts(s) +INE2 / 10 (A) x CS(F) 4.9V +INE2 CS terminal voltage Error Amp block comparison voltage to -INE2 voltage 0V Soft-start time ts VREF 10uA 10uA -INE2 <Error Amp.2> 14 CS 19 +INE2 Cs 13 Q2 Soft-start circuit UVLO (16/18) * PROCESSING WITHOUT USING OF THE SOFT-START FUNCTION When soft-start function is not used, the CS terminal (pin 19) should be left open. "Open" CS 19 When no soft-start function is specified * PROCESSING WITHOUT USING OF THE UNDER VOLTAGE DETECTION COMPARATOR When under voltage detection comparator is not used, the +INUV terminal (pin 2) should be made a short circuit to VCC. VCC 1 2 +INUV When no under voltage detection comparator is specified (17/18) * NOTE ON AN EXTERNAL REVERSE-CURRENT PREVENTIVE DIODE * Insert a reverse-current preventive diode at one of the three locations marked * to prevent reverse current from the battery. * When selecting the reverse current prevention diode, be sure to consider the reverse voltage (VR) and reverse current (IR) of the diode. VIN Vcc * 1 CB 29 * A OUT-1 28 B Ichg VS 27 * OUT-2 26 BATT RS1 Battery (18/18) * PACKAGE DIMENSIONS (19/18) FUJITSU LINITED For further information please contact Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices Akiruno Technology Center 50 Fuchigami, Akiruno, Tokyo, 197-0833, Japan Tel: 81(42) 532-2132 Fax: 81(42) 532-2414 http://www.fujitsu.co.jp/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179 http://www.fujitsumicro.com/ Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 http://www.fujitsu-ede.com/ All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 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You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. All right Reserved. FUJITSU Limited