Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16L2551
LOW VOLTAGE DUART WITH POWERSAVE
MAY 2007 REV. 1.1.3
GENERAL DESCRIPTION
The XR16L2551 (L2551) is a low voltage dual
universal asynchronous receiver and transmitter
(UART) with 5 Volt tolerant inputs. The device
includes additional capability over the ST16C2550:
Intel and Motorola data bus interface selection,
hardware and software flow control, infrared encoder/
decoder, sleep mode and a PowerSave mode for
battery oper ation. The L255 1’s enhanced registe r set
is compatible to the ST16C2550 and XR16L2550. It
supports the Exar’s enhanced features of 16 bytes of
TX and RX FIFOs and a complete modem interface.
Onboard registers provide the user with operational
status and data error tags. An internal loopback
capability allows onboard diagnostics. Independent
programmable baud rate generator is provided in
each channel to support data rates up to 3.125 Mbps.
NOTE: 1 Covered by U.S. Patent #5,649,122.
APPLICATIONS
•Battery Operated Instruments
•Data Port Adapters
•Handheld Appliances
•Radio Frequency Data Modems
•Base Stations
•USB Hubs
•Industrial Automation Controls
FEATURES
•2.25 to 5.5 Volt Operat ion
•5 Volt Tolerant Inputs
•Intel or Motorola Bus Interface Select (16/68#)
pin
•Pin-to-pin compatible to XR16L2751CM
•Two Independent UARTs
■Up to 3.125 Mbps at 5V, 2 Mbps at 3.3V, and 1
Mbps at 2.5V with external clock input
■Up to 1.5 Mbps at 5V, 1.25 Mbps at 3.3V and 1
Mbps at 2.5V with crystal clock input
■16 bytes of Transmit and Receive FIFOs
■Automatic RTS/CTS hardware flow control
■Automatic Xon/Xoff software flow control
■Wireless infrared encoder/decoder
■Receive FIFO trigger levels select
■Programmable character lengths (5, 6, 7 or 8)
with even, odd, forced or no parity
■Full Modem Interface (CTS#, RTS#, DSR#,
DTR#, RI#, CD#) in the 48-TQFP package
•Sleep Mode with PowerSave feature for battery
operation
•Industrial Temperature range
•Tiny 32-QFN, no lead package (5x5x0.9mm)
•48-TQFP Package
FIGURE 1. XR16L2551 BLOCK DIAGRAM
XTAL1
XTAL2
Crystal Osc/Buffer
TXA, RXA,
RTSA#, CTSA#,
( DTR#, DSR#
CD#, RIA#, OP2A# )
Intel or
Motorola
Data Bus
Interface
UART Channel A
16 Byte TX FIFO
16 Byte RX FIFO
BRG
IR
ENDEC
TX & RX
UART
Regs
2.25 to 5.5 Volt VCC
GND
*5 Volt Tolerant Inputs
2551BLK
UART Channel B
(same as Channel A)
A2:A0
D7:D0
CSA# (CS#)
16/68#
CSB# (A3)
INTA (IR Q#)
INTB (logic 0)
PwrSave
IOW# (R/W#)
IOR# (VCC)
Reset (Reset#)
TXRDYA#
TXRDYB#
RXRDYA#
RXRDYB#
TXB, RXB,
RTSB#, CTSB#,
( DTRB#, DSRB#
CDB#, RIB#, OP2B# )
XR16L2551
2
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
FIGURE 2. PIN OUT ASSIGNMENT
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE
RANGE DEVICE STATUS
XR16L2551IL 32-Lead QFN -40°C to +85°C Active
XR16L2551IM 48-Lead TQFP -40°C to +85°C Active
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CSA#
CSB#
PWRSAVE
XTAL1
XTAL2
IOW#
CDB#
GND
RXRDYB#
IOR#
DSRB#
RIB#
RTSB#
CTSB#
16/68#
RESET
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
INTA
INTB
A0
A1
A2
NC
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
XR16L2551
48-pin TQFP
in 16 (Intel) Mode
VCC
NC
48
47
46
45
44
43
42
41
40
39
38
37
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
13
14
15
16
17
18
19
20
21
22
23
24
D5
D6
D7
RXB
RXA
TXRDYB#
TXA
TXB
OP2B#
CS#
A3
PWRSAVE
XTAL1
XTAL2
IOW#
CDB#
GND
RXRDYB#
VCC
DSRB#
RIB#
RTSB#
CTSB#
16/68#
RESET#
DTRB#
DTRA#
RTSA#
OP2A#
RXRDYA#
IRQ#
NC
A0
A1
A2
NC
D4
D3
D2
D1
D0
TXRDYA#
VCC
RIA#
CDA#
DSRA#
CTSA#
NC
XR16L2551
48-pin TQFP in
68 (Motorola) Mode)
GND
32
31
30
29
1
2
3
4
5
6
7
8
24
23
22
21
20
19
11
12
13
14
15
16
9
10
D5
D6
D7
RXB
RXA
TXA
TXB
CSA#
CSB#
XTAL1
XTAL2
IOW#
GND
IOR#
RTSB#
CTSB#
RESET
RTSA#
INTA
INTB
A0
A1
A2
D4
D3
D2
D1
D0
VCC
CTSA#
XR16L2551
32-pin QFN in
16 (Intel) Mode
28
27
26
25
18
17
PWRSAVE
16/68#
VCC
32
31
30
29
1
2
3
4
5
6
7
8
24
23
22
21
20
19
11
12
13
14
15
16
9
10
D5
D6
D7
RXB
RXA
TXA
TXB
CS#
A3 (CSB#)
XTAL1
XTAL2
R/W#
GND
VCC (IOR#)
RTSB#
CTSB#
RESET# (Reset)
RTSA#
IRQ#
NC (INTB)
A0
A1
A2
D4
D3
D2
D1
D0
VCC
CTSA#
XR16L2551
32- pin QFN in
68 (Motorola) Mode
28
27
26
25
18
17
PWRSAVE
16/68#
GND
XR16L2551
3
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
PIN DESCRIPTIONS
Pin Description
NAME 32-QFN
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
18
19
20
26
27
28
IAddress data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
2
1
32
31
30
29
28
27
3
2
1
48
47
46
45
44
IO Data bus lines [7:0] (bidirectional).
IOR#
(VCC) 14 19 IWhen 16/68# pin is at logic 1, the Intel bus interface is selected and
this input becomes read strobe (active low). The falling edge instigates
an internal read cycle and retrieves the data byte from an internal regis-
ter pointed by the address lines [A2:A0], puts the data byte on the data
bus to allow the host processor to read it on the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input is not used and should be connected to VCC.
IOW#
(R/W#) 12 15 IWhen 16/68# pin is at logic 1, it selects Intel bus interface and this input
becomes write strobe (active low). The falling edge instigate s the inter-
nal write cycle and the rising edge transfers the data byte on the data
bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is selected
and this input becomes read (logic 1) and write (logic 0) signal.
CSA#
(CS#) 710 IWhen 16/68# pin is at logic 1, this input is chip select A (active low) to
enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select (active
low) for the Motorola bus interface.
CSB#
(A3) 811 IWhen 16/68# pin is at logic 1, this input is chip select B (active low) to
enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface. Input
logic 0 selects channel A and logic 1 selects channel B.
INTA
(IRQ#) 22 30 OWhen 16/68# pin is at logic 1 for Intel bus interface, this output
becomes channel A interrupt output. The output state is defined by the
user through the software setting of MCR[3]. INTA is set to the active
mode and OP2A# output to a logic 0 when MCR[3] is set to a logic 1.
INTA is set to the three state mode and OP2A# to a logic 1 when
MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An external
pull-up resistor is required for proper operation.
XR16L2551
4
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
INTB
(NC) 21 29 OWhen 16/68# pin is at logic 1 for Intel bus interface, this output
becomes channel B interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 whe n MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0. See MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this outp ut is
not used and will stay at logic zero level. Leave this output uncon-
nected.
TXRDYA# -43 OUART channel A Transmitter Ready (active low). The output
provides the TX FIFO/THR status for transmit channel A. If it is
not used, leave it unconnected.
RXRDYA# -31 OUART channel A Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel A. If it is not used, leave it
unconnected.
TXRDYB# - 6 O UART channel B Transmitter Ready (active low). The output provides
the TX FIFO/THR status for transmit channel B. If it is not used, leave it
unconnected.
RXRDYB# -18 OUART channel B Receiver Ready (active low). This output provides the
RX FIFO/RHR status for receive channel B. If it is not used, leave it
unconnected.
MODEM OR SERIAL I/O INTERFACE
TXA 5 7 O UART channel A Transmit Data. If it is not used, leave it unconnected.
RXA 4 5 I UART channel A Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSA# 23 33 OUART channel A Request-to-Send (active low) or general pu rpose out-
put. If it is not used, leave it unconnected.
CTSA# 25 38 IUART channel A Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used.
DTRA# -34 OUART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
DSRA# -39 IUART channel A Data-Set-Ready (active low) or general purpose
input. This input should be connec ted to VCC when not used. This
input has no effect on the UART.
CDA# -40 IUART channel A Carrier-Detect (active low) or general purpose input.
This input should be connecte d to VCC when not used. This input has
no effect on the UART.
RIA# -41 IUART channel A Ring-Indicator (active low) or general purpose input.
This input should be connecte d to VCC when not used. This input has
no effect on the UART.
Pin Description
NAME 32-QFN
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
XR16L2551
5
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
OP2A# -32 OOutput Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTA output functionality. If it is not used at all, leave it
unconnected.
TXB 6 8 O UART channel B Tr ansmit Data. If it is not used, leave it unconnected.
RXB 3 4 I UART channel B Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSB# 15 22 OUART channel B Request-to-Send (active low) or general pu rpose out-
put. If it is not used, leave it unconnected.
CTSB# 16 23 IUART channel B Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used.
DTRB# -35 OUART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
DSRB# -20 IUART channel B Data-Set-Ready (active low) or general purpose
input. This input should be connec ted to VCC when not used. This
input has no effect on the UART.
CDB# -16 IUART channel B Carrier-Detect (active low) or general purpose input.
This input should be connecte d to VCC when not used. This input has
no effect on the UART.
RIB# -21 IUART channel B Ring-Indicator (active low ) or general purpose input.
This input should be connecte d to VCC when not used. This input has
no effect on the UART.
OP2B# - 9 O Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTB output functionality. If it is not used, leave it uncon-
nected.
ANCILLARY SIGNALS
XTAL1 10 13 ICrystal or external clock input.
XTAL2 11 14 OCrystal or buffered clock output.
16/68# 17 24 IIntel or Motorola Bus Select.
When 16/68# pin is at logic 1, 16 or Intel Mode, the device will operate
in the Intel bus type of int erface.
When 16/68# pin is at logic 0, 68 or Motorola mode, the device will
operate in the Motorola bus type of interface.
Pin Description
NAME 32-QFN
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
XR16L2551
6
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
PwrSave 912 IPowerSave (active high). This feature isolates the L2551’s data bus
interface from the host preventing other bus activities that cause higher
power drain during sleep mode. See Sleep Mode with Auto Wake-up
and PowerSave Feature section for details.
RESET
(RESET#) 24 36 IWhen 16/68# pin is at logic 1 for Intel bus interface, this input becomes
RESET (active high). When 16/68# pin is at logic 0 for Motorola bus
interface, this input becomes RESET# (active low).
A 40 ns minimum active pulse on this pin will reset the internal registers
and all outputs of channel A and B. The UART transmitter output will be
held at logic 1, the receiver input will be igno red and outputs are reset
during reset period (see UART Reset Conditions).
VCC 26 42 Pwr 2.25V to 5.5V power supply. All inputs are 5V tolerant.
GND 13 17 Pwr Power supply common , ground.
GND Center Pad N/A Pwr The center pad on the backside of the 32-QFN package is met allic and
should be connected to GND on the PCB. The thermal pad size on the
PCB should be the approximate size of this center pad and should be
solder mask defined. The solder mask opening shoul d be at least
0.0025" inwards from the edge of the PCB thermal pad.
N.C. -25, 37 No Connection. These pins are not connected internally. But if there is
a possibility of migrating to the XR16L2751 for future needs, please
refer to the XR16L2751 datasheet to determine if these pins should be
connected to VCC or GND.
Pin Description
NAME 32-QFN
PIN # 48-TQFP
PIN # TYPE DESCRIPTION
XR16L2551
7
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
1.0 PRODUCT DESCRIPTION
The XR16L2551 (L2551) provides serial asynchronous receive data synchronization, parallel-to-serial and
serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are
necessary for converting the serial data stream into parallel data that is required with digital data systems.
Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to
form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the
data character . The parity bit is checked by the receiver for any transmission bit errors. The e lectron ic circ uitry
to provide all these functions is fairly complex especially when manufactured on a single integrated silicon
chip. The L2551 represents such an integration with greatly enhanced features. The L2551 is fabricated with
an advanced CMOS process.
Transmit and Receive FIFOs (16 Byte s each)
The L2551 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive
FIFO memory, instead of none in the 16C2450. The L2551 is designed to work with high speed modems and
shared ne twork e nviro nme nts, that requ ire fa st d ata proc essing tim e. In crea sed p erfo rma nce is re alized in the
L2551 by the transmit and receive FIFO’s. This allows the exter nal processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in
93 microseconds (This example u ses a character length of 11 bits, including st ar t/stop bit s at 115.2 Kbps). This
means the external CPU will have to service the receive FIFO less than every 100 microseconds. However
with the 16 byte FIFO in the L2551, the data buffer will not require unloading/loading for 1.53 ms. This
increases the service interval giving the external CPU additional time for other applications and reducing the
overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is
uniquely provided for maximum data throughput performance especially when operating in a multi-channel
environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
Data Bus Interface, Intel or Motorola Type
The L2551 provides a single host interface for the 2 UARTs and supports Intel or Motorola microprocessor
(CPU) data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type
of CPUs using IOR#, IOW# and CSA# or CSB# inputs for data bus operation. The Motorola bus compatible
interface instead uses the R/W#, CS# an d A3 sig nals for da ta bus transactions. Few data bus interface signals
change their functions depending on user’s selection, see pin description for details. The Intel and Motorola
bus interface selection is made through the 16/68# pin (pin 24 for 48-TQFP package and pin 17 for 32-QFN
package).
Enhanced Features
The XR16L2551 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Its features set is compatible to the XR16L2550 device but offers Intel or Motorola data
bus interface and PowerSave to isolate the data bus interface during Sleep mode. Each UART is
independently controlled having its own set of device configuration registers. The configuration registers set is
16550 UART compatible for control, status and data transfer. Additionally, each UART channel has automatic
RTS/CTS hardware flow control, automatic Xon/Xoff and special character software flow control, infrared
encoder and decoder (IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4,
and data rate up to 3.125 Mbps at 5V with a 50 MHz external clock.
The rich feature set of the L2551 is available through internal registers. Selectable receive FIFO trigger levels,
selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power
on reset or an external reset (and operating in 16 or Intel Mode), the L2551 is functionally and software
compatible with the previous generation ST16C2450 and ST16C2550.
XR16L2551
8
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactio ns. The L2551 dat a interf ace support s the Intel comp atible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CSA/B#, IOR# and IOW# or CS#, R/W# and A3 inputs.
Both UART channels share the same data bus for host operations. A typical data bus interconnection for Intel
and Motorola mode is shown in Figure 3.
2.2 5-Volt Tolerant Inputs
The L2551 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2551 is
operating at 2.5V, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial
transceiver that is operating at 5V.
FIGURE 3. XR16L2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
2.25 to 5.5 Volt VCC
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CSA#
UART_CSB#
IOR#
IOW#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_INTB
UART_INTA
INTB
INTA
RXRDYA#
TXRDYA# RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
UART_RESET RESET
RS - 2 3 2 S eria l In te r fa ce
In te l D a ta B u s In t er c on n e c ti o n s
(no connect)
(no connect)
RS-2 32 Se rial Interface
2.25 to 5.5 Volt VCC
VCC
OP2A#
DSRA#
CTSA#
RTSA#
DTRA#
RXA
TXA
RIA#
CDA#
OP2B#
DSRB#
CTSB#
RTSB#
DTRB#
RXB
TXB
RIB#
CDB#
GND
A0
A1
A2
UART_CS#
A3
R/W#
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSA#
CSB#
D0
D1
D2
D3
D4
D5
D6
D7
IOR#
IOW#
UART
Channel A
UART
Channel B
UART_IRQ#
INTB
INTA
RXRDYA#
TXRDYA#
RXRDYA#
TXRDYA#
RXRDYB#
TXRDYB#
RXRDYB#
TXRDYB#
RESET#
RS-23 2 Se rial Interface
RS - 2 3 2 S eria l In te rface
Motorola Data Bus Interconnections
VCC
UART_RESET#
(no connect)
(no connect)
(no co nn ec t)
VCC
XR16L2551
9
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
2.3 Device Reset
The RESET or RESET# input resets the internal registers and the serial interface outputs in both channels to
their default state (see Table 14). An active high pulse of at least 40 ns duration will be required to activate the
reset function in the device.
2.4 Device Identification and Revision
The L2551 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is req uired to se t th e b aud ra te ge ner ator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2551
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
2.5 Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UAR Ts can be useful during power up initialization to write to the same intern al registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1.
During Motorola Bus Mode (16/68# pin connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the L2551 decodes an
additional address, A3, to select one of the UART ports. The A3 address decode fun ct ion is use d only wh en in
the Motorola Bus Mode. See Table 2.
Channel A and B Internal Registers
Each UART channel in the L2551 has a standard register set for controlling, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratch pad register (SPR).
2.6 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE
CSA# CSB# FUNCTION
1 1 UART de-selected
0 1 Channel A selected
1 0 Channel B selected
0 0 Channel A and B selected
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE
CS# A3 FUNCTION
1 N/A UART de-selected
0 0 Channel A selected
0 1 Channel B selected
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the L2551 is placed in single-character mode for data transmit or receive operation.
When DMA mode is en abled (FC R bit-3 = 1), the user takes adva ntage of block mo de operati on by loadin g or
unloading the FIFO in a block seq uence dete rmined by th e progra mmed trigg er level. The fo llowing t able show
their behavior. Also see Figure 20 through Figure 25.
2.7 INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 4 and Table 5 summarize the operating behavior for the transmitter and receiver. Also see Figure 20
through Figure 25.
2.8 Crystal Oscillator or External Clock Input
The L2551 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. Please note that the input XTAL1 is not
5V tolerant and so the maximum at the pin should be VCC. For programming details, see “Programmable
Baud Rate Generator.”
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS FCR BIT-0=0
(FIFO DISABLED)FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled) FCR Bit-3 = 1
(DMA Mode Enabled)
RXRDY# A/B 0 = 1 byte.
1 = no data. 0 = at least 1 byte in FIFO
1 = FIFO empty. 1 to 0 transition when FIFO reache s the trigger
level, or time-out occurs.
0 to 1 transition when FIFO empties.
TXRDY# A/B 0 = THR empty.
1 = byte in THR. 0 = FIFO empty.
1 = at least 1 byte in FIFO. 0 = FIFO has at least 1 empty location.
1 = FIFO is full.
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER
FCR BIT-0 = 0
(FIFO DISABLED)FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin 0 = a byte in THR
1 = THR empty 0 = at least 1 byte in FIFO
1 = FIFO empty
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER
FCR BIT-0 = 0
(FIFO DISABLED)FCR BIT-0 = 1
(FIFO ENABLED)
INTA/B Pin 0 = no data
1 = 1 byte 0 = FIFO below trigger level
1 = FIFO above trigger level
XR16L2551
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 kΩ
to 1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4.
For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.9 Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24
MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as
shown in Figure 5) it can extend its operation up to 50 MHz (3.125Mbps serial data rate) at room temperature
and 5.0V.
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE
C1
22-47 pF C2
22-47 pF
Y1 1.8432 MHz
to
24 MH z
R1
0-120 Ω
(Optional)
R2
500 KΩ - 1 MΩ
XTAL1 XTAL2
2K
XTAL1
XTAL2
R1
VCC
External Clock
vcc
gnd
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock
operating frequency over power supply voltage chart in Figure 6.
The L2551 divid es the basic e xternal clock by 16. The basic 16X cl ock provides t able ra tes to supp ort sta ndard
and custom applications using the same system de sign. The Baud Rate Generator divides the input 16X clock
by any divisor from 1 to 216 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and L SB sections
of baud rate generator.
Table 6 shows the standard data rates availa ble with a 14 .74 56 MHz crystal or exte rnal clo ck at 16X samp ling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR
ON XTAL2 PIN TO INCREASE OPERATING SPEED
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
60
50
40
30
3.0 4.5 5.53.5 4.0 5.0
Suppy V oltage
XTAL1 External Clock Frequency in MHz.
70
80
85oC
25oC
-40oC
Operating frequency for XR16L2551
with external clock and a 2K ohms
pull-up resistor on XTAL2 pin.
XR16L2551
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which
includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal
clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,
insert s the proper p arity-bit if enab led, and adds the stop-bit(s). The status of the FIFO and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6 ).
2.10.1 Transmit Holding Register (THR) - Write Only
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and st op-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
2.10.2 Transmitter Operation in non-FIFO Mode
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is tran sferred to TSR. THR flag ca n generate a transmit emp ty interrupt (I SR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
OUTPUT Data Rate
MCR Bit-7=0 DIVISOR FOR 16x
Clock (Decimal) DIVISOR FOR 16x
Clock (HEX) DLM PROGRAM
VALUE (HEX) DLL PROGRAM
VALUE (HEX) DATA RATE
ERROR (%)
400 2304 900 09 00 0
2400 384 180 01 80 0
4800 192 C0 00 C0 0
9600 96 60 00 60 0
19.2k 48 30 00 30 0
38.4k 24 18 00 18 0
76.8k 12 0C 00 0C 0
153.6k 606 00 06 0
230.4k 404 00 04 0
460.8k 202 00 02 0
921.6k 101 00 01 0
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
2.10.3 Transmitter Oper ation in FIFO Mode
The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR
become emp ty.
2.11 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timi ng. It verifies and validate s every bit
on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an
internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in
this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bit s 2- 4. Upon unloading the receive d ata byte from RHR, the receive FIF O pointer
is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.
RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO
trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Transmit
Holding
Register
(THR)
Transmit Shift Register (TSR)
Data
Byte
L
S
B
M
S
B
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
TXNOFIFO1
16X Clock
T ran s mit D a ta S h ift Re g ist er
(TSR)
Transmit
D ata B yte TH R Inte rrupt (IS R b it-1) falls
below the programm ed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
Transmit
FIFO
16X Clock
Auto CTS Flow Control (CTS# pin)
Au to So ftw are F low C on trol
Flow Control Characters
(Xoff1 /2 a n d X o n1 /2 Re g.
TXFIFO1
XR16L2551
15
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
when data is n ot received for 4 word lengths as de fined by LCR[1:0] plus 12 b its time. This is equiva lent to 3.7-
4.6 character times. The RHR interrupt is enabled by IER bit-0.
2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reporte d in LSR regis ter. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bit s 2-4.
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE
Receive Dat a S hift
Register (RS R)
Receive
Data Byte
and Errors RHR Interrupt (ISR bit-2)
Receive Dat a
Holding Register
(RHR)
RXFIFO1
16X Clock
Receive Data Characters
Data Bit
Validation
Error
Tags in
LSR bits
4:2
Re ce iv e Da ta S h if t
Register (RSR)
RXFIFO1
16X Clock
Error Tags
(16-sets)
Error Tags in
LSR bits 4:2
16 bytes by 11-bit
wide
FIFO
Receive Data Characters
FIFO Trigger=8
Example
:
- RX F IFO trigger level selected at 8 bytes
Da ta fil ls to 14
Data falls to 4
Data Bit
Validation
Receive
Data FIFO
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) programmed for
desired FIFO trigger level.
FIFO is Enabled by FCR bit-0=1
RTS# de-asserts when data fills above the flow
control trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS# re-asserts when data falls below the flow
control trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
2.12 Auto RTS (Hardware) Flow Control
Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#
output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control
features is enab le d to fit sp ec ific application req uir em e nt (see Figure 11):
- Enable auto RTS flow control using EFR bit-6.
- The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled ).
- Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the
RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.
2.13 Auto CTS Flow Control
Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is
monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific
application requirement (see Figure 11):
- Enable auto CTS flow control using EFR bit-7.
- Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the
CTS# pin is de-asserted (logic 1): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as
the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-
asserted (logic 0), indicating more data may be sent.
XR16L2551
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION
The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of
remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO
(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-
tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA
monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows
(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-
mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lowe r threshold of RTS del a y (9),
UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until
next receive FIFO trigger (12). This same event applies to the reverse direction when UART A sends data to UARTB
with RTSB# and CTSA# controlling the data flow.
RTSA# CTSB#
RXA TXB Transmitter
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level Auto CTS
Monitor
RTSA#
TXB
RXA FIFO
CTSB#
Remote UART
UARTB
Local UART
UARTA
ON OFF ON
Suspend Restart
RTS High
Threshold
Data Starts
ON OFF ON
Assert RTS# to Begin
Transmission
1
2
3
4
5
6
7
Receive
Data RTS Low
Threshold
9
10
11
Receiver FIFO
Trigger Reached
Auto RTS
Trigger Level
Transmitter
Auto CTS
Monitor RTSB#CTSA#
RXBTXA
INTA
(RXA FIFO
Interrupt)
RX FIFO
Trigger Level RX FIFO
Trigger Level
8
12
RTSCTS1
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
2.14 Auto Xon/Xoff (Software) Flow Control
When sof tware flow contro l is enabled (See Table 13), the L2551 compares one or two sequ ential receive dat a
characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the
programmed values, the L2551 will halt transmission (TX) as soon as the current character has completed
transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output
pin will be activated. Following a suspension due to a match of the Xoff character, the L2551 will monitor the
receive data stream for a match to the Xon-1,2 character. If a match is found, the L2551 will resume operation
and clear the flags (ISR bit-4).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user
can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/
Xoff characters (See Table 13) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters
are selected, the L2551 compares two consecutive receive characters with two software flow control 8-bit
values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow
control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or
FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed, the L2551 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L2551 sends the
Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)
after the receive FIFO crosses the programmed trigger level. To clear this condition, the L2551 will transmit the
programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programme d
trigger level. See Table 7 below.
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2
characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.
2.15 Special Character Detect
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data.
The L2551 compares each incoming receive character with Xof f-2 dat a. If a match exists, the received data will
be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal
Register Table shows Xon, Xoff Registers with eight bits of characte r information, the actu al number of bits is
dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of
character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also
determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds with the LSB bit for the receive character.
TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL
RX TRIGGER LEVEL INT PIN ACTIVATION XOFF CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)XON CHARACTER(S) SENT
(CHARACTERS IN RX FIFO)
1 1 1* 0
4 4 4* 1
8 8 8* 4
14 14 14* 8
XR16L2551
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
2.16 Infrared Mode
The L2551 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit
wide HIGH-pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the
infrared LED, hence reduces the power consumption. See Figure 12 below.
The infrared encode r and de co de r are en able d by settin g MCR register bit-6 to a ‘1’. When the infrared feature
is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level
of logic zero from a reset and power up, see Figure 12.
Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.
Each time it senses a light pulse, it returns a logic 1 to the data bit stream.
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING
Character
Data Bits
Start
Stop
0000 0
11 111
Bit Time
1/16 Clock Delay
IRdecoder
-
RX Data
Receive
IR Pulse
(RX pin)
Character
Data Bits
Start
Stop
0000 0
11 111
TX Data
Transmit
IR Pulse
(TX Pin) Bit Time 1/2 Bit Time
3/16 Bit Time
IrEncoder-1
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
2.17 Sleep Mode with Auto Wake-Up and PowerSave Feature
The L2551 supports low voltage system designs, hence, a sleep mode with auto wake-up and PowerSave
feature is included to reduce power consumption when the device is not actively used.
2.17.1 Sleep Mode
All of these conditions must be satisfied for the L2551 to enter sleep mode:
■no interrupts pending for both channels of the L2551 (ISR bit-0 = 1)
■divisor is a non-zero value (ie. DLL = 0x1)
■sleep mode of both channels are enabled (IER bit-4 = 1)
■modem inputs are not toggling (MSR bits 0-3 = 0)
■RX input pins are idling at a logic 1
The L2551 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for
no clock output as an indication that the device has entered the sleep mode.
The L2551 resumes normal operation by any of the following when PowerSave mode is disabled:
■a receive data start bit transition (lo gic 1 to 0)
■a data byte is loaded to the transmitter, THR or FIFO
■a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
If the L2551 is awakened by any one of the above conditions, it will return to the sleep mode automatically after
all interrupting conditions have been serviced and cleared. If the L2551 is awakened by the modem inputs, a
read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while
an interrupt is pending from channel A or B. The L2551 will stay in the sleep mode of operation until it is
disabled by setting IER bit-4 to a logic 0.
A word of caution: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the
first few receive characters may be lost. The number of characters lost during the rest a rt al so de pen ds on your
operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep
RX A/B inputs idling at logic 1 or “markin g” condition dur ing sleep mode to avoid receiving a “break” condition
upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)
are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, th e desig ner can use a
47k-100k ohm pull-up resistor on the RXA and RXB pins.
2.17.2 PowerSave Feature
If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and mo dem input lines remain steady when the
L2551 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electric al
Characteristics on page 36. If the input lines are floating or are toggling while the L2551 is in sleep mode, the
current can be up to 100 times more. If not using the PowerSave feature, then an external buffer would be
required to keep the a ddres s and da ta bus lines from toggling or floating to achieve the low current. But if the
PowerSave feature is enabled (pin 12 of the 48-TQFP or pin 9 of the 32-QFN is connected to VCC), this will
eliminate the need for an external buffer by internally isolating the address, data and control signals (see
Figure 1 on page 1) from other bus activities that could cause wasteful power drain. The L2551 enters
PowerSave mode when the PWRSAVE pin is connected to VCC and the L2551 is in sleep mode (see Sleep
Mode section above).
Since PowerSave mode isolates the address, data and control signals, the device will wake-up by:
■a receive data start bit transition (lo gic 1 to 0)
■a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#
The L2551 will return to the PowerSave mode automatically after a read to the MSR (to reset the modem
inputs) and all interrupting conditions have been serviced and cleared. The L2551 will stay in the PowerSave
mode of operation until it is disabled by setting IER bit-4 to a logic 0 and/or the PowerSave pin is connected to
GND.
XR16L2551
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
2.18 Internal Loopback
The L2551 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR regi ster bit-4 to logic 1. Al l regular UART functions operate norm ally.
Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is intern ally routed to th e r ec eiv e sh ift regist er input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during
loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also,
Auto RTS/CTS is not suppor ted during internal loopback.
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B
TXA/TXB
RXA/RXB
Modem / General Purpose Control Logic
Internal Data Bus Lines and Control Signals
RTSA#/RTSB#
MCR bit-4=1
VCC
VCC
Transmit Shift Register
(THR/FIFO)
Receive Shift Register
(RHR/FIFO)
CTSA#/CTSB#
DTRA#/DTRB#
DSRA#/DSRB#
RIA#/RIB#
CDA#/CDB#
OP1#
OP2#
RTS#
CTS#
DTR#
DSR#
RI#
CD#
VCC
VCC
OP2A#/OP2B#
XR16L2551
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the L2551 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C550 compatible. The complete
register set is show n on Table 8 and Table 9....INTERNAL Register descr iptio n s
TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES REGISTER READ/WRITE COMMENTS
16C550 COMPATIBLE REGISTERS
0 0 0 RHR - Receive Holding Register
THR - Transmit Holding Register Read-only
Write-only LCR[7] = 0
0 0 0 DLL - Div Latch Low Byte Read/Write LCR[7] = 1, LCR ≠ 0xBF
0 0 1 DLM - Div Latch High Byte Read/Write
0 0 0 DREV - Device Revision Read/Write LCR[7] = 1, LCR ≠ 0xBF,
DLL = 0x00, DLM = 0x0 0
0 0 1 DVID - Device ID Read/Write
0 0 1 IER - Interrupt Enable Register Read/Write LCR[7] = 0
0 1 0 ISR - Interrupt Status Register
FCR - FIFO Control Register Read-only
Write-only LCR ≠ 0xBF
0 1 1 LCR - Line Control Register Read/Write
1 0 0 MCR - Modem Control Register Read/Write
LCR ≠ 0xBF
1 0 1 LSR - Line S tatus Register
Reserved Read-only
Write-only
1 1 0 MSR - Modem Status Register
Reserved Read-only
Write-only
1 1 1 SPR - Scratch Pad Register Read/Write
ENHANCED REGISTERS
0 1 0 EFR - Enhanced Function Register Read/Write
LCR = 0xBF
1 0 0 Xon-1 - Xon Character 1 Read/Write
1 0 1 Xon-2 - Xon Character 2 Read/Write
1 1 0 Xoff-1 - Xoff Character 1 Read/Write
1 1 1 Xoff-2 - Xoff Character 2 Read/Write
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0 REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0 0 0 RHR RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
LCR[7] = 0
0 0 0 THR WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 1 IER RD/WR 0/ 0/ 0/ 0/ Modem
Stat.
Int.
Enable
RX Line
Stat.
Int.
Enable
TX
Empty
Int
Enable
RX
Data
Int.
Enable
CTS Int.
Enable RTS Int.
Enable Xoff Int.
Enable Sleep
Mode
Enable
0 1 0 ISR RD FIFOs
Enabled FIFOs
Enabled 0/ 0/ INT
Source
Bit-3
INT
Source
Bit-2
INT
Source
Bit-1
INT
Source
Bit-0
LCR ≠ 0xBF
INT
Source
Bit-5
INT
Source
Bit-4
0 1 0 FCR WR RX FIFO
Trigger RX FIFO
Trigger 0 0 DMA
Mode
Enable
TX
FIFO
Reset
RX
FIFO
Reset
FIFOs
Enable
0 1 1 LCR RD/WR Divisor
Enable Set TX
Break Set Par-
ity Even
Parity Parity
Enable Stop
Bits Word
Length
Bit-1
Word
Length
Bit-0
1 0 0 MCR RD/WR 0/ 0/ 0/ Internal
Loop-
back
Enable
OP2#/
INT
Output
Enable
Rsvd
(OP1#) RTS#
Output
Control
DTR#
Output
Control
LCR ≠ 0xBF
BRG
Pres-
caler
IR Mode
ENable XonAny
1 0 1 LSR RD RX FIFO
Global
Error
THR &
TSR
Empty
THR
Empty RX
Break RX
Fram-
ing
Error
RX
Parity
Error
RX
Over-
run
Error
RX
Data
Ready
1 1 0 MSR RD CD#
Input RI#
Input DSR#
Input CTS#
Input Delta
CD# Delta
RI# Delta
DSR# Delta
CTS#
1 1 1 SPR RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
0 0 0 DLL RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7] = 1
LCR ≠ 0xBF
0 0 1 DLM RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
0 0 0 DREV RD Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 LCR[7]=1
DLL=0x00
DLM=0x00
0 0 1 DVID RD 0 0 0 0 0 0 1 0
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
SEE ”RECEIVER” ON PAGE 14.
4.2 Tr ansmit Holding Register (THR) - Write-Only
SEE ”TRANSMITTER” ON PAGE 13.
4.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.3.1 IER versus Receive FIFO Interrupt Mode Operation
When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (I ER BIT-0 = 1) are enabled, the RHR interrupt s
(see ISR bits 2 and 3) status will reflect the following:
A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed
trigger level. It will be cleared when the FIFO drops below the programmed trigger level.
B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register
status bit and the interrupt will be cleared when the FIFO drops below the trigger level.
C. The receive data ready bit ( LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the FIFO is empty.
4.3.2 I ER versus Receive/Transmit FIFO Polled Mode Operation
When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2551 in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can
be used in the polled mode by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in RHR or RX FIFO.
B. LSR BIT-1 indicates an overrun error has occurred and that da ta in the FIFO may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates Transmit FIFO is empty.
E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.
F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.
Enhanced Registers
0 1 0 EFR RD/WR Auto
CTS
Enable
Auto
RTS
Enable
Special
Char
Select
Enable
IER [7:4],
ISR [5:4],
FCR[5:4],
MCR[7:5]
Soft-
ware
Flow
Cntl
Bit-3
Soft-
ware
Flow
Cntl
Bit-2
Soft-
ware
Flow
Cntl
Bit-1
Soft-
ware
Flow
Cntl
Bit-0 LCR=0XBF
1 0 0 XON1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 0 1 XON2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 1 0 XOFF1 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
1 1 1 XOFF2 RD/WR Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1
ADDRESS
A2-A0 REG
NAME
READ/
WRITE BIT-7 BIT-6 BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
•Logic 0 = Disable the receive data ready interr upt (default).
•Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
•Logic 0 = Disable Transmit Ready interrupt (default).
•Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the
character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of
the FIFO.
•Logic 0 = Disable the receiver line status interrupt (default).
•Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
•Logic 0 = Disable the modem status register interrupt (default).
•Logic 1 = Enable the modem status register interrupt.
IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)
•Logic 0 = Disable Sleep Mode (default).
•Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.
IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)
•Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)
•Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for
details.
IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)
•Logic 0 = Disable the RTS# interrupt (default).
•Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition
from low to high.
IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)
•Logic 0 = Disable the CTS# interrupt (default).
•Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pi n makes a transit ion from
low to high.
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
4.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 10, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
4.4.1 Interrupt Generation:
•LSR is by any of the LSR bits 1, 2, 3 and 4.
•RXRDY is by RX trigger level.
•RXRDY Time-out is by a 4-char plus 12 bits delay timer.
•TXRDY is by TX FIFO empty.
•MSR is by any of the MSR bits 0, 1, 2 and 3.
•Receive Xoff/Special character is by detection of a Xoff or Special character.
•CTS# is when its transmitter toggles the input pin (from low to high) during au to CTS flow control.
•RTS# is when its receiver toggles the output pin (from low to hi gh) during auto RTS flow control.
4.4.2 Interrupt Clearing:
•LSR interrupt is cle ared by a read to the LSR regis ter (but flags and tags not cleared until character(s) that
generated the interrupt(s) has been emptie d or cleared from FIFO).
•RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
•RXRDY Time-out interrupt is cleared by reading RHR.
•TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
•MSR interrupt is cleared by a read to the MSR register.
•Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.
•Special character interrupt is cleared by a read to ISR or after the next character is received.
•RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.
]
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY ISR REGISTER STATUS BITS SOURCE OF INTERRUPT
LEVEL BIT-5 BIT-4 BIT-3 BIT-2 BIT-1 BIT-0
1 0 0 0 1 1 0 LSR (Receiver Line Status Register)
2 0 0 1 1 0 0 RXRDY (Receive Data Time-out)
3 0 0 0 1 0 0 RXRDY (Received Data Ready)
4 0 0 0 0 1 0 TXRDY (Transmit Ready)
5 0 0 0 0 0 0 MSR (Modem Status Register)
6 0 1 0 0 0 0 RXRDY (Received Xoff or Special character)
7 1 0 0 0 0 0 CTS#, RTS# change of state
- 0 0 0 0 0 1 None (default)
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
ISR[0]: Interrupt Status
•Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine .
•Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source
Table 10).
ISR[4]: Xoff or Special Character Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates tha t the receiver detected a data match
of the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR or when an Xon
character is received. If it is a special character interrupt, it will automatically clear after the next character is
received.
ISR[5]: RTS#/CTS# Interrupt Status
This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed
state from low to high.
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.5 FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
•Logic 0 = Disable the transmit and receive FIFO (default).
•Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No receive FIFO reset (default)
•Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
•Logic 0 = No transmit FIFO reset (default).
•Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of theTXRDY# and RXRDY# pins. See DMA operation section for details.
•Logic 0 = Normal Operation (default).
•Logic 1 = DMA Mode.
FCR[5:4]: Reserved
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UAR T will issue a receive interrupt when
the number of the char acters in the FIFO c rosse s t he trig ge r lev el. Table 11 shows the complete selections.
4.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
LCR[2]: TX and RX Stop-bit Length Selec t
The length of stop bit is specified by this bit in conjunction with the programmed word length.
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 12 for parity selection summary below.
•Logic 0 = No parity.
•Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
TABLE 11: RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR BIT-7 FCR BIT-6 RECEIVE
TRIGGER
LEVEL COMPATIBILITY
0
0
1
1
0
1
0
1
1 (default)
4
8
14
16C550, 16C2550,
16C2552 , 16C554,
16C580 compatible.
BIT-1 BIT-0 WORD LENGTH
0 0 5 (default)
0 1 6
1 0 7
1 1 8
BIT-2 WORD LENGTH STOP BIT LENGTH (BIT TIME(S))
05,6,7,8 1 (default)
1 5 1-1/2
16,7,8 2
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
•Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
•Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
•LCR[5] = logic 0, parity is not forced (d efault).
•LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
•LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
•Logic 0 = No TX break condition (default).
•Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
•Logic 0 = Data registers are select ed (defa ult ).
•Logic 1 = Divisor latch registers are selected.
4.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•Logic 0 = Force DTR# output to a logic 1 (default).
•Logic 1 = Force DTR# output to a logic 0.
TABLE 12: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3 PARITY SELECTION
X X 0 No parity
0 0 1 Odd parity
0 1 1 Even parity
1 0 1 Force parity to mark, “1”
1 1 1 Forced parity to space, “0”
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
•Logic 0 = Force RTS# output to a logic 1 (default).
•Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the L2551. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# inte rfa ce signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be
used as a general purpose output. This bit does not affect the IRQ# output during Motorola mode.
•Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
•Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.
MCR[4]: Internal Loopback Enable
•Logic 0 = Disable loopback mode (default).
•Logic 1 = Enable local loopback mode, see loopback section and Figure 13.
MCR[5]: Xon-Any Enable
•Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).
•Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or X off character and
the L2551 is programmed to use the Xon/Xoff flow control.
MCR[6]: Infrared Encoder/Decoder Enable
•Logic 0 = Enable the st andard modem receive and transmit input/output interface. (Default)
•Logic 1 = Enable infrared IrDA receive and tran smit inputs/outputs. The TX/RX output/input are ro uted to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface
requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.
MCR[7]: Clock Prescaler Select
•Logic 0 = Divide by one. The input clock from the cryst al or exter nal clock is fed directly to the Programmabl e
Baud Rate Generator without further modi fication, i.e., divide by one (default).
•Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and
feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.
4.8 Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
•Logic 0 = No data in receive holding register or FIFO (default).
•Logic 1 = Data has been re ceived and is saved in the receive holding register or FIFO.
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REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
LSR[1]: Receiver Overrun Flag
•Logic 0 = No overrun error (defau lt).
•Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register
is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into
the FIFO, therefore the data in the FIFO is not corrupted by the error. An interrupt will be generated
immediately if LSR interrupt is enabled (IER bit-2).
LSR[2]: Receiv e Data Parity Error Flag
•Logic 0 = No parity error (default).
•Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
LSR[3]: Receive Data Framin g Error Flag
•Logic 0 = No framing error (default).
•Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
•Logic 0 = No break condition (default).
•Logic 1 = The receiver received a bre ak signal (RX was a logic 0 for at least one char acter frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or logic 1. If the LSR interrupt is enabled (IER bit-2), an interrupt will
be generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when th e la st data byte is transfer red fro m
the transmit holding register to the transmit shift register. The bit is re set to logic 0 concurrently with the data
loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is
empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
•Logic 0 = No FIFO error (default).
•Logic 1 = A global indicato r for the sum of all er ror bit s in the RX FIFO. At least one parity error , framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.
4.9 Modem Status Regist er (M SR) - Rea d On ly
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
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LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
MSR[0]: Delta CTS# Input Flag
•Logic 0 = No change on CTS# input (default).
•Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[1]: Delta DSR# Input Flag
•Logic 0 = No change on DSR# input (default).
•Logic 1 = The DSR# in put has chan ged state since the last time it was monitor ed. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
•Logic 0 = No change on RI# input (default).
•Logic 1 = The RI# input has change d from a logic 0 to a lo gic 1, ending of th e ringin g signal. A mode m st atus
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
•Logic 0 = No change on CD# input (default).
•Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally this bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to
the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem
interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the mo dem inte rface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a gen er al pu rp os e inp u t whe n th e mode m inte rfa ce is not us ed .
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.10 Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16 -b it counte r that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. SEE
”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 11. for more details.
4.12 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x02 for XR16L2551). Prior to reading this register, DLL and DLM should
be set to 0x00.
XR16L2551
33
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
4.13 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.14 Enhanced Feature Re gister (EFR)
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 13). When the Xon1 and Xon2 and Xof f1 and Xof f2 mod es
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 to be modified.
After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature
prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is
recommended to leave it enabled, logic 1.
•Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 are
saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, and MCR bits 5-7are set to a
logic 0 to be compatible with ST16C550 mode (default).
•Logic 1 = Enables the above-mentioned register bits to be modified by the user.
TABLE 13: SOFTWARE FLOW CONTROL FUNCTIONS
EFR BIT-3
CONT-3 EFR BIT-2
CONT-2 EFR BIT-1
CONT-1 EFR BIT-0
CONT-0 TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL
0 0 0 0 No TX and RX flow control (default and reset)
0 0 X X No transmit flow control
1 0 X X Transmit Xon1, Xoff1
0 1 X X Transmit Xon2, Xoff2
1 1 X X Transmit Xon1 and Xon2, Xoff1 and Xoff2
X X 0 0 No receive flow control
X X 1 0 Receiver compares Xon1, Xoff1
X X 0 1 Receiver compares Xon2, Xoff2
1 0 1 1 Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
0 1 1 1 Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
1 1 1 1 Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
0 0 1 1 No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
XR16L2551
34
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
EFR[5]: Special Character Detect Enable
•Logic 0 = Special Character Detect Disabled (default).
•Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt, if enabled via IER bit-5. Special character interrupts are cleared automatically after the next
received character.
EFR[6]: Auto RTS Flow Control Enable
RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is
selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and
RTS de-asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when FIFO data falls
below the next lower trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take
effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.
•Logic 0 = Automatic RTS flow control is disabled (default).
•Logic 1 = Enable Automatic RTS flow control.
EFR[7]: Auto CTS Flow Control Enable
Automatic CTS Flow Control.
•Logic 0 = Automatic CTS flow control is disabled (default).
•Logic 1 = Enab le Automatic CTS flow co ntrol. Data transmission stops when CTS# input de-asserts to logic
1. Data transmission resumes when CTS# returns to a logic 0.
4.15 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write
These registers are used as the programmable software flow control characters XOFF1, XOFF2, XON1, and
XON2. For more details, see Table 7.
XR16L2551
35
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
TABLE 14: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS RESET STATE
DLM Bits 7-0 = 0xXX
DLL Bits 7-0 = 0xXX
RHR Bits 7-0 = 0xXX
THR Bits 7-0 = 0xXX
IER Bits 7-0 = 0x0 0
FCR Bits 7-0 = 0x0 0
ISR Bits 7-0 = 0x0 1
LCR Bits 7-0 = 0x00
MCR Bits 7-0 = 0x0 0
LSR Bit s 7 -0 = 0x60
MSR Bits 3-0 = Logic 0
Bits 7-4 = Logic levels of the inputs
inverted
SPR Bits 7-0 = 0xF F
EFR Bits 7-0 = 0x0 0
XON1 Bits 7-0 = 0x0 0
XON2 Bits 7-0 = 0x0 0
XOFF1 Bits 7-0 = 0x00
XOFF2 Bits 7-0 = 0x00
I/O SIGNALS RESET STATE
TX Logic 1
OP2# Logic 1
RTS# Logic 1
DTR# Logic 1
RXRDY# Logic 1
TXRDY# Logic 0
INT Three-State Condition
XR16L2551
36
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
Test 1: The following inputs must remain steady at VCC or GND state to minimize slee p current: A0-A2, D0-D7,
IOR#, IOW# (R/W#), CSA# (CS#), CSB# (A3) and all modem inputs. Also, RXA and RXB inputs must idle at
logic 1 state while asleep. Floating inputs may result in sleep currents in the mA range. For Powersave, the
UART internally isolates all of these inputs therefore not requirin g them to re m ain stea d y.
ABSOLUTE MAXIMUM RATINGS
Power Supply Range 7 Volts
Voltage at Any Pin GND-0.3 V to +5 .5 V
Operating Temperature -40o to +85oC
Storage Temperature -65o to +150oC
Package Dissipation 500 mW
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
Thermal Resistance (48-TQFP) theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (32-QFN) theta-ja = 33oC/W, theta-jc = 22oC/W
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc is 2.25 to 5.5V
SYMBOL PARAMETER 2.5V LIMITS
MIN MAX
3.3V LIMITS
MIN MAX
5.0V LIMITS
MIN MAX UNITS CONDITIONS
VILCK Clock Input Low Level -0.3 0.2 -0.3 0.6 -0.5 0.6 V
VIHCK Clock Input High Level 2.0 5.5 2.4 5.5 3.0 5.5 V
VIL Input Low Volt ag e -0.3 0.6 -0.3 0.8 -0.5 0.8 V
VIH Input High Voltage 2.0 5.5 2.0 5.5 2.2 5.5 V
VOL Output Low Voltage
0.4 0.4 0.4 V
V
V
IOL = 6 mA
IOL = 4 mA
IOL = 2 mA
VOH Output High Voltage
1.8 2.0 2.4 V
V
V
IOH = -6 mA
IOH = -1 mA
IOH = -400 uA
IIL Input Low Leakage Current ±10 ±10 ±10 uA
IIH Input High Leakage Current ±10 ±10 ±10 uA
CIN Input Pin Capacitance 555pF
ICC Power Supply Current 11.3 3mA
ISLEEP
IPWRSV
Sleep Current/
Powersave Current 615 30 uA See Test 1
XR16L2551
37
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V,
70 pF load where applicable
SYMBOL PARAMETER
LIMITS
2.5
MIN MAX
LIMITS
3.3
MIN MAX
LIMITS
5.0
MIN MAX
UNIT
-Crystal Frequency 16 20 24 MHz
CLK External Clock Low/High Time 31 17 10 ns
OSC External Clock Frequency 16 30 50 MHz
TAS Address Setup Time (16 Mode) 10 10 10 ns
TAH Address Hold Time (16 Mode) 10 10 10 ns
TCS Chip Select Width (16 Mode) 150 75 50 ns
TRD IOR# Strob e Width (16 Mode) 150 75 50 ns
TDY Read Cycle Delay (16 Mode) 150 75 50 ns
TRDV Data Access Time (16 Mode) 125 70 45 ns
TDD Data Disable Time (16 Mode) 045 030 030 ns
TWR IOW# Strobe Width (16 Mode) 150 75 50 ns
TDY Write Cycle Delay (16 Mode) 150 75 50 ns
TDS Data Setup Time (16 Mode) 25 20 15 ns
TDH Data Hold Time (16 Mode) 15 10 10 ns
TADS Address Setup (68 Mode) 10 10 10 ns
TADH Address Hold (68 Mode) 10 10 10 ns
TRWS R/W# Setup to CS# (68 Mode) 10 10 10 ns
TRDA Read Data Access (68 mode) 125 70 45 ns
TRDH Read Data Disable (68 mode) 45 30 30 ns
TWDS Write Data Setup (68 mode) 25 20 15 ns
TWDH Write Data Hold (68 Mode) 15 10 10 ns
TRWH R/W# Hold (68 Mode) 15 10 10 ns
TCSL CS# Width (68 Mode) 150 75 50 ns
TCSD CS# Cycle Delay (6 8 Mo de ) 150 75 50 ns
TWDO Delay From IOW# To Output 150 75 50 ns
TMOD Delay To Set Interrupt From MODEM Input 150 75 50 ns
TRSI Delay To Reset Interrupt From IOR# 150 75 50 ns
XR16L2551
38
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
TSSI Delay From Stop To Set Interrupt 1 1 1 Bclk
TRRI Delay From IOR# To Reset Interrupt 150 75 50 ns
TSI Delay From Stop To Interrupt 150 75 50 ns
TINT Delay From Initial INT Reset To Transmit Start 824 824 824 Bclk
TWRI Delay From IOW# To Reset Interrupt 150 75 50 ns
TSSR Delay From Stop To Set RXRDY# 1 1 1 Bclk
TRR Delay From IOR# To Reset RXRDY# 150 75 50 ns
TWT Delay From IOW# To Set TXRDY# 150 75 50 ns
TSRT Delay From Center of Start To Reset TXRDY# 8 8 8 Bclk
TRST Reset Pulse Width 40 40 40 ns
NBaud Rate Divisor 1216-1 1216-1 1216-1 -
Bclk Baud Clock 16X of data rate Hz
FIGURE 14. CLOCK TIMING
AC ELECTRICAL CHARACTERISTICS
Unless otherwise noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V,
70 pF load where applicable
SYMBOL PARAMETER
LIMITS
2.5
MIN MAX
LIMITS
3.3
MIN MAX
LIMITS
5.0
MIN MAX
UNIT
OSC
CLK
CLK
EXTERNAL
CLOCK
XR16L2551
39
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING
IOW#
RTS#
DTR#
CD#
CTS#
DSR#
INT
IOR#
RI#
TWDO
TMOD TMOD
TRSI
TMOD
Active
Active
Chan ge of state Chan ge of state
Active Active Active
Change of state Change of state
Chan ge of state
Active Active
TAS
TDD
TAH
TRD
TRDV
TDY
TDD
TRDV
TAH
TAS TCS
Valid Address Valid Address
Valid Da ta Valid D a ta
A0-A2
CSA#/
CSB#
IOR#
D0-D7
RDTm
TCS
TRD
XR16L2551
40
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING
16Write
TAS
TDH
TAH
TWR
TDS
TDY
TDH
TDS
TAH
TAS TCS
Valid Address Valid Address
Valid Data Valid Data
A0-A2
CSA#/
CSB#
IOW#
D0-D7
TCS
TWR
68Read
TADS
TRDH
TADHTCSL
TRDA
TCSD
TRWS
Valid
Address Valid
Address
Valid
Data
A0-A3
CS#
R/W#
D0-D7
TRWH
Valid
Data
XR16L2551
41
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
68Write
TADS TADHTCSL
TWDS
TCSD
TRWS
Valid
Address Valid
Address
Valid
Data
A0-A3
CS#
R/W#
D0-D7
TRWH
Valid
Data
TWDH
RX
RXRDY#
IOR#
INT
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TSSR
1 Byte
in RHR
Active
Data
Ready
Active
Data
Ready
Active
Data
Ready
1 Byte
in RHR 1 Byte
in RHR
TSSR TSSR
RXNFM
TRR TRR TRR
TSSR TSSR TSSR
(Reading data
out of RHR)
XR16L2551
42
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
D0:D7
Start
Bit D0:D7
Stop
Bit D0:D7
TWT
TXNonFIFO
TWT TWT
TWRI TWRI TWRI
TSRT TSRT TSRT
*INT is cleared when the ISR is read or when data is loaded into the THR.
ISR is read ISR is readISR is read
(Loading data
into THR)
(Unloading)
IER[1]
enabled
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXINTDMA#
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below RX
Trigger Level
FIFO
Empties
First Byte is
Received in
RX FIFO
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit
Stop
Bit
TRR
TRRI
TSSI
(Reading data out
of RX FIFO)
XR16L2551
43
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B
RX
RXRDY#
IOR#
INT
D0:D7
S
TSSR
RXFIFODMA
RX FIFO fills up to RX
Trigger Level or RX Data
Timeout
RX FIFO drops
below R X
Trigger Level
FIFO
Empties
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit Stop
Bit
TRR
TRRI
TSSI
(Reading da ta out
of RX FIFO)
TX
TXRDY#
IOW#
INT*
TXDMA#
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit Stop
Bit
TWRI
(Unloading)
(Loading d ata
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
Data in
TX FIFO
TX FIFO
Empty
TWT
TSRT
TX FIFO
Empty
T
TS
TSI
ISR is read
IER[1]
enabled
*INT is cleare d when t he I S R i s r ead or when th er e i s at lea s t on e c h ar acter i n t h e F IFO.
XR16L2551
44
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B
TX
TXRDY#
IOW#
INT*
TXDMA
D0:D7
SD0:D7TD0:D7
SD0:D7
S
TD0:D7
S
TTD0:D7
ST
Start
Bit Stop
Bit
TWRI
(Unloading)
(Loading data
into FIFO)
Last Data Byte
Transmitted
TX FIFO no
longer empty
TX FIFO
Empty
TX FIFO
Empty
T
TS
TSI
ISR is read
IER[1]
enabled
*INT is cleared when the ISR is read or when there is at least one character in the FIFO.
At least 1
empty loc at ion
in FIFO
TSRT
TX FIFO
Full
TWT
XR16L2551
45
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.039 0.047 1.00 1.20
A1 0.002 0.006 0.05 0.15
A2 0.037 0.041 0.95 1.05
B0.007 0.011 0.17 0.27
C0.004 0.008 0.09 0.20
D0.346 0.362 8.80 9.20
D1 0.272 0.280 6.90 7.10
e0.020 BSC 0.50 BSC
L0.018 0.030 0.45 0.75
a 0°7°0°7°
36 25
24
13
11
2
37
48
D
D
1
D
D
1
B
e
α
A
2
A
1
A
Seating
Plane
L
C
XR16L2551
46
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)
Note: The control dimension is in millimeter.
INCHES MILLIMETERS
SYMBOL MIN MAX MIN MAX
A0.031 0.039 0.80 1.00
A1 0.000 0.002 0.00 0.05
A3 0.006 0.010 0.15 0.25
D0.193 0.201 4.90 5.10
D2 0.138 0.150 3.50 3.80
b0.007 0.012 0.18 0.30
e0.0197 BSC 0.50 BSC
L0.012 0.020 0.35 0.45
k0.008 -0.20 -
Note: the actual center pad
is met a llic a n d the s iz e (D 2 )
is device-dependent with a
typical tolerance of 0.3mm
47
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits descr ibed herein , conveys no license unde r any p atent or other ri ght, and makes no represent ation th at
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user ’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect it s safety or effectiven ess. Products ar e not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected un de r the circumstances.
Copyright 2007 EXAR Corporation
Datasheet May 2007.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XR16L2551
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
REVISION HISTORY
DATE REVISION DESCRIPTION
November 2002 P1.0.0 Preliminary Datasheet.
March 2003 P1.0.1 Updated AC Electrical Characteristics. Updated register set with enhanced features.
May 2003 P1.0.2 Added patent number to first page. Added 32 pin QFN package dimensions.
June 2003 P1.0.3 Added Device Status to Ordering Information.
July 2003 P1.0.4 Updated AC Electrical Characteristics.
September 2003 1.0.0 Final Production Release. Update d 5V tolerance information.
September 2004 1.1.0 Corrected 32-QFN package dimension descriptions. Added GND center pad pin
description. Added Device Revision and Device ID registers and descriptions.
May 2005 1.1.1 Updated the Data Access Time (TRDV and TRDA) in AC Electrical Characteristics.
April 2006 1.1.2 Updated the "Voltage at Any Pin" to "GND-0.3 V to +5.5 V." SEE ”ABSOLUTE
MAXIMUM RATINGS” ON PAGE 36.
May 2007 1.1.3 Updated the QFN package drawing and added the parameter "k".
XR16L2551
I
LOW VOLTAGE DUART WITH POWERSAVE REV. 1.1.3
TABLE OF CONTENTS
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS................................................................................................................................................1
FEATURES .....................................................................................................................................................1
FIGURE 1. XR16L2551 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION.................................................................................................................................2
PIN DESCRIPTIONS .........................................................................................................3
1.0 PRODUCT DESCRIPTION .....................................................................................................................7
2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................................8
2.1 CPU INTERFACE .............................................................................................................................................. 8
FIGURE 3. XR16L2751 TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS........................................................................... 8
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 8
2.3 DEVICE RESET ................................................................................................................................................ 9
2.4 DEVICE IDENTIFICATION AND REVISION ..................................................................................................... 9
2.5 CHANNEL A AND B SELECTION .................................................................................................................... 9
TABLE 1: CHANNEL A AND B SELECT IN 16 MODE ............................................................................................................................ 9
TABLE 2: CHANNEL A AND B SELECT IN 68 MODE ............................................................................................................................ 9
2.6 DMA MODE ....................................................................................................................................................... 9
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE........................................................................................... 10
2.7 INTA AND INTB OUTPUTS ............................................................................................................................ 10
TABLE 4: INTA AND INTB PINS OPERATION FOR TRANSMITTER ...................................................................................................... 10
TABLE 5: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................. 10
2.8 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ........................................................................... 10
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS............................................................................................................................... 11
2.9 PROGRAMMABLE BAUD RATE GENERATOR ........................................................................................... 11
FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE.......................................................................................... 11
FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR ON XTAL2 PIN TO INCREASE OPERATING SPEED12
TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 13
2.10 TRANSMITTER ............................................................................................................................................. 13
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 13
2.10.2 TRANSMITTER OPERATION IN NON-FIFO MODE................................................................................................ 13
2.10.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 14
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 14
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 14
2.11 RECEIVER .................................................................................................................................................... 14
2.11.1 RECEIVE HOLDING REGISTER (RHR) - REA D-ONLY .......................................................................................... 15
FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 15
FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 15
2.12 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 16
2.13 AUTO CTS FLOW CONTROL ..................................................................................................................... 16
FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 17
2.14 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 18
TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 18
2.15 SPECIAL CHARACTER DETECT ............................................................................................................... 18
2.16 INFRARED MODE ........................................................................................................................................ 19
FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 19
2.17 SLEEP MODE WITH AUTO WAKE-UP AND POWERSAVE FEATURE ................................................... 20
2.17.1 SLEEP MODE .......................................................................................................... ................................................. 20
2.17.2 POWERSAVE FEATURE.......................................................................................................................................... 20
2.18 INTERNAL LOOPBACK .............................................................................................................................. 21
FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B .............................................................. .................... ..................... ......... 21
3.0 UART INTERNAL REGISTERS ...........................................................................................................22
TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS...................................................................................... 22
TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 23
4.0 INTERNAL REGISTER DESCRIPTIO NS ... ... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ... ... .... ...24
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 24
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............. ... .............. ... ... .............. .. ............... .. ... .... 24
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .............................................................................. 24
4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 24
XR16L2551
II
REV. 1.1.3 LOW VOLTAGE DUART WITH POWERSAVE
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 24
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 26
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 26
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 26
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 26
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ..................................................................................... 27
TABLE 11: RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................................... 28
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 28
TABLE 12: PARITY SELECTION........................................................................................................................................................ 29
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 29
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 30
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 31
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 32
4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 32
4.12 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 32
4.13 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 33
4.14 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 33
TABLE 13: SOFTWARE FLOW CONTROL FUNCTIONS........................................................................................................................ 33
4.15 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 34
TABLE 14: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 35
ABSOLUTE MAXIMUM RATINGS ..................................................................................36
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)36
ELECTRICAL CHARACTERISTICS................................................................................36
DC ELECTRICAL CHARACTERISTICS..............................................................................................................36
AC ELECTRICAL CHARACTERISTICS..............................................................................................................37
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 38
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING................................................................................................................... 39
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B................................................................................................. 39
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING ................................................................................................................. 40
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING .......................................................................................................... 40
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING......................................................................................................... 41
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 41
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 42
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 42
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 43
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B ........................... 43
FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 44
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)................................................45
PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)...............................................46
REVISION HISTORY ......................................................................................................................................47
TABLE OF CONTENTS ............................................................................................................ I
