CY8C21x34B
PSoC® Programmable System-on-Chip™ CapSense®
Controller with SmartSense™ Auto-tuning
1–21 Buttons, 0–4 Sliders, Proximity
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-67345 Rev. *G Revised February 3, 2017
PSoC® Programmable S ystem-on-Chip™ CapSense® Controller with SmartSense™ Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity
Features
■Advanced CapSense® block with SmartSense™ Auto-Tuning
❐Patented CSD sensing algorithm
❐SmartSense_EMC Auto-Tuning
• Sets and maintains optimal sensor performance during run
time
• Eliminates system tuning during development and
production
• Compensates for variations in manufacturing process
■Driven shield
❐Delivers best-in class water tolerant designs
❐Robust proximity sensing in the presence of metal objects
❐Supports longer trace lengths
■Powerful Harvard-architecture processor
❐M8C processor speeds up to 24 MHz
❐Low power at high speed
❐Operatin g volta ge : 2.4 V to 5.25 V
❐Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐Industrial temperature range: -40 °C to 85 °C
■Advanced peripherals (PSoC® blocks)
❐Four analog Type E PSoC blocks provide:
• Two comparators with digital-to-analog converter (DAC)
references
• Single or dual 10-bit 28 channel analog-to-digital
converters (ADC)
❐Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receive r transmitter
(UART), serial peripheral interface (SPI) master or slave
• Connectable to all general purpose I/O (GPIO) pins
❐Implement a combination up to 21 buttons or 4 sliders using
4 analog blocks and 3 digital blocks
❐Complex peripherals by combining blocks
■Flexible on-chip memory
❐8-KB Flash /512-B SRAM
❐50,000 erase/write cycles
❐In-system serial programming (ISSP)
❐Partial flash updates
❐Flexible protection modes
❐EEPROM emulation in flash
■Complete development tools
❐Free development software (PSoC Designer™)
❐Full-featured, in-circuit emulator (ICE) and programmer
❐Full-speed emulation
❐Complex breakpoint structure
❐128-KB trace memory
■Precision, programmable clocking
❐Internal ±2.5% 24- / 48-MHz main oscillator[1]
❐Internal oscillator for watchdog and sleep
■Programmable pin configurations
❐25-mA sink, 10-mA source on all GPIOs
❐Pull-up, pull-down, high-Z, strong, or open-drain drive modes
on all GPIOs
❐Up to eight analog inputs on GPIOs
❐Configurable interrupt on all GPIOs
■Versatile analog mux
❐Common internal analog bus
❐Simultaneous connection of I/O combinations
❐Capacitive sensing application capability
■Additional system resources
❐I2C[2] master, slave, and multi-master to 400 kHz
❐Watchdog and sleep timers
❐User-configurable low-voltage detection (LVD)
❐Integrated supervisory circuit
❐On-chip precision voltage reference
■Package options
❐16-pin SOIC
❐20-pin, 28-pin, 56-pin SSOP
❐32-pin QFN
Errata: For information on silicon errata, see “Errata” on page 48. Details include trigger conditions, devices af fected, and proposed wor ka r ound.
Notes
1. Errata: The worst case IMO frequency deviation when operated below 0 °C and above +70 °C and within the upper and lower datash eet temperature range is ±5%.
2. Errata: The I 2C block exhibits occasiona l data and bus corrupt ion errors when the I2C master init iates transactions while the device i s transitioning in to or out of sleep
mode.
CY8C21x34B
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Logic Block Diagram
CY8C21x34B
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More Information
Cypress provides a wealth of data at www.cypress.com to help
you to select the right PSoC device for your design, and to help
you to quickly and effectively integrate the device into your
design. For a comprehensive list of resources, see the
knowledge base article “How to Design with PSoC® 1,
PowerPSoC®, and PLC – KBA88292”. Following is an
abbreviated list for PSoC 1:
■Overview: PSoC Portfolio, PSoC Roadmap
■Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
■In addition, PSoC Designer includes a device selection tool.
■Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 1 are:
❐Getting Started with PSoC® 1 – AN75320.
❐PSoC® 1 - Getting Started with GPIO – AN2094.
❐PSoC® 1 Analog Structure and Configuration – AN74170.
❐PSoC® 1 Switched Capacitor Analog Blocks – AN2041.
❐Selecting Analog Ground and Reference – AN2219.
Note: For CY8C21x34B devices related Application note please
click here.
■Development Kits:
❐CY3210-PSoCEval1 supports all PSoC 1 Mixed-Signal Array
families, including automotive, except CY8C25/26xxx
devices. The kit includes an LCD module, potentiometer,
LEDs, and breadboarding space.
❐CY3214-PSoCEvalUSB features a development board for
the CY8C24x94 PSoC device. S pecial features of the board
include USB and CapSense development and debugging
support.
Note: For CY8C21x34B devices related Development Kits
please click here.
The MiniProg1 and MiniProg3 devices provide interfaces for
flash programming and debug.
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design
Environment (IDE). Develop your applications using a library of
pre-characterized analog and digital peripherals in a
drag-and-drop design environment. Then, customize your
design leveraging the dynamically generated API libraries of
code. Figure 1 shows PSoC Designer windows. Note: This is not
the default view.
1. Global Resources – all device hardware settings.
2. Parameters – the parameters of the currently selected User
Modules.
3. Pinout – information related to device pins.
4. Chip-Level Edito r – a diagram of the resources available on
the selected chip.
5. Datasheet – the datasheet for the currently selected UM
6. User Modules – all availa ble User Modules for the selected
device.
7. Device Resource Meter – device resource usage for the
current project configuration.
8. Worksp ace – a tree level diagram of files associated with the
project.
9. Output – output from project build and debug operations.
Note: For detailed information on PSoC Designer, go to
PSoC® Designer > Help > Documentation >
Designer Specific Documents > IDE User Guide .
Figure 1. PSoC Designer Layout
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 4 of 52
Contents
PSoC Functional Overview ............ ... .............. ... .. ............5
The PSoC Core ...........................................................5
The Digital System ......................................................5
The Analog System .....................................................6
Additional System Resources .....................................6
PSoC Device Characteristics ......................................7
Development Tools ............. .............. ... .............. .. ... .........8
PSoC Designer Software Subsystems ........................8
Designing with PSoC Designer ......................... ..............9
Select User Modules ......... .. ............................ ... ... ......9
Configure User Modules .................. .. ... .......................9
Organize and Connect ................................................9
Generate, Verify, and Debug .......................................9
SmartSense .................................................................9
Pin Information ...............................................................10
16-pin Part Pinout ................ .............. ... ... .............. ... .10
20-pin Part Pinout ................ .............. ... ... .............. ... .11
28-pin Part Pinout ................ .............. ... ... .............. ... .12
32-pin Part Pinout ................ .............. ... ... .............. ... .13
56-pin Part Pinout ................ .............. ... ... .............. ... .15
Register Reference ....................................... ... .............. .17
Register Conventions ................................................17
Register Mapping Tables ..........................................17
Electrical Specifications ................................................20
Absolute Maximum Ratings .......................................20
Operating Temperature .............................................21
DC Electrical Characteristics .....................................21
AC Electrical Characteristics .....................................27
Packaging Information .................... ... .............. ... ... ........35
Thermal Impedances ............... ... .............. ... ... ...........38
Solder Reflow Pea k Te mp era ture .............................38
Development Tool Selection .........................................39
Software ....................................................................39
Development Kits ......................................................39
Evaluation Tools ........................................................39
Device Programmers .................................................40
Accessories (Emulation and Programming) ..............40
Ordering Information ......................................................41
Ordering Code Definitions .........................................41
Acronyms ........................................................................ 42
Reference Documents ........................ ... ... .............. ... .. ...42
Document Conventions ............... ... .............. ... ... ...........43
Units of Measure ........................ ... ... .............. ... ........43
Numeric Conventions ................................................43
Glossary .......................................................................... 43
Errata ...............................................................................48
Part Numbers Affected ..............................................48
CY8C21X34 Qualification Status ..............................48
CY8C21X34 Errata Summary ...................................49
Document History Page ................................... ... ...........50
Sales, Solutions, and Legal Information ......................52
Worldwide Sales and Design Support .......................52
Products .................................................................... 52
PSoC® Solutions ......................................................52
Cypress Developer Community ...................... ... ........52
Technical Support .....................................................52
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 5 of 52
PSoC Functional Overview
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programma ble component. A PSoC device in cludes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The PSoC architecture, shown in Figure 2, consists of four main
areas: the core, the system resources, the digital system, and
the analog system. Configurable global bus resources allow
combining all of the device resources into a complete custom
system. Each CY8C21x34B PSoC device includes four digital
blocks and four analog blocks. Depending on the PSoC
package, up to 28 GPIOs are also included. The GPIOs provide
access to the global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low speed oscillator (ILO). The CPU
core, called the M8C, is a powerful proces sor with speeds up to
24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System resources provide these additional capabilities:
■Digital clocks for increased flexibility
■I2C functionality to implement an I2C master and slave
■An internal voltage reference, multi-master, that provides an
absolute value of 1.3 V to a number of PSoC subsystems
■A SMP that generates normal operating voltages from a single
battery cell
■Various system resets supported by the M8C
The digital system consists of an array of digital PSoC blocks that
may be configured into any number of digital peripherals. The
digital blocks are connected to the GPIOs through a series of
global buses. These buses can route any signal to any pin,
freeing designs from the constraints of a fixed peripheral
controller.
The analog system consists of four analog PSoC blocks,
supporting comparators, and analog-to-digital conversion up to
10 bits of precision.
The Digital System
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that is used alone or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■PWMs (8- to 32-bit)
■PWMs with dead band (8- to 32-bit)
■Counters (8- to 32-bit)
■Timers (8- to 32-bit)
■UART 8- with selectable parity
■Serial peripheral interface (SPI) master and slave
■I2C slave and multi-master
■CRC/generator (8-bit)
■IrDA
■PRS generators (8-bit to 32-bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controlle r.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 7.
Figure 2. Digital System Block Diagram
DIGITAL SYSTEM
To System Bus
Digital Clocks
From Core
Digital PSoC Block Array
To Analog
System
8
Row Input
Configuration
Row Output
Configuration
88
8
Row 0
DBB00 DBB01 DCB02 DCB03
4
4
GIE[7:0]
GIO[7:0]
GOE[7:0]
GOO[7:0]
Global Digita l
Interconnect
Port 3
Port 2
Port 1
Port 0
CY8C21x34B
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The Analog System
The analog system consists of four configurable blocks that allow
for the creation of complex analog signal flows. Analog
peripherals are very flexible and can be customized to support
specific application requirements. Some of the common PSoC
analog functions for this device (most available as user modules)
are:
■ADCs (single or dual, with 8-bit or 10-bit resolution)
■Pin-to-pin comparator
■Single-ended comparators (up to two) with absolute (1.3 V)
reference or 8-bit DAC reference
■1.3-V reference (as a system resource)
In most PSoC devices, analog blocks are provided in columns of
three, which includes one continuous time (CT) and two switched
capacitor (SC) blocks. The CY8C21x34B devices provide limited
functionality Type E analog blocks. Each column contains one
CT Ty pe E block and one SC Type E block. Refer to the PSoC
Technical Reference Manual for detailed information on the
CY8C21x34B’s Type E analog blocks.
Figure 3. Analog System Block Diagram
The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin. Pins may
be connected to the bus individual ly or in any combination. The
bus also connects to the analog system for analysis with
comparators and analog-to-digital converters. An additional 8 :1
analog input multiple xer provides a second path to bring Port 0
pins to the ana l og arra y.
Switch-control logic enables selected pins to precharge
continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
■Track pad, finger sensing
■Chip-wide mux that allows analog input from any I/O pin
■Crosspoint connection between any I/O pin combinations
Additional System Resources
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a switch-mode pump,
low-voltage detection, and power-on-reset (POR ).
■Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■The I2C module provides 100- and 400-kHz communication
over two wires. Slave, master , and multi-master modes are all
supported.
■LVD interrupts can signal the application of falling voltage
levels, while the advanced POR circuit eliminates the need for
a system supervisor.
■An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■An integrated switch-mode pump generates normal operating
voltages from a single 1.2-V battery cel l, providing a low cost
boost converter.
■Versatile analog multiplexer system.
ACOL1MUX
ACE00 ACE01
Array
Array Input
Configuration
ASE10 ASE11
X
X
X
X
X
Analog Mux Bus
All I/O
ACI0[1:0] ACI1[1:0]
CY8C21x34B
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PSoC Device Characteristics
Depending on your PSoC device characte ristics, the digital and analog systems can have 16, 8, or 4 digital blocks a nd 12, 6, or 4
analog blocks. Table 1 lists the resources availa ble for speci fic PSoC d evice gr oups. The PSoC de vice cove red by this datasheet i s
highlighted in Table 1.
Table 1. PSoC Device Characteristics
PSoC Part
Number Digital
I/O Digital
Rows Digital
Blocks Analog
Inputs Analog
Outputs Analog
Columns Analog
Blocks SRAM
Size Flash
Size SmartSense
Enabled
CY8C29x66 up to 64 4 16 up to 12 4 4 12 2K 32K –
CY8C28xxx up to 44 up to 3 up to 12 up to 44 up to 4 up to 6 up to
12 + 4[3] 1K 16K –
CY8C27x43 up to 44 2 8 up to 12 4 4 12 256 16K –
CY8C24x94 up to 56 1 4 up to 48 2 2 6 1K 16K –
CY8C24x23A up to 24 1 4 up to 12 2 2 6 256 4K –
CY8C23x33 up to 26 1 4 up to 12 2 2 4 256 8K –
CY8C22x45 up to 38 2 8 up to 38 0 4 6[3] 1 K 16K –
CY8C21x45 up to 24 1 4 up to 24 0 4 6[3] 512 8K –
CY8C21x34 up to 28 1 4 up to 28 0 2 4[3] 512 8K –
CY8C21x34B up to 28 1 4 up to 28 0 2 4[3] 512 8K Y
CY8C21x23 up to 16 1 4 up to 8 0 2 4[3] 256 4K –
CY8C20x34 up to 28 0 0 up to 28 0 0 3[3,4] 512 8K –
CY8C20xx6A up to 36 0 0 up to 36 0 0 3[3,4] up to 2K up to
32K Y
Notes
3. Limited analog functionality.
4. Two analog blocks and one CapSense®.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 8 of 52
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated applicatio n programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■Extensive user module catalog
■Integrated source-code editor (C and assembly)
■Free C compiler with no size restrictions or time limits
■Built-in debugger
■In-circuit emulation
■Built-in support for communication interfaces:
❐Hardware and software I2C slaves and masters
❐Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modu les are ADCs, DACs , amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC’s resources for an application.
Code Generati on Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. Y ou can develop your design in C, assembly ,
or a combinatio n of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C comp ilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embed ded
libraries providing port and bus operations, standard keypad and
display support, and extende d math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
Y ou can read and write CPU registers, set and clear breakpoints,
and provide program run, halt , and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for develo pment support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates wi th
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
CY8C21x34B
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Designing with PSoC Designer
The development p rocess for the PSo C device differs from th at
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of use r-selectable functions.
The PSoC development process is summarized in four steps:
1. Select User Modules.
2. Configure User Modules.
3. Organize and Connect.
4. Generate, Verify, and Debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select e stablishes the ba sic regi ste r
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets expla in the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information you may need to
successfully implement your design.
Organize and Connect
You buil d si gnal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and r outing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applic ations in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events.
These include monitoring address and data bus values, memory
locations, and external signals.
SmartSense
A key differentiation between the current offering of CY8C21x34
and CY8C21x34B, is the addition of the SmartSense user
module in the ‘B’ version.
SmartSense is an innovative solution from Cypress that
eliminates the manual tuning process from CapSense
applications. This solution is easy to use and provides robust
noise immunity. It is the only auto-tuning solution that
establishes, monitors and maintains all required tuning
parameters. SmartSense allows engineers to go from
prototyping to mass production without re-tuning for
manufacturing variations in PCB and/or overlay material
properties.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 10 of 52
Pin Information
The CY8C21x34B PSoC devi ce is available in a variety of packages which are listed in the follo wing tables. Every port pin (labeled
with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, SMP, and XRES are not capable
of Digital I/O.
16-pin Part Pinout
Figure 4. CY8C21234B 16-pin PSoC Device
SOIC
VDD
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
16
15
14
13
12
11
1
2
3
4
5
6
7
8
A, I, M, P0 [7 ]
A, I, M , P 0[5]
A, I, M , P 0[3]
A, I, M , P 0[1]
SMP
VSS
M, I2C SCL, P1[1]
VSS
10
9
Table 2. Pin Definitions – CY8C21234B 16-pin (SOIC)
Pin No. Type Name Description
Digital Analog
1I/O I, M P0[7] Analog column mux input
2I/O I, M P0[5] Analog column mux input
3I/O I, M P0[3] Analog column mux input, integrating input
4I/O I, M P0[1] Analog column mux input, integrating input
5Power SMP Switch-mode pump (SMP) connection to required external components
6Power VSS Ground connection
7I/O MP1[1] I2C serial clock (SCL), ISSP-SCLK[5]
8Power VSS Ground connection
9I/O MP1[0] I2C serial data (SDA), ISSP-SDATA[5]
10 I/O MP1[2]
11 I/O MP1[4] Optional external clock input (EXTCLK)
12 I/O I, M P0[0] Analog column mux input
13 I/O I, M P0[2] Analog column mux input
14 I/O I, M P0[4] Analog column mux input
15 I/O I, M P0[6] Analog column mux input
16 Power VDD Supply voltage
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
5. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 11 of 52
20-pin Part Pinout
Figure 5. CY8C21334B 20-pin PSoC Device
SSOP
VDD
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, I2C SCL, P1[7]
M, P1[3]
VSS
VSS
M, I2C SDA, P1[5]
M, I2C SCL, P1[1]
Table 3. Pin Definitions – CY8C21334B 20-pin (SSOP)
Pin No. Type Name Description
Digital Analog
1I/O I, M P0[7] Analog column mux input
2I/O I, M P0[5] Analog column mux input
3I/O I, M P0[3] Analog column mux input, integrating input
4I/O I, M P0[1] Analog column mux input, integrating input
5Power VSS Ground connection
6I/O MP1[7] I2C SCL
7I/O MP1[5] I2C SDA
8I/O MP1[3]
9I/O MP1[1] I2C SCL, ISSP-SCLK[6]
10 Power VSS Ground connection.
11 I/O MP1[0] I2C SDA, ISSP-SDATA[6]
12 I/O MP1[2]
13 I/O MP1[4] Optional external clock input (EXTCLK)
14 I/O MP1[6]
15 Input XRES Active high external reset with internal pull-down
16 I/O I, M P0[0] Analog column mux input
17 I/O I, M P0[2] Analog column mux input
18 I/O I, M P0[4] Analog column mux input
19 I/O I, M P0[6] Analog column mux input
20 Power VDD Supply voltage
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
6. These are the ISSP pins, which are not High Z at POR. Se e the PSoC Technical Reference Manual for details.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 12 of 52
28-pin Part Pinout
Figure 6. CY8C21534B 28-pin PSoC Device
A, I, M, P0[7]
A, I, M, P0[5]
A, I, M, P0[3]
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
VSS
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
VSS
VDD
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], EXTCLK, M
P1[2], M
P1[0], I2C SDA, M
SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Table 4. Pin Definitions – CY8C21534B 28-pin (SSOP)
Pin No. Type Name Description
Digital Analog
1I/O I, M P0[7] A nalog column mux input
2I/O I, M P0[5] A nalog column mux input and column output
3I/O I, M P0[3] A nalog column mux input and column outpu t, integrating input
4I/O I, M P0[1] A nalog column mux input, integrating input
5I/O MP2[7]
6I/O MP2[5]
7I/O I, M P2[3] Direct switched capacitor block input
8I/O I, M P2[1] Direct switched capacitor block input
9Power VSS Ground connection
10 I/O MP1[7] I2C SCL
11 I/O MP1[5] I2C SDA
12 I/O MP1[3]
13 I/O MP1[1] I2C SCL, ISSP-SCLK[7]
14 Power VSS Ground connection
15 I/O MP1[0] I2C SDA, ISSP-SDATA[7]
16 I/O MP1[2]
17 I/O MP1[4] Optional external clock input (EXTCLK)
18 I/O MP1[6]
19 Input XRES Active high external reset with intern al pull-down
20 I/O I, M P2[0] Direct switched capacitor block input
21 I/O I, M P2[2] Direct switched capacitor block input
22 I/O MP2[4]
23 I/O MP2[6]
24 I/O I, M P0[0] A nalog column mux input
25 I/O I, M P0[2] A nalog column mux input
26 I/O I, M P0[4] A nalog column mux input
27 I/O I, M P0[6] A nalog column mux input
28 Power VDD Supply voltage
LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input.
Note
7. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 13 of 52
32-pin Part Pinout
Figure 7. CY8C21434B 32-pin PSoC Device Figure 8. CY8C21634B 32-pin PSo C Device
Figure 9. CY8C21434B 32-pin Sawn PSoC Device Sawn Figure 10. CY8C21634B 32-pin Sawn PSoC Device Sawn
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
M, P3[3]
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
M, P3[1]
M, I2C SCL, P1[7]
P0[0], A, I, M
P2[6] , M
P3[0] , M
XRES
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P2[4] , M
P2[2] , M
P2[0] , M
P3[2] , M
P0[5], A, I, M
A, I, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
SMP
QFN
(Top View)
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
Vss
P0[3], A, I, M
P0[7], A, I, M
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
Vss
M, I2C SCL, P1[7]
P0[0], A, I, M
P2[6] , M
P3[0] , M
XRES
M, I2C SDA, P1[5]
M, P1[3]
M, I2C SCL, P1[1]
Vss
M, I2C SDA, P1[0]
M, P1[2]
M, EXTCLK, P1[4]
M, P1[6]
P2[4] , M
P2[2] , M
P2[0] , M
P3[2] , M
P0[5], A, I, M
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 14 of 52
Table 5. Pin Definitions - CY8C21434B/CY8C2163 4B 32-pin (QFN)[8]
Pin No. Type Name Description
Digital Analog
1I/O I, M P0[1] Analog column mux input, integrating input
2I/O M P2[7]
3I/O M P2[5]
4I/O MP2[3]
5I/O MP2[1]
6I/O M P3[3] In CY8C21434B part
6Power SMP SMP connection to required external components in CY8C21634B part
7I/O MP3[1] In CY8C21434B part
7Power VSS Ground connection in CY8C21634B part
8I/O MP1[7] I2C SCL
9I/O MP1[5] I2C SDA
10 I/O MP1[3]
11 I/O MP1[1] I2C SCL, ISSP-SCLK[9]
12 Power VSS Ground connection
13 I/O MP1[0] I2C SDA, ISSP-SDATA[9]
14 I/O MP1[2]
15 I/O MP1[4] Optional external clock inp ut (EXTCLK)
16 I/O MP1[6]
17 Input XRES Active high external reset with internal pull-down
18 I/O M P3[0]
19 I/O M P3[2]
20 I/O MP2[0]
21 I/O MP2[2]
22 I/O MP2[4]
23 I/O MP2[6]
24 I/O I, M P0[0] Analog column mux input
25 I/O I, M P0[2] Analog column mux input
26 I/O I, M P0[4] Analog column mux input
27 I/O I, M P0[6] Analog column mux input
28 Power VDD Supply voltage
29 I/O I, M P0[7] Analog column mux input
30 I/O I, M P0[5] Analog column mux input
31 I/O I, M P0[3] Analog column mux input, integrating input
32 Power VSS Ground connection
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes
8. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground,
it must be electrically floated and not connected to any other signal.
9. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 15 of 52
56-pin Part Pinout
The 56-Pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device.
Note This part is only used for in-circuit debuggin g. It is NOT available for production.
Figure 11. CY8C21001 56-pin PSoC Device
SSOP
156 Vdd
2
A I, P0[7] 55 P 0[6], AI
3
A I, P0[5] 54 P 0[4], AI
4
A I, P0[3] 53 P 0[2], AI
5
A I, P0[1] 52 P 0[0], AI
6
P2[7] 51 P2[6]
7
P2[5] 50 P2[4]
8
P2[3] 49 P2[2]
9P2[1] 48 P2[0]
10
NC 47 NC
11
NC 46 NC
12NC 45 P3[2]
13
NC 44 P3[0]
14OCDE 43 CCLK
15
OCDO 42 HCLK
16
SMP 41 XRES
17
Vss 40 NC
18
Vss 39 NC
19
P3[3] 38 NC
20
P3[1] 37 NC
21
NC 36 NC
22
NC 35 NC
23I2 C S CL , P1[7] 3 4 P1[6]
24
I2 C SD A, P 1 [5] 33 P 1[4], EXT CLK
25
NC 32 P1[2]
26
P1[3] 31 P1[0], I2C SDA, SDATA
27
S CL K , I2C SC L , P1[1] 30 NC
28Vss 29 NC
Vss
Table 6. Pin Definitions – CY8C21001 56-pin (SSOP)
Pin No. Type Pin Name Description
Digital Analog
1Power VSS Ground connection
2I/O I P0[7] Analog column mux input
3I/O I P0[5] Analog column mux input and column output
4I/O I P0[3] Analog column mux input and column output
5I/O I P0[1] Analog column mux input
6I/O P2[7]
7I/O P2[5]
8I/O I P2[3] Direct switched capacitor block input
9I/O I P2[1] Direct switched capacitor block input
10 NC No connection
11 NC No connection
12 NC No connection
13 NC No connection
14 OCD OCDE OCD even data I/O
15 OCD OCDO OCD odd data output
16 Power SMP SMP connection to required external components
17 Power VSS Ground connection
18 Power VSS Ground connection
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 16 of 52
19 I/O P3[3]
20 I/O P3[1]
21 NC No connection
22 NC No connection
23 I/O P1[7] I2C SCL
24 I/O P1[5] I2C SDA
25 NC No connection
26 I/O P1[3] IFMTEST
27 I/O P1[1] I2C SCL, ISSP-SCLK[10]
28 Power VSS Ground connection
29 NC No connection
30 NC No connection
31 I/O P1[0] I2C SDA, ISSP-SDATA[10]
32 I/O P1[2] VFMTEST
33 I/O P1[4] Optional external clock input (EXTCLK)
34 I/O P1[6]
35 NC No connection
36 NC No connection
37 NC No connection
38 NC No connection
39 NC No connection
40 NC No connection
41 Input XRES Active high external reset with internal pull-down
42 OCD HCLK OCD high-speed clock ou tput
43 OCD CCLK OCD CPU clock output
44 I/O P3[0]
45 I/O P3[2]
46 NC No connection
47 NC No connection
48 I/O I P2[0]
49 I/O I P2[2]
50 I/O P2[4]
51 I/O P2[6]
52 I/O I P0[0] Analog column mux input
53 I/O I P0[2] Analog column mux input and column output
54 I/O I P0[4] Analog column mux input and column output
55 I/O I P0[6] Analog column mux input
56 Power VDD Supply voltage
LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug.
Table 6. Pin Definitions – CY8C21001 56-pin (SSOP) (continued)
Pin No. Type Pin Name Description
Digital Analog
Note
10.These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 17 of 52
Register Reference
This chapter lists the registers of the CY8C21x34B PSoC device. For detailed register information, see the PSoC Technical Reference
Manual.
Register Conventions
The register conventions spe ci fic to this section are listed in Table 7.
Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The regi ster space is referre d to as I/O space and is di vided into
two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU _F) determines which bank the user is currently in. When the
XOI bit is set to 1, the user is in Bank 1.
Note In the following register mapping tables, blank fields are reserved and must not be accessed.
Table 7. Register Conventions
Convention Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 18 of 52
Table 8. Register Map 0 Table: User Space
Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access
PRT0DR 00 RW 40 ASE10CR0 80 RW C0
PRT0IE 01 RW 41 81 C1
PRT0GS 02 RW 42 82 C2
PRT0DM2 03 RW 43 83 C3
PRT1DR 04 RW 44 ASE11CR0 84 RW C4
PRT1IE 05 RW 45 85 C5
PRT1GS 06 RW 46 86 C6
PRT1DM2 07 RW 47 87 C7
PRT2DR 08 RW 48 88 C8
PRT2IE 09 RW 49 89 C9
PRT2GS 0A RW 4A 8A CA
PRT2DM2 0B RW 4B 8B CB
PRT3DR 0C RW 4C 8C CC
PRT3IE 0D RW 4D 8D CD
PRT3GS 0E RW 4E 8E CE
PRT3DM2 0F RW 4F 8F CF
10 50 90 CUR_PP D0 RW
11 51 91 STK_PP D1 RW
12 52 92 D2
13 53 93 IDX_PP D3 RW
14 54 94 MVR_PP D4 RW
15 55 95 MVW_PP D5 RW
16 56 96 I2C_CFG D6 RW
17 57 97 I2C_SCR D7 #
18 58 98 I2C_DR D8 RW
19 59 99 I2C_MSCR D9 #
1A 5A 9A INT_CLR0 DA RW
1B 5B 9B INT_CLR1 DB RW
1C 5C 9C DC
1D 5D 9D INT_CLR3 DD RW
1E 5E 9E INT_MSK3 DE RW
1F 5F 9F DF
DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RW
DBB00DR1 21 W AMUXCFG 61 RW A1 INT_MSK1 E1 RW
DBB00DR2 22 RW PWM_CR 62 RW A2 INT_VC E2 RC
DBB00CR0 23 # 63 A3 RES_WDT E3 W
DBB01DR0 24 # CMP_CR0 64 # A4 E4
DBB01DR1 25 W 65 A5 E5
DBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RW
DBB01CR0 27 # 67 A7 DEC_CR1 E7 RW
DCB02DR0 28 # ADC0_CR 68 # A8 E8
DCB02DR1 29 W ADC1_CR 69 # A9 E9
DCB02DR2 2A RW 6A AA EA
DCB02CR0 2B # 6B AB EB
DCB03DR0 2C # TMP_DR0 6C RW AC EC
DCB03DR1 2D W TMP_DR1 6D RW AD ED
DCB03DR2 2E RW TMP_DR2 6E RW AE EE
DCB03CR0 2F # TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 ACE00CR1 72 RW RDI0IS B2 RW F2
33 ACE00CR2 73 RW RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 ACE01CR1 76 RW RDI0RO1 B6 RW F6
37 ACE01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FA
3B 7B BB FB
3C 7C BC FC
3D 7D BD DAC_D FD RW
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are reserved and must not be accessed. # Access is bit specific.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 19 of 52
Table 9. Register Map 1 Table: Configuration Space
Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access
PRT0DM0 00 RW 40 ASE10CR0 80 RW C0
PRT0DM1 01 RW 41 81 C1
PRT0IC0 02 RW 42 82 C2
PRT0IC1 03 RW 43 83 C3
PRT1DM0 04 RW 44 ASE11CR0 84 RW C4
PRT1DM1 05 RW 45 85 C5
PRT1IC0 06 RW 46 86 C6
PRT1IC1 07 RW 47 87 C7
PRT2DM0 08 RW 48 88 C8
PRT2DM1 09 RW 49 89 C9
PRT2IC0 0A RW 4A 8A CA
PRT2IC1 0B RW 4B 8B CB
PRT3DM0 0C RW 4C 8C CC
PRT3DM1 0D RW 4D 8D CD
PRT3IC0 0E RW 4E 8E CE
PRT3IC1 0F RW 4F 8F CF
10 50 90 GDI_O_IN D0 RW
11 51 91 GDI_E_IN D1 RW
12 52 92 GDI_O_OU D2 RW
13 53 93 GDI_E_OU D3 RW
14 54 94 D4
15 55 95 D5
16 56 96 D6
17 57 97 D7
18 58 98 MUX_CR0 D8 RW
19 59 99 MUX_CR1 D9 RW
1A 5A 9A MUX_CR2 DA RW
1B 5B 9B MUX_CR3 DB RW
1C 5C 9C DC
1D 5D 9D OSC_GO_EN DD RW
1E 5E 9E OSC_CR4 DE RW
1F 5F 9F OSC_CR3 DF RW
DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RW
DBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RW
DBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW
23 AMD_CR0 63 RW A3 VLT_CR E3 RW
DBB01FN 24 RW CMP_GO_EN 64 RW A4 VLT_CMP E4 R
DBB01IN 25 RW 65 A5 ADC0_TR E5 RW
DBB01OU 26 RW AMD_CR1 66 RW A6 ADC1_TR E6 RW
27 ALT_CR0 67 RW A7 E7
DCB02FN 28 RW 68 A8 IMO_TR E8 W
DCB02IN 29 RW 69 A9 ILO_TR E9 W
DCB02OU 2A RW 6A AA BDG_TR EA RW
2B CLK_CR3 6B RW AB ECO_TR EB W
DCB03FN 2C RW TMP_DR0 6C RW AC EC
DCB03IN 2D RW TMP_DR1 6D RW AD ED
DCB03OU 2E RW TMP_DR2 6E RW AE EE
2F TMP_DR3 6F RW AF EF
30 70 RDI0RI B0 RW F0
31 71 RDI0SYN B1 RW F1
32 ACE00CR1 72 RW RDI0IS B2 RW F2
33 ACE00CR2 73 RW RDI0LT0 B3 RW F3
34 74 RDI0LT1 B4 RW F4
35 75 RDI0RO0 B5 RW F5
36 ACE01CR1 76 RW RDI0RO1 B6 RW F6
37 ACE01CR2 77 RW B7 CPU_F F7 RL
38 78 B8 F8
39 79 B9 F9
3A 7A BA FLS_PR1 FA RW
3B 7B BB FB
3C 7C BC FC
3D 7D BD DAC_CR FD RW
3E 7E BE CPU_SCR1 FE #
3F 7F BF CPU_SCR0 FF #
Blank fields are reserved and must not be accessed. # Access is bit specific.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 20 of 52
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C21x34B PSoC device. For up-to-date electrical
specifications, visit the Cypress web site at http://www.cypress.com.
Specifications are valid for –40 C TA 85 C and TJ 100 C as specified, except where note d.
Refer to Table 23 on page 27 for the electrical specifications for the IMO using SLIMO mode.
Absolute Maximum Ratings
Figure 12. Voltage versus CPU Frequenc y Figure 13. IMO Frequency Trim Options
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
CPU Frequency
Vdd Voltage
5.25
4.75
3.00
93 kHz 12 MHz 24 MHz
IMO Frequency
Vdd Voltage
3.60
6 MHz
SLIMO Mode = 0
SLIMO
Mode=0
2.40
SLIMO
Mode=1
SLIMO
Mode=1 SLIMO
Mode=1
2.40
3 MHz
Valid
Operating
Region
SLIMO
Mode=1
SLIMO
Mode=0
Table 10. Absolute Maximum Ratings
Symbol Description Min Typ Max Units Notes
TSTG Storage temperature –55 25 +100 °C Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C
degrade reliability.
TBAKETEMP Bake temperature –125 See
package
label
°C
tBAKETIME Bake time See
package
label
–72 Hours
TAAmbient temperature with power applied –40 –+85 °C
VDD Supply voltage on VDD relative to VSS –0.5 –+6.0 V
VIO DC input voltage VSS – 0.5 – VDD + 0.5 V
VIOZ DC voltage applied to tri-state VSS – 0.5 – VDD + 0.5 V
IMIO Maximum current into any port pin –25 –+50 mA
ESD Electrostatic discharge voltage 2000 – – V Human body model ESD.
LU Latch-up current – – 200 mA
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 21 of 52
Operating Temperature
DC Electrical Characteristics
DC Chip-Level Specifications
Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidan ce only.
Table 11. Operating Temperature
Symbol Description Min Typ Max Units Notes
TAAmbient temperature –40 –+85 °C
TJJunction temperature –40 –+100 °C The temperature rise from ambient to
junction is package specific. See
Table 36 on page 38. You must limit
the power consumption to comply
with this requirement.
Table 12. DC Chip-level Specifications
Symbol Description Min Typ Max Units Notes
VDD Supply voltage 2.40 –5.25 VSee Table 20 on page 25
IDD Supply current, IMO = 24 MHz – 3 4 mA Cond itions are VDD = 5.0 V,
TA = 25 °C, CPU = 3 MHz,
48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz
IDD3 Supply current, IMO = 6 MHz using
SLIMO mode. –1.2 2mA Conditions are VDD = 3.3 V,
TA = 25 °C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
IDD27 Supply current, IMO = 6 MHz using
SLIMO mode. –1.1 1.5 mA Conditions are VDD = 2.55 V,
TA = 25 °C, CPU = 3 MHz, clock
doubler disabled. VC1 = 375 kHz,
VC2 = 23.4 kHz, VC3 = 0.091 kHz
ISB27 Sleep (mode) current with POR, LVD,
sleep timer, WDT, and internal slow
oscillator active. Mid temperature
range.
–2.6 4µA VDD = 2.55 V, 0 °C TA 40 °C
ISB Sleep (mode) current with POR, LVD,
Sleep Timer, WDT, and internal slow
oscillator active.
–2.8 5µA VDD = 3.3 V, –40 °C TA 85 °C
VREF Reference voltage (Bandgap) 1.28 1.30 1.32 VTrimmed for appropriate VDD
VDD = 3.0 V to 5.25 V
VREF27 Reference voltage (Bandgap) 1.16 1.30 1.33 VTrimmed for appropriate VDD
VDD = 2.4 V to 3.0 V
AGND Analog ground VREF – 0.003 VREF VREF + 0.003 V
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 22 of 52
DC General-Purpose I/O Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only.
Table 13. 5 V and 3.3 V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull-up resistor 4 5.6 8 k
RPD Pull-down resistor 4 5.6 8 k
VOH High output level VDD – 1.0 – – V IOH = 10 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])
VOL Low output level – – 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V
(8 total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5]))
IOH High level source current 10 – – mA VOH = VDD – 1.0 V , see the limitations
of the total current in the note for VOH
IOL Low level sink current 25 – – mA VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VIL Input low level – – 0.8 V VDD = 3.0 to 5.25
VIH Input high level 2.1 – V VDD = 3.0 to 5.25
VHInput hysteresis –60 –mV
IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 µA
CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent
Temp = 25 °C
COUT Capacitive load on pins as output –3.5 10 pF Package and pin dependent
Temp = 25 °C
Table 14. 2.7 V DC GPIO Specifications
Symbol Description Min Typ Max Units Notes
RPU Pull-up resistor 4 5.6 8 k
RPD Pull-down resistor 4 5.6 8 k
VOH High output level VDD – 0.4 – – V IOH = 2.5 mA (6.25 T yp), VDD = 2.4 to
3.0 V (16 mA maximum, 50 mA Typ
combined IOH budget)
VOL Low output level – – 0.75 V IOL = 10 mA, VDD = 2.4 to 3.0 V
(90 mA maximum combined IOL
budget)
IOH High level source current 2.5 – – mA VOH = VDD – 0.4 V , see the limitations
of the total current in the note for VOH
IOL Low level sink current 10 – – mA VOL = 0.75 V, see the limitations of the
total current in the note for VOL
VIL Input low level – – 0.75 V VDD = 2.4 to 3.0
VIH Input high level 2.0 – – V VDD = 2.4 to 3.0
VHInput hysteresis – 90 – mV
IIL Input leakage (absolute value) – 1 – nA Gross tested to 1 µA
CIN Capacitive load on pins as input – 3.5 10 pF Package and pin dependent
Temp = 25 °C
COUT Capacitive load on pins as output – 3.5 10 pF Package and pin dependent
Temp = 25 °C
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 23 of 52
DC Operational Amplifier Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 15. 5 V DC Operatio nal Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value) – 2.5 1 5 mV
TCVOSOA Average input offset voltage drift – 10 – µV/°C
IEBOA Input leakage current (Port 0 analog pins
7-to-1) – 200 – pA Gross tested to 1 µA
IEBOA00 Input leakage current (Port 0, Pin 0 analog pin) – 50 – nA Gross tested to 1 µA
CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25 °C
VCMOA Common mode voltage range 0.0 – VDD – 1.0 V
GOLOA Open loop gain – 80 – dB
ISOA Amplifier supply current – 10 30 µA
Table 16. 3.3 V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value) – 2.5 15 mV
TCVOSOA Average input offset voltage drift – 10 – µV/°C
IEBOA Input leakage current (Port 0 analog pins) – 200 – pA Gross tested to 1 µA
IEBOA00 Input leakage current (Port 0, Pin 0 analog pin) – 50 – nA Gross tested to 1 µA
CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin depend ent.
Temp = 25 °C
VCMOA Common mode voltage range 0 – VDD –
1.0 V
GOLOA Open loop gain – 8 0 – dB
ISOA Amplifier supply current – 10 30 µA
Table 17. 2.7 V DC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
VOSOA Input offset voltage (absolute value) – 2.5 15 mV
TCVOSOA Average input offset voltage drift – 10 – µV/°C
IEBOA Input leakage current (Port 0 analog pins) – 200 – pA Gross tested to 1 µA
IEBOA00 Input leakage current (Port 0, Pin 0 analog pin) – 50 – nA Gross tested to 1 µA
CINOA Input capacitance (Port 0 analog pins) – 4.5 9.5 pF Package and pin dependent.
Temp = 25 °C
VCMOA Common mode voltage range 0 – VDD –
1.0 V
GOLOA Open loop gain – 80 – dB
ISOA Amplifier supply current – 10 30 µA
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 24 of 52
DC Switch Mode Pump Specifications
Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidan ce only.
Figure 14. Basic Switch Mode Pump Circuit
Battery C1
D1
+PSoC
Vdd
Vss
SMP
VBAT
L1
VPUMP
Table 18. DC Switch Mode Pump (SMP) Specifications
Symbol Description Min Typ Max Units Notes
VPUMP5V 5 V output voltage from pump 4.75 5.0 5.25 V Configured as in Note 11
Average, neglecting ripple
SMP trip voltage is set to 5.0 V
VPUMP3V 3.3 V output voltage from pump 3.00 3.25 3.60 V Configured as in Note 11
Average, neglecting ripple.
SMP trip voltage is set to 3.25 V
VPUMP2V 2.6 V output voltage from pump 2.45 2.55 2.80 V Configured as in Note 11
Average, neglecting ripple.
SMP trip voltage is set to 2.55 V
IPUMP Available output current
VBAT = 1.8 V, VPUMP = 5.0 V
VBAT = 1.5 V, VPUMP = 3.25 V
VBAT = 1.3 V, VPUMP = 2.55 V
5
8
8
–
–
–
–
–
–
mA
mA
mA
Configured as in Note 11
SMP trip voltage is set to 5.0 V
SMP trip voltage is set to 3.25 V
SMP trip voltage is set to 2.55 V
VBAT5V Input voltage range from battery 1.8 – 5.0 V Configured as in Note 11
SMP trip voltage is set to 5.0 V
VBAT3V Input voltage range from battery 1.0 – 3.3 V Configured as in Note 11
SMP trip voltage is set to 3.25 V
VBAT2V Input voltage range from battery 1.0 – 2.8 V Configured as in Note 11
SMP trip voltage is set to 2.55 V
VBATSTART Minimum input voltage from
battery to start pump 1.2 – – V Configured as in Note 11
0 C TA 100. 1.25 V at TA = –40 °C
VPUMP_Line Line regulation (over Vi range) – 5 – %V OConfigured as in Note 11
VO is the “VDD Value for PUMP Trip”
specified by the VM[2:0] setting in the DC
POR and LVD Specification, Table 20 on
page 25
VPUMP_Load Load regulation – 5 – %V OConfigured as in Note 11
VO is the “VDD Value for PUMP Trip”
specified by the VM[2:0] setting in the DC
POR and LVD Specification, Table 20 on
page 25
VPUMP_Ripple Output voltage ripple (depends
on cap/load) – 100 – mVpp Configured as in Note 11
Load is 5 mA
Note
11. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 14.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 25 of 52
DC Analog Mux Bus Specifications
Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
DC POR and LVD Specifications
Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
E3Efficiency 35 50 – % Configured as in Note 11
Load is 5 mA. SMP trip voltage is set to
3.25 V
E2Efficiency 35 80 – % For I load = 1mA, VPUMP = 2.55 V , VBAT = 1.3 V ,
10 µH inductor, 1 µF capacitor, and Schottky
diode
FPUMP Switching frequency – 1.3 – MHz
DCPUMP Switching duty cycle – 50 – %
Table 18. DC Switch Mode Pump (SMP) Specifications (continued)
Symbol Description Min Typ Max Units Notes
Table 19. DC Analog Mux Bus Specifications
Symbol Description Min Typ Max Units Notes
RSW Switch resistance to common analog bus – – 400
800 VDD 2.7 V
2.4 V VDD 2.7 V
RVDD Resistance of initialization switch to VDD – – 800
Table 20. DC POR and LVD Specifications
Symbol Description Min Typ Max Units Notes
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
VDD must be greate r than o r equ al
to 2.5 V during startup, the reset
from the XRES pin, or reset from
watchdog
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[12]
2.99[13]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
VPUMP0
VPUMP1
VPUMP2
VPUMP3
VPUMP4
VPUMP5
VPUMP6
VPUMP7
VDD value for pump trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
2.45
2.96
3.03
3.18
4.54
4.62
4.71
4.89
2.55
3.02
3.10
3.25
4.64
4.73
4.82
5.00
2.62[14]
3.09
3.16
3.32[15]
4.74
4.83
4.92
5.12
V
V
V
V
V
V
V
V
Notes
12.Always greater than 50 mV above VPPOR (PORLEV = 00) for falling suppl y.
13.Always greater than 50 mV above VPPOR (PORLEV = 01) for falling suppl y.
14.Always greater than 50 mV above VLVD0.
15.Always greater than 50 mV above VLVD3.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 26 of 52
DC Programming Specifications
Table 21 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
DC I2C Specifications
Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C
TA
85 °C, 3.0 V to 3.6 V and –40 °C
TA
85 °C, or 2.4 V to 3.0 V and –40 °C
TA
85 °C, respective ly . T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 21. DC Programming Specifications
Symbol Description Min Typ Max Units Notes
VDDP VDD for programming and erase 4.5 55.5 VThis specification applies to the
functional requirements of
external programmer tools
VDDLV Low VDD for verify 2.4 2.5 2.6 VThis specification applies to the
functional requirements of
external programmer tools
VDDHV High VDD for verify 5.1 5.2 5.3 VThis specification applies to the
functional requirements of
external programmer tools
VDDIWRITE Supply voltage for flash write operation 2.7 –5.25 VThis specification applies to this
device when it is executing
internal flash writes
IDDP Supply current during programming or verify – 5 25 mA
VILP Input low voltage during programming or
verify – – 0.8 V
VIHP Input high voltage during programmi ng or
verify 2.2 – – V
IILP Input current when applying VILP to P1[0] or
P1[1] during programming or verify – – 0.2 mA Driving internal pull-down resistor
IIHP Input current when applying VIHP to P1[0] or
P1[1] during programming or verify – – 1.5 mA Driving internal pull-down resistor
VOLV Outp ut low voltage during programming or
verify – – VSS + 0.75 V
VOHV Output high voltage during programming or
verify VDD – 1.0 – VDD V
FlashENPB Flash endurance (per block) 50,000[16] – – – Erase/write cycles per block
FlashENT Flash endurance (total)[17] 1,800,000 – – – Erase/write cycles
FlashDR Flash data retention 10 – – Years
Table 22. DC I2C Specifications[18]
Symbol Description Min Typ Max Units Notes
VILI2C Input low level – – 0.3 × VDD V 2.4 V VDD 3.6 V
– – 0.25 × VDD V4.75 V VDD 5.25 V
VIHI2C Input high level 0.7 × VDD – – V 2.4 V VDD 5.25 V
Notes
16.The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V,
and 4.75 V to 5.25 V.
17.A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between oper ations on 36 × 1 blocks of 50,000 maximum cycles each , 36×2
blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no
single block ever sees more than 50,000 cycles). For the full industr ial range, you must employ a temperature sensor user modul e (FlashTemp) and feed the result
to the temperature argu ment before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and W riting PSoC® Flash) for more information.
18.All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet th e above specs.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 27 of 52
AC Electrical Characteristics
AC Chip-Level Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 23. 5 V and 3.3 V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO24 IMO frequency for 24 MHz 23.4 24 24.6[19,20] MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 13 on
page 20. SLIMO mode = 0
FIMO6 IMO frequency for 6 MHz 5.5 66.5[19,20] MHz Trimmed for 5 V or 3.3 V
operation using factory trim
values. See Figure 13 on
page 20. SLIMO mode = 1
FCPU1 CPU frequency (5 V nominal) 0.091 24 24.6[19] MHz 24 MHz only for
SLIMO mode = 0
FCPU2 CPU frequency (3.3 V nominal) 0.091 12 12.3[20] MHz SLIMO mode = 0
FBLK5 Digital PSoC block frequency0(5 V nominal) 048 49.2[19,21] MHz Refer to AC Digital Block
Specifications on page 30
FBLK33 Digital PSoC block frequency (3.3 V nominal) 024 24.6[21] MHz
F32K1 ILO frequency 15 32 64 kHz
F32K_U ILO untrimmed frequency 5 – 100 kHz After a reset and before the
M8C start s to run, the ILO is
not trimmed. See the system
resets section of the PSoC
T echnical Reference Manual
for details on this timing
tXRST External reset pulse width 10 – – s
DC24M 24 MHz duty cycle 40 50 60 %
DCILO ILO duty cycle 20 50 80 %
St ep24M 24 MHz trim step size – 50 – kHz
Fout48M 48 MH z output frequency 46.8 48.0 49.2[19,20] MHz Trimmed. Using factory trim
values
FMAX Maximum frequency of signal on row input or
row output. – – 12.3 MHz
SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate durin g
power-up
tPOWERUP Time from end of POR to CPU executing
code –16 100 ms Power-up from 0 V. See the
System Resets section of the
PSoC Techn ical Reference
Manual
tjit_IMO 24-MHz IMO cycle-to-cycle jitter (RMS)[22] – 200 700 ps
24-MHz IMO long term N cycle-to-cycle jitter
(RMS)[22] – 300 900 ps N = 32
24-MHz IMO period jitter (RMS)[22] – 100 400 ps
Notes
19.4.75 V < VDD < 5.25 V.
20.3.0 V < VDD < 3.6 V . See application note AN2012 “Adjusting PSoC Microcontroller T rims for Dual Voltage-Range Operation” for information on trimming for operation
at 3.3 V.
21.See the individual user module datasheets for information on maximum fr equencies for user modules.
22.R efer to Cypress Jitter Specifications Application Note AN5054 “Understanding Dat asheet Jitter Specifications for Cypress Timing Products” at
www.cypress.com under Application Notes for more information.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 28 of 52
Table 24. 2.7 V AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
FIMO12 IMO frequency for 12 MHz 11.5 12012.7[23,24] MHz Trimmed for 2.7 V operation
using factory trim values.
See Figure 13 on page 20.
SLIMO mode = 1
FIMO6 IMO frequency for 6 MHz 5.5 66.5[23,24] MHz Trimmed for 2.7 V operation
using factory trim values.
See Figure 13 on page 20.
SLIMO mode = 1
FCPU1 CPU frequency (2.7 V nominal) 0.093 33.15[23] MHz 12 MHz only for
SLIMO mode = 0
FBLK27 Digital PSoC block frequency (2.7 V nominal) 012 12.5[23,24] MHz Refer to AC Digital Block
Specifications on page 30
F32K1 ILO frequency 832 96 kHz
F32K_U ILO untrimmed frequency 5 – 100 kHz After a reset and before the
M8C start s to run, the ILO is
not trimmed. See the System
Resets section of the PSoC
T echnical Reference Manual
for details on this timing
tXRST External reset pulse width 10 – – µs
DCILO IILO duty cycle 20 50 80 %
FMAX Maximum frequency of signal on row input or
row output. – – 12.3 MHz
SRPOWER_UP Power supply slew rate – – 250 V/ms VDD slew rate during
power-up
tPOWERUP Time from end of POR to CPU executing
code –16 100 ms Power-up from 0 V. See the
System Resets section of the
PSoC Technical Reference
Manual.
tjit_IMO 12 MHz IMO cycle-to-cycle jitter (RMS)[25] –400 1000 ps
12 MHz IMO long term N cycle-to-cycle jitter
(RMS)[25] –600 1300 ps N = 32
12 MHz IMO period jitter (RMS)[25] –100 500 ps
Note
23.2.4 V < VDD < 3.0 V.
24.See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” available at http://www.cypress.com for information on
maximum frequency for user modules.
25.R efer to Cypress Jitter Specifications Application Note AN5054 “Understanding Dat asheet Jitter Specifications for Cypress Timing Products” at
www.cypress.com under Application Notes for more information.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 29 of 52
AC General Purpose I/O Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Figure 15. GPIO Timing Diagram
AC Operational Amplifier Specifications
Table 27 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively. T ypical parameters
are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 25. 5 V and 3.3 V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO operating frequency 0 – 12 MHz Normal strong mode
TRiseF Rise time, normal strong mode, Cload = 50 pF 3 – 18 ns VDD = 4.5 to 5.25 V, 10% to 90%
TFallF Fall time, normal strong mode, Cload = 50 pF 2 – 18 ns VDD = 4.5 to 5.25 V, 10% to 90%
TRiseS Rise time, slow strong mode, Cload = 50 pF 727 –ns VDD = 3 to 5.25 V, 10% to 90%
TFallS Fall time, slow strong mode, Cload = 50 pF 722 –ns VDD = 3 to 5.25 V, 10% to 90%
Table 26. 2.7 V AC GPIO Specifications
Symbol Description Min Typ Max Units Notes
FGPIO GPIO operating frequency 0 – 3 MHz Normal strong mode
TRiseF Rise time, normal strong mode, Cload = 50 pF 6 – 50 ns VDD = 2.4 to 3.0 V, 10% to 90%
TFallF Fall time, normal strong mode, Cload = 50 pF 6 – 50 ns VDD = 2.4 to 3.0 V, 10% to 90%
TRiseS Rise time, slow strong mode, Cload = 50 pF 18 40 120 ns VDD = 2.4 to 3.0 V, 10% to 90%
TFallS Fall time, slow strong mode, Cload = 50 pF 18 40 120 ns VDD = 2.4 to 3.0 V, 10% to 90%
TFallF
TFallS
TRiseF
TRiseS
90%
10%
GPIO
Pin
Output
Voltage
Table 27. AC Operational Amplifier Specifications
Symbol Description Min Typ Max Units Notes
TCOMP Comparator mode response time, 50 mV
overdrive – – 100
200 ns
ns VDD 3.0 V
2.4 V < VDD <3.0 V
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 30 of 52
AC Digital Block Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 28. 5 V and 3.3 V AC Digital Block Specifications
Function Description Min Typ Max Unit Notes
All functions Block input clock frequency
VDD 4.75 V – – 49.2 MHz
VDD < 4.75 V – – 24.6 MHz
Timer Inp ut clock frequency
No capture, VDD 4.75 V – – 49.2 MHz
No capture, VDD < 4.75 V – – 24.6 MHz
With capture – – 24.6 MHz
Capture pulse width 50[26] – – ns
Counter Input clock frequency
No enable input, VDD 4.75 V – – 49.2 MHz
No enable input, VDD < 4.75 V – – 24.6 MHz
With enable input – – 24.6 MHz
Enable input pulse width 50[26] – – ns
Dead Band Kill pulse width
Asynchronous restart mode 20 – – ns
Synchronous restart mode 50[26] – – ns
Disable mode 50[26] – – ns
Input clock frequency
VDD 4.75 V – – 49.2 MHz
VDD < 4.75 V – – 24.6 MHz
CRCPRS
(PRS Mode) Input clock frequency
VDD 4.75 V – – 49.2 MHz
VDD < 4.75 V – – 24.6 MHz
CRCPRS
(CRC Mode) Input clock frequency – – 24.6 MHz
SPIM Input clock frequency – – 8.2 MHz The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz The input clock is the SPI SCLK in SPIS mode.
Width of SS_negated between
transmissions 50[26] – – ns
Transmitter Input clock frequency The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits – – 49.2 MHz
VDD 4.75 V, 1 stop bit – – 24.6 MHz
VDD < 4.75 V – – 24.6 MHz
Receiver Input clock frequency The baud rate is equal to the input clock frequency
divided by 8.
VDD 4.75 V, 2 stop bits – – 49.2 MHz
VDD 4.75 V, 1 stop bit – – 24.6 MHz
VDD < 4.75 V – – 24.6 MHz
Note
26.50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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Document Number: 001-67345 Rev. *G Page 31 of 52
AC External Clock Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters are measured at 5 V,
3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 29. 2.7 V AC Digital Block Specifications
Function Description Min Typ Max Units Notes
All
functions Block input clock frequency – – 12.7 MHz 2.4 V < VDD < 3.0 V
Timer C apture pulse width 100[27] – – ns
Input clock frequency, with or without capture – – 12.7 MHz
Counter Enable input pulse width 100 – – ns
Input clock frequency, no enable input – – 12.7 MHz
Input clock frequency, enable input – – 12.7 MHz
Dead Band Kill pulse width:
Asynchronous restart mode 20 – – ns
Synchronous restart mode 100 – – ns
Disable mode 100 – – ns
Input clock frequency – – 12.7 MHz
CRCPRS
(PRS Mode) Input clock frequency – – 12.7 MHz
CRCPRS
(CRC Mode) Input clock frequency – – 12.7 MHz
SPIM Input clock frequency – – 6.35 MHz The SPI serial clock (SCLK)
frequency is equal to the input
clock frequency divided by 2.
SPIS Input clock (SCLK) frequency – – 4.1 MHz
Width of SS_ Negated between transmissions 100 – – ns
Transmitter Input clock frequency – – 12.7 MHz T he baud rate is equal to the
input clock frequency divided by
8.
Receiver Input clock frequency – – 12.7 MHz The baud rate is eq ual to the
input clock frequency divided by
8.
Table 30. 5 V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency 0.093 –24.6 MHz
–High period 20.6 –5300 ns
–Low period 20.6 – – ns
–Power-up IMO to switch 150 – – µs
Note
27.100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period).
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Table 31. 3.3 V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU clock divide by 1 0.093 –12.3 MHz Maximum CPU frequency is 12 MHz
at 3.3 V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements
FOSCEXT Frequency with CPU clock divide by 2 or
greater 0.186 –24.6 MHz If the frequency of the external clock
is greater than 12 MHz, the CPU
clock divider must be set to 2 or
greater . In this case, the CPU clock
divider ensures that the fifty percent
duty cycle requirement is met
–High period with CPU clock divide by 1 41.7 –5300 ns
–Low period with CPU clock divide by 1 41.7 – – ns
–Power-up IMO to switch 150 – – µs
Table 32. 2.7 V AC External Clock Specifications
Symbol Description Min Typ Max Units Notes
FOSCEXT Frequency with CPU clock divide by 1 0.093 –3.080MHz Maximum CPU frequency is 3 MHz
at 2.7 V. With the CPU clock divider
set to 1, the external clock must
adhere to the maximum frequency
and duty cycle requirements
FOSCEXT Frequency with CPU clock divide
by 2 or greater 0.186 –6.35 MHz If the frequency of the external clock
is greater than 3 MHz, the CPU clock
divider must be set to 2 or greater. In
this case, the CPU clock divider
ensures that the fifty percent duty
cycle requirement is met
–High period with CPU clock divide by 1 160 –5300 ns
–Low period with CPU clock divide by 1 160 – – ns
–Power-up IMO to switch 150 – – µs
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 33 of 52
AC Programming Specifications
Table 33 lists the guaranteed maximum and minimum specifications for the voltage and temperature ran ges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C T A 85 °C, respectively. T ypical p arameters are measured at 5 V, 3.3 V, or 2.7 V
at 25 °C and are for design guidance only.
AC I2C Specifications
The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, 3.0 V to 3.6 V and –40 °C TA 85 °C, or 2.4 V to 3.0 V and –40 °C TA 85 °C, respectively.
Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only.
Table 33. AC Programming Specifications
Symbol Description Min Typ Max Units Notes
TRSCLK Rise time of SCLK 1 – 20 ns
TFSCLK Fall time of SCLK 1 – 20 ns
TSSCLK Data setup time to falling edge of SCLK 40 – – ns
THSCLK Data hold time from falling edge of SCLK 40 – – ns
FSCLK Frequency of SCLK 0 – 8 MHz
TERASEB Flash erase time (block) –10 –ms
TWRITE Flash block write time –40 –ms
TDSCLK Data out delay from falling edge of SCLK – – 45 ns 3.6 VDD
TDSCLK3 Data out delay from falling edge of SCLK – – 50 ns 3.0 VDD 3.6
TDSCLK2 Data out delay from falling edge of SCLK – – 70 ns 2.4 VDD 3.0
TERASEALL Flash erase time (Bulk) –20 –ms Erase all blocks and protection
fields at once
TPROGRAM_HOT Flash block erase + flash block write time – – 100[28] ms 0 °C Tj 100 °C
TPROGRAM_COLD Flash block erase + flash block write time – – 200[28] ms –40 °C Tj 0 °C
Table 34. AC Characteristics of the I 2C SDA and SCL Pins for VDD 3.0 V
Symbol Description Standard M ode Fast Mode Units
Min Max Min Max
FSCLI2C SCL clock frequency 0100 0400 kHz
THDSTAI2C Hold time (repeated) start condition. After this
period, the first clock pulse is generated 4.0 –0.6 –µs
TLOWI2C Low period of the SCL clock 4.7 –1.3 –µs
THIGHI2C High period of the SCL clock 4.0 –0.6 –µs
TSUSTAI2C Setup time for a repeated start condition 4.7 –0.6 –µs
THDDATI2C Data hold time 0 – 0 – µs
TSUDATI2C Data setup time 250 –100[29] –ns
TSUSTOI2C Setup time for stop condition 4.0 –0.6 –µs
TBUFI2C Bus free time between a stop and start
condition 4.7 –1.3 –µs
TSPI2C Pulse width of spikes suppressed by the input
filter. – – 0 50 ns
Notes
28.For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC® Flash) for more information.
29.A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but it must meet the requir ement TSU;DAT 250 ns. This is automatically the case if
the device does not stre tch the LOW p eriod of the SCL signa l. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA
line Trmax + TSU;DAT = 1000 + 250 = 1250 ns (according to the S tandard-Mode I2C-bu s specification) before the SCL line is released.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 34 of 52
Figure 16. Definition for Timing for Fast/Standard Mode on the I2C Bus
Table 35. 2.7 V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported)
Symbol Description Standard Mode Fast Mode Units
Min Max Min Max
FSCLI2C SCL clock frequency 0100 – – kHz
THDSTAI2C Hold time (repeated) start condition. After this
period, the first clock pulse is generated. 4.0 – – – µs
TLOWI2C Low period of the SCL clock 4.7 – – – µs
THIGHI2C High period of the SCL clock 4.0 – – – µs
TSUSTAI2C Setup time for a repeated start condition 4.7 – – – µs
THDDATI2C Data hold time 0 – – – µs
TSUDATI2C Data setup time 250 – – – ns
TSUSTOI2C Setup time for stop condition 4.0 – – – µs
TBUFI2C Bus free time between a stop and start
condition 4.7 – – – µs
TSPI2C Pulse width of spikes are suppressed by the
input filter. – – – – ns
I2C_SDA
I2C_SCL
SSr SP
TBUFI2C
TSPI2C
TSUSTOI2C
TSUSTAI2C
TLOWI2C
THIGHI2C
THDDATI2C
THDSTAI2C
TSUDATI2C
START Condition Repeated START Condition STOP Condition
CY8C21x34B
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Packaging Information
This section shows the packaging specifications for the CY8C21x34B PSoC device with the thermal impedances for each package.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Figure 17. 16-pin SOIC (150 Mils) Package Outlin e, 51-85068
Figure 18. 20-pin SSOP (210 Mils) Package Outline, 51-85077
51-85068 *E
51-85077 *F
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 36 of 52
Figure 19. 28-pin SSOP (210 Mils) Package Outline, 51-85079
Figure 20. 32-pin QFN (5 × 5 × 1.0 mm) LT32B (3.5 × 3.5) E-Pad (Sawn) Package Outline, 001-30999
51-85079 *F
001-30999 *D
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Document Number: 001-67345 Rev. *G Page 37 of 52
Figure 21. 32-pin QFN (5 × 5 × 0.55 mm) 1.3 × 2.7 E-Pad (Sawn Type) Package Outline, 001-48913
Important Note For information on the preferred dimensions for mounting QFN packages, see the following application note, Design
Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devi ces – AN72845 available at http://www.cypress.com.
Figure 22. 56-pin SSOP (300 Mils) Package Outline, 51-85062
001-48913 *D
51-85062 *F
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 38 of 52
Thermal Impedances
Solder Reflow Peak Temperature
Table 37 lists the maximum solder reflow peak temperatures to achieve good solderability. Thermal ramp rate during preheat should
be 3 °C/s or lower.
Table 36. Thermal Impedances per Package
Package Typical JA [30] Typical JC
16-pin SOIC 123 °C/W 55 °C/W
20-pin SSOP 117 °C/W 41 °C/W
28-pin SSOP 96 °C/W 39 °C/W
32-pin QFN[31] 5 × 5 mm 0.60 Max 27 °C/W 15 °C/W
32-pin QFN[31] 5 × 5 mm 0.93 Max 22 °C/W 12 °C/W
56-pin SSOP 48 °C/W 24 °C/W
Table 37. Solder Reflow Pea k Temperature
Package Maximum Peak Temperature Time at Maximum Temperature
16-pin SOIC 260 °C 30 s
20-pin SSOP 260 °C 30 s
28-pin SSOP 260 °C 30 s
32-pin QFN 260 °C 30 s
56-pin SSOP 260 °C 30 s
Notes
30.TJ = TA + Power × JA
31.To achieve the thermal impedance specified for the QFN package, refer to Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices
– AN72845 available at http://www.cypress.com.
32.Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5C with Sn-Pb or 245 ± 5 C with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 39 of 52
Development Tool Selection
This section presents the development tools available for all
current PSoC device families including the CY8C21x34B family.
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer, used to generate PSoC firmware app lications.
PSoC Designer is available free of cost at
http://www.cypress.com and includes a free C compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or operates
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube In-Circuit Emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store.
CY3280-BK1 Universal CapSense Controller - Basic Kit 1
The CY3280-BK1 Universal CapSense Controller Kit is designed
for easy prototyping and debug of CapSense designs with
pre-defined control circuitry and plug-in hardware. The kit comes
with controller boards for the CY8C20x34 and CY8C21x34
PSoC devices as well as a breadbo ard module an d a button(5 )
/ slider module.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with
PSoC Designer. This kit supports in-circuit emulation, and the
software interface allows you to run, halt, and single step the
processor, and view the content of specific memory locations.
Advance emulation features also supported through PSoC
Designer. The kit includes:
■PSoC Designer software CD
■ICE-Cube in-circuit emulator
■ICE Flex-Pod for CY8C29x66 family
■Cat-5 adapter
■Mini-Eval programming board
■110 ~ 240 V power supply, Euro-Plug adapter
■iMAGEcraft C compiler
■ISSP cable
■USB 2.0 cable and Blue Cat-5 cable
■Two CY8C29466-24PXI 28-PDIP chip samples
Evaluation Tools
All evaluation tools can be pu rchased from the Cypress Online
Store.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows you to program PSoC devices
through the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
through a provided USB 2.0 cable. Th e kit includes:
■MiniProg programming unit
■MiniEval socket programming and evaluation board
■28-Pin CY8C29466-24PXI PDIP PSoC device sample
■28-Pin CY8C27443-24PXI PDIP PSoC device sample
■PSoC Designer software CD
■Getting S tarted guide
■USB 2.0 cable
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of
breadboarding space to meet all of your e valuation needs. The
kit includes:
■Evaluation board with LCD module
■MiniProg programming unit
■Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples
■PSoC Designer software CD
■Getting S tarted guide
■USB 2.0 cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a
development board for the CY8C24794-24LFXI PSoC device.
The board includes both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator
and plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■PSoCEvalUSB board
■LCD module
■MIniProg programming unit
■Mini USB cable
■PSoC Designer and example projects CD
■Getting S tarted guide
■Wire pack
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 40 of 52
Device Programmers
All device programmers can be purchased from the Cypress Online Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■Modular programmer base
■Three programming module cards
■MiniProg programming unit
■PSoC Designer software CD
■Getting S tarted guide
■USB 2.0 cable
Accessories (Emulation and Programming)
Table 38. Emulation and Programmin g Acc essories
Part Number Pin Package Flex-Pod Kit[33] Foot Kit[34] Adapter
CY8C21234B-24SXI 16-Pin SOIC CY3250-21X34 CY3250-16SOIC-FK Adapters can be found at
http://www.emulation.com.
CY8C21334B-24PVXI 20-Pin SSOP CY3250-21X34 CY3250-20SSOP-FK
CY8C21534B-24PVXI 28-Pin SSOP CY3250-21X34 CY3250-28SSOP-FK
Notes
33.Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods.
34.Foot kit includes surface mount feet that can be soldered to the target PCB.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 41 of 52
Ordering Information
Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Ordering Code Definitions
Package
Ordering
Code
Flash
(Bytes)
SRAM
(Bytes)
Switch Mode
Pump
Temperature
Range
Digital
Blocks
Analog
Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
16-Pin (150-Mil ) SOIC CY8C21234B-24SXI 8 K 512 Yes –40 °C to +85 °C 4 4 12 12[35] 0No
16-Pin (150-Mil ) SOIC
(Tape and Reel) CY8C21234B-24SXIT 8 K 512 Yes –40 °C to +85 °C 4 4 12 12[35] 0No
20-Pin (210-Mil ) SS OP CY8C21334B-24PVXI 8 K 512 No –40 °C to +85 °C 4 4 16 16[35] 0Yes
20-Pin (210-Mil ) SSOP
(Tape and Reel) CY8C21334B-24PVXIT 8 K 512 No –40 °C to +85 °C 4 4 16 16[35] 0Yes
28-Pin (210-Mil ) SS OP CY8C21534B-24PVXI 8 K 512 No –40 °C to +85 °C 4 4 24 24[35] 0Yes
28-Pin (210-Mil ) SSOP
(Tape and Reel) CY8C21534B-24PVXIT 8 K 512 No –40 °C to +85 °C 4 4 24 24[35] 0Yes
32-Pin (5 × 5 mm 1.00 max)
Sawn QFN CY8C21434B-24LTXI 8 K 512 No –40 °C to +85 °C 4 4 28 28[35] 0Yes
32-Pin (5 × 5 mm 1.00 max)
Sawn QFN [36] (Tape and
Reel)
CY8C21434B-24LTXIT 8 K 512 No –40 °C to +85 °C 4 4 28 28[35] 0Yes
32-Pin (5 × 5 mm 0.60 max)
Thin Sawn QFN CY8C21434B-24LQXI 8 K 512 No –40 °C to +85 °C 4 4 28 28[35] 0Yes
32-Pin (5 × 5 mm 0.60 max)
Thin Sawn QFN
(Tape and Reel)
CY8C21434B-24LQXIT 8 K 512 No –40 °C to +85 °C 4 4 28 28[35] 0Yes
56-Pin OCD SSOP CY8C21001-24PVXI 8 K 512 Yes –40 °C to +85 °C 4 4 26 26[35] 0Yes
CY
Mark eting Code: 8 = Cypr ess PSoC
8C
Family Code
Technology Code: C = CMOS
Company ID:CY = Cypress
21
Part Numb er
Speed: 24 MHz
xx
xxxx-24
Package Type: Thermal Rating:
PX = PDI P Pb-fre e C = Com m e rcial
SX = SOIC Pb-free I = Industrial
PVX = SSOP Pb-free E = Extended
LFX/ LKX/LTX/LQX = QFN Pb- f ree
Notes
35.All Digital I/O Pins also connect to the common analog mux.
36.Refer to the section 32-pin Part Pinout on page 13 for pin differences.
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Document Number: 001-67345 Rev. *G Page 42 of 52
Acronyms
Table 39 lists the acronyms that are used in this document.
Reference Document s
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34 B,
CY8C21x23, CY7C64215, CY7C603 xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash - AN2015 (001-40459)
Design Guidelines for Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845 (001-72845) available at
http://www.cypress.com.
Table 39. Acrony ms Used in this Datasheet
Acronym Description Acronym Description
AC alternating current MIPS mi llion instructions per second
ADC analog-to-digital converter OCD on-chip debug
API application programming interface PCB pr inted circuit board
CMOS complementary metal oxide semiconductor PDIP plastic dual-in-line package
CPU central processing unit PGA programmable gai n amplifier
CRC cyclic redundancy check PLL phase-locked loop
CT continuous time POR power on reset
DAC digit al-to-analog converter PPOR precision power on reset
DC direct current PRS pseudo-random sequence
DTMF du al-tone multi-frequency PSoC®Programmable System-on-Chip
ECO external crystal oscillator PWM pulse width modulator
EEPROM electrically erasable programmable read-only
memory QFN quad flat no leads
GPIO general purpose I/O RTC real time clock
ICE in-circuit emulator SAR successive approximation
IDE integrated development environment SC sw itched capacitor
ILO internal low speed oscillator SLIMO slow IMO
IMO internal main oscillator SMP switch-mode pump
I/O input/output SOIC small-outline integrated circuit
IrDA infrared data association SPITM serial peripheral interface
ISSP in-system serial programming SRAM static random access memory
LCD liquid crystal display SROM supervisory read only memo ry
LED light-emitting diode SSOP shrink sma ll-outline package
LPC low power comparator UART universal asynchronous receiver / transmitter
LVD low voltage detect USB universal serial bus
MAC multiply-accumulate WDT watchdog timer
MCU microcontroller unit XRES external reset
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 43 of 52
Document Conventions
Units of Measure
Table 40 lists the units of measures.
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Table 40. Units of Measure
Symbol Unit of Measure Symbol Unit of Meas ure
kB 1024 bytes µH microhenry
dB decibels µs microsecond
°C degree Celsius ms millisecond
µF microfarad ns nanosecond
fF femto farad ps picosecond
pF picofarad µV microvolts
kHz kilohertz mV millivolts
MHz megahertz mVpp millivolts peak-to-peak
rt-Hz root hertz nV nanovolts
kkilohm V volts
ohm µW microwatts
µA microampere W watt
mA milliampere mm millimeter
nA nanoampere ppm parts per million
pA pikoampere % percent
mH millihenry
Glossary
active high 1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
(ADC) A device that changes an analog signal to a digital signal of corresponding magnitude. Typically , an ADC converts
a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create
software applications.
asynchronous A signal whose data is acknowledged or acted upon immediate ly, irrespective of any clock signal.
bandgap
reference A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth 1. The frequency range of a message or information proc essing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
CY8C21x34B
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bias 1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block 1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another . Usually refers to an area reserved for IO operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler A program that translates a high level language, such as C, into machine lang uage.
configuration
space In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. T ypically a piezoelectric crystal is less
sensitive to ambient te mperature than other circuit components.
cyclic redundancy
check (CRC) A calculation used to detect errors in data communications, typically performed using a linear feedback shift
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus A bi-directional set of signals used by a computer to convey informa ti on from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step throug h the firmware one step at a time, set break points, and
analyze memory.
dead band A period of time when neither of two or more signals are in their active state or in transition.
digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter , CRC gener ator,
pseudo-random number generator, or SPI.
digital-to-analog
(DAC) A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)
converter performs the reverse ope ration.
Glossary (continued)
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 45 of 52
duty cycle The relationship of a clock period high time to its low time, expressed as a percent.
emulator Du plicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
External Reset
(XRES) An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
Flash An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
OFF.
Flash block The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash
space that may be protected. A Flash block holds 64 bytes.
frequency The number of cycles or events per unit of time, for a periodic function.
gain The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated
Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in
the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building
control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with
resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt A suspension of a process, such as the execution of a computer program, caused by an even t external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR) A block of code that normal code exec ution is diverted to when the M8C receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
jitter 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variatio ns of one or more signal characteristi c s, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect
(LVD) A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.
M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the Flash, SRAM, and register space.
master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
Glossary (continued)
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 46 of 52
microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal The reference to a circuit containing both an alog and digital techniques and components.
modulator A device that imposes a signal on a carrier.
noise 1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator A circuit that may be crystal controlled and is used to generate a clock frequency.
parity A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
Phase-locked
loop (PLL) An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts The pin number assignment: the relation between th e logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port A group of pins, usually eight.
Power on reset
(POR) A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC® Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
modulator (PWM) An output in the form of duty cycle which varies as a function of the app lied measurement
RAM An acronym for random access memory. A data-storage device from which data can be read out and new data
can be writte n in.
register A storage device with a specific capacity, such as a bit or byte.
reset A means of bringing a system back to a know state. See hardware reset and software reset.
ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be writte n in.
serial 1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
Glossary (continued)
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 47 of 52
shift register A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM An acronym for st atic random access memory . A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be acces sed in normal user code ,
operating from Flash.
stop bit A signal following a character or block that prepares the receiving device to recei v e the next character or block.
synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART A UART or universal asynchronous receiver-transmitter translate s between parallel bits of data and serial bits.
user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD A name for a power net meaning ‘voltage drain’. The most positive power supply signal. Usually 5 V or 3.3 V.
VSS A name for a power net meaning ‘voltage source’. The most negative power supply signal.
watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Glossary (continued)
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 48 of 52
Errata
This section describes the errata for the PSoC® Programmable System-on-Chip CY8C21X34. Details include errata trigger conditions,
scope of impact, available workarounds, and silicon revision applicability.
Contact your local Cypress Sales Representative if you have questions.
Part Numbers Af fe ct ed
CY8C21X34 Qualification Status
Product Status: Production
Part Number Ordering Information
CY8C21X34 CY8C21234-24SXI
CY8C21234-24SXIT
CY8C21334-24PVXI
CY8C21334-24PVXIT
CY8C21534-24PVXI
CY8C21534-24PVXIT
CY8C21434-24LFXI
CY8C21434-24LFXIT
CY8C21434-24LKXI
CY8C21434-24LKXIT
CY8C21634-24LFXI
CY8C21634-24LFXIT
CY8C21434-24LTXI
CY8C21434-24LTXIT
CY8C21434-24LQXI
CY8C21434-24LQXIT
CY8C21634-24LTXI
CY8C21634-24LTXIT
CY8C21001-24PVXI
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 49 of 52
CY8C21X34 Errata Summary
The following table defines the errata applicability to available CY8C21X34 family devices. An "X" indicates that the errata pertains to
the selected device.
Note Errata items, in the table below, are hyperlinked. Click on any item entry to jump to its description.
1. Internal Main Oscillator (IMO) To lerance Deviation at Tempe rature Extremes
■Problem Definition
Asynchronous Digital Communications Interfaces may fail framing beyond 0 °C to 70 °C. This problem does not affect
end-product usage between 0 °C and 70 °C.
■Parameters Affected
The IMO frequency tolerance. The worst case deviation wh en operated below 0 °C and ab ove +70 °C and within th e upper
and lower datasheet temperature range is ±5%.
■Trigger Condition(S)
The asynchronous Rx/Tx clock source IMO frequency tolerance may deviate beyond the datasheet limit of ±2.5% when
operated beyond the temperature range of 0 °C to +70 °C.
■Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■Workaround
Implement a quartz crystal stabilized clock source on at least one end of the asynchronous digital communications interface.
■Fix Status
No fix is currently planned.
2. I2C Errors
■Problem Definition
The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is
transitioning in to or out of sleep mode.
■Parameters Affected
Affects reliability of I2C communication to device, between I2C master, and third party I2C slaves.
■Trigger Condition(S)
Triggered by transitions into and out of the device's sleep mode.
■Scope of Impact
This problem may affect UART, IrDA, and FSK implementations.
■Workaround
Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I 2C block from the
bus prior to going to sl eep modes. I2C transactions d uring sleep are supported by a protocol in which the master wakes the
device prior to the I2C transaction
■Fix Status
Will not be fixed.
Items Part Number Silicon Revision Fix Status
[1.]. Internal Main Oscillator (IMO)
Tolerance Deviation at Temperature
Extremes
CY8C21X34 ANo fix is currently planned.
[2]. I2C Errors CY8C21X34 ANo fix is currently pla nned.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 50 of 52
Document History Page
Document Title: CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™
Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity
Document Number: 001-67345
Revision ECN Orig. of
Change Submission
Date Description of Change
** 3169205 YVA 02/16/2011 New data sheet.
*A 3247292 YVA 05/11/2011 Updated Packaging In formation.
Post to external web.
*B 3846480 SRLI 12/19/2012 Updated Features.
Updated Packaging Information:
spec 51-85062 – Changed Revision from *D to *F.
spec 001-48913 – Changed Revision from *B to *C.
spec 001-44368 – Changed Revision from *B to *C.
spec 001-30999 – Changed Revision from *C to *D.
spec 51-85068 – Changed Revision from *D to *E.
Updated Ordering Information (Updated part numbers).
*C 3894458 SRLI 02/09/2013 Update d Document Title to read as “CY8C21x34B, PSoC® Programmable
System-on-Chip™ CapSense® Controller with SmartSense™ Auto-tu ning
1–21 Buttons, 0–4 Sliders, Proximity”.
Updated Packaging Information (Updated Solder Reflow Peak Temperature
(Changed Time at Maximum Temperature from 20 s to 30 s in Table 37)).
*D 4297481 DCHE 03/04/2014 Updated Development Tools:
Added hyperlink for “PSoC Designer™”.
Updated PSoC Designer Software Subsystems:
Updated In-Circuit Emulator:
Added hyperlink for “in-circuit emulator” in description.
Updated Development Tool Selection:
Updated Software:
Updated PSoC Designer:
Updated hyperlinks in description.
Updated PSoC Programmer:
Updated hyperlinks in description.
Updated Development Kits:
Updated description.
Updated Evaluation Tools:
Updated CY3210-MiniProg1:
Updated hyperlinks in description.
Updated CY3214-PSoCEvalUSB:
Updated hyperlinks in description.
Updated Device Programmers:
Updated CY3216 Modular Programmer:
Updated hyperlinks in description.
Updated Packaging Information:
spec 001-44368 – Changed Revision from *C to *D.
spec 001-48913 – Changed Revision from *C to *D.
Updated to new te mplate.
Completing Sunset Review.
CY8C21x34B
Document Number: 001-67345 Rev. *G Page 51 of 52
*E 4476297 DCHE /
ASRI 08/28/2014 Replaced references of “Application Notes for Surface Mount Assembly of
Amkor’s MicroLeadFrame (MLF) Packages” with “Design Guidelines for
Cypress Quad Flat No Extended Lead (QFN) Packaged Devices – AN72845”
in all instances across the document.
Added More Information.
Added PSoC Designer.
Removed “Getting Started”.
Updated Electrical Specifications:
Updated AC Electrical Characteristics:
Updated AC Operational Amplifier Specifications:
Updated Table 27:
Replaced VCC with VDD.
Updated Packaging Information:
Removed spec 001-44368 *D.
Updated Development Tool Selection:
Updated Device Programmers:
Removed “CY3207ISSP In-System Serial Programmer (ISSP)”.
Updated Ordering Information (Updated part numbers).
*F 4670626 DCHE 02/25/2015 Added Errata and references to errata items on page 1.
*G 5617615 DCHE 02/03/2017 Updated Packaging Info rmation:
spec 51-85077 – Changed Revision from *E to *F.
spec 51-85079 – Changed Revision from *E to *F.
Updated Reference Documents:
Removed spec 001-17397 and spec 001-14503 as both specs are obsolete.
Updated to new te mplate.
Completing Sunset Review.
Document History Page (continued)
Document Title: CY8C21x34B, PSoC® Programmable System-on-Chip™ CapSense® Controller with SmartSense™
Auto-tuning 1–21 Buttons, 0–4 Sliders, Proximity
Document Number: 001-67345
Revision ECN Orig. of
Change Submission
Date Description of Change
Document Number: 001-67345 Rev. *G Revised February 3, 2017 Pag e 52 of 52
PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these component s in an I2C system, p rovided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
CY8C21x34B
© Cypress Semiconductor Corporation, 2011–2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property la ws an d treaties of the United States and other coun tr ie s
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accom panied by a license agr eement and you do not other wise have a written agre ement with Cypress gove rning the use of the Sof tware, then Cypres s
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