DATA SH EET
Product specification
Supersedes data of 2003 Oct 30 2004 Mar 12
INTEGRATED CIRCUITS
74LVC273
Octal D-type flip-flop with reset;
positive-edge trigger
2004 Mar 12 2
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
FEATURES
•Wide supply voltage range from 1.2 to 3.6 V
•Inputs accept voltages up to 5.5 V
•CMOS low power consumption
•Direct interface with TTL levels
•Output drive capability 50 Ω transmission lines at 85 °C
•Complies with JEDEC standard no. 8-1A
•ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
•Specified from −40 to +85 °C and −40 to +125 °C.
DESCRIPTION
The 74LVC273 is a low-voltage Si-gate CMOS device,
superior to most advanced CMOS compatible TTL
families.
The 74LVC273 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common clock
(CP) and master reset (MR) inputs load and reset (clear)
allflip-flopssimultaneously.ThestateofeachD input,one
set-up time before the LOW-to-HIGH clock transition, is
transferred to the corresponding output (Qn) of the
flip-flop.
All outputs will be forced LOW independently of clock or
data inputs by a LOW voltage level on the MR input.
The device is useful for applications where the true output
only is required and the clock and master reset are
common to all storage elements.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25°C; tr=t
f≤2.5 ns.
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW)
PD=C
PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:
fi= input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL×VCC2×fo) = sum of the outputs.
2. The definition is VI= GND to VCC.
SYMBOL PARAMETER CONDITIONS TYPICAL UNIT
tPHL/tPLH propagation delay CP to Qn CL= 50 pF; VCC = 3.3 V 4.8 ns
propagation delay MR to Qn CL= 50 pF; VCC = 3.3 V 4.8 ns
fmax maximum clock frequency 230 MHz
CIinput capacitance 5.0 pF
CPD power dissipation capacitance per flip-flop outputs disabled; notes 1 and 2 22 pF
2004 Mar 12 3
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition;
↑= LOW-to-HIGH transition;
X = don’t care.
ORDERING INFORMATION
OPERATING MODES INPUT OUTPUT
MR CP Dn Qn
Reset (clear) L X X L
Load ‘1’ H ↑hH
Load ‘0’ H ↑lL
TYPE NUMBER PACKAGE
TEMPERATURE RANGE PINS PACKAGE MATERIAL CODE
74LVC273D −40 to +125 °C 20 SO20 plastic SOT163-1
74LVC273DB −40 to +125 °C 20 SSOP20 plastic SOT339-1
74LVC273PW −40 to +125 °C 20 TSSOP20 plastic SOT360-1
74LVC273BQ −40 to +125 °C 20 DHVQFN20 plastic SOT764-1
PINNING
PIN SYMBOL DESCRIPTION
1 MR master reset input (active LOW)
2 Q0 flip-flop output
3 D0 data input
4 D1 data input
5 Q1 flip-flop output
6 Q2 flip-flop output
7 D2 data input
8 D3 data input
9 Q3 flip-flop output
10 GND ground (0 V)
11 CP clock input (LOW-to-HIGH,
edge-triggered)
12 Q4 flip-flop output
13 D4 data input
14 D5 data input
15 Q5 flip-flop output
16 Q6 flip-flop output
17 D6 data input
18 D7 data input
19 Q7 flip-flop output
20 VCC supply voltage
PIN SYMBOL DESCRIPTION
2004 Mar 12 4
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
handbook, halfpage
MR
Q0
D0
D1
Q1 273
Q2
D2
D3
Q3
GND
VCC
Q7
D7
D6
Q5
D5
Q6
D4
Q4
CP
MNA762
1
2
3
4
5
6
7
8
9
10 11
12
20
19
18
17
16
15
14
13
Fig.1 Pin configuration SO20 and (T)SSOP20.
handbook, halfpage
1
2
3
4
5
6
7
8
9
Q0
D0
D1
Q1
Q2
D2
D3
Q3
19
18
17
16
15
14
13
12
D7
D6
Q6
Q7
Q5
D5
D4
Q4
20
MR VCC
10 11
GND
Top view CP
GND
(1)
MNA975
Fig.2 Pin configuration DHVQFN20.
(1) The die substrate is attached to this pad using conductive die
attach material. It can not be used as a supply pin or input.
handbook, halfpage
MNA763
D0
D1
D2
D3
D4
D5
D6
D7 MR
CP Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
11
1
19
16
15
12
9
6
5
2
18
17
14
13
8
7
4
3
Fig.3 Logic symbol.
handbook, halfpage
MNA764
19
16
15
12
9
6
5
11 C1
1R
1D 2
18
17
14
13
8
7
4
3
D7
D0
D1
D2
D3
D4
D5
D6
Q7
Q6
Q5
Q4
Q3
Q2
Q0
Q1
CP
MR
Fig.4 Logic symbol (IEEE/IEC).
2004 Mar 12 5
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
RECOMMENDED OPERATING CONDITIONS
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. For SO20 packages: above 70 °C derate linearly with 8 mW/K.
For SSOP20 and TSSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.
For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage maximum speed performance 2.7 3.6 V
low-voltage applications 1.2 3.6 V
VIinput voltage 0 5.5 V
VOoutput voltage 0 VCC V
Tamb operating ambient temperature in free air −40 +125 °C
tr, tfinput rise and fall times VCC = 1.2 to 2.7 V 0 20 ns/V
VCC = 2.7 to 3.6 V 0 10 ns/V
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +6.5 V
IIK input diode current VI<0 −−50 mA
VIinput voltage note 1 −0.5 +6.5 V
IOK output diode current VO>V
CC or VO<0 −50 mA
VOoutput voltage note 1 −0.5 VCC + 0.5 V
IOoutput source or sink current VO=0toV
CC −±50 mA
ICC,I
GND VCC or GND current −±100 mA
Tstg storage temperature −65 +150 °C
Ptot power dissipation per package Tamb =−40 to +125 °C; note 2 −500 mW
2004 Mar 12 6
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
DC CHARACTERISTICS
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
Tamb =−40 to +85 °C; note 1
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
VIL LOW-level input
voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.2 −−V
IO=−12 mA 2.7 VCC −0.5 −−V
IO=−18 mA 3.0 VCC −0.6 −−V
IO=−24 mA 3.0 VCC −0.8 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.2 V
IO=12mA 2.7 −−0.4 V
IO=24mA 3.0 −−0.55 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −±0.1 ±5µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 3.6 −0.1 10 µA
∆ICC additional quiescent
supply current per
input pin
VI=VCC −0.6 V;
IO=0 2.7 to 3.6 −5 500 µA
2004 Mar 12 7
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
Note
1. Typical values are measured at VCC = 3.3 V and Tamb =25°C.
Tamb =−40 to +125 °C
VIH HIGH-level input
voltage 1.2 VCC −−V
2.7 to 3.6 2.0 −−V
VIL LOW-level input
voltage 1.2 −−GND V
2.7 to 3.6 −−0.8 V
VOH HIGH-level output
voltage VI=V
IH or VIL
IO=−100 µA 2.7 to 3.6 VCC −0.3 −−V
IO=−12 mA 2.7 VCC −0.65 −−V
IO=−18 mA 3.0 VCC −0.75 −−V
IO=−24 mA 3.0 VCC −1.0 −−V
VOL LOW-level output
voltage VI=V
IH or VIL
IO= 100 µA 2.7 to 3.6 −−0.3 V
IO=12mA 2.7 −−0.6 V
IO=24mA 3.0 −−0.8 V
ILI input leakage
current VI= 5.5 Vor GND 3.6 −−±20 µA
ICC quiescent supply
current VI=V
CC or GND;
IO=0 3.6 −−40 µA
∆ICC additional quiescent
supply current per
input pin
VI=VCC −0.6 V;
IO=0 2.7 to 3.6 −−5000 µA
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
OTHER VCC (V)
2004 Mar 12 8
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
AC CHARACTERISTICS
GND = 0 V; tr=t
f= 2.5 ns; CL= 50 pF; RL= 500 Ω.
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
Tamb =−40 to +85 °C; note 1
tPHL/tPLH propagation delay CP to Qn see Fig.5 and Fig.8 1.2 −18 −ns
2.7 1.5 4.9 8.4 ns
3.0 to 3.6 1.5 4.8(2) 8.2 ns
tPHL propagation delay MR to Qn see Fig.6 and Fig.8 1.2 −18 −ns
2.7 1.5 5.2 8.9 ns
3.0 to 3.6 1.5 4.8(2) 8.7 ns
tWclock pulse width HIGH or LOW see Fig.5 and Fig.8 1.2 −−−ns
2.7 5.0 1.8 −ns
3.0 to 3.6 4.0 1.2(2) −ns
tWmaster reset pulse width LOW see Fig.6 and Fig.8 1.2 −−−ns
2.7 5.0 1.7 −ns
3.0 to 3.6 4.0 1.2(2) −ns
trem removal time MR to CP see Fig.6 and Fig.8 1.2 −−−ns
2.7 +3.0 −1.0 −ns
3.0 to 3.6 +2.0 −1.0(2) −ns
tsu set-up time Dn to CP see Fig.7 and Fig.8 1.2 −−−ns
2.7 3.0 1.0 −ns
3.0 to 3.6 1.0 0.0(2) −ns
thhold time Dn to CP see Fig.7 and Fig.8 1.2 −−−ns
2.7 +3.0 −0.2 −ns
3.0 to 3.6 1.0 0.0(2) −ns
fmax maximum clock frequency see Fig.5 and Fig.8 1.2 −−−MHz
2.7 150 −−MHz
3.0 to 3.6 150 230(2) −MHz
tsk(0) skew note 3 3.0 to 3.6 −−1.0 ns
2004 Mar 12 9
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
Notes
1. All typical values are measured at Tamb =25°C.
2. This typical value is measured at VCC = 3.3 V.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed
by design.
Tamb =−40 to +125 °C
tPHL/tPLH propagation delay CP to Qn see Fig.5 and Fig.8 1.2 −−−ns
2.7 1.5 −10.5 ns
3.0 to 3.6 1.5 −10.5 ns
tPHL propagation delay MR to Qn see Fig.6 and Fig.8 1.2 −−−ns
2.7 1.5 −11.5 ns
3.0 to 3.6 1.5 −11.0 ns
tWclock pulse width HIGH or LOW see Fig.5 and Fig.8 1.2 −−−ns
2.7 5.0 −−ns
3.0 to 3.6 4.0 −−ns
tWmaster reset pulse width LOW see Fig.6 and Fig.8 1.2 −−−ns
2.7 5.0 −−ns
3.0 to 3.6 4.0 −−ns
trem removal time MR to CP see Fig.6 and Fig.8 1.2 −−−ns
2.7 3.0 −−ns
3.0 to 3.6 2.0 −−ns
tsu set-up time Dn to CP see Fig.7 and Fig.8 1.2 −−−ns
2.7 3.0 −−ns
3.0 to 3.6 1.0 −−ns
thhold time Dn to CP see Fig.7 and Fig.8 1.2 −−−ns
2.7 3.0 −−ns
3.0 to 3.6 1.0 −−ns
fmax maximum clock frequency see Fig.5 and Fig.8 1.2 −−−MHz
2.7 150 −−MHz
3.0 to 3.6 150 −−MHz
tsk(0) skew note 3 3.0 to 3.6 −−1.5 ns
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT
WAVEFORMS VCC (V)
2004 Mar 12 10
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
AC WAVEFORMS
handbook, full pagewidth
MNA765
CP input
Qn output
tPHL tPLH
tW
VM
VOH
VI
GND
VOL
VMVM
1/fmax
Fig.5 Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse
frequency.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
handbook, full pagewidth
MNA464
MR input
CP input
Qn output
tPLH
tWtrem
VM
VI
GND
VI
GND
VM
VM
Fig.6 Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset
to clock (CP) removal time.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
2004 Mar 12 11
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
handbook, full pagewidth
MNA767
GND
GND
th
tsu th
tsu
VM
VM
VM
VI
VOH
VOL
VI
Qn output
CP input
Dn input
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM= 1.5 V at VCC ≥2.7 V.
VM= 0.5VCC at VCC < 2.7 V.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig.7 Data set-up and hold times for the data input (Dn).
2004 Mar 12 12
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
handbook, full pagewidth
VEXT
VCC
VIVO
MNA616
D.U.T.
CL
RT
RL
RL
PULSE
GENERATOR
Fig.8 Load circuitry for switching times.
Definitions for test circuit:
RL= Load resistor.
CL= Load capacitance including jig and probe capacitance.
RT= Termination resistance should be equal to the output impedance Zo of the pulse generator.
Note
1. The circuit performs better when RL = 1000 Ω.
VCC VICLRLVEXT
tPLH/tPHL tPZH/tPHZ tPZL/tPLZ
1.2 V VCC 50 pF 500 Ω(1) open GND 2 ×VCC
2.7 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC
3.0 to 3.6 V 2.7 V 50 pF 500 Ωopen GND 2 ×VCC
2004 Mar 12 13
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
PACKAGE OUTLINES
UNIT A
max. A
1
A
2
A
3
b
p
cD
(1)
E
(1) (1)
eH
E
LL
p
QZ
ywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
2.65 0.3
0.1 2.45
2.25 0.49
0.36 0.32
0.23 13.0
12.6 7.6
7.4 1.27 10.65
10.00 1.1
1.0 0.9
0.4 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.1
0.4
SOT163-1
10
20
w
M
b
p
detail X
Z
e
11
1
D
y
0.25
075E04 MS-013
pin 1 index
0.1 0.012
0.004 0.096
0.089 0.019
0.014 0.013
0.009 0.51
0.49 0.30
0.29 0.05
1.4
0.055
0.419
0.394 0.043
0.039 0.035
0.016
0.01
0.25
0.01 0.004
0.043
0.016
0.01
0 5 10 mm
scale
X
θ
A
A
1
A
2
H
E
L
p
Q
E
c
L
v
M
A
(A )
3
A
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
99-12-27
03-02-19
2004 Mar 12 14
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(1)
eH
E
LL
p
Q
(1)
Zywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 7.4
7.0 5.4
5.2 0.65 7.9
7.6 0.9
0.7 0.9
0.5 8
0
o
o
0.131.25 0.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT339-1 MO-150 99-12-27
03-02-19
X
w
M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v
M
A
(A )
3
A
110
20 11
y
0.25
pin 1 index
0 2.5 5 mm
scale
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
A
max.
2
2004 Mar 12 15
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
UNIT A
1
A
2
A
3
b
p
cD
(1)
E
(2) (1)
eH
E
LL
p
QZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.95
0.80 0.30
0.19 0.2
0.1 6.6
6.4 4.5
4.3 0.65 6.6
6.2 0.4
0.3 0.5
0.2 8
0
o
o
0.13 0.10.21
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT360-1 MO-153 99-12-27
03-02-19
w
M
b
p
D
Z
e
0.25
110
20 11
pin 1 index
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v
M
A
X
A
y
0 2.5 5 mm
scale
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
A
max.
1.1
2004 Mar 12 16
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
terminal 1
index area
0.51
A1Eh
b
UNIT ye
0.2
c
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 4.6
4.4
Dh
3.15
2.85
y1
2.6
2.4 1.15
0.85
e1
3.5
0.30
0.18
0.05
0.00 0.05 0.1
DIMENSIONS (mm are the original dimensions)
SOT764-1 MO-241 - - -- - -
0.5
0.3
L
0.1
v
0.05
w
0 2.5 5 mm
scale
SOT764-1
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
20 terminals; body 2.5 x 4.5 x 0.85 mm
A
(1)
max.
AA1c
detail X
y
y1C
e
L
Eh
Dh
e
e1
b
29
19 12
11
10
1
20
X
D
E
C
BA
terminal 1
index area
AC
CB
v
M
w
M
E
(1)
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
D
(1)
02-10-17
03-01-27
2004 Mar 12 17
Philips Semiconductors Product specification
Octal D-type flip-flop with reset;
positive-edge trigger 74LVC273
DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
LimitingvaluesdefinitionLimitingvaluesgivenarein
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in
the Characteristics sections of the specification is not
implied. Exposure to limiting values for extended periods
may affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will
be suitable for the specified use without further testing or
modification.
DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury.
Philips Semiconductors customers using or selling these
products for use in such applications do so at their own
risk and agree to fully indemnify Philips Semiconductors
for any damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full
production (status ‘Production’), relevant changes will be
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© Koninklijke Philips Electronics N.V. 2004 SCA76
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Printed in The Netherlands R20/04/pp18 Date of release: 2004 Mar 12 Document order number: 9397 750 12969
This datasheet has been download from:
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Datasheets for electronics components.
