0
10
20
30
40
50
60
70
80
0 200 400 600 800 1000
Radiated EMI Emissions (dBµV/m)
Frequency (MHz)
Evaluation Board
EN 55022 Class B Limit
EN 55022 Class A Limit
C001
C001
SWVIN
PGND
CBOOT
VCC
BIAS
SYNC
RT
ENABLE
SS/TRK
AGND
FB
LM43602
VIN COUT
CBOOT
CIN
CVCC
VOUT
CBIAS RFBT
RFBB
CFF
L
PGOOD
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Now
Technical
Documents
Support &
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM43602
SNVSA36C APRIL 2014REVISED OCTOBER 2017
LM43602 3.5-V to 36-V, 2-A Synchronous Step-Down Voltage Converter
1
1 Features
1 27-µA Quiescent Current in Regulation
High Efficiency at Light Load (DCM and PFM)
Meets EN55022/CISPR 22 EMI standards
Integrated Synchronous Rectification
Adjustable Frequency Range: 200 kHz to 2.2 MHz
(500 kHz Default)
Frequency Synchronization to External Clock
Internal Compensation
Stable with Almost Any Combination of Ceramic,
Polymer, Tantalum, and Aluminum Capacitors
Power-Good Flag
Soft-Start into a Pre-Biased Load
Internal Soft Start: 4.1 ms
Extendable Soft-Start Time by External Capacitor
Output Voltage Tracking Capability
Precision Enable to Program System UVLO
Output Short Circuit Protection with Hiccup Mode
Overtemperature Thermal Shutdown Protection
Create a Custom Design Using the LM43602 with
the WEBENCH® Power Designer
2 Applications
Industrial Power Supplies
Telecommunications Systems
Sub-AM Band Automotive
General Purpose Wide VIN Regulation
High Efficiency Point-Of-Load Regulation
space
3 Description
The LM43602 regulator is an easy-to-use
synchronous step-down DC-DC converter capable of
driving up to 2 A of load current from an input voltage
ranging from 3.5 V to 36 V (42-V absolute maximum).
The LM43602 provides exceptional efficiency, output
accuracy, and dropout voltage in a very small solution
size. An extended family is available in 0.5-A, 1-A,
and 3-A load current options in pin-to-pin compatible
packages. Peak current-mode control is employed to
achieve simple control loop compensation and cycle-
by-cycle current limiting. Optional features such as
programmable switching frequency, synchronization,
power-good flag, precision enable, internal soft start,
extendable soft start, and tracking provide a flexible
and easy-to-use platform for a wide range of
applications. Discontinuous conduction and automatic
frequency modulation at light loads improve light-load
efficiency. The family requires few external
components and terminal arrangement allows simple,
optimum PCB layout. Protection features include
thermal shutdown, VCC undervoltage lockout, cycle-
by-cycle current limit, and output short circuit
protection. The LM43602 device is available in a 16-
lead HTSSOP package (5.1 mm × 6.6 mm × 1.2 mm)
and 16-pin VSON package with wettable flanks.
Device Information
ORDER NUMBER PACKAGE BODY SIZE
LM43602 HTSSOP (16) 5.10 mm × 6.60 mm
VSON (16) 4.10 mm × 5.10 mm
Simplified Schematic LM43602PWPEVM Radiated Emission Graph
12VIN to 3.3 VOUT,
FS= 500 kHz, IOUT =2A
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 6
6.7 Switching Characteristics.......................................... 7
6.8 Typical Characteristics.............................................. 8
7 Detailed Description............................................ 12
7.1 Overview................................................................. 12
7.2 Functional Block Diagram....................................... 12
7.3 Feature Description................................................. 13
7.4 Device Functional Modes........................................ 20
8 Applications and Implementation ...................... 22
8.1 Application Information............................................ 22
8.2 Typical Applications ................................................ 22
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 36
11 Device and Documentation Support................. 37
11.1 Device Support .................................................... 37
11.2 Documentation Support ....................................... 37
11.3 Related Links ........................................................ 37
11.4 Receiving Notification of Documentation Updates 38
11.5 Community Resources.......................................... 38
11.6 Trademarks........................................................... 38
11.7 Electrostatic Discharge Caution............................ 38
11.8 Glossary................................................................ 38
12 Mechanical, Packaging, and Orderable
Information........................................................... 38
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (February 2017) to Revision C Page
No technical changes, editorial only ...................................................................................................................................... 1
Changed Handling Ratings to ESD Ratings per latest format requirements; move "storage temperature" to Absolute
Maximum Ratings table ......................................................................................................................................................... 4
Changes from Revision A (April 2014) to Revision B Page
Added new package............................................................................................................................................................... 1
Added pinout drawing ............................................................................................................................................................ 3
Added pin functions for VSON................................................................................................................................................ 3
Updated BIAS Pin Abs Max .................................................................................................................................................. 4
Updating Recommended Operation Voltage for BIAS........................................................................................................... 4
Added new Thermal Information (VSON) .............................................................................................................................. 5
Changed PGOOD Resistance values on EC Table............................................................................................................... 6
Updating EN Falling Threshold Figure 13............................................................................................................................ 10
Updating Figure 14 EN Rising Threshold ............................................................................................................................ 10
Updating Figure 15 EN Hysteresis ...................................................................................................................................... 10
Added Equation 25 .............................................................................................................................................................. 28
Added Equation 26 .............................................................................................................................................................. 28
Changes from Original (April 2014) to Revision A Page
Changed device from Product Preview to Production Data................................................................................................... 1
SW
VIN
PGND
CBOOT
VCC
BIAS
SYNC
RT PGOOD
EN
SS/TRK
FB
SW PGND
VIN
PAD
116
2
3
4
5
6
8
7
9
15
14
13
12
11
10
SW
SW
VIN
PGND
CBOOT
VCC
BIAS
SYNC
RT
PGOOD
EN
SS/TRK
AGND
FB
SW PGND
VIN
PAD
1 16
2
3
4
5
6
8
79
15
14
13
12
11
10
3
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5 Pin Configuration and Functions
PWP Package
16-Pin HTSSOP
Top View DSU Package
16-Pin VSON
Top View
(1) P = Power, A = Analog, G = Ground
Pin Functions
PIN
DESCRIPTIONNAME NUMBER TYPE(1)
TSSOP VSON
SW 1,2 1,2,3 P Switching output of the regulator. Internally connected to both power MOSFETs.
Connect to power inductor.
CBOOT 3 4 P Boot-strap capacitor connection for high-side driver. Connect a high quality 470-nF
capacitor from CBOOT to SW.
VCC 4 5 P Internal bias supply output for bypassing. Connect bypass capacitor from this pin to
AGND. Do not connect external loading to this pin. Never short this pin to ground during
operation.
BIAS 5 6 P Optional internal LDO supply input. To improve efficiency, it is recommended to tie to
VOUT when 3.3 V VOUT 28 V, or tie to an external 3.3 V or 5 V rail if available. When
used, place a bypass capacitor (1 to 10 µF) from this pin to ground. Tie to ground when
not in use.
SYNC 6 7 A Clock input to synchronize switching action to an external clock. Use proper high speed
termination to prevent ringing. Connect to ground if not used.
RT 7 8 A Connect a resistor RTfrom this pin to AGND to program switching frequency. Leave
floating for 500 kHz default switching frequency.
PGOOD 8 9 A Open drain output for power-good flag. Use a 10 kΩto 100 kΩpull-up resistor to logic
rail or other DC voltage no higher than 12 V.
FB 9 10 A Feedback sense input pin. Connect to the midpoint of feedback divider to set VOUT. Do
not short this pin to ground during operation.
AGND 10 G Analog ground pin. Ground reference for internal references and logic. Connect to
system ground.
SS/TRK 11 11 A Soft-start control pin. Leave floating for internal soft-start slew rate. Connect to a
capacitor to extend soft start time. Connect to external voltage ramp for tracking.
EN 12 12 A Enable input to the internal LDO and regulator. High = ON and low = OFF. Connect to
VIN, or to VIN through resistor divider,or to an external voltage or logic source. Do not
float.
VIN 13,14 13,14 P Supply input pins to internal LDO and high side power FET. Connect to power supply
and bypass capacitors CIN. Path from VIN pin to high frequency bypass CIN and PGND
must be as short as possible.
PGND 15,16 15,16 G Power ground pins, connected internally to the low side power FET. Connect to system
ground, PAD, AGND, ground pins of CIN and COUT. Path to CIN must be as short as
possible.
PAD Low impedance connection to AGND. Connect to PGND on PCB. Major heat dissipation
path of the die. Must be used for heat sinking to ground plane on PCB.
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) At maximum duty cycle of 0.01%
(3) Whichever is lower
6 Specifications
6.1 Absolute Maximum Ratings(1)
over the recommended operating junction temperature (TJ) range of –40°C to +125°C (unless otherwise noted)
PARAMETER MIN MAX UNIT
Input voltages VIN to PGND –0.3 42(2)
V
EN to PGND –0.3 VIN + 0.3
FB, RT, SS/TRK to AGND –0.3 3.6
PGOOD to AGND –0.3 15
SYNC to AGND –0.3 5.5
BIAS to AGND –0.3 30 or VIN(3)
AGND to PGND –0.3 0.3
Output voltages SW to PGND –0.3 VIN + 0.3
V
SW to PGND less than 10-ns transients –3.5 42
CBOOT to SW –0.3 5.5
VCC to AGND –0.3 3.6
Operating junction temperature TJ–40 125 °C
Storage temperature, Tstg –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500
(1) Operating Ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. For
ensured specifications, see Electrical Characteristics.
(2) Whichever is lower
6.3 Recommended Operating Conditions(1)
over the recommended operating junction temperature (TJ) range of –40°C to +125°C (unless otherwise noted)
PARAMETER MIN MAX UNIT
Input voltages
VIN to PGND 3.5 36
V
EN –0.3 VIN
FB –0.3 1.1
PGOOD –0.3 12
BIAS input not used –0.3 0.3
BIAS input used 3.3 28 or VIN(2)
AGND to PGND –0.1 0.1
Output voltage VOUT 1 28 V
Output current IOUT 0 2 A
Temperature Operating junction temperature range, TJ–40 125 °C
5
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(1) The package thermal impedance is calculated in accordance with JESD 51-7.
(2) Thermal Resistances were simulated on a 4 layer, JEDEC board.
(3) See Figure 64 for θJA vs Copper Area Curve.
6.4 Thermal Information
THERMAL METRIC (1)(2) LM43602
UNITHTSSOP VSON
(16 PINS) (16 PINS)
RθJA Junction-to-ambient thermal resistance 38.9(3) 31.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.3 22.8 °C/W
RθJB Junction-to-board thermal resistance 19.9 9.6 °C/W
ψJT Junction-to-top characterization parameter 0.7 0.2 °C/W
ψJB Junction-to-board characterization parameter 19.7 9.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.7 1.3 °C/W
6.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VOUT = 3.3 V, FS= 500 kHz.
PARAMETER CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE (VIN PIN)
VIN-MIN-ST Minimum input voltage for start-up 3.8 V
ISHDN Shutdown quiescent current VEN = 0 V 1.2 3.1 µA
IQ-NONSW Operating quiescent current (non-
switching) from VIN
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external 5 10 µA
IBIAS-NONSW Operating quiescent current (non-
switching) from external VBIAS
VEN = 3.3 V
VFB = 1.5 V
VBIAS = 3.4 V external 85 130 µA
IQ-SW Operating quiescent current (switching)
VEN = 3.3 V
IOUT = 0 A
RT= open
VBIAS = VOUT = 3.3 V
RFBT = 1.0 Meg
27 µA
ENABLE (EN PIN)
VEN-VCC-H Voltage level to enable the internal LDO
output VCC VENABLE high level 1.2 V
VEN-VCC-L Voltage level to disable the internal LDO
output VCC VENABLE low level 0.525 V
VEN-VOUT-H Precision enable level for switching and
regulator output: VOUT VENABLE high level 2 2.2 2.42 V
VEN-VOUT-HYS Hysteresis voltage between VOUT
precision enable and disable thresholds VENABLE hysteresis –290 mV
ILKG-EN Enable input leakage current VEN = 3.3 V 0.85 1.75 µA
INTERNAL LDO (VCC and BIAS PINS)
VCC Internal LDO output voltage VCC VIN 3.8 V 3.28 V
VCC-UVLO
Undervoltage lock out (UVLO)
thresholds for VCC VCC rising threshold 3.1 V
Hysteresis voltage between rising and
falling thresholds –520 mV
VBIAS-ON
Internal LDO input change over
threshold to BIAS VBIAS rising threshold 2.94 3.15 V
Hysteresis voltage between rising and
falling thresholds –75 mV
6
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and Maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VOUT = 3.3 V, FS= 500 kHz.
PARAMETER CONDITIONS MIN TYP MAX UNIT
(1) Specified by design
(2) Measured at the pins
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage TJ= 25ºC 1.004 1.011 1.018 VTJ= –40ºC to 85ºC 0.994 1.011 1.026
TJ= –40ºC to 125ºC 0.994 1.011 1.030
ILKG-FB Input leakage current at FB pin FB = 1 V 0.2 65 nA
THERMAL SHUTDOWN
TSD (1) Thermal shutdown Shutdown threshold 160 °C
Recovery threshold 150 °C
CURRENT LIMIT AND HICCUP
IHS-LIMIT Peak inductor current limit 3.65 4.5 5.15 A
ILS-LIMIT Inductor current valley limit 1.75 2 2.25 A
SOFT START (SS/TRK PIN)
ISSC Soft-start charge current 1.25 2 2.75 µA
RSSD Soft-start discharge resistance UVLO, TSD, OCP, or EN = 0 V 18 kΩ
POWER GOOD (PGOOD PIN)
VPGOOD-HIGH Power-good flag overvoltage tripping
threshold % of FB voltage 110% 113%
VPGOOD-LOW Power-good flag undervoltage tripping
threshold % of FB voltage 77% 88%
VPGOOD-HYS Power-good flag recovery hysteresis % of FB voltage 6%
RPGOOD PGOOD pin pulldown resistance when
power bad VEN = 3.3 V 69 150 Ω
VEN = 0 V 150 350
MOSFETS (2)
RDS-ON-HS High-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V 120 mΩ
RDS-ON-LS Low-side MOSFET ON-resistance IOUT = 1 A
VBIAS = VOUT = 3.3 V 65 mΩ
6.6 Timing Requirements MIN NOM MAX UNIT
CURRENT LIMIT AND HICCUP
NOC Hiccup wait cycles when LS current limit tripped 32 Cycles
TOC Hiccup retry delay time 5.5 ms
SOFT START (SS/TRK PIN)
TSS Internal soft-start time when SS pin open circuit 4.1 ms
POWER GOOD (PGOOD PIN)
TPGOOD-RISE Power-good flag rising transition deglitch delay 220 µs
TPGOOD-FALL Power-good flag falling transition deglitch delay 220 µs
7
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(1) Specified by design
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SW (SW PIN)
tON-MIN(1) Minimum high side MOSFET ON-
time 125 165 ns
tOFF-MIN(1) Minimum high side MOSFET OFF-
time 200 250 ns
OSCILLATOR (SW and SYNC PINS)
FOSC-
DEFAULT Oscillator default frequency RT pin open circuit 425 500 580 kHz
FADJ
Minimum adjustable frequency With 1% resistors at RT pin 200 kHz
Maximum adjustable frequency 2200 kHz
Frequency adjust accuracy 10%
VSYNC-HIGH Sync clock high level threshold 2 V
VSYNC-LOW Sync clock low level threshold 0.4 V
DSYNC-MAX Sync clock maximum duty cycle 90%
DSYNC-MIN Sync clock minimum duty cycle 10%
TSYNC-MIN Mininum sync clock ON and OFF
time 80 ns
40
50
60
70
80
90
100
0 0.5 1 1.5 2
Efficiency (%)
Current (A)
12VIN
24VIN
C001
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Efficiency (%)
Current (A)
12VIN
24VIN
C001
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Efficiency (%)
Current (A)
5VIN
12VIN
24VIN
C001
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Efficiency (%)
Current (A)
12VIN
24VIN
C001
40
50
60
70
80
90
100
0.001 0.01 0.1 1
Efficiency (%)
Current (A)
5VIN
12VIN
24VIN
C001
40
50
60
70
80
90
100
0 0.5 1 1.5 2
Efficiency (%)
Current (A)
5VIN
12VIN
24VIN
C001
8
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6.8 Typical Characteristics
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS= 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See
Application Performance Curves for Bill of materials for other VOUT and FScombinations.
VOUT = 3.3V FS= 500 kHz
Figure 1. Efficiency at Room Temperature
VOUT = 3.3V FS= 500 kHz
Figure 2. Efficiency at Room Temperature
VOUT = 3.3V FS= 500 kHz
Figure 3. Efficiency at 85°C
VOUT = 5V FS= 500 kHz
Figure 4. Efficiency at Room Temperature
VOUT = 5V FS= 500 kHz
Figure 5. Efficiency at Room Temperature
VOUT = 5V FS= 500 kHz
Figure 6. Efficiency at 85°C
1000
10000
100000
1000000
3.5 3.7 3.9 4.1 4.3 4.5
FREQUENCY (Hz)
VIN (V)
0.1A
0.5A
1A
1.5A
2A
C007
10000
100000
1000000
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
Frequency (Hz)
VIN (V)
0.1A
0.5A
1A
1.5A
2A
C007
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.5 3.7 3.9 4.1 4.3 4.5
VOUT (V)
VIN (V)
0.1A
0.5A
1A
1.5A
2A
C007
4.0
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.00 5.20 5.40 5.60 5.80 6.00 6.20 6.40 6.60 6.80 7.00
VOUT (V)
VIN (V)
0.1A
0.5A
1A
1.5A
2A
C007
3.20
3.22
3.24
3.26
3.28
3.30
3.32
3.34
3.36
3.38
3.40
0.001 0.01 0.1 1
VOUT (V)
Current (A)
5VIN
12VIN
24VIN
C001
4.75
4.80
4.85
4.90
4.95
5.00
5.05
5.10
5.15
5.20
5.25
0.001 0.01 0.1 1
VOUT (V)
Current (A)
8VIN
12VIN
24VIN
C004
9
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS= 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See
Application Performance Curves for Bill of materials for other VOUT and FScombinations.
VOUT = 3.3V FS= 500 kHz
Figure 7. VOUT Regulation
VOUT = 5V FS= 500 kHz
Figure 8. VOUT Regulation
VOUT = 3.3V FS= 500 kHz
Figure 9. Dropout Curve
VOUT = 5V FS= 500 kHz
Figure 10. Dropout Curve
VOUT = 3.3V FS= 500 kHz
Figure 11. Frequency vs VIN
VOUT = 5V FS= 500 kHz
Figure 12. Frequency vs VIN
3.600
3.700
3.800
3.900
4.000
4.100
4.200
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
HS Current Limit (A)
Temperature (deg C)
C001
1.800
1.900
2.000
2.100
2.200
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
LS Current Limit (A)
Temperature (deg C)
C001
250
260
270
280
290
300
310
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
EN Hysteresis (mV)
Temperature (deg C)
C001
1.000
1.005
1.010
1.015
1.020
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
FB Voltage (V)
Temperature (deg C)
C001
1.600
1.650
1.700
1.750
1.800
1.850
1.900
1.950
2.000
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
EN Voltage (V)
Temperature (deg C)
C001
1.900
1.950
2.000
2.050
2.100
2.150
2.200
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
EN Voltage (V)
Temperature (deg C)
C001
10
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS= 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See
Application Performance Curves for Bill of materials for other VOUT and FScombinations.
Figure 13. EN Falling Threshold vs Junction Temperature Figure 14. EN Rising Threshold vs Junction Temperature
Figure 15. EN Hysteresis vs Junction Temperature Figure 16. FB Voltage vs Junction Temperature
Figure 17. HS Current Limit vs Junction Temperature Figure 18. LS Current Limit vs Junction Temperature
86.0
87.0
88.0
89.0
90.0
91.0
92.0
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
Percentage of FB Voltage (%)
Temperature (deg C)
C001
92.0
93.0
94.0
95.0
96.0
97.0
98.0
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
Percentage of FB Voltage (%)
Temperature (deg C)
C001
109.0
109.5
110.0
110.5
111.0
111.5
112.0
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
Percentage of FB Voltage (%)
Temperature (deg C)
C001
104.0
104.5
105.0
105.5
106.0
106.5
107.0
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
Percentage of FB Voltage (%)
Temperature (deg C)
C001
90
100
110
120
130
140
150
160
170
180
190
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
HS Rds-on (mŸ)
Temperature (deg C)
C001
40
45
50
55
60
65
70
75
80
85
90
±40 ±25 ±10 5 20 35 50 65 80 95 110 125
LS Rds-on (mŸ)
Temperature (deg C)
C001
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Typical Characteristics (continued)
Unless otherwise specified, VIN = 12 V, VOUT = 3.3 V, FS= 500 kHz, L = 6.8 µH, COUT = 120 µF, CFF = 100 pF. See
Application Performance Curves for Bill of materials for other VOUT and FScombinations.
Figure 19. High Side FET On Resistance vs Junction
Temperature Figure 20. Low Side FET On Resistance vs Junction
Temperature
Figure 21. PGOOD OVP Falling Threshold vs Junction
Temperature Figure 22. PGOOD OVP Rising Threshold vs Junction
Temperature
Figure 23. PGOOD UVP Falling Threshold vs Junction
Temperature Figure 24. PGOOD UVP Rising Threhsold vs Junction
Temperature
Precision
Enable
VCC
Enable
Slope
Comp
LDO
HICCUP
Detector
PFM
Detector
TSD
Oscillator
PWM CONTROL LOGIC
Freq
Foldback Zero
Cross
UVLO
CBOOT
VIN
BIAS
PGOOD
ENABLE
AGND
PGNDSYNC
VCC
SW
FB
HS I Sense
RT
ISSC
+
±
LS I Sense
PGood
PGood
FB
SS/TRK
+
OV/UV
Detector
REF EA
Internal
SS
RC
CC
+±
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7 Detailed Description
7.1 Overview
The LM43602 regulator is an easy to use synchronous step-down DC-DC converter that operates from 3.5 V to
36 V supply voltage. It is capable of delivering up to 2 A DC load current with exceptional efficiency and thermal
performance in a very small solution size. An extended family is available in 0.5 A, 1A, and 3 A load options in
pin to pin compatible packages.
The LM43602 employs fixed frequency peak current mode control with Discontinuous Conduction Mode (DCM)
and Pulse Frequency Modulation (PFM) mode at light load to achieve high efficiency across the load range. The
device is internally compensated, which reduces design time, and requires fewer external components. The
switching frequency is programmable from 200 kHz to 2.2 MHz by an external resistor RT. It is default at 500 kHz
without RTresistor. The LM43602 is also capable of synchronization to an external clock within the 200-kHz to
2.2-MHz frequency range. The wide switching frequency range allows the device to be optimized to fit small
board space at higher frequency, or high efficient power conversion at lower frequency.
Optional features are included for more comprehensive system requirements, including power-good (PGOOD)
flag, precision enable, synchronization to external clock, extendable soft-start time, and output voltage tracking.
These features provide a flexible and easy to use platform for a wide range of applications. Protection features
include overtemperature shutdown, VCC undervoltage lockout (UVLO), cycle-by-cycle current limit, and short-
circuit protection with hiccup mode.
The family requires few external components and the pin arrangement was designed for simple, optimum PCB
layout. The LM43602 device is available in the 16-lead HTSSOP (PWP) and 16-pin VSON packages.
7.2 Functional Block Diagram
0
0
VIN
-VD1
tON
t
t
Inductor Current
D = tON / TSW
VSW
tOFF
TSW
iL
SW Voltage
ûiL
IOUT
ILPK
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7.3 Feature Description
7.3.1 Fixed Frequency Peak Current-Mode Controlled Step-Down Regulator
The following operating description of the LM43602 will refer to the Functional Block Diagram and to the
waveforms in Figure 25. The LM43602 is a step-down Buck regulator with both high-side (HS) switch and low-
side (LS) switch (synchronous rectifier) integrated. The LM43602 supplies a regulated output voltage by turning
on the HS and LS NMOS switches with controlled ON time. During the HS switch ON time, the SW pin voltage
VSW swings up to approximately VIN, and the inductor current iLincreases with a linear slope (VIN - VOUT) / L.
When the HS switch is turned off by the control logic, the LS switch is turned on after a anti-shoot-through dead
time. Inductor current discharges through the LS switch with a slope of -VOUT / L. The control parameter of buck
converters are defined as Duty Cycle D = tON / TSW, where tON is the HS switch ON time and TSW is the switching
period. The regulator control loop maintains a constant output voltage by adjusting the duty cycle D. In an ideal
Buck converter, where losses are ignored, D is proportional to the output voltage and inversely proportional to
the input voltage: D = VOUT / VIN.
Figure 25. SW Node and Inductor Current Waveforms in Continuous Conduction Mode (CCM)
The LM43602 synchronous Buck converter employs peak current mode control topology. A voltage feedback
loop is used to get accurate DC voltage regulation by adjusting the peak current command based on voltage
offset. The peak inductor current is sensed from the HS switch and compared to the peak current to control the
ON time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewer external
components, makes it easy to design, and provides stable operation with almost any combination of output
capacitors. The regulator operates with fixed switching frequency in Continuous Conduction Mode (CCM) and
Discontinuous Conduction Mode (DCM). At very light load, the LM43602 will operate in PFM to maintain high
efficiency and the switching frequency will decrease with reduced load current.
7.3.2 Light Load Operation
DCM operation is employed in the LM43602 when the inductor current valley reaches zero. The LM43602 will be
in DCM when load current is less than half of the peak-to-peak inductor current ripple in CCM. In DCM, the LS
switch is turned off when the inductor current reaches zero. Switching loss is reduced by turning off the LS FET
at zero current and the conduction loss is lowered by not allowing negative current conduction. Power conversion
efficiency is higher in DCM than CCM under the same conditions.
In DCM, the HS switch ON time will reduce with lower load current. When either the minimum HS switch ON time
(tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency will decrease to
maintain regulation. At this point, the LM43602 operates in PFM. In PFM, switching frequency is decreased by
the control loop when load current reduces to maintain output voltage regulation. Switching loss is further
reduced in PFM operation due to less frequent switching actions.
FB
FBB FBT
OUT FB
V
R R
V V
FB
RFBT
RFBB
VOUT
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Feature Description (continued)
In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. The
lower the frequency in PFM, the more DC offset is needed at VOUT. Please refer to the Typical Characteristics for
typical DC offset at very light load. If the DC offset on VOUT is not acceptable for a given application, a static load
at output is recommended to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and
RFBB can also serve as a static load. In conditions with low VIN and/or high frequency, the LM43602 may not
enter PFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector.
Once the LM43602 is operating in PFM mode at higher VIN, it will remain in PFM operation when VIN is reduced
7.3.3 Adjustable Output Voltage
The voltage regulation loop in the LM43602 regulates output voltage by maintaining the voltage on FB pin ( VFB)
to be the same as the internal REF voltage (VREF). A resistor divider pair is needed to program the ratio from
output voltage VOUT to VFB. The resistor divider is connected from the VOUT of the LM43602 to ground with the
mid-point connecting to the FB pin.
Figure 26. Output Voltage Setting
The voltage reference system produces a precise voltage reference over temperature. The internal REF voltage
is 1.011 V typically. To program the output voltage of the LM43602 to be a certain value VOUT, RFBB can be
calculated with a selected RFBT by
(1)
The choice of the RFBT depends on the application. RFBT in the range from 10 kΩto 100 kis recommended for
most applications. A lower RFBT value can be used if static loading is desired to reduce VOUT offset in PFM
operation. Lower RFBT will reduce efficiency at very light load. Less static current goes through a larger RFBT and
might be more desirable when light load efficiency is critical. But RFBT larger than 1 MΩis not recommended
because it makes the feedback path more susceptible to noise. Larger RFBT value requires more carefully
designed feedback path on the PCB. The tolerance and temperature variation of the resistor dividers affect the
output voltage regulation. It is recommended to use divider resistors with 1% tolerance or better and temperature
coefficient of 100 ppm or lower.
If the resistor divider is not connected properly, output voltage cannot be regulated since the feedback loop is
broken. If the FB pin is shorted to ground, the output voltage will be driven close to VIN, since the regulator sees
very low voltage on the FB pin and tries to regulator it up. The load connected to the output could be damaged
under such a condition. Do not short FB pin to ground when the LM43602 is enabled. It is important to route the
feedback trace away from the noisy area of the PCB. For more layout recommendations, please refer to the
Layout section.
7.3.4 Enable (EN)
Voltage on the EN pin (VEN) controls the ON or OFF operation of the LM43602. Applying a voltage less than 0.4
V to the EN input shuts down the operation of the LM43602. In shutdown mode the quiescent current drops to
typically 1.2 µA at VIN = 12 V.
The internal LDO output voltage VCC is turned on when VEN is higher than 1.2 V. The LM43602 switching action
and output regulation are enabled when VEN is greater than 2.1 V (typical). The LM43602 supplies regulated
output voltage when enabled and output current up to 2 A.
The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operation of the
LM43602 is to connect the EN pin to VIN pins directly. This allows self-start-up of the LM43602 when VIN is
within the operation range.
SS SSC SS
C I t u
VIN
ENABLE
RENT
RENB
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Feature Description (continued)
Many applications will benefit from the employment of an enable divider RENT and RENB in Figure 27 to establish
a precision system UVLO level for the stage. System UVLO can be used for supplies operating from utility power
as well as battery power. It can be used for sequencing, ensuring reliable operation, or supply protection, such
as a battery. An external logic signal can also be used to drive EN input for system sequencing and protection.
Figure 27. System UVLO By Enable Dividers
7.3.5 VCC, UVLO and BIAS
The LM43602 integrates an internal LDO to generate VCC for control circuitry and MOSFET drivers. The nominal
voltage for VCC is 3.2 V. The VCC pin is the output of the LDO must be properly bypassed. A high quality
ceramic capacitor with 2.2 µF to 10 µF capacitance and 6.3 V or higher rated voltage should be placed as close
as possible to VCC and grounded to the exposed PAD and ground pins. The VCC output pin should not be
loaded, left floating, or shorted to ground during operation. Shorting VCC to ground during operation may cause
damage to the LM43602.
Under voltage lockout (UVLO) prevents the LM43602 from operating until the VCC voltage exceeds 3.15 V
(typical). The VCC UVLO threshold has 575 mV of hysteresis (typically) to prevent undesired shuting down due to
temperary VIN droops.
The internal LDO has two inputs: primary from VIN and secondary from BIAS input. The BIAS input powers the
LDO when VBIAS is higher than the change-over threshold. Power loss of an LDO is calculated by ILDO * (VIN-LDO -
VOUT-LDO). The higher the difference between the input and output voltages of the LDO, the more power loss
occur to supply the same output current. The BIAS input is designed to reduce the difference of the input and
output voltages of the LDO to reduce power loss and improve LM43602 efficiency, especially at light load. It is
recommended to tie the BIAS pin to VOUT when VOUT 3.3 V. The BIAS pin should be grounded in applications
with VOUT less than 3.3 V. BIAS input can also come from an external voltage source, if available, to reduce
power loss. When used, a 1 µF to 10 µF high quality ceramic capacitor is recommended to bypass the BIAS pin
to ground.
7.3.6 Soft-Start and Voltage Tracking (SS/TRK)
The LM43602 has a flexible and easy to use start up rate control pin: SS/TRK. Soft-start feature is to prevent
inrush current impacting the LM43602 and its supply when power is first applied. Soft-start is achieved by slowly
ramping up the target regulation voltage when the device is first enabled or powered up.
The simplest way to use the part is to leave the SS/TRK pin open circuit or floating. The LM43602 will employ
the internal soft-start control ramp and start up to the regulated output voltage in 4.1 ms