AT28C010E-25EM/883 - Atmel Corporation

AT28C01 0 Mil

1 Megabit

(128K x 8)

Paged

CMOS

E2PROM

Military

Features

•Fast Rea d Access Ti me - 120 ns

•Automatic Page Write Operation

Internal Address and Data Latches for 128-Bytes

Internal Control Timer

•Fast Wri te Cyc le Tim e

Page Write Cycle Time - 10 ms Maximum

1 to 128-Byte Page Write Ope rati on

•Low Power Dissipation

80 mA Active Current

300 µA CMOS Standby Current

•Hardware and Software Data Protection

•DATA Polli ng for End of Wri te Dete cti on

•High Rel ia bility C MOS Te chnolo gy

Endura nc e: 10 4 or 105 Cycles

Data Retention: 10 Years

•Singl e 5V ± 10 % Supply

•CMOS and TTL Compatible Inputs and Outputs

•JEDEC Approv ed Byte-W id e Pin ou t

Description

The AT28C010 is a high-perfor mance Electric ally Erasable and Programmable Read

Only Memory. Its one megabit of memory is organized as 131,072 words by 8 bits.

Manufactured with Atmel’s advanc ed nonvolatile CMOS technology, the device offers

(continued)

CERDIP, FLATPACK

Top View

Pin Name Function

A0 - A16 Addresses

CE Chip Enable

OE Output Enable

WE Write Enable

I/O0 - I/O7 Data Inputs/O utput s

NC No Connect

Pin Configur a tions 44 LCC

Top View

32 LCC

Top View

PGA

Top View

0353C

AT28C010 Mil

2-243

Block Diagram

Temperature Under Bias.................-55°C to +125°C

Storage Temperature......................-65°C to +150°C

All Input Voltages

(including NC Pins)

with Respect to Ground ................... -0.6V to +6.25V

All Output Voltages

with Respect to Ground .............-0.6V to VCC + 0.6V

Voltage on OE and A9

with Respect to Ground ................... -0.6V to +13.5V

*NOTICE: Stresse s beyond those liste d unde r “Absolu te Maxi-

mum Ratin gs” may cau se perman en t da ma ge to th e de vi ce.

This is a stress rating only and functional operation of the

device at these or any other conditions beyond those indi-

cated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions

for extended periods may affect device reliability.

Absolute Maximum Ratings*

access times to 120 ns with power dissipation of just 440

mW. When the device is deselected, the CMOS standby

current is less than 300 µA.

The AT28C010 is accessed like a Static RAM for the read

or write cycle without the need for external components.

The device contains a 128-byte page r egister to allow writ-

ing of up to 128-bytes simultaneously. During a write cy-

cle, the address and 1 to 128-bytes of data are internally

latched, freeing the address and data bus for other opera-

tions. Following the initiation of a write cycle, the device

will automatically write the latched data using an internal

control timer. The end of a write cycle can be detected by

DATA POLLING of I/O7. Once the end of a write cycle has

been detected a new access for a read or write can begin.

Atmel’s 28C010 has additional features to ensure high

quality and manufacturability. The device utilizes internal

error correction for extended endurance and improved

data retention characteristics. An optional software data

protection mechanism is available to guard against inad-

vertent writes. The device also includes an extra 128-

bytes of E2PROM for device identification or tracking.

Description (Continued)

2-244 AT28C010 Mil

Device Ope ration

READ: The AT28C010 is accessed like a Static RAM.

When CE and OE are low and WE is high, the data stor ed

at the memory location determined by the address pins is

asserted on the outputs. The outputs are put in the high

impedance state when either CE or OE is high. This dual-

line control gives designers flexibility in preventing bus

contention in their system.

BYTE WRITE: A low pulse on the WE or CE input with CE

or W E low (respectively) and OE high initiates a write cy-

cle. The address is latched on the falling edge of CE or

WE, whichever occur s last. The data is latched by the firs t

rising edge of CE or WE. Once a byte write has been

started it will automatically time itself to completion. Once

a programming operation has been initiated and for the

duration of tWC, a read operation will effectively be a poll-

ing operation.

PAGE WRITE: The page write operation of the AT28C010

allows 1 to 128-bytes of data to be written into the device

during a single internal programming period. A page write

operation is initiated in the same manner a s a byte write;

the first byte written can then be followed by 1 to 127 ad-

ditional bytes. Each successive byte must be written within

150 µs (tBLC) of the previous byte. If the tBLC limit is ex-

ceeded the AT28C010 will cease accepting data and com-

mence the internal programming operation. All bytes dur-

ing a page write operation must reside on the same page

as defined by the state of the A7 - A16 inputs. For each

WE high to low transition during the page write operation,

A7 - A16 must be the same.

The A0 to A6 inputs are used to spec ify which bytes within

the page are to be written. The bytes may be loaded in any

order and may be altered within the same load period.

Only bytes which are specified for writing will be written;

unnecessary cycling of other bytes within the page does

not occur.

DATA POLLING: The AT28C010 features DATA Polling

to indicate the end of a write cycle. During a byte or page

write cycle an attempted read of the last byte written will

result in the complement of the written data to be pre-

sented on I/O7. Once the write cycle has been completed,

true data is valid on all outputs, and the next write cycle

may begin. DATA Polling may begin at anytime during the

write cycle.

TOGGLE BIT: In addition to DATA Polling the AT28C010

provides another method for determining the end of a write

cycle. During the write operation, successive attempts to

read data from the device will result in I/O6 toggling be-

tween one and zero. O nce the write has completed, I/O6

will stop toggling and valid data will be read. Reading the

toggle bit may begin at any time during the write cycle.

DATA PROTECTION: If precautions are not taken, inad-

vertent writes may occur during transitions of the host sys-

tem power supply. Atmel has incorporated both hardware

and software features that will protec t the memory against

inadvertent writes.

HARDWARE PROTECTION: Hardware features protect

against inadvertent writes to the AT28C010 in the follow-

ing ways: (a) VCC sense - if VCC is below 3.8V (typical) the

write function is inhibited; (b) VCC power-on delay - once

VCC has reached 3.8V the device will automatically time

out 5 ms (typical) before allowing a write: (c) write inhibit -

holding any one of OE low, CE high or WE high inhibits

write cycles; (d) noise filter - pulses of less than 15 ns (typi-

cal) on the WE or CE inputs will not initiate a write cycle.

SOFTWARE DATA PROTECTION: A software controlled

data protection feature has been implemented on the

AT28C010. When enabled, the software data protection

(SDP), will prevent inadvertent writes. The SDP feature

may be enabled or disabled by the user ; the AT28C010 is

shipped from Atmel with SDP disabled.

SDP is enabled by the host system issuing a series of

three write commands; three specific bytes of data are

written to three specific addr esses (r efer to Software Data

Protection Algorithm). After writing the 3-byte command

sequence and after tWC the entire AT28C010 will be pro-

tected against inadvertent write operations. It should be

noted, that once protected the host may still perform a

byte or page write to the AT28C010. This is done by pre-

ceding the data to be written by the same 3-byte command

sequence used to enable SDP.

Once set, SDP will remain active unless the disable com-

mand sequence is issued. Power transitions do not dis-

able SDP and SDP will protect the AT28C010 during

power-up and power-down conditions. All command se-

quences must conform to the page write timing specifica-

tions. The data in the enable and disable command se-

quences is not written to the device and the memory ad-

dresses used in the sequence may be written with data in

either a byte or page write operation.

After setting SDP, any attempt to write to the device with-

out the 3-byte command sequence will start the internal

write timers. No data will be written to the device; however,

for the duration of tWC, read operations will effectively be

polling operations.

(continued)

AT28C010 Mil

2-245

Mode CE OE WE I/O

Read VIL VIL VIH DOUT

Write (2) VIL VIH VIL DIN

Standby/Write Inhibit VIH X (1) X High Z

Write Inhibit X X VIH

Write Inhibit X VIL X

Output Disable X VIH X High Z

Notes: 1. X can be VIL or V IH.

2. Refer to AC Programming Waveforms.

Operating Modes

Symbol Parameter Condition Min Max Units

ILI Input Load Current VIN = 0V to VCC + 1V 10 µA

ILO Output Leakage Current VI/O = 0V to VCC 10 µA

ISB1 VCC Standby Current CMOS CE = VCC - 0.3V to VCC + 1V 300 µA

ISB2 VCC Standby Current TTL CE = 2.0V to VCC + 1V 3 mA

ICC VCC Active Current f = 5 MHz; IOUT = 0 mA 80 mA

VIL Input Low Voltage 0.8 V

VIH Input High Voltage 2.0 V

VOL Output Low Voltage IOL = 2.1 mA .45 V

VOH1 Output High Voltage IOH = -400 µA 2.4 V

VOH2 Output High Voltage CMOS IOH = -100 µA; VCC = 4.5V 4.2 V

DC Characteristics

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

Operating

Temperature (Case) Mil. -55°C - 125°C -55°C - 125°C -55°C - 125°C -55°C - 125°C

VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

DC and AC Operat ing Range

DEVICE IDENTIFICATION: An extra 128-bytes of

E2PROM memory are available to the user for device

identification. By raising A9 to 12V ± 0.5V and using ad-

dress locations 1F F80H to 1FFFFH the bytes may be writ-

ten to or read from in the same manner as the regular

memory array.

OPTIONAL CHIP ERASE MODE: The entire device can

be erased using a 6-byte software code. Please see Soft-

ware Chip Erase application note for details.

Device Operation (Continued)

2-246 AT28C010 Mil

AT28C010-12 AT28C010-15 AT28C010-20 AT28C010-25

Symbol Parameter Min Max Min Max Min Max Min Max Units

tACC Address to Output Delay 120 150 200 250 ns

tCE (1) CE to Output Delay 120 150 200 250 ns

tOE (2) OE to Output Delay 0 50 0 55 0 55 0 55 ns

tDF (3, 4) CE or OE to Output

Float 050055055055ns

OH Output Hold from OE,

CE or Address,

whichever occurred first 0000ns

AC Read Characteristics

Notes: 1. CE may be delayed up to tACC - tCE after the ad dress

transition without impact on tACC.

2. OE may be delayed up to tCE - tOE after the falling

edge of CE withou t impa ct on tCE or by tACC - tOE

after an address change without impact on tACC .

3. tDF is specified from OE or C E w h i chev e r occu rs fi r st

(CL = 5 pF).

4. This parameter is characterized and is not 100% tested.

AC Read Wavef or ms (1, 2, 3, 4)

tR, tF < 5 ns

Input Test Wav ef or ms and

Measure me nt Leve l Output Te st Load

Typ Max Units Conditions

CIN 410pFV

IN = 0V

COUT 812pFV

OUT = 0V

Pin Capacitanc e (f = 1 MHz , T = 25°C) (1)

Note: 1. This parameter is characterized and is not 100% tested.

AT28C010 Mil

2-247

Symbol Parameter Min Max Units

tAS, tOES Address, OE Set-up Time 0 ns

tAH Address Hold Time 50 ns

tCS Chip Select Set-up Time 0 ns

tCH Chip Select Hold Time 0 ns

tWP Write Pulse Width (WE or CE) 100 ns

tDS Data Set-up Time 50 ns

tDH, tOEH Data, OE Hold Time 0 ns

AC Write Characteristics

AC Write Waveforms

WE Controlled

CE Controll ed

2-248 AT28C010 Mil

Symbol Parameter Min Max Units

tWC Write Cycle Time 10 ms

tAS Address Set-up Time 0 ns

tAH Address Hold Time 50 ns

tDS Data Set-up Time 50 ns

tDH Data Hold Time 0 ns

tWP Write Pulse Width 100 ns

tBLC Byte Load Cycle Time 150 µs

tWPH Write Pulse Width High 50 ns

Page Mode Char a ct eris tic s

Page Mode Wr it e Wave for m s (1, 2)

Notes: 1. A7 through A16 must specify the page address during each high to low transition of WE (or CE).

2. OE must be high only when WE and CE are both low.

Chip Erase Waveforms

tS = 5 µsec (min.)

tW = tH = 10 msec (min.)

VH = 12.0 V ± 0. 5V

AT28C010 Mil

2-249

LOAD LAST BYTE

LAST ADDRE SS

LOAD DATA A0

ADDRESS 5555

LOAD DATA 55

ADDRESS 2AAA

LOAD DATA AA

ADDRESS 5555

Notes:

1. Da ta Format : I/O7 - I/O0 (Hex);

Addre ss Format : A14 - A0 (Hex).

2. W rite Protec t st at e will be act iv at ed at en d of write eve n if no

other data is loaded.

3. W rite Protec t st at e will be dea ct iv at ed at en d of write period

even if no other data is loaded.

4. 1 t o 12 8-bytes of data are lo ad ed.

ENTER DA TA

PROTECT STATE

WRITES ENABLED (2)

Software Data

Protection E nabl e Al gor it hm (1)

LOAD DATA XX

ANY ADDRESS (4)

LOAD LAST BYTE

LAST ADDRE SS

LOAD DA TA 55

ADDRESS 2AAA

LOAD DATA AA

ADDRESS 5555

LOAD DA TA 80

ADDRESS 5555

LOAD DA TA 55

ADDRESS 2AAA

LOAD DATA AA

ADDRESS 5555

LOAD DA TA 20

ADDRESS 5555 EXIT DATA

PROTECT STATE (3)

Software Data

Prot ec ti on Di s abl e Al gor it hm (1)

LOAD DATA XX

ANY ADDRESS

(4)

Softwa re Prote ct ed P rogr am Cyc le Wave for m (1, 2, 3)

Notes: 1. A0 - A14 must conform to the addressing sequence for

the first 3-bytes as shown above.

2. After the command sequence has been issued and a

page write opera ti on fol lo ws, the pag e ad dre ss inp ut s

(A7 - A16) must be the same fo r eac h high to lo w

transition of WE (or CE).

3. OE must be high only when WE and CE are both low.

2-250 AT28C010 Mil

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay (2) ns

tWR Write Recovery Time 0 ns

Data Polling Characteristics (1)

Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Data Polling Waveforms

Symbol Parameter Min Typ Max Units

tDH Data Hold Time 10 ns

tOEH OE Hold Time 10 ns

tOE OE to Output Delay (2) ns

tOEHP OE High Pulse 150 ns

tWR Write Recovery Time 0 ns

Toggle Bi t Charac te rist ics (1)

Notes: 1. These parameters are characterized and not 100% tested. 2. See AC Read Characteristics.

Notes: 1. Toggling either OE or CE or both OE and CE will

operate toggle bit.

2. Beginning and ending state of I/O6 will vary.

Toggle Bit Wavef or ms (1, 2, 3)

3. Any address location may be used but the address

should not vary.

AT28C010 Mil

2-251

tACC

(ns)

ICC (mA) Ordering Code Package Operation Range

Active Standby

120 80 0.3 AT28C010(E)-12DM/883 32D6 Military/883C

AT28C010(E)-12EM/883 32L Class B, Fully Compliant

AT28C010-12FM/883 32F (-55°C to 125°C)

AT28C010(E)-12LM/883 44L

AT28C010(E)-12UM/883 30U

150 80 0.3 AT28C010(E)-15DM/883 32D6 Military/883C

AT28C010(E)-15EM/883 32L Class B, Fully Compliant

AT28C010-15FM/883 32F (-55°C to 125°C)

AT28C010(E)-15LM/883 44L

AT28C010(E)-15UM/883 30U

200 80 0.3 AT28C010(E)-20DM/883 32D6 Military/883C

AT28C010(E)-20EM/883 32L Class B, Fully Compliant

AT28C010-20FM/883 32F (-55°C to 125°C)

AT28C010(E)-20LM/883 44L

AT28C010(E)-20UM/883 30U

250 80 0.3 AT28C010(E)-25DM/883 32D6 Military/883C

AT28C010(E)-25EM/883 32L Class B, Fully Compliant

AT28C010-25FM/883 32F (-55°C to 125°C)

AT28C010(E)-25LM/883 44L

AT28C010(E)-25UM/883 30U

120 80 0.3 5962-38267 07 MXX 32D6 Military/883C

5962-38267 07 MZX 32F Class B, Fully Compliant

5962-38267 07 MYX 44L (-55°C to 125°C)

5962-38267 07 MTX 30U

150 80 0.3 5962-38267 05 MXX 32D6 Military/883C

5962-38267 05 MUX 32L Class B, Fully Compliant

5962-38267 05 MZX 32F (-55°C to 125°C)

5962-38267 05 MYX 44L

5962-38267 05 MTX 30U

200 80 0.3 5962-38267 03 MXX 32D6 Military/883C

5962-38267 03 MUX 32L Class B, Fully Compliant

5962-38267 03 MZX 32F (-55°C to 125°C)

5962-38267 03 MYX 44L

5962-38267 03 MTX 30U

250 80 0.3 5962-38267 01 MXX 32D6 Military/883C

5962-38267 01 MUX 32L Class B, Fully Compliant

5962-38267 01 MZX 32F (-55°C to 125°C)

5962-38267 01 MYX 44L

5962-38267 01 MTX 30U

80 0.3 AT28C010-W DIE

Note: 1. See Valid Part Numb er ta bl e on nex t pa ge .

Ordering Inf or ma tion (1)

2-252 AT28C010 Mil

Package Type

32D6 32 Lead, 0.6 00 " Wide , Non -Wi nd owe d, Ceramic Dual Inl ine (CERDIP)

32F 32 Lead, No n-W in do wed , Cera mi c Bot to m-Bra ze d Fl at Package (Flatpa ck)

32L 32 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC)

30U 30 Pin, Ceramic Pin Grid Array (PGA)

WDie

Options

Blank Stand ard Device : End ura nc e = 10K Write Cycles; Write Time = 10 ms

EHigh Endurance Option: Endurance = 100K Write Cycles

The following table lists standard Atmel products that can be ordered.

Device Numbers Speed Package and Temperature Combinations

AT28C010 12 DM/883, EM/88 3, FM/883, LM/883, UM/883

AT28C010E 12 DM/883, EM/88 3, LM/883, UM/883

AT28C010 15 DM/883, EM/88 3, FM/883, LM/883, UM/883

AT28C010E 15 DM/883, EM/88 3, LM/883, UM/883

AT28C010 20 DM/883, EM/88 3, FM/883, LM/883, UM/883

AT28C010E 20 DM/883, EM/88 3, LM/883, UM/883

AT28C010 25 DM/883, EM/88 3, FM/883, LM/883, UM/883

AT28C010E 25 DM/883, EM/88 3, LM/883, UM/883

Valid Part Numbe rs

AT28C010 Mil

2-253