MC74HC390ADT - Motorola / Freescale Semiconductor



SEMICONDUCTOR TECHNICAL DATA

1REV 0

 Motorola, Inc. 1995

10/95

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 #"

High–Performance Silicon–Gate CMOS

The MC54/74HC390A is identical in pinout to the LS390. The device

inputs are compatible with standard CMOS outputs; with pullup resistors,

they are compatible with LSTTL outputs.

This device consists of two independent 4–bit counters, each composed

of a divide–by–two and a divide–by–five section. The divide–by–two and

divide–by–five counters have separate clock inputs, and can be cascaded to

implement various combinations of ÷ 2 and/or ÷ 5 up to a ÷ 100 counter.

Flip–flops internal to the counters are triggered by high–to–low transitions

of the clock input. A separate, asynchronous reset is provided for each 4–bit

counter. State changes of the Q outputs do not occur simultaneously

because of internal ripple delays. Therefore, decoded output signals are

subject to decoding spikes and should not be used as clocks or strobes

except when gated with the Clock of the HC390A.

•Output Drive Capability: 10 LSTTL Loads

•Outputs Directly Interface to CMOS, NMOS, and TTL

•Operating Voltage Range: 2 to 6 V

•Low Input Current: 1 µA

•High Noise Immunity Characteristic of CMOS Devices

•In Compliance with the Requirements Defined by JEDEC Standard

No 7A

•Chip Complexity: 244 FETs or 61 Equivalent Gates

LOGIC DIAGRAM

1, 15

4, 12

2, 14

3, 13

5, 11

6, 10

7, 9

PIN 16 = VCC

PIN 8 = GND

CLOCK A

RESET

CLOCK B

COUNTER

This document contains information on a product under development. Motorola reserves the right

to change or discontinue this product without notice.



PIN ASSIGNMENT

125

CLOCK Bb

QAb

RESET b

CLOCK Ab

VCC

QDb

QCb

QBb

CLOCK Ba

QAa

RESET a

CLOCK Aa

GND

QDa

QCa

QBa

FUNCTION TABLE

Clock

A B Reset Action

X X H Reset

÷ 2 and ÷ 5

X L Increment

÷ 2

X L Increment

÷ 5

D SUFFIX

SOIC PACKAGE

CASE 751B–05

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ORDERING INFORMATION

MC54HCXXXAJ

MC74HCXXXAN

MC74HCXXXAD

MC74HCXXXADT

Ceramic

Plastic

SOIC

TSSOP

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

16 DT SUFFIX

TSSOP PACKAGE

CASE 948F–01

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS*

ÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎÎ

± 20

ÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎÎ

± 25

ÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎÎ

± 50

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air,Plastic or Ceramic DIP†

SOIC Package†

TSSOP Package†

ÎÎÎÎÎÎ

750

500

450

ÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP, SOIC or TSSOP Package

(Ceramic DIP)

ÎÎÎÎÎÎ

260

300

ÎÎÎ

*Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

†Derating — Plastic DIP: – 10 mW/

C from 65

to 125

Ceramic DIP: – 10 mW/

C from 100

to 125

SOIC Package: – 7 mW/

C from 65

to 125

TSSOP Package: – 6.1 mW/

C from 65

to 125

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Figure 1) VCC = 3.0 V

VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

600

500

400

ÎÎÎ

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎÎ

1.5

2.1

3.15

4.2

ÎÎÎ

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Input

Voltage

ÎÎÎÎÎÎÎÎÎ

Vout = 0.1 V or VCC – 0.1 V

|Iout|

20 µA

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎÎ

0.5

0.9

1.35

1.8

ÎÎÎ

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Minimum High–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎÎ

1.9

4.4

5.9

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

2.4 mA

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

3.0

4.5

6.0

ÎÎÎ

2.48

3.98

5.48

ÎÎÎÎ

2.34

3.84

5.34

ÎÎÎÎ

2.20

3.70

5.20

ÎÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high–impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND

(Vin or V out)

VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC54/74HC390A

High–Speed CMOS Logic Data

DL129 — Rev 6 3 MOTOROLA

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎ

Unit

ÎÎÎÎ

125

ÎÎÎÎ

ÎÎÎ

– 55 to

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Maximum Low–Level Output

Voltage

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL

|Iout|

20 µA

ÎÎÎÎ

2.0

4.5

6.0

ÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎ

Vin = VIH or VIL |Iout|

2.4 mA

|Iout|

4.0 mA

|Iout|

5.2 mA

ÎÎÎÎ

3.0

4.5

6.0

ÎÎÎ

0.26

ÎÎÎÎ

0.33

ÎÎÎÎ

0.40

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎÎ

6.0

ÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎ

± 1.0

ÎÎÎ

µA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎÎ

Vin = VCC or GND

Iout = 0 µA

ÎÎÎÎ

6.0

ÎÎÎ

ÎÎÎÎ

160

ÎÎÎ

µA

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

MHz

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock A to QA

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock A to QC

(QA connected to Clock B)

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

200

160

ÎÎÎÎ

250

185

ÎÎÎÎ

300

210

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock B to QB

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock B to QC

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

105

ÎÎÎÎ

180

100

ÎÎÎ

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Clock B to QD

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns)

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎ

Unit

ÎÎÎÎ

125

ÎÎÎÎ

ÎÎÎ

– 55 to

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

Symbol

ÎÎÎÎ

tTLH,

tTHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎ

—

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

NOTES:

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

CPD

Power Dissipation Capacitance (Per Counter)*

Typical @ 25°C, VCC = 5.0 V

CPD Power Dissipation Capacitance (Per Counter)*

*Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

Motorola High–Speed CMOS Data Book (DL129/D).

TIMING REQUIREMENTS (Input tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎÎ

Unit

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎ

VCC

ÎÎÎ

– 55 to

ÎÎÎÎ

125

ÎÎÎ

Unit

ÎÎÎÎ

trec

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Recovery Time, Reset Inactive to Clock A or Clock B

(Figure 2)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Clock A, Clock B

(Figure 1)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Minimum Pulse Width, Reset

(Figure 2)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

ÎÎÎÎ

110

ÎÎÎ

ÎÎÎÎ

tf, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Input Rise and Fall Times

(Figure 1)

ÎÎÎÎ

2.0

3.0

4.5

6.0

ÎÎÎ

1000

800

500

400

ÎÎÎÎ

1000

800

500

400

ÎÎÎÎ

1000

800

500

400

ÎÎÎ

NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).

MC54/74HC390A

High–Speed CMOS Logic Data

DL129 — Rev 6 5 MOTOROLA

PIN DESCRIPTIONS

INPUTS

Clock A (Pins 1, 15) and Clock B (Pins 4, 15)

Clock A is the clock input to the ÷ 2 counter; Clock B is the

clock input to the ÷ 5 counter. The internal flip–flops are

toggled by high–to–low transitions of the clock input.

CONTROL INPUTS

Reset (Pins 2, 14)

Asynchronous reset. A high at the Reset input prevents

counting, resets the internal flip–flops, and forces QA through

QD low.

OUTPUTS

QA (Pins 3, 13)

Output of the ÷ 2 counter.

QB, QC, QD (Pins 5, 6, 7, 9, 10, 11)

Outputs of the ÷ 5 counter. QD is the most significant bit.

QA is the least significant bit when the counter is connected

for BCD output as in Figure 4. QB is the least significant bit

when the counter is operating in the bi–quinary mode as in

Figure 5.

SWITCHING WAVEFORMS

tPLH tPHL

tTLH tTHL

VCC

GND

CLOCK 10% 50%

90%

1/fmax

trec

RESET

Figure 1. Figure 2.

VCC

GND

VCC

GND

10%

50%

90% Q

CLOCK

50%

tPHL

10%

TEST CIRCUIT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

Figure 3.

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

0 1 2 3 4 5 6 7 8 9

EXPANDED LOGIC DIAGRAM

TIMING DIAGRAM

(QA Connected to Clock B)

CLOCK A

RESET

CLOCK A

CLOCK B

RESET

3, 13

5, 11

6, 10

7, 9

1, 15

4, 12

2, 14

DRQ

0 1 2 3 4 5 6

MC54/74HC390A

High–Speed CMOS Logic Data

DL129 — Rev 6 7 MOTOROLA

APPLICATIONS INFORMATION

Each half of the MC54/74HC390A has independent ÷ 2

and ÷ 5 sections (except for the Reset function). The ÷ 2 and

÷ 5 counters can be connected to give BCD or bi–quinary

(2–5) count sequences. If Output QA is connected to the

Clock B input (Figure 4), a decade divider with BCD output is

obtained. The function table for the BCD count sequence is

given in Table 1.

To obtain a bi–quinary count sequence, the input signals

connected to the Clock B input, and output QD is connected

to the Clock A input (Figure 5). QA provides a 50% duty cycle

output. The bi–quinary count sequence function table is

given in Table 2.

Table 1. BCD Count Sequence*

Count

Output

Count

QDQCQBQA

0 LLLL

1 L L L H

2 L L H L

3 L L H H

4 L H L L

5 L H L H

6 L H H L

7 L H H H

8 H L L L

9 H L L H

*QA connected to Clock B input.

Table 2. Bi–Quinary Count Sequence**

Count

Output

Count

QAQDQCQB

0 LLLL

1 L L L H

2 L L H L

3 L L H H

4 L H L L

8 H L L L

9 H L L H

10 H L H L

11 H L H H

12 H H L L

**QD connected to Clock A input.

CONNECTION DIAGRAMS

1, 15

COUNTER

CLOCK A

RESET

Figure 4. BCD Count Figure 5. Bi-Quinary Count

COUNTER

CLOCK B

CLOCK A

RESET

CLOCK B

1, 15 QA

3, 13

5, 11

6, 10

7, 9

4, 12

2, 14

3, 13

5, 11

6, 10

7, 9

4, 12

2, 14

MC54/74HC390A

MOTOROLA High–Speed CMOS Logic Data

DL129 — Rev 6

OUTLINE DIMENSIONS

J SUFFIX

CERAMIC PACKAGE

CASE 620–10

ISSUE V

N SUFFIX

PLASTIC PACKAGE

CASE 648–08

ISSUE R

19.05

6.10

—

0.39

1.40

0.21

3.18

19.93

7.49

5.08

0.50

1.65

0.38

4.31

0.51 15

1.01

1.27 BSC

2.54 BSC

7.62 BSC

MIN MINMAX MAX

INCHES MILLIMETERS

DIM 0.750

0.240

—

0.015

0.055

0.008

0.125

0.785

0.295

0.200

0.020

0.065

0.015

0.170

0.050 BSC

0.100 BSC

0.300 BSC

0.020 15

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEAD WHEN

FORMED PARALLEL.

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE

THE LEAD ENTERS THE CERAMIC BODY.

1 8

916

–A

–

–B

–

D 16 PL

–T

–

SEATING

PLANE

J 16 PL

0.25 (0.010) T A

MS0.25 (0.010) T B

MIN MINMAX MAX

INCHES MILLIMETERS

DIM

18.80

6.35

3.69

0.39

1.02

0.21

2.80

7.50

0.51

19.55

6.85

4.44

0.53

1.77

0.38

3.30

7.74

1.01

0.740

0.250

0.145

0.015

0.040

0.008

0.110

0.295

0.020

0.770

0.270

0.175

0.021

0.070

0.015

0.130

0.305

0.040

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS WHEN

FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

2.54 BSC

1.27 BSC

0.100 BSC

0.050 BSC

–A

–

1 8

916

HGD 16 PL

–T

–

SEATING

PLANE

KJM

T A0.25 (0.010) M M

0.25 (0.010) T B A

MS S

MIN MINMAX MAX

MILLIMETERS INCHES

DIM

9.80

3.80

1.35

0.35

0.40

0.19

0.10

5.80

0.25

10.00

4.00

1.75

0.49

1.25

0.25

6.20

0.50

0.386

0.150

0.054

0.014

0.016

0.008

0.004

0.229

0.010

0.393

0.157

0.068

0.019

0.049

0.009

0.244

0.019

1.27 BSC 0.050 BSC

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

916

–A

–

–B

–

D16 PL

–T

–

SEATING

PLANE

R X 45°

P 8 PL

0.25 (0.010) B

M M

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B–05

ISSUE J

MC54/74HC390A

High–Speed CMOS Logic Data

DL129 — Rev 6 9 MOTOROLA

OUTLINE DIMENSIONS

DT SUFFIX

PLASTIC TSSOP PACKAGE

CASE 948F–01

ISSUE O

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C––– 1.20 ––– 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH.

PROTRUSIONS OR GATE BURRS. MOLD FLASH OR

GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER

SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED AT

DATUM PLANE –W–.

_ _ _ _

SECTION N–N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉ

DETAIL E

2X L/2

–U–

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

–T–

–V–

–W–

0.25 (0.010)

16X REFK

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

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MC54/74HC390A/D

*MC54/74HC390A/D*

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