SEMICONDUCTOR TECHNICAL DATA $ # !& $#! %# / / #" J SUFFIX CERAMIC PACKAGE CASE 620-10 16 1 High-Performance Silicon-Gate CMOS The MC54/74HC390A is identical in pinout to the LS390. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This device consists of two independent 4-bit counters, each composed of a divide-by-two and a divide-by-five section. The divide-by-two and divide-by-five counters have separate clock inputs, and can be cascaded to implement various combinations of / 2 and/or / 5 up to a / 100 counter. Flip-flops internal to the counters are triggered by high-to-low transitions of the clock input. A separate, asynchronous reset is provided for each 4-bit counter. State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the Clock of the HC390A. N SUFFIX PLASTIC PACKAGE CASE 648-08 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 16 1 DT SUFFIX TSSOP PACKAGE CASE 948F-01 16 1 * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No 7A * Chip Complexity: 244 FETs or 61 Equivalent Gates ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP PIN ASSIGNMENT LOGIC DIAGRAM CLOCK A 1, 15 /2 COUNTER 3, 13 CLOCK Aa 1 16 VCC RESET a 2 15 CLOCK Ab QAa 3 14 RESET b CLOCK Ba 4 13 QAb QBa 5 12 CLOCK Bb QCa 6 11 QBb QDa 7 10 QCb GND 8 9 QDb QA 5, 11 CLOCK B 4, 12 /5 COUNTER QB 6, 10 QC 7, 9 QD FUNCTION TABLE Clock RESET 2, 14 A B Reset Action X X H X L Reset / 2 and / 5 Increment /2 Increment /5 PIN 16 = VCC PIN 8 = GND X This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 10/95 Motorola, Inc. 1995 1 REV 0 L IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIII IIIIII III IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HC390A MAXIMUM RATINGS* Symbol VCC Parameter DC Supply Voltage (Referenced to GND) Value Unit - 0.5 to + 7.0 V V Vin DC Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 Vout DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package 750 500 450 mW Tstg Storage Temperature - 65 to + 150 _C Iin TL This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v _C Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP, SOIC or TSSOP Package (Ceramic DIP) 260 300 * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII IIIIII IIIIIIIIIIIIIII IIIIIIIIIIIII IIIIIIIII IIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III v v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII v IIII IIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol VCC Vin, Vout Parameter DC Supply Voltage (Referenced to GND) Min Max Unit 2.0 6.0 V 0 VCC V - 55 + 125 _C 0 0 0 0 1000 600 500 400 ns DC Input Voltage, Output Voltage (Referenced to GND) TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Figure 1) VCC = 2.0 V VCC = 3.0 V VCC = 4.5 V VCC = 6.0 V DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85_C 125_C Unit VIH Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 V Minimum High-Level Output Voltage Vin = VIH or VIL |Iout| 20 A 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 VOH Vin = VIH or VIL |Iout| |Iout| |Iout| MOTOROLA 2 2.4 mA 4.0 mA 5.2 mA High-Speed CMOS Logic Data DL129 -- Rev 6 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII v IIII v III IIIIIIIIIIIIIIIIIIIIII IIII III IIII IIII III v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII III IIII IIII III v IIII v IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIII v IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII v IIII v III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HC390A DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol VOL Parameter Test Conditions Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20 A Vin = VIH or VIL |Iout| |Iout| |Iout| Iin ICC 2.4 mA 4.0 mA 5.2 mA VCC V - 55 to 25_C 85_C 125_C 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Unit V Maximum Input Leakage Current Vin = VCC or GND 6.0 0.1 1.0 1.0 A Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Iout = 0 A 6.0 4 40 160 A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns) Guaranteed Limit Symbol Parameter VCC V - 55 to 25_C 85_C 125_C Unit fmax Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 3) 2.0 3.0 4.5 6.0 10 15 30 50 9 14 28 45 8 12 25 40 MHz tPLH, tPHL Maximum Propagation Delay, Clock A to QA (Figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 20 16 80 45 25 21 90 50 30 27 ns tPLH, tPHL Maximum Propagation Delay, Clock A to QC (QA connected to Clock B) (Figures 1 and 3) 2.0 3.0 4.5 6.0 200 160 35 30 250 185 45 40 300 210 60 50 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QB (Figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 20 16 80 45 25 21 90 50 30 27 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QC (Figures 1 and 3) 2.0 3.0 4.5 6.0 90 56 32 25 105 70 38 31 180 100 45 40 ns tPLH, tPHL Maximum Propagation Delay, Clock B to QD (Figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 20 16 80 45 25 21 90 50 30 27 ns tPHL Maximum Propagation Delay, Reset to any Q (Figures 2 and 3) 2.0 3.0 4.5 6.0 80 48 28 21 95 65 32 25 110 75 40 30 ns High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII v IIII v III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII MC54/74HC390A AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tf = tf = 6 ns) Guaranteed Limit VCC V - 55 to 25_C 85_C 125_C Maximum Output Transition Time, Any Output (Figures 1 and 3) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns Maximum Input Capacitance -- 10 10 10 pF Symbol tTLH, tTHL Cin Parameter Unit NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII v IIII v III IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII CPD Power Dissipation Capacitance (Per Counter)* pF 35 * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). TIMING REQUIREMENTS (Input tr = tf = 6 ns) Guaranteed Limit VCC V - 55 to 25_C Minimum Recovery Time, Reset Inactive to Clock A or Clock B (Figure 2) 2.0 3.0 4.5 6.0 tw Minimum Pulse Width, Clock A, Clock B (Figure 1) tw Symbol trec tf, tf 85_C 125_C 25 15 5 5 30 20 6 5 40 30 10 7 ns 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns Minimum Pulse Width, Reset (Figure 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns Maximum Input Rise and Fall Times (Figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns Parameter Unit NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA 4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC390A PIN DESCRIPTIONS INPUTS OUTPUTS Clock A (Pins 1, 15) and Clock B (Pins 4, 15) QA (Pins 3, 13) Clock A is the clock input to the / 2 counter; Clock B is the clock input to the / 5 counter. The internal flip-flops are toggled by high-to-low transitions of the clock input. Output of the / 2 counter. QB, QC, QD (Pins 5, 6, 7, 9, 10, 11) CONTROL INPUTS Outputs of the / 5 counter. QD is the most significant bit. QA is the least significant bit when the counter is connected for BCD output as in Figure 4. QB is the least significant bit when the counter is operating in the bi-quinary mode as in Figure 5. Reset (Pins 2, 14) Asynchronous reset. A high at the Reset input prevents counting, resets the internal flip-flops, and forces QA through QD low. SWITCHING WAVEFORMS CLOCK tf 90% 50% 10% 10% tw tr tw VCC VCC 50% RESET GND GND tPHL 1/fmax tPLH Q tPHL 50% Q 90% 50% 10% trec tTLH tTHL VCC 50% CLOCK GND Figure 1. Figure 2. TEST CIRCUIT TEST POINT OUTPUT DEVICE UNDER TEST CL* * Includes all probe and jig capacitance Figure 3. High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HC390A EXPANDED LOGIC DIAGRAM 1, 15 CLOCK A Q C D 4, 12 CLOCK B R R 5, 11 Q QB Q C D QA Q C D 3, 13 Q R Q 6, 10 Q C Q 7, 9 Q D C D R 2, 14 RESET TIMING DIAGRAM (QA Connected to Clock B) 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 CLOCK A RESET QA QB QC QD MOTOROLA 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC390A APPLICATIONS INFORMATION Each half of the MC54/74HC390A has independent / 2 and / 5 sections (except for the Reset function). The / 2 and / 5 counters can be connected to give BCD or bi-quinary (2-5) count sequences. If Output QA is connected to the Clock B input (Figure 4), a decade divider with BCD output is obtained. The function table for the BCD count sequence is given in Table 1. To obtain a bi-quinary count sequence, the input signals connected to the Clock B input, and output Q D is connected to the Clock A input (Figure 5). QA provides a 50% duty cycle output. The bi-quinary count sequence function table is given in Table 2. Table 1. BCD Count Sequence* Table 2. Bi-Quinary Count Sequence** Output Output Count QD QC QB QA Count QA QD QC QB 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H L L L L H H H H L L L L H H L L H H L L L H L H L H L H L H 0 1 2 3 4 8 9 10 11 12 L L L L L H H H H H L L L L H L L L L H L L H H L L L H H L L H L H L L H L H L * QA connected to Clock B input. ** QD connected to Clock A input. CONNECTION DIAGRAMS CLOCK A CLOCK B RESET 1, 15 4, 12 /2 COUNTER 3, 13 5, 11 /5 COUNTER 6, 10 7, 9 1, 15 QA CLOCK A QB CLOCK B QC QD /5 COUNTER 3, 13 QA 5, 11 QB 6, 10 7, 9 QC QD 2, 14 2, 14 RESET Figure 4. BCD Count High-Speed CMOS Logic Data DL129 -- Rev 6 4, 12 /2 COUNTER Figure 5. Bi-Quinary Count 7 MOTOROLA MC54/74HC390A OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -A - 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIM F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. -B - L C DIM A B C D E F G J K L M N -T K N SEATING - PLANE E M F J 16 PL 0.25 (0.010) G D 16 PL 0.25 (0.010) T A M 9 1 8 T B N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A - 16 M C DIM A B C D F G H J K L M S L S -T - SEATING PLANE K H D 16 PL 0.25 (0.010) M M J G T A M D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A - 16 1 P 8 PL 0.25 (0.010) 8 M B M G K F R X 45 C -T SEATING - PLANE MOTOROLA J M D 16 PL 0.25 (0.010) M T B S A S 8 INCHES MILLIMETERS MIN MAX MIN MAX 0.740 0.770 18.80 19.55 6.35 0.250 0.270 6.85 3.69 0.145 0.175 4.44 0.39 0.015 0.021 0.53 1.02 0.040 0.070 1.77 0.100 BSC 2.54 BSC 0.050 BSC 1.27 BSC 0.21 0.008 0.015 0.38 2.80 0.110 0.130 3.30 7.50 0.295 0.305 7.74 0 0 10 10 0.020 0.040 0.51 1.01 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B - MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. B F S S INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC390A OUTLINE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948F-01 ISSUE O 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S CCC EE CCC EE CCC EE CCC EE S S K K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. 8 1 N 0.25 (0.010) 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. M N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE H D DETAIL E DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ G Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 High-Speed CMOS Logic Data DL129 -- Rev 6 CODELINE 9 *MC54/74HC390A/D* MC54/74HC390A/D MOTOROLA