X2040CF-08ST - ON Semiconductor L.L.C.

August, 2011 − Rev. 3

1Publication Order Number:

P2040C/D

P2040C

LCD Panel EMI Reduction IC

Description

The P2040C is a selectable spread spectrum frequency modulator

designed specifically for digital flat panel applications. The P2040C

reduces electromagnetic interference (EMI) at the clock source which

provides system wide reduction of EMI of all clock dependent signals.

The P2040C allows significant system cost savings by reducing the

number of circuit board layers and shielding that are traditionally

required to pass EMI regulations.

The P2040C uses the most efficient and optimized modulation

profile approved by the FCC and is implemented in a proprietary

all−digital method. The P2040C modulates the output of a single PLL

in order to “spread” the bandwidth of a synthesized clock and, more

importantly, decreases the peak amplitudes of its harmonics. This

results in a significantly lower system EMI compared to the typical

narrow band signal produced by oscillators and most frequency

generators. Lowering EMI by increasing a signal’s bandwidth is called

‘spread spectrum clock generation.’

Applications

The P2040C is targeted towards digital flat panel applications for

Notebook PCs, Palm−size PCs, Office Automation Equipments, and

LCD Monitors.

Features

•FCC Approved Method of EMI Attenuation

•Provides up to 15 dB of EMI Suppression

•Generates a Low EMI Spread Spectrum Clock of the Input

Frequency

•50 MHz to 173 MHz Input Frequency Range

•Optimized for 54 MHz, 65 MHz, 81 MHz, 140 MHz, and 162 MHz

Pixel Clock Frequencies

•Internal Loop Filter Minimizes External Components and Board

Space

•8 Selectable Spread Ranges, up to ±2.2%

•SSON# Control Pin for Spread Spectrum Enable and Disable Options

•2 Selectable Modulation Rates

•Low Cycle−to−Cycle Jitter

•3.3 V Operating Voltage

•Ultra Low Power CMOS Design

•Supports Most Mobile Graphic Accelerator and LCD Timing

Controller Specifications

•Available in 8−pin SOIC and TSSOP Packages

•These are Pb−Free Devices

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SOIC−8

S SUFFIX

CASE 751BD

PIN CONFIGURATION

(Top View)

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

ORDERING INFORMATION

VDD

SR0

ModOUT

SSON#

MRA

SR1

CLKIN

VSS

TSSOP−8

T SUFFIX

CASE 948AL

P2040C

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Figure 1. Block Diagram

VSS

CLKIN Frequency

Divider

Feedback

Divider

Modulation

Phase

Detector

VDD

Loop

Filter

PLL

VCO

ModOUT

Output

Divider

SR1SR0 MRA SSON#

Table 1. ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Rating Unit

VDD, VIN Voltage on any pin with respect to Ground −0.5 to +4.6 V

TSTG Storage temperature −65 to +125 °C

TAOperating temperature −40 to +125 °C

TsMax. Soldering Temperature (10 sec) 260 °C

qJA Thermal Resistance from Junction to Ambient

(No Air Flow)

For SOIC Package 156.5 °C/W

For TSSOP Package 124

TJJunction Temperature 150 °C

TDV Static Discharge Voltage (As per JEDEC STD22− A114−B) 2 KV

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

Table 2. PIN DESCRIPTION

Pin# Pin Name Type Description

1 CLKIN I External reference frequency input. Connect to externally generated reference signal.

2 MRA I Digital logic input used to select modulation rate. This pin has an internal pull−up resistor.

3 SR1 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.

4 VSS P Ground to entire chip. Connect to system ground.

5 SSON# I Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function

enabled when LOW, disabled when HIGH. This pin has an internal pull−low resistor.

6 ModOUT O Spread spectrum Clock Output.

7 SR0 I Digital logic input used to select Spreading Range. This pin has an internal pull−up resistor.

8 VDD P Power supply for the entire chip.

P2040C

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Table 3. MODULATION SELECTION (Commercial)

MRA SR1 SR0

Spreading Range

Modulation Rate

54 MHz 65 MHz 81 MHz 140 MHz 162 MHz

0 0 0 ±1.4% ±1.2% ±1.0% ±0.6% ±0.4% (Fin/80) * 62.49 KHz

0 0 1 ±2.0% ±1.9% ±1.6% ±1.0% ±0.8% (Fin/80) * 62.49 KHz

0 1 0 ±1.1% ±0.9% ±0.5% ±0.3% ±0.3% (Fin/80) * 62.49 KHz

0 1 1 ±1.8% ±1.5% ±1.0% ±0.54% ±0.4% (Fin/80) * 62.49 KHz

1 0 0 ±1.3% ±1.3% ±1.3% ±1.25% ±1.1% (Fin/80) * 20.83 KHz

1 0 1 ±2.2% ±2.1% ±2.1% ±2.0% ±1.8% (Fin/80) * 20.83 KHz

1 1 0 ±1.4% ±1.3% ±1.4% ±1.2% ±0.9% (Fin/80) * 20.83 KHz

1 1 1 ±2.1% ±2.1% ±2.1% ±1.9% ±1.4% (Fin/80) * 20.83 KHz

Spread Spectrum Selection

Table 3 illustrates the possible spread spectrum options.

The optimal setting should minimize system EMI to the

fullest without affecting system performance. The spreading

is described as a percentage deviation of the center

frequency (Note: The center frequency is the frequency of

the external reference input on CLKIN, Pin 1).

Example:

P2040C is designed for high resolution flat panel

applications and is able to support panel frequencies from

50 MHz to 173 MHz. For a 65 MHz pixel clock frequency,

a spreading selection of MRA = 0, SR1 = 1 and SR0 = 1

provides a percentage deviation of ±1.50% (see Table 3).

This result in frequency on ModOUT being swept from

64.03 MHz to 65.98 MHz at a modulation rate of 50.77 KHz

(see Table 3). This particular example (see figure below)

given here is a common EMI reduction method for notebook

LCD panel and has already been implemented by most of the

leading OEM and mobile graphic accelerator

manufacturers.

Figure 2. Application Schematic for Mobile LCD Graphics Controllers

P2040C

+3.3 V

0.1 mF

65 MHz from graphics accelerator.

VDD

SR0

ModOUT

SSON#

CLKIN

MRA

SR1

VSS

Modulated 65 MHz signal with

±1.5% deviation and modulation

rate of 50.77 KHz. This signal is

connected back to the spread

spectrum input pin (SSIN) of the

graphics accelerator.

Digital control for the SS

enable or disable.

P2040C

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Table 4. DC ELECTRICAL CHARACTERISTICS

(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated.)

Symbol Parameter Min Typ Max Unit

VIL Input low voltage VSS−0.3 −0.8 V

VIH Input high voltage 2.0 −VDD+0.3 V

IIL Input low current (pull−up resistor on inputs SR0, SR1 and MRA) − − −40 mA

IIH Input high current (pull−down resistor on input SSON#) − − 40 mA

VOL Output low voltage (VDD = 3.3 V, IOL = 20 mA) − − 0.4 V

VOH Output high voltage (VDD = 3.3 V, IOL = 20 mA) 2.5 − − V

IDD Static supply current standby mode −0.7 −mA

ICC Dynamic supply current (3.3 V and 10 pF loading) 9 16 22 mA

VDD Operating Voltage 3.0 3.3 3.6 V

tON Power−up time (first locked cycle after power up) −0.18 −mS

ZOUT Clock output impedance −50 −W

Table 5. AC ELECTRICAL CHARACTERISTICS

Symbol Parameter Min Typ Max Unit

fIN Input frequency 50 173 MHz

tLH (Note 1) Output rise time (measured at 0.8 V to 2.0 V) 0.3 0.7 1.0 nS

tHL (Note 1) Output fall time (measured at 2.0 V to 0.8 V) 0.3 0.7 1.0 nS

tJC Jitter (cycle−to−cycle) − − 360 pS

tDOutput duty cycle 45 50 55 %

1. tLH and tHL are measured into a capacitive load of 15 pF.

P2040C

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PACKAGE DIMENSIONS

TSSOP8, 4.4x3

CASE 948AL−01

ISSUE O

E1 E

TOP VIEW

SIDE VIEW END VIEW

L1 L

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MO-153.

SYMBOL

MIN NOM MAX

0º 8º

0.05

0.80

0.19

0.09

0.50

2.90

6.30

4.30

0.65 BSC

1.00 REF

1.20

0.15

1.05

0.30

0.20

0.75

3.10

6.50

4.50

0.90

0.60

3.00

6.40

4.40

P2040C

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

P2040C

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Table 6. ORDERING INFORMATION

Part Number Marking Package Type Temperature

P2040CF−08ST P2040CF 8−Pin SOIC, TUBE, Pb Free Commercial

P2040CF−08SR P2040CF 8−Pin SOIC, TAPE & REEL, Pb Free Commercial

P2040CF−08TT P2040CF 8−Pin TSSOP, TUBE, Pb Free Commercial

P2040CF−08TR P2040CF 8−Pin TSSOP, TAPE & REEL, Pb Free Commercial

I2040CF−08ST I2040CF 8−Pin SOIC, TUBE, Pb Free Industrial

I2040CF−08SR I2040CF 8−Pin SOIC, TAPE & REEL, Pb Free Industrial

I2040CF−08TT I2040CF 8−Pin TSSOP, TUBE, Pb Free Industrial

I2040CF−08TR I2040CF 8−Pin TSSOP, TAPE & REEL, Pb Free Industrial

X2040CF−08ST X2040CF 8−Pin SOIC, TUBE, Pb Free Automotive

X2040CF−08SR X2040CF 8−Pin SOIC, TAPE & REEL, Pb Free Automotive

X2040CF−08TT X2040CF 8−Pin TSSOP, TUBE, Pb Free Automotive

X2040CF−08TR X2040CF 8−Pin TSSOP, TAPE & REEL, Pb Free Automotive

P2040CG−08ST P2040CG 8−Pin SOIC, TUBE, Green Commercial

P2040CG−08SR P2040CG 8−Pin SOIC, TAPE & REEL, Green Commercial

P2040CG−08TT P2040CG 8−Pin TSSOP, TUBE, Green Commercial

P2040CG−08TR P2040CG 8−Pin TSSOP, TAPE & REEL, Green Commercial

I2040CG−08ST I2040CG 8−Pin SOIC, TUBE, Green Industrial

I2040CG−08SR I2040CG 8−Pin SOIC, TAPE & REEL, Green Industrial

I2040CG−08TT I2040CG 8−Pin TSSOP, TUBE, Green Industrial

I2040CG−08TR I2040CG 8−Pin TSSOP, TAPE & REEL, Green Industrial

X2040CG−08ST X2040CG 8−Pin SOIC, TUBE, Green Automotive

X2040CG−08SR X2040CG 8−Pin SOIC, TAPE & REEL, Green Automotive

X2040CG−08TT X2040CG 8−Pin TSSOP, TUBE, Green Automotive

X2040CG−08TR X2040CG 8−Pin TSSOP, TAPE & REEL, Green Automotive

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

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P2040C/D

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