AM29F200AT-150SE - Advanced Micro Devices

PRELIMINARY

Publicati on# 20637 Rev: BAmendment/+4

Issue Date: January 3, 2000

Am29F200A

2 Megabit (256 K x 8-Bit/128 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory

DISTINCTIVE CHARACTERISTICS

■5.0 V ± 10% for read and write operations

— Minimizes system level power requirements

■High performan c e

— Access times as fast as 55 ns

■Low power consumptio n

— 20 mA typical active read current (byte mode)

— 28 mA typical active read current for

(word mode)

— 30 mA typical program/erase current

—1

µA typical standby current

■Sector erase architectu re

— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and

three 64 Kbyt e sec tors (byte mode)

— One 8 Kword, two 4 Kword, one 16 Kword, and

three 32 Kword sectors (word mode)

— Supports full chip erase

— Sector Protection features:

A hardware method of locking a sector to

prevent any program or erase operations within

that sector

Sectors can be locked via programming

equipment

Temporary Sector Unprotect feature allows code

changes in prev iously locked sectors

■Top or bottom boot block confi gu rations

available

■Embe dded Algorithms

— Embedded Erase algorithm automatically

preprogr ams and erases the ent ire chip or any

combination of designated sectors

— Embedded Program algorithm automatically

writes and verifies data at specif ied addresses

■Minimum 100,000 write/ erase cyc les guaranteed

■Package options

— 44-pin SO

— 48-pin TSOP

■Compatible with JEDEC standar ds

— Pinout and software compatible with

single-power-supply flash

— Superior inadvertent write protection

■Data# Polling and Toggle Bit

— Detects program or eras e cycle completion

■Ready/Busy# output (RY/BY#)

— Hardware method for detection of program or

erase cycle completi on

■Erase Suspend/Erase Resume

— Supports reading data from a sector not being

erased

■Hardware RESET# pin

— Resets internal state machine to the reading

array data

2 Am29F200A

PRELIMINARY

GENERAL DESCRIPTION

The Am29F200A is a 2 Mbit, 5.0 Volt-only Flash mem-

ory organized as 262,144 bytes or 131,072 words . The

8 bits of data appear on DQ0–DQ7; the 16 bits on DQ0–

DQ15. The Am29F200A is offered in 44-pin SO and

48-pin TSOP packages. This device is designed to be

programmed in-system with the standard system 5.0

volt VCC supply. A 12.0 volt VPP is not required for

program or erase operations. The device can also be

reprogrammed in standard EPROM programmers.

The standard device offers access times of 55, 70,

90, 120, and 150 ns, allowing operation of

high- spe ed mi crop roc essor s withou t w ait s tat es. To

eliminate bus contention the device has separate

chip enable (CE#), write enable (WE#) and output

enable (OE#) controls.

The de vice requires only a single 5. 0 v o lt po wer sup-

ply for both read and write functions. Inter nally gener-

ated and regulated voltages are provided for the

program and erase operations.

The de vice is entirely command set compatib le with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using stan-

dard microprocessor write timings. Register contents

serve as input to an internal state-machine that con-

trols the er ase and programming circuitry. Write cycles

also internally latch addresses and data neede d f or the

programming and erase operations. Reading data out

of the device is similar to reading from other Flash or

EPROM de vices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin.

Device erasure occurs by executing the erase com-

mand sequence. This initiates the Embedded Erase

algorithm—an internal algorithm that automatically

preprograms the array (if it is not already pro-

grammed) before executing the erase operat ion. Dur-

ing erase, the device automatically times the erase

pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by observing the RY/BY#

pin, or by reading the DQ7 (Data# Polling) and DQ6

status bits. After a program or erase cycle has been

completed, the de vice is ready to read arra y data or ac-

cept another command.

The sector erase arch itecture all ows memory sect ors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of mem-

ory. This can be achie v ed via prog ramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure . True background er ase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading arr a y data. The RESET# pin ma y be tied to the

system reset circuitr y. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The system can place the device into the standby mode.

Power cons umption is g re atly r educed in t his mode .

AMD’s Flash technolo gy c ombines years of Flash me m-

ory manufacturing experience to produce the highest le v-

els of quality, reliability and cost effectiveness. The de vice

electrically erases all bits within a sector simulta-

neously via Fowler-Nordheim tunneling. The data is

prog rammed us ing ho t e l e ct r on i n je ct i on.

Am29F200A 3

PRELIMINARY

PRODUCT SELECTOR GUIDE

BLOCK DIAGRAM

Family Part Number Am29F200A

Speed Option VCC = 5.0 V ± 5% -55

VCC = 5.0 V ± 10% -70 -90 -120 -150

Max access time, ns (tACC) 55 70 90 120 150

Max CE# access time, ns (tCE) 55 70 90 120 150

Max OE# access time, ns (tOE) 3030355055

Erase Voltage

Generator Input/Output

Buffers

Data

Latch

Y-Gating

Cell MatrixX-Decoder

Y-Decoder

Address Latch

Chip Enable

Output Enable

Logic

PGM Vo ltag e

Generator

Timer

VCC Detector

State

Control

Command

WE#

CE#

OE#

A0–A16

STB

DQ0–DQ15

RY/BY#

Buffer RY/BY#

BYTE#

RESET#

A-1

VCC

VSS

20637B-1

4 Am29F200A

PRELIMINARY

CONNECTION DIAGRAMS

RY/BY#

CE#

VSS

OE#

DQ0

DQ8

DQ1

DQ9

DQ2

DQ10

DQ3

DQ11

RESET#

WE#

A10

A11

A12

A13

A14

A15

A16

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ5

DQ12

DQ4

VCC

20637B-2

Am29F200A 5

PRELIMINARY

CONNECTION DIAGRAMS

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

20637B-3

Standard TSOP

A16

DQ2

BYTE#

VSS

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

VSS

CE#

DQ5

DQ12

DQ4

VCC

DQ11

DQ3

DQ10

A15

A14

A13

A12

A11

A10

WE#

RESET#

RY/BY#

20637B-4

Reverse TSOP

6 Am29F200A

PRELIMINARY

PIN CONFIGURATION

A0–A16 = 17 addresses

DQ0–DQ14 = 15 data inputs/outputs

DQ15/A-1 = DQ15 (data input/output, word mode),

A-1 (LSB address input, byte mode)

BYTE# = Selects 8-bit or 16-bit mode

CE# = Chip enable

OE# = Output enable

WE# = Write enable

RESET# = Hardware reset pin, active low

RY/BY# = Ready/Busy# output

VCC = +5.0 V single power supply

(see Product Selector Guide for

device speed ratings and voltage

supply toler ances )

VSS = Device ground

NC = Pin not connected internally

LOGIC SYMBOL

20637B-5

17 16 or 8

DQ0–DQ15

(A-1)

A0–A16

CE#

OE#

WE#

RESET#

BYTE# RY/BY#

Am29F200A 7

PRELIMINARY

ORDERING INFORMATION

Standard Prod ucts

AMD standard products are a vailable in se veral packages and operating ranges. The order number (V alid Combination) is formed

by a combination of:

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in v olume for this device. Consult the local AMD sales

office to confirm a vailability of specific valid combinations and

to check on newly released combinations.

DEVICE NUMBER/DESCRIPTION

Am29F200A

2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Program and Erase

OPTION AL PROCES SI NG

Blank = Standard Processing

B = Burn-in

(Contact an AMD representative for more information)

TEMPER ATURE RA NG E

C=Comm erc ial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PACKAG E TY PE

E = 48-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 048)

F = 48-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR048)

S = 44-Pin Small Outline Package (SO 044)

SPEED OPTION

See Product Selector Guide and Valid Combinations

BOOT CODE SECTOR ARCHITECTURE

T = Top Sector

B = Bottom Sector

CE-55Am29F200A T

Valid Combinations

AM29F200AT-55,

AM29F200AB-55 EC, EI, FC, FI, SC, SI

AM29F200AT-70,

AM29F200AB-70

EC, EI, EE,

FC, FI, FE,

SC, SI, SE

AM29F200AT-90,

AM29F200AB-90

AM29F200AT-120,

AM29F200AB-120,

AM29F200AT-150,

AM29F200AB-150,

8 Am29F200A

PRELIMINARY

DEVICE BUS OPERATIONS

This section describes the requirements and use of the

device bus operations, which are initiated through the

internal command register. The command register it-

self does not occupy any addressable memory loca-

tion. The regi st er is composed of latches that store the

commands, along with the address and data informa-

tion needed to execute the command. The contents of

the register serve as inputs to the internal state ma-

chine. The state machine outputs dictate the function of

the device. The appropriate device bus operations

table lists the inputs and control le vels required, and the

resulting output. The following subsections describe

each of these operations in further detail.

Table 1. Am29F200A Device Bus Operati o ns

Legend:

L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0

0.5 V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In

Note: See the sections on Sector Protection and Temporary Sector Unprotect for more information.

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O

pins DQ15–DQ0 oper ate in t he b y te or word c onfigur a-

tion. If the BYTE# pin is set at logic ‘1’, the device is in

word configuration, DQ15–DQ0 are active and con-

trolled by CE# and OE#.

If the BYTE# pin is set at logic ‘0’, the device is in byte

configurat ion, and only data I/O pins DQ0–DQ7 are ac-

tive and controlled by CE# and OE#. The data I/O pins

DQ8–DQ14 are tri-stated, and the DQ15 pin is used as

an input for the LSB (A-1) address function.

Requirements for Reading Array Data

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device . OE# is the output control

and gates arra y dat a to the output pins . WE# should re-

main at VIH. On x16 (word-wide) devices , the BYTE# pin

determines whether the device outputs array data in

words or bytes.

The internal state machine is set for reading array

data upon device power-up , or after a hardware reset.

This ensures that no spur ious alteration of the mem-

ory content occurs during the power transition. No

command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that as-

sert valid addresses on the device address inputs

produce valid data on the device data outputs. The

device remains enabled for read access until the

command register contents are altered.

See “Reading Array Data” for more information. Refer

to the AC Read Operations table for timing specifica-

tions and to the Read Operations Timings diagram for

the timing waveforms. ICC1 in the DC Characteristics

table represents the active current specification for

reading array data.

Writing Commands/Command Sequences

To wr ite a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and O E # to V IH.

On x16 (word-wide) devices, for program operations,

the BYTE# pin determines whether the device ac-

cepts program data in bytes or words. Refer to

“Word/Byte Configuration” for more infor mation.

Operation CE# OE# WE# RESET# A0–A16 DQ0–DQ7

DQ8–DQ15

BYTE#

= VIH

BYTE#

= VIL

Read L L H H AIN DOUT DOUT High-Z

Write L H L H AIN DIN DIN High-Z

CMOS Sta ndby VCC ± 0.5 V X X VCC ± 0.5 V X High-Z High-Z High-Z

TTL Standby H X X H X High-Z High-Z High-Z

Output Disable L H H H X High-Z High-Z High-Z

Hardware Reset X X X L X High-Z High-Z High-Z

Temporary Sector Unprotect

(See Note) XXX V

ID AIN DIN DIN X

Am29F200A 9
PRELIMINARY
An erase oper at ion can er ase  one sect or, multiple sec-
tors, or the entire de vice. The Sector Address Tables in-
dicate the address s pace that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
tions” section for details on erasing a sector or the en-
tire chip, or suspending/resuming the erase operation.
After the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autos elect codes from the inter-
nal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in this
mode. Refer to the “Autoselect Mode” and “Autoselect
Command Sequence” sections f or more information.
ICC2 in the DC Characteristics table represents the ac-
tive current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and tim ing diagrams for write operations.
Program and Erase Operation Status
During an erase or prog ram oper ation, th e system ma y
check the status of the operation by reading the status
bits on DQ7–DQ0. St andard read cycle timings and I CC
read specifications apply. Refer to “Write Operation
Status” for more information, and to each AC Charac-
teristics section in th e appropriate data sheet for timing
diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current  co nsumption is g reat ly reduced,  and  the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The de vice enters the CMOS standb y mode when CE#
and RESET# pins are both held at VCC ± 0.5 V. (Note
that this is a more restricted voltage range than VIH.)
The device enters the TTL standby mode when CE#
and RESET# pins are both held at VIH. The device re-
quires standard access time (tCE) f or read access when
the de vice is in either of these standb y modes, bef ore it
is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is dr iven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during  eras ure or program -
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, ICC3 represents the
standby current specification.
RESET#: Hardware Reset Pin 
The RESET# pin p rovides a hard ware method of  reset-
ting the device to reading arr ay data. When the s ystem
drives the RESET# pin low for  at least a period of tRP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another comm and sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. W hen RESET# is held at VIL, the device enters
the TTL standby mode; if RESET# is held at VSS ±
0.5 V, the de vice enters the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system res et would thus also reset the Flash
memory, enabling the system to read the boot-up f i rm-
ware from the Flash memory.
If RESET# is ass erted during a progr am or er ase oper-
ation, the RY/BY# pin remains a “0” (busy) until the  in-
ternal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor R Y/BY# to determine whether
the reset operation is complete. If RESET# is  asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algo-
rithms). The system can read data tRH after the RE-
SET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at VIH, output  from the de vice is
disabled.  The output  pins are plac ed in the h igh imped-
ance state.

10 Am29F200A

PRELIMINARY

Table 2. Am29F200T Top Boot Block Sector Address Table

Table 3. Am29F200B Bottom Boot Block Sector Address Table

Note for Tables 2 and 3: Address range is A16:A-1 in byte mode and A16:A0 in word mode. See “Word/Byte Configuration”

section for more information.

Autoselect Mode

The autoselect mode provides manufacturer and de-

vice identification, and sector protection verification,

through identifier codes output on DQ7–DQ0. This

mode is primarily intended f or programming equipment

to automatically match a de vice to be programmed with

its corresponding programming algorithm. However,

the autoselect codes can also be accessed in-system

through the c ommand register.

When using programming equipment, the autoselect

mode requires VID (11.5 V to 12.5 V) on address pin

A9. Address pins A6, A1, and A0 must be as shown in

Aut oselect Codes (High Voltage Method) table. In addi-

tion, when verifying sector protection, the sector ad-

dress must appear on the appropriate highest order

address bits. Refer to the corresponding Sector Ad-

dress Tables. The Command Definitions table shows

the remaining address bits that are don’t care . When all

necessary b its hav e been set as required, the progr am-

ming equipment may then read the corresponding

identifier code on DQ7–DQ0.

To access the autoselect codes in-system, the host

system can issue the autoselect command via the

command register, as shown in the Command Defini-

tions tabl e. This method does not require V ID. See “Au-

toselect Command Sequence” for details on using the

autoselect mode.

Sector A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Ran g e (in hexade cim al )

(x8)

Address Range (x16)

Address Range

SA0 0 0 X X X 64/32 00000h–0FFFFh 00000h–07FFFh

SA1 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA2 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA3 1 1 0 X X 32/16 30000h–37FFFh 18000h–1BFFFh

SA4 1 1 1 0 0 8/4 38000h–39FFFh 1C000h–1CFFFh

SA5 1 1 1 0 1 8/4 3A000h–3BFFFh 1D000h–1DFFFh

SA6 1 1 1 1 X 16/8 3C000h–3FFFFh 1E000h–1FFFFh

Sector A16 A15 A14 A13 A12

Sector Size

(Kbytes/

Kwords)

Address Ran g e (in hexade cim al )

(x8)

Address Range (x16)

Address Range

SA0 0 0 0 0 X 16/8 00000h–03FFFh 00000h–01FFFh

SA1 0 0 0 1 0 8/4 04000h–05FFFh 02000h–02FFFh

SA2 0 0 0 1 1 8/4 06000h–07FFFh 03000h–03FFFh

SA3 0 0 1 X X 32/16 08000h–0FFFFh 04000h–07FFFh

SA4 0 1 X X X 64/32 10000h–1FFFFh 08000h–0FFFFh

SA5 1 0 X X X 64/32 20000h–2FFFFh 10000h–17FFFh

SA6 1 1 X X X 64/32 30000h–3FFFFh 18000h–1FFFFh

Am29F200A 11

PRELIMINARY

Table 4. Am29F200A Autoselect Codes (High Voltag e Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase operations in any sector. The

hardware sector unprotection feature re-enables both

program and erase operations in previously pro-

tected sectors.

Sector protection/unprotection must be implemented

using programming equipment. The procedure re-

quires a high voltage (VID) on address pin A9 and the

control pins. Details on this method are provided in a

supplement, publication number 20551. Contact an

AMD representativ e to obtain a copy of the ap propriate

document.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possib le to determine whether a sector is protected

or unprotected. See “Autoselect Mode” for details.

Temporary Sector Unprotect

This feature allows temporary unprotection of previ-

ously protected sectors to change data in-system.

The Sector Unpr otect mode is activ at ed by setting the

RESET# pin to VID. During this mode, formerly pro-

tected sectors can be programmed or erased by se-

lecting the sector addresses. Once VID is removed

from the RESET# pin, all the previously protected

sectors are protected again. Figure 1 shows the algo-

rithm, and the Temporary Sector Unprotect diagram

(Fig ure 17) show s the timing waveforms, for this fea-

ture.

Figure 1. Temporary Sector Unprotect Operation

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to the Command Defi-

nitions table). In addition, the following hardware data

protection meas ures pre vent a ccidental eras ure or pro-

Description Mode CE# OE# WE#

A16

A12

A11

A10 A9

A7 A6

A2 A1 A0

DQ8

DQ15

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL X 01h

Device ID:

Am29F200A

(Top Boot Block)

Word L L H XXV

ID XLXLH22h 51h

Byte L L H X 51h

Device ID:

Am29F200A

(Bottom Boot Block)

Word L L H XXV

ID XLXLH22h 57h

Byte L L H X 57h

Sector Protection V erification L L H SA X VID XLXHL X01h

(protected)

X00h

(unprotected)

START

Perform Erase or

Program Operations

RESET# = VIH

Temporary Sector

Unprotect

Completed (Note 2)

RESET# = VID

(Note 1)

Notes:

1. All protected sectors unprotected.

2. All previously protected sectors are protected once

again.

20637B-6

12 Am29F200A

PRELIMINARY

gramming, which might otherwise be caused by spuri-

ous system level signals during VCC power-up and

pow er-down transitions, or from system noise.

Low V CC Write Inhibit

When VCC is less than VLKO, the device does not ac-

cept any write cycles. This protects data during VCC

pow er-up and power-do wn. The command register and

all internal program/er ase circuits are disabled, and the

dev ice resets . Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical In hibit

Write c ycles are inhibi ted by holding any one of OE#

= VIL, CE# = VIH or WE# = VIH. To initiate a write cy-

cle, CE# and WE# must be a logical zero while OE#

is a logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL and OE# = VIH during power

up, the device does not accept commands on the

rising edge of WE#. The inter nal state machine is

automatically reset to reading array data on

power-up.

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates de vice op-

erations. The Command Definitions table defines the

valid register command sequences. Writing incorrect

address and data values or writing them in the im-

proper sequence resets the device to reading array

data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

“AC Charac teristics” section.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a progr amming operation in the Erase

Suspend mode, th e system ma y once again read array

data with the same exception. See “Erase Suspend/

Erase Resume Commands” for more infor mation on

this mode.

The system

must

issue the reset command to re-en-

abl e the de vice f or reading arr ay data if DQ5 goes high,

or while in the autoselect mode. See the “Res et Com-

mand” se ctio n , next.

See also “Requirements for Reading Arr a y Data” in the

“Device Bus Operations” section for more infor mation.

The Read Operations table provides the read param e-

ters, and Read Operation Timings diagram shows the

timing diagram.

Reset Command

Writing the reset command to the device re sets the de-

vice to reading array data. Address bits are don’t care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the dev ice to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the aut oselect mode , the re set command

must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command retur ns the device to read-

ing array data (also applies during Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the man uf acturer and devices codes ,

and determine whether or not a sector is protected.

The Command Definitions table shows the address

and data requirements . This method is an alternativ e to

that shown in the Autoselect Codes (High Voltage

Am29F200A 13

PRELIMINARY

Method) table, which is intended for PROM program-

mers and requires VID on address bit A9.

The autoselect command sequence is initiated by

writing two unlock cycles, followed by the autoselect

command. The device then enters the autoselect

mode, and the system may read at any address any

number of times, without initiating another command

sequence.

A read cycle at address XX00h retrie v es the manuf ac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) retur ns the device code.

A read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protec ted, or 00h if it is un-

protec ted. Refer to the Se cto r Ad dre ss tables for v alid

sector add resses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by byte or word,

on depending on the state of t he BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is

not

required to provide further controls or t im-

ings. T he device automatically provides inter nally gen-

erated program pulses and ver ify the programmed cell

margin. The Command Definitions take shows the ad-

dress and data r equirements for t he byte progr am com-

mand sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using DQ7,

DQ6, or RY/BY#. See “Write Operation Status” for in-

formation on these status bits.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the program-

ming operation. The program command sequence

should be reinitiated once the de vice has res et to read-

ing array data, to ensure data integr ity.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed

from a “0” back to a “1”. Attempt ing to do so ma y halt

the operation and set DQ5 to “1”, or cause the Data#

Polling algorithm to indicate the operation was suc-

cessful. Howe ver , a succeeding read will show that the

data is still “0”. Only erase operations can con vert a “0”

to a “1”.

Note: See the appropriate Command Definitions table for

program comma nd seque nce.

Figure 2. Program Operation

Chip Erase Command Sequence

Chip erase i s a six -bus-cycle operat ion. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Eras e

algorithm. The device does

not

require the system to

preprogr am prior to erase. The Embedded Erase algo-

rithm automatically preprogr ams and verifies the entire

memor y for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. The Command

Definitions table shows the address and data require-

ments for the chip erase command sequence.

Any commands written to the chip during the Embed-

ded Erase algorithm are ignored. Not e that a hardware

reset during the chip erase operation imm ediately ter-

minates the operation. The Chip Erase command se-

quence should be reinitiated once the device has

returned to reading array data, to ensure data int eg rity.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

20637B-7

14 Am29F200A
PRELIMINARY
The system can determine the status of the erase
operation by using DQ7, DQ6, or RY/BY#. See
“Write Operation Status” for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data
and addresses  are no  longer latc hed. 
Figure 3 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
Characteristic s” f or par ameters,  and to the Chip/Sec tor
Erase Operation Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cyc les, followed by a set-up command. Two ad-
ditional unloc k write cycles  are then followed b y  the ad-
dress of the sector to be erased, and the sector eras e
command. The Command D efinitions table shows the
address and data requirements for the sector erase
command sequence.
The device does 
not
 require the system to preprog ram
the memory prior to e rase.  The Embedded Erase algo-
rithm automatically progr ams and verifies  the sector f or
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or tim-
ings during these operations. 
After the command sequence is written, a sector er ase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be written. Loading the sector er ase buffer
ma y be done in any sequence , and the nu mber of sec-
tors ma y be from one sector to a ll sectors. The time be-
tween these additio nal cycles mus t be less than 50 µs,
otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended
that processor  interrupts be disab led during this time to
ensure all commands are accepted. The interrupts can
be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other
than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array
data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor  DQ3 to determine if the  sector
erase timer has timed out. (See the “DQ3: Sector Er ase
Timer” section.) The time-out begins from the rising
edge of the final  WE# pulse in the command sequence .
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All oth er commands
are ignored. Note that a hardware reset during the
sector erase operation im mediately terminates the op-
eration. The Sector Eras e command sequence should
be reinitiated once the device has returned to reading
array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
dev ice returns to  reading arr a y dat a and addr esses are
no longer latched. T he sys tem can deter mine the sta-
tus of the erase operation by using DQ7, DQ6, or RY/
BY#. Refer to “Wr ite Operation Status” for infor mation
on these status bits.
Figure 3 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “A C Char acteristics ” section for parameters , and to
the Sector Er ase Opera tions  Timing diagr am for timing
waveforms.
Erase Suspend/Erase Resume Commands
The Erase  Suspend co mmand allo ws the s yste m to in-
terrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure.  This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded  Program algo-
rithm. Writing the Erase Suspe nd command during the
Sector Erase time-out immediately terminates the
time-out period an d sus pends t he  er ase oper at ion.  Ad-
dresses are “don’t-cares” when writing the Erase Sus -
pend command.
When the Erase Suspend command is written during a
sector erase oper ation, the devi ce requires  a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not select ed for er asure . (The devic e “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended sec-
tors produces status data on DQ7–DQ0. The system
can use DQ7 or DQ6 to determine if a sector is actively
erasing or is erase-suspended. See “Write Operation
Status” for information on these status bits.
After an erase-suspended program operation is com-
plete,  the system c an once again r ead arra y d ata within
non-suspended sectors . The system can determine the
status of the program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Operation Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the

Am29F200A 15

PRELIMINARY

codes are not stored in the memory array. When the

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Autoselect Command Sequence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase oper ation. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the de-

vice has resumed erasing.

Notes:

1. See the appropriate Command Definitions table for erase

command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

20637B-8

16 Am29F200A
PRELIMINARY
Table 5. Am29F200A Command Definition s
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read op eration.
PA = Address of the memory location to be programmed. 
Addresses latch on the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be programmed at location PA. Data latches on the 
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be v erified (in autoselect mode) or 
erased. Address bits A16–A12 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles 
are write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and 
command cycles.
5. Address bits A16–A11 are don’t cares for unlock and 
command cycles, unless SA or PA required.
6. No unlock or command cycles required when read ing array 
data.
7. The Reset command is requ ired to return to reading array 
data when device is in the autoselect mode, or if DQ5 goes 
high (while the device is providing status data).
8. The fourth cycle of the autoselect command sequence is a 
read cycle.
9. The data is 00h for an unprotected sector and 01h for a 
protected sector. See “Autoselect Command Sequence” for 
more information.
10. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend 
mode. The Erase Sus pend command is valid on ly during a 
sector erase operation.
11. The Erase Resume command is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Bus Cycles (Notes 2–5)
First Second Third  Fourth Fifth Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Manufacturer ID Word 4555 AA 2AA 55 555 90 X00 01
Byte AAA 555 AAA
Device ID, 
Top Boot Block  Word 4555 AA 2AA 55 555 90 X01 2251
Byte AAA 555 AAA X02 51
Device ID,
Bottom Boot Block Word 4555 AA 2AA 55 555 90 X01 2257
Byte AAA 555 AAA X02 57
Sector Pro tect Verify 
(Note 9)
Word 4555 AA 2AA 55 555 90
(SA)
X02 XX00
XX01
Byte AAA 555 AAA (SA)
X04 00
01
Program Word 4555 AA 2AA 55 555 A0 PA PD
Byte AAA 555 AAA
Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Byte AAA 555 AAA AAA 555 AAA
Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Byte AAA 555 AAA AAA 555
Erase Sus pend (Note 10) 1 XXX B0
Erase Resume (Note 11) 1 XXX 30
Cycles
Autoselect (Note 8)

Am29F200A 17

PRELIMINARY

WRITE OPERATION STATUS

The device provides several bits to deter mine the sta-

tus of a write operation: DQ3, DQ5, DQ6, DQ7, and

RY/BY#. Table 9 and the following subsections de-

scribe the functions of these bits. DQ7, RY/BY#, and

DQ6 each offer a method for determining whether a

program or erase operation is complete or in progress.

These three bits are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the ris-

ing edge of the final WE# pulse in the program or

erase command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. If a program address falls within a

protected sector, Data# P olling on DQ7 is acti ve f or ap-

proximately 2 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When t he Embedded Erase al-

gorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous t o the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status in-

formation on DQ7.

After an er ase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling

on DQ7 is active f or appro ximately 100 µs , t hen th e de-

vice returns to reading array data. If not all selected

sectors are protec ted, the Embedded Erase algorithm

erases the unprotected sectors, and ignores the se-

lected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid dat a at DQ7–

DQ0 on the

following

read cycles . This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asser ted low. The D ata# Poll-

ing Timings (During Embedded Algorithms) figure in

the “AC Characteristics” section il lustrates this.

Table 9 shows the outputs for Data# Polling on DQ7.

Figure 4 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

20637B-9

Figure 4. Data# Polling Algorithm

18 Am29F200A

PRELIMINARY

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the command

sequence. Since RY/BY# is an open- drain output, sev-

eral RY/BY# pins can be tied together in parallel with a

pull-up resistor to VCC.

If the outpu t is low (Busy ), the de vice is activ ely er asing

or programming. (This includes programming in the

Erase Suspend mode.) If the output is high (Ready),

the device is ready to read array data (including during

the Erase Suspend mode), or is in the standby mode.

Table 9 shows the outputs for RY/BY#. The timing dia-

grams for read, reset, program, and erase shows the

relationship of RY/BY# to other signals.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Er ase algorithm is in prog ress or complete ,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address, and is

valid after the rising edge of the final WE# pulse in the

command sequence (prior to the program or erase op-

eration), and during the sector erase time-out.

During an Embedded Program or Erase algorithm op-

eration, successive read cycles to any address cause

DQ6 to toggle. (The system may use either OE# or

CE# to control the read c ycles.) When the operation is

complete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6 tog-

gles f or appr o x ima tely 100 µs , then ret urns to reading

array data. If not all selected sectors are protected,

the Embedded Erase algorithm erases the unpro-

tected sectors, and ignores the selected sectors that

are protected.

If a program address falls within a protected sector,

DQ6 toggles for approximately 2 µs after the program

command sequence is written, then retur ns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded Pro-

gram algorithm is complete.

The Write Operation Status tab le shows the out puts for

Toggle Bit I on DQ6. Ref er to Figure 5 f or the toggle bit

algorithm, and to the Toggle Bit Timings figure in the

“AC Char acteristics” section for the timing diagram.

Reading Toggle Bit DQ6

Refer to Figure 5 for the following discussion. When-

ever the system initially begins reading toggle bit sta-

tus, it must read DQ7–DQ0 at least twice in a row to

determine whether a toggle bi t is togg ling. Typica lly, a

system w ould note and store the v alue of the toggle bit

after the first read. After t he second read, the syst em

would co mpare the ne w v alue of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The sys-

tem can r ead arra y data on DQ7–DQ0 on the f ollowing

read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the

system also should note whether the value of DQ5 is

high (see the section on DQ5). If it is, the system

should then determine again whether the toggle bit is

toggling, since the toggle bit may have stopped tog-

gling just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the

dev ice did not complete the operat ion successfully, and

the system must wr ite the reset command to retur n to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 t hrough successive read cycles, de-

termining the statu s as described in the previous para-

graph. Alternatively, it may choose to perform other

syst em task s. In thi s case , the syst em m ust st art at the

beginning of the algorithm when it ret urns to determine

the status of the operation (top of Figure 5).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exc eeded a specified inter nal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the pro gram or er ase cycle w as

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is pre viously pro-

grammed to “0.” Only an erase operation can change

a “0” back to a “1.” Under this condition, the device

halts the operation, and when the operation has ex-

ceeded the timing limits, D Q5 produces a “1.”

Under both these conditions, the system must issue the

reset command to return the device to reading array

data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system ma y re ad DQ3 to dete rmine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selec ted f or er asure , the e ntire t ime-

out also applies after each additional sector erase

command. When the time-out is complete, DQ3

switches from “0” to “1 .” The system may ignore DQ3

Am29F200A 19

PRELIMINARY

if the s ystem can gua rant ee that t he ti me betw een ad-

ditional sector erase commands will always be less

than 50 µs . See also the “Sec tor Erase Command Se-

quence” sect ion.

After the sector erase command sequence is written,

the system should re ad the s tatus on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence , and then read DQ3. If

DQ3 is “1”, the internally controlled erase cycle has be-

gun; all further commands (other th an Er ase Su spend)

are ignored until the erase operation is complete. If

DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the s ystem softw are should chec k the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 9 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1”. See text.

20637B-10

Figure 5. Toggle Bit Algorithm

(Notes

1, 2)

(Note 1)

20 Am29F200A

PRELIMINARY

Table 9. Write Operation Status

Notes:

1. DQ7 requires a valid address when reading status information. Refer to the appropriate subsection for further details.

2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

Operation DQ7

(Note 1) DQ6 DQ5

(Note 2) DQ3 RY/BY#

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A 0

Embedded Erase Algorithm 0 Toggle 0 1 0

Erase

Suspend

Mode

Reading with in Erase

Suspend ed Sec tor 1 No toggle 0 N/ A 1

Reading within Non-Erase Suspended

Sector Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0 N/A 0

Am29F200A 21

PRELIMINARY

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C

Ambient Temperature

with Power Applied. . . . . . . . . . . . . . –55°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . .–2.0 V to +7.0 V

A9, OE#, and

RESET# (Note 2). . . . . . . . . . . .–2.0 V to +12.5 V

All other pins (Note 1) . . . . . . . . .–0.5 V to +7.0 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

voltage transitions, input or I/O pins may undershoot VSS

to –2.0 V for periods of up to 20 ns. See Figure 6.

Maximum DC voltage o n input or I/O pin s is V CC +0.5 V.

During voltage transitions, input or I/O pins may ov ershoot

to VCC +2.0 V for periods up to 20 ns. See Figure 7.

2. Minimum DC input v oltage on pins A9, OE#, and RESET#

is –0.5 V. During voltage transitions, A9, OE#, and

RESET# may undershoot VSS to –2.0 V for periods of up

to 20 ns. See Figure 6. Maximum DC input voltage on pin

A9 is +12.5 V which may ov ershoot to +13.5 V for periods

up to 20 ns.

3. No more tha n one outpu t may be shor ted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresse s above those liste d under “Absolut e Maximum Rat-

ings” may cause p erman ent dam age to th e device . This is a

stress rati ng on ly; fu nct iona l ope rat ion of the de vic e at the se

or any other conditions above those indicated in the opera-

tional s ections o f this dat a sheet is not im plied. Exp osure of

the device to absolute maximum rating conditions for extend-

ed periods may affect device reliability.

Figure 6. Maximu m Negative Overshoot

Waveform

Figure 7. Maximum Positive Overshoot

Waveform

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for ± 5% devi ces. . . . . . . . . . .+4.75 V to +5.25 V

VCC for± 10% de vices . . . . . . . . . . . .+4.5 V to +5.5 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20637B-11

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

20637B-12

22 Am29F200A

PRELIMINARY

DC CHARACTERISTICS

TTL/NMOS Compatible

Notes:

1. The ICC current is typically less than 2 mA/MHz, with OE

at VIH.

2. ICC active while Embedded Program or Erase Algorithm is in progress.

3. Not 100% tested.

Parameter

Symbol Pa ra me ter Des cri ptio n Test Cond itio ns Min Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9, OE#, RESET# Input Load

Current VCC = VCC Max,

A9, OE#, RESET# = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Read Current (Note 1) CE# = VIL, OE# = VIH Byte 40 mA

Word 50

ICC2 VCC Active Program/Erase Current

(Notes 2, 3) CE# = VIL, OE# = VIH 60 mA

ICC3 VCC Standby Current VCC = VCC Max, CE# = VIH, OE# = VIH 1.0 mA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 2.0 VCC + 0.5 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH Output High Voltage IOH = –2.5 mA, VCC = VCC Min 2.4 V

VLKO Low VCC Lock-Out Volta ge 3.2 4.2 V

Am29F200A 23

PRELIMINARY

DC CHARACTERISTICS (continued)

CMOS Compatible

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.

2. ICC active while Embedded Program or Erase Algorithm is in progress.

3. Not 100% tested.

4. ICC3 for extended temperature is 20

A max.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

ILI Input Load Current VIN = VSS to VCC, VCC = VCC Max ±1.0 µA

ILIT A9, OE#, RESET# Input

Load Current VCC = VCC Max;

A9, OE#, RESET# = 12.5 V 50 µA

ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC Max ±1.0 µA

ICC1 VCC Active Read Current

(Note 1) CE# = VIL, OE# = VIH Byte 20 40 mA

Word 28 50

ICC2 VCC Active Program/Erase

Current (No tes 2, 3) CE# = VIL, OE# = VIH 30 50 mA

ICC3 VCC Standby Current

Note (Note 4) VCC = VCC Max,

CE# = VCC ± 0.5 V, OE# = VIH 15

µA

VIL Input Low Voltage –0.5 0.8 V

VIH Input High Voltage 0.7 x VCC VCC + 0.3 V

VID Voltage for Autoselect and

Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V

VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC Min 0.45 V

VOH1 Output Low Voltage IOH = –2.5 mA, VCC = VCC Min 0.85 VCC V

VOH2 IOH = –100 µA, VCC = VCC Min VCC – 0.4 V

VLKO Low VCC Lock-Out Voltage 3.2 4.2 V

24 Am29F200A

PRELIMINARY

TEST CONDITIONS

Table 6. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

5.0

Device

Under

Test

20637B-13

Figure 8. Test Setup

Note:

Diodes are IN3064 or equivalents.

Test Condition -55 All

others Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 20 ns

Input Pulse Levels 0.0–3.0 0.45–2.4 V

Input timing measurement

reference levels 1.5 0.8, 2.0 V

Output timing measurement

reference levels 1.5 0.8, 2.0 V

KS000010-PAL

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changi ng from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

Am29F200A 25

PRELIMINARY

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 8 and Table 6 for test specifications

Figure 9. Read Operations Timings

Parameter

Description

Speed Option

JEDEC Std Test Setup -55 -70 -90 -120 -150 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 55 70 90 120 150 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 150 ns

tGLQV tOE Output Enable to Output Delay

(Note 1) Max 30 30 35 50 55 ns

tEHQZ tDF Chip Enable to Output High Z

(Note 1) Max 20 20 20 30 35 ns

tGHQZ tDF Output Enable to Output High Z

(Note 1) Max 20 20 20 30 35 ns

tOEH

Output Enable

Hold Time

(Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tAXQX tOH

Output Hold Time From Addresses,

CE# or OE#, Whichever Occurs

First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

RY/BY#

RESET#

tDF

tOH

26 Am29F200A

PRELIMINARY

AC CHARACTERISTICS

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed OptionsJEDEC Std Test Setup Unit

tREADY RESET# Pin Low (During Embedded

Algorithms) to Read or Write (See Note) Max 20 µs

tREADY RESET# Pin Low (NOT During Embedded

Algorithms) to Read or Write (See Note) Max 500 ns

tRP RESET# Pulse Width Min 500 ns

tRH RESET# High Time Before Read (See Note) Min 50 ns

tRB RY/BY# Recovery Time Min 0 ns

RESET#

RY/BY#

tRP

tReady

Reset Timings NOT during Embedded Algorithms

tReady

CE#, OE#

tRH

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

tRP

tRB

20637B-14

Figure 10. RESET# Timings

Am29F200A 27

PRELIMINARY

AC CHARACTERISTICS

Word/Byte Configuration (BYTE#)

Parameter

-55 -70 -90 -120 -150JEDEC Std. Description Unit

tELFL/tELFH CE# to BYTE# Switching Low or High Max 5 ns

tFLQZ BYTE# Switching Low to Output HIGH Z Max 20 20 20 30 35 ns

tFHQV BYTE# Switching High to Output Active Max 55 70 90 120 150 ns

DQ15

Output

Data Output

(DQ0–DQ7)

CE#

OE#

BYTE#

tELFL

DQ0–DQ14 Data Output

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Output

(DQ0–DQ7)

BYTE#

tELFH

DQ0–DQ14 Data Outpu t

(DQ0–DQ14)

DQ15/A-1 Address

Input

tFHQV

BYTE#

Switching

from byte

to word

mode

20637B-15

Figure 11. BYTE# Timing s for Read Operations

Note:

Refer to the Erase/Program Operations table for tAS and tAH specifications.

20637B-16

Figure 12. BYTE # Timi ngs for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

tHOLD (tAH)

tSET

(tAS)

28 Am29F200A

PRELIMINARY

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

-55 -70 -90 -120 -150JEDEC Std. Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVWL tAS Address Setup Time Min 0 ns

tWLAX tAH Address Hold Time Min 45 45 45 50 50 ns

tDVWH tDS Data Setup Time Min 25 30 45 50 50 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWLWH tWP Write Pulse Width Min 30 35 45 50 50 ns

tWHWL tWPH Write Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 7 µs

Word Typ 14

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

tRB Recovery Time from RY/BY# Min 0 ns

tBUSY Program/Erase Valid to RY/BY# Delay Min 30 30 35 50 55 ns

Am29F200A 29

PRELIMINARY

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tGHWL

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

Notes:

1. PA = program address, PD = program data, DOUT is the true data at the program address.

2. Illustration shows device in word mode.

20637B-17

Figure 13. Progr am O peration Ti mi ng s

30 Am29F200A

PRELIMINARY

AC CHARACTERISTICS

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tGHWL

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

Notes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).

2. Illustration shows device in word mode.

20637B-18

Figure 14. Chip/Sector Erase Operatio n Timings

Am29F200A 31

PRELIMINARY

AC CHARACTERISTICS

Note: Illustration shows first two status cycles after command sequence, last status read cycle, and array data read cycle.

20637B-20

Figure 16. Toggle Bit Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid Address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

20637B-19

Figure 15. Data# P olling Timings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

DQ6

RY/BY#

BUSY

Addresses VA

OEH

VA VA

ACC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

32 Am29F200A

PRELIMINARY

AC CHARACTERISTICS

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std. Description Unit

tVIDR VID Rise and Fall Tim e (S ee Note) Min 500 ns

tRSP RESET# Setup Time for Temporary Sector

Unprotect Min 4 µs

RESET#

tVIDR

12 V

0 or 5 V

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

0 or 5 V

20637B-21

Figure 17. Temporary Sector Unprotect Timi ng Diagram

Am29F200A 33

PRELIMINARY

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter

-55 -70 -90 -120 -150JEDEC Std. Description Unit

tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 150 ns

tAVEL tAS Address Setup Time Min 0 ns

tELAX tAH Address Hold Time Min 45 45 45 50 50 ns

tDVEH tDS Data Setup Time Min 25 30 45 50 50 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tELEH tCP CE# Pulse Width Min 30 35 45 50 50 ns

tEHEL tCPH CE# Pulse Width High Min 20 ns

tWHWH1 tWHWH1 Programming Operation

(Note 2) Byte Typ 7 µs

Word Typ 14

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

34 Am29F200A

PRELIMINARY

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

RESET#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tRH

tWHWH1 or 2

RY/BY#

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

tBUSY

Notes:

1. PA = Program Address, PD = Program Data, SA = Sector Address, DQ7# = Complement of Data Input, DOUT = Array Data.

2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

20637B-22

Figure 18. Alternate CE# Controlled Write Operation Timings

Am29F200A 35

PRELIMINARY

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

C, 5.0 V VCC, 100,0 00 cyc les. Additiona lly,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 4.5 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum byte program time listed. If the maximum byte program time given is exceeded, only then

does the device set DQ5 = 1. See the section on DQ5 for further information.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to ex ecute the four-bus-cycle command sequence for programming. See Tab le 1

for further information on command definitions.

6. The device has a guaranteed minimum erase and program cycle endurance of 100,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25

C, f = 1.0 MHz.

DATA RETENTION

Parameter

Limits

CommentsTyp (Note 1) Max (Note 2) Unit

Sector Erase Time 1 8 sec Excludes 00h programming prior to

erasure (Note 4)

Chip Erase Time 7 56 sec

Byte Programming Time 7 300 µsExcludes system-level overhead

(Note 5)

Word Programming Time 14 600 µs

Chip Programming Time (Note 3) 1.8 5.4 sec

Parameter Description Min Max

Input Voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Cap ac itan ce VOUT = 0 8.5 12 pF

CIN2 Control Pin Capa cita nce VIN = 0 8 10 pF

Parameter Test Con dit ion s Min Un it

Minimum Patter n Data Ret ent ion Time 150°C 10 Years

125°C 20 Years

36 Am29F200A

PRELIMINARY

PH YS ICAL DIMENSIONS

SO 044—44-Pin Small Outline Package (measured in millimeters)

44 23

122

13.10

13.50 15.70

16.30

1.27 NOM.

28.00

28.40

2.17

2.45

0.35

0.50 0.10

0.35

2.80

MAX. SEATING

PLANE

16-038-SO44-2

SO 044

DF83

8-8-96 lv

0.10

0.21

0.60

1.00

0°

8°

END VIEW

SIDE VIEW

TOP VIEW

Am29F200A 37

PRELIMINARY

PH YS ICAL DIMENSIONS

TS 048—48-Pin Standard Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48-2

TS 048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

38 Am29F200A

PRELIMINARY

PH YS ICAL DIMENSIONS

TSR048—48-Pin Reverse Thin Small Outline Package (measured in millimeters)

18.30

18.50

19.80

20.20

11.90

12.10

SEATING PLANE

0.05

0.15

0.50 BSC

0.95

1.05

16-038-TS48

TSR048

DT95

8-8-96 lv

Pin 1 I.D.

1.20

MAX

0.50

0.70

0.10

0.21

0.25MM (0.0098") BSC 0°

5°

0.08

0.20

Am29F200A 39

PRELIMINARY

REVISION SUMMARY

Revision B (January 1998)

Global: Made formatting and layout consistent with

other data sheets. Used updated common tab les and

diagrams

Revision B+1 (January 1998)

Minor formatting changes only.

Revision B+2 (February 1998)

Connection Diagrams

Swapped standard and reversed TSOP drawings in

online version (data book vers ion is correct).

Revision B+3 (March 1998)

DC Characteristics, CMOS Compatible

Corrected the ICC3 CE# test condition to VCC±0.5 V.

AC Characteristics

Read-Only Operations:

Corrected parameter descrip-

tions to match parameters.

Erase/Program Operations; Alternate CE# Controlled

Erase/Program Operations:

Corrected the notes refer-

ence for tWHWH1 and tWHWH2. These parameters are

100% tested. Corrected the note reference for tVCS.

This parameter is not 100% tested.

Temporary Sector Unprotect Table

Added note reference for tVIDR. This parameter is not

100% tested.

Revision B+4 (January 3, 2000)

Global

Removed all references to DQ2. The Am29F200A

does not have this status bit.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.