rT Advanced Am2864AE Micro 8192 x 8-Bit Electrically Erasable PROM Devices DISTINCTIVE CHARACTERISTICS 5-V only operation Military temperature range available Self-timed Write Cycle with on-chip latches Data Polling for end-of-write indication Data protection features to prevent writes from occur- ting during Voc power-up/down @ 32-byte page write mode @ Minimum endurance of 10,000 write cycles per byte with a 10-year retention. For detailed information, see the reliability section within this Handbook. @ Allows WE and CE controlled Writes GENERAL DESCRIPTION The Am2864AE is a 65,536-bit Electrically Erasable Pro- grammable Read-Only Memory (EEPROM) organized as 8192 words by 8 bits per word. It operates from a single 5-volt supply and has a fully self-timed write cycle with address, data, and control lines latched during the write operation. The 32-byte page write mode allows program- ming in as little as 2.6 seconds. The Am2864AE is fabricated on AMD's highly manufacturable N-Channel Silicon gate process, and uses AMD's proprietary EEPROM technology to achieve electrically alterable nonvolatile storage. This technology employs the industry-accepted Fowler-Nordheim tunneling across a thin oxide. The Am2864AE provides the on-chip logic necessary to interface with most microprocessors. The latched inputs and self-timed write cycle free the microprocessor to perform other tasks during a write. A transparent automatic erase before write enhances system performance. BLOCK DIAGRAM MODE SELECT TABLE ro Inputs Outputs tre : S| xoccooen | 3 | sss CE | O& | WE| 1/0 | As [Mode S L L H | Data Out X |Read ; a L H | LI | Data In X {Write Mo-ag {ow 3 | v-vecover : V-GATING LE tH L | Data In X | Write : s * H | xX | xX Hi-Z X |Standby we St Tourur ewamie i | Ht aH] HZ X |Read inhibit c = CHIP ENABLE : INPUT xX L x - X {Write Inhibit _ 5 | Ano voc Gen. . LATCHES Lj} L | H | Code VH |Auto Select oe L L H Din X {Data Polling Yeo | cee | VH=120Vt.5V Gno + H=HIGH Da, ba, L=LOWw X = Don't Care BD003055 LT = Pulse PRODUCT SELECTOR GUIDE ha er Am26864AE-205 | Am2864AE-200 | Am2864AE-255 | Am2864AE-250 | Am2864AE-305 | Am2864AE-300 | Am2B64AE-355 | Am2864AE-350 Maximum Access 200 ns 250 ns 300 ns 350 ns Time Vec Supply +5% +10% +5% 1D% +5% 410% +5% +10% Tolerance Pyblication# ev. Amendment 09625 B a Issue Date: November 1988 3-102CONNECTION DIAGRAMS Top View DIP SY nc [J 28 [7] Voc Ae C]2 27 {_] WE a4 (3 26 [] NC 4 C4 asi] A A, ((]5 24 = A A(l]6 2atyay A, [_]? 22 [7] OF A (ls 21 [7] Aw A, [je 20 [7} CE Ay [-] 10 19 [7 ) 00, pa, (411 18 [_] 0 pa, [7] 12 17 [7] pa, pa, (7) 13 16 [_] 0a, GND [_] 14 15 [J] 0a, cDoase09 CDoo60e1 LOGIC SYMBOL Ag - Ai2 = Address Pins CE =Chip Enable 13 DQp - DQ? = Data Pins ] >} Ag-Ay2 GND = Ground NC = No Connect _ OE = Output Enable cE Voc = Power Supply _ WE = Write Enable OE NC = No Connect ~+} WE DQ9-DQ7 8 Ls002272 Am2864AE 3-103ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Device Number b. Speed Option c. Package Type d. Temperature Range e. Optional Processing Cc B [| OPTIONAL PROCESSING Blank = Standard Processing B = Burn-in AM2864AE I is |e d. TEMPERATURE RANGE C = Commercial (0 to + 70C) | = Industrial (-40 to + 85C) E = Extended Commercial (-55 to + 125C) c. PACKAGE TYPE D = 28-Pin Ceramic or Sidebrazed Ceramic DIP (CO 028 or SD 028) L = 32-Pin Rectangular Ceramic Leadiess Chip Carrier (CLA032) z SPEED OPTION See Product Selector Guide a. DEVICE NUMBER/DESCRIPTION Am2864AE 8192 x 8-Bit EEPROM Valid Combinations AM2864AE-205 Valid Combinations AM2864AE-200 Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD AM2B64AE-255 DC, DCB, sales office to confirm availability of specific valid AM2864AE-250 OF eB combinations, to check on newly released valid combinations, AM2864AE-305 Lc. LCB, and to obtain additional data on AMD's standard military LL LIB grade products. AM2864AE-300 LE, LEB AM2864AE-355 AM2864AE-350 3-104 Am2864AEMILITARY ORDERING INFORMATION APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL {Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination} for APL products is formed by a combination of: a. Device Number b. Speed Option c. Device Class d. Package Type e. Lead Finish AM2864AE 200 4B Xx A | LEAD FINISH A=Hot Solder Dip (CD 028 pkg. only) d. PACKAGE TYPE X = 28-Pin Ceramic or Sidebrazed Ceramic DIP (CD 028 or SD 028) U = 32-Pin Rectangular Leadiess Chip Carrier (CLRO32) c. DEVICE CLASS /B =Class B ov . SPEED OPTION - 200 = 200 ns - 250 = 250 ns -300 = 300 ns ~350 = 350 ns a. DEVICE NUMBER/DESCRIPTION Am2864AE 8192 x 8-Bit EEPROM Valid Combinations Valid Combinations Valid Combinations list configurations planned to be AM2B64AE-200 supported in volume for this device. Consult the local AMD AM2864AE-250 /BXA, /BUA sales office to confirm availability of specific valid . combinations or to check for newly released valid AM2664AE-300 combinations. AM2864AE-350 Group A Tests Group A tests consist of Subgroups 1, 2, 3, 7, 8, 9, 10, 11. Am2864AE 3-105FUNCTIONAL DESCRIPTION Read Mode The Am2864AE has two control functions which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins independent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output {tc_e). Data is available at the outputs tog after the falling edge of OE, assuming that CE has been LOW and addresses have been stable for at least tacc-toe- Standby Mode The Am2864AE has a standby mode which reduces the active power dissipation by 50%, from 735 mW to 368 mW (Voc 5%). The Am2864AE is placed in the standby mode by applying a TTL HIGH signal to the CE input. When in the standby mode, the outputs are in a high-impedance state, independent of the OE input. Data Protection The Am2864AE incorporates several features that prevent unwanted write cycles during Voc power-up and power-down. These features protect the integrity of the stored data. To avoid the initiation of a write cycle during Voc power-up and power-down, a write cycle is locked out for Vcc less than 3.0 volts (typical 3.3 V). It is the users's responsibility to ensure that the control levels are logically correct when Vcc is above 3.0 volts. There is a WE lockout circuit that prevents WE pulses of less than 20 ns duration from initiating a write cycle. When the OE contrel is in logic zero condition, a write cycle cannot be initiated. Write Cycle Control Pins For system design simplification, the Am2864AE is designed in such a way that either CE or WE can be used to initiate a write cycle. During a system write cycle, the address is latched into the internal address latches upon the last falling edge of WE or CE providing that OE is a logic '1". The first rising edge of WE or CE latches the data into the data latches. All setup and hoid times are with respect to the WE signal. To simplify the following discussion, the WE pin is used as the write cycle control pin throughout the rest of this functional description. Page Write Mode The page write allows from 1 to 32 bytes of data to be written into the EEPROM in a single write cycle. The page write mode consists of a load sequence followed by an automatic write sequence. : During the load portion, sequential WE pulses load the byte address and the byte data into a 32-byte register. The bytes can be loaded into this register in any order. On each WE pulse, the ''Y'' address is latched on the falling edge of the WE, the data input is latched on the rising edge of WE, and the page address {As5-A12) is latched on the falling edge of the last WE. Note that in order for a write to occur, CE and WE must be LOW and OE must be HIGH. The load portion of the page write is complete when all the data (up to 32 bytes) is loaded into the register. The automatic write portion starts twy after each transition of WE from LOW-to-HIGH. if WE transitions from HIGH-to-LOW before tww minimum (100 ys), the timer is reset and the automatic write portion does not start. This is how the bytes are loaded into the register. If WE is held LOW, this tww timer never starts and the write cycle is held indefinitely. When a write pulse is not given to the device within the tww minimum time (100 ys) from the rising edge of the previous write pulse, the automatic write sequence is initiated. At completion of the automatic write sequence (twa maximum time has elapsed, or Data Polling indicates the write operation is compiete), at least one of the control pins must deselect the device from accidental writes (OE LOW, CE HIGH, or WE HIGH). The automatic write sequence consists of an erase cycie, which erases any data that existed in each addressed cell; and a write cycle, which puts data back into the erased cells. Note that a page write will only write data to the locations being addressed and will not rewrite the entire page. Byte Mode Write When WE is toggled once, the Am2864AE operates in the byte mode. A single byte is loaded into the register, and after WE goes HIGH and tyww is satisfied, the automatic write cycle starts. It is in this made that the Am2864AE is identical to the Am2864BE and Am9864. Auto Select Mode The auto select mode allows the reading out of a binary code from an EEPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional at 25C +5C ambient temperature. To activate this mode, programming equipment must force 11.5 V to 12.5 V on address line Ag of the Am2864AE. Two identifier bytes may then be sequenced from the device outputs by toggling address line Ag from Vi to Vip. All other address lines must be held at Vi_ during auto select mode. Byte 0 (Ao = Vi_) represents the manufacturer code and byte 1 (Ap = Vin) the device identifier code. For the Am2864AE, these two identifier bytes are given in Tabie 1. All identifiers for manufacturer and device codes will possess odd parity, with the MSB (07) defined as the parity bit. Tne auto select code for the Am2864AE is identical to the Am2864BE. Output OR-Tieing To accommodate multiple memory connections, a two-line control function is provided to allow for: 1. Low memory power dissipation, and 2. Assurance that output bus contention will not occur. It is recommended that CE be decoded and used as the primary device-selecting function, while OE be made a com- mon connection to all devices in the array and be connected to the read line from the system contro! bus. This assures that all deselected memory devices are in their low-power standby mode and that the output pins are only active when data is desired from a particular memory device. Data Polling Bata Polling makes the Am2864AE highly flexibie. It allows the designer the option of a software polling technique for end-of- write indication. Data Polling requires a simple software rou- tine that performs a read operation when the chip is in the automatic write mode. The data that becomes valid during this Data Polling read is the inverse of all 8 bits last written to the outputs. The true data (OQp - DQ7) will become valid when the automatic write has been completed. Note that ali 8 bits invert during Data Polling, thereby giving the user more flexibility during design and layout. 3-106 Am2864AEChip Clear Mode (Military only) Another feature included on AMD's Am2864AE for military applications is a single-pulse chip erase. This optional mode allows the user to program all bits to a logic ONE with a single 10-ms write. Additional information is available from AMD regarding this test mode consult the local AMD sales office. Endurance Since endurance testing is a destructive test, it is sampled and not 100% tested. To test for endurance, a sample of devices are written 10,000 times and checked for data retention capability. There is one main failure mechanism associated with endur- ance failures in EEPROMs. This failure mechanism is due to charge trapping in the thin tunneling dielectric. At a point when the amount of trapped charge creates an electric field that exceeds the dielectric breakdown of the oxide, the oxide becomes conductive and reliable storage of charge on the floating gate is no longer possible. This results in the failure of a single bit to properly write and retain data. There are three different failure rates associated with this failure mechanism, and the failure rates are a function of the number of write cycles. For less than a few hundred write cycles, the failure rate is relatively high. During AMD testing, each part is written hundreds of times to allow those cells that would be infant-mortality failures to be screened out. For the next 20,000 to 30,000 write cycles the failure rate is low. It is in this region that AMD EEPROMs are operated. Somewhere above this region, typically well above the guarantee of 104 total write cycles, the failure rate again starts increasing. The endurance failure rate is a function of the number of write cycles that the part has experienced. All parts that pass the AMD test screens will write a minimum of 10,000 times and retain data for a period of ten years at every byte location with a maximum failure rate of 5%. In other words, 5% (maximum) of a sample of devices will fail to write or to retain information after write if they are written 10,000 times. Those devices that fail will typically have a single bit that fails to retain the correct data after being written. This failure rate is measured from a sample of devices, in the same manner that other reliability failure mechanisms are measured. For more detailed information on how this data was obtained please refer to the reliability section within this Handbook. APPLICATIONS During the switch between active and standby conditions, transient current peaks are produced on the rising and falling edges of Chip Enable. The magnitude of these transient current peaks is dependent on the output capacitance loading of the device. A 0.1 uF ceramic capacitor (high frequency, low inherent inductance) should be used on each device between Vcc and GND to minimize transient effects. In addition, to overcome the voltage drop caused by the inductive effects of the printed circuit board traces on EEPROM arrays, a 4.7 uF bulk electrolytic capacitor should be used between Vcc and GND for each eight devices. The location of the capacitor should be close to where the power supply is connected to the array. PROGRAMMING TABLE 1. IDENTIFIER BYTES (Notes 1, 2 & 3) Identifier Ao DQ; DQ. DQ@s DQ, DQ3 DQ2 DQ, DQo Hex Manufacturer Code Vit 0 0 Oo 0 Go 0 1 01 Device Code Vin 1 0 1 0 1 0 8A Legend: 1 = HIGH 0 = LOW. Notes: 1. Ag=12.0 V +t05V 2. Ay-Ag, Ajo-At2, CE, OE = Vic 3. WE = Vin Am2864AE 3-107ABSOLUTE MAXIMUM RATINGS Storage Temperature ..................... ~65 to + 150C Ambient Temperature with Power Applied .-65 to + 135C Voltage on All Inputs with Respect to GND 20... cece ee cee cere ee ecn eee ee eens +7.0 to -10V Valtage on Ag with Respect to GND 000. cece eee e entree +13.5 to -0.6 V Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Temperature (TC).........cecee cece cece eee eens Supply Voltage (Vcc (Woc + Industrial (1) Devices Temperature (To)... ccc cee eee ees Supply Voltage (Vcc (Vcc Extended Commercial (E) and Military (M) Devices Temperature (To)....... cece ereee renee -55 to +125C Supply Voltage (Voc +10%) ........... +450 to +5.50 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating range unless otherwise specified (for APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Parameter Parameter Symbol Description Test Condition Min. Typ. Max. Unit to Input Leakage Current Vin = 0 and 5.5 V 10 uA Ilo Output Leakage Current Vout = 0 and 5.6 V 10 vA Iec1 Voc Current (Standby) CE = Vin. OE = Vit 70 mA loc2 Voc Current (Active) All Outputs Open 140 mA Vit Input LOW Voltage. ~1.0 8 v Vin Input HIGH Voltage 2.0 Voct+ t v Vou Output LOW Voltage lo. = 2.1 MA 4 v Vou Qutput HIGH Voltage loH =-400 yA 2.4 v Cin Input Capacitance (Note 1, 2) VIN=O V 4 8 pF Cout Qutput Capacitance (Note 1, 2) OE = CE = Vin, Vout =0 V 8 10 pF Vwi Write inhibit Voltage 3.0 3.3 v Notes: 1. This parameter is measured only for the initial qualification and after process or design changes which affect capacitance. 2. Freq. = 1 MHz @ 25C. 3. Typical values are for nominal supply voltages. 3-108 Am2864AESWITCHING CHARACTERISTICS over operating range unless otherwise specified (for APL Products, Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) Am2864AE-205, | Am2864AE- 255,| Am2864AE-305,) Am2864AE-355, Am2864AE-200 | Am2864AE-250 | Am2864AE-300 | Am2864AE-350 Parameter Parameter Test No. | Symbol Description Condition | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit READ 1 Itacc Address to Output Delay CE = OF = Vi 200 250 300 350 ns 2 |tce TE to Output Delay OE = Vit 200 250 300 350 ns 3 Itoe Output Enable to Output = fee. yy 150 150 150 150 | ns Delay t Output Enable or Chip 4 | OF Enable HIGH to Output 10 60 10 60 10 80 10 80 ns (Note 1) Float toH Output Hold from Address jap _ = 5 (Note 1) Change E=OE=Vi_| 20 20 20 20 ns 6 |tac Read Cycle Time CE=OE=Vy_| 200 250 300 350 ns t Output Enable or Chip 7 {DA Enable LOW to Output 10 10 10 10 ns {Note 1) Active WRITE 8 |tas Address to Write Setup 10 10 10 20 ns 9 Jtcs CE to Write Setup Time 0 0 0 0 ns WE or CE Write Pulse 10 |twe Width 150 150 150 200 ns 110] tay Address Hold Time 200 200 200 200 ns 12 |tps Data Setup Time 100 100 100 120 ns 13 |tpH Data Hold Time 20 20 20 30 ns 14 |tcH CE Hold Time 0 0 0 0 ns 15 |toes OE Setup Time 10 10 10 40 ns 16 ltoex OE Hold Time 10 10 10 10 ns 17 ltwo Byte Load Cycle Time 3 3 3 3 us Page Write Window 18 |tww (Note 3) 20 20 20 20 us WE or TE Write Pulse 19 JtwH HIGH Time 50 50 50 100 ns 20 |twe Bye N 55%) Write Cycle 10 10 10 10 | ms 21 ltweu (Nowe a Hold Time 50 50 50 50 ns 22 grotes 1& Jnumber of Writes per Byte 10 10 10 10 x1000 Notes: 1. This parameter is measured only at the initial qualification and after process or design changes which affect the parameter. 2. See Reliability Section within this HANDBOOK. __ 3. A timer of tww duration starts at every LOW-to-HIGH transition of WE. If it is allowed to time out, a page write will start. A transition of WE from HIGH-to-LOW will stop the timer. 4, When twe maximum time has elapsed or Data Poll must deselect the device (WE HIGH, CE HIGH, or next operation. a na . This is the time from deselecting the device (WE or CE = Vi4 or GE =Vj,) to the other control pins becoming don't cares. indicates the write operation is complete, at least one of the control pins LOW). Once the write cycle is complete, the device is available for the Am2864AE 3-109SWITCHING TEST CONDITIONS Output load: 1 TTL gate and C, = 100 pF SWITCHING TEST CIRCUIT Input pulse levets: 0.45 V to 2.4 V Timing Measurement Reference Levels Input: 0.8 V and 2.0 V ouTPUT 2.7 ko ~ UNDE! 5.0 V Output: 0.8 V and 2.0 V TEST c DIODES = 1N3066 | OR EQUIVALENT Tc002491 C_ = 100 pF, including jig capacitance. SWITCHING TEST WAVEFORM 24V 24V 20V 20V TEST POINT 0.8V 0BVv 0.45V 045 V INPUT OUTPUT WFO25110 AC Testing: Inputs are driven at 2.4 V for logic "1" and 0.45 V for logic ''0". Timing measurements are made at 0.8 V and 2.0 V. Input pulse rise and fall times are 10 ns. SWITCHING WAVEFORMS KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE WILL BE STEADY STEADY WILL BE MAY CHANGE CHANGING FROMHTOL FROMH TOL WILL BE MAY CHANGE CHANGING FROMLTOH = FRom. TOH eS 2 | DON'T CARE. CHANGING; ANY CHANGE = STATE PERMITTED UNKNOWN CENTER GOES NOT LINE IS HIGH APPLY IMPEDANCE OFF STATE KS000010 3-110 Am2864AESWITCHING WAVEFORMS (Cont'd.} < 'Re > 2.4 - - ADDRESSES 2.0 ADDRESSES 20 -A Ag: Ato os VALID 08 0.45 _ + taco (NOTE 1) cE tcp OE a t OE > t (NOTE 1) (OTE 2 t ba j+ "OH (NOTE 3) HIGH Z F 20v VALID HIGH Z OUTPUT OUTPUT 08Vv WE = Va, WF025120 Read Notes: 1. OE may be delayed up to tacc-tog after the falling edge of CE without impact on tacc. 2. tpg is specified from OE or CE, whichever occurs first. 3. toa is specified trom OE or CE, whichever occurs last. Mn -- ADDRESSES. ADORY AODR2 | ADDR n AoAr2) i . (NOTE 1) > tas tag \ See }e "AH Vie -- on Va tweoy be two 'oH os oH vy DATA iH ~ K . DATAINA 4 (009007) DATA IN} gk DATA IN 2 (NOTE t) }-________- us L -| 1 77 t tos4| tps le DH le Page Write WF025132 Notes: 1. n<92. Am2864AE 3-117SWITCHING WAVEFORMS (Cont'd.) v appresses !H (ApAi2) x em" \J _/ VALID otaso /gp- tay - twp P4 ml tcH fee i+ 'cs> + ' OES Py f+ 08} } NOTE 1-4 Notes: 1. This time period = tc: + tise + twPH. Rl al DATA OH (009-007) | el fon J Byte Write WF025142 twee q a tp y__ 4 DATA IN az) t DATA OUT RZ) BS DATA OUT (xvZ) we (NOTE 3) Data Polling WF025150 Notes:. 1. When the write cycle is completed (data out TRUE), the user must meet one of the following conditions to prevent an accidental write: OF LOW, CE HIGH, or WE HIGH. 3-112 Am2864AE