SiHU2N80E www.vishay.com Vishay Siliconix E Series Power MOSFET FEATURES D * Low figure-of-merit (FOM) Ron x Qg IPAK (TO-251) * Low input capacitance (Ciss) * Reduced switching and conduction losses D G * Ultra low gate charge (Qg) * Avalanche energy rated (UIS) G D S * Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S N-Channel MOSFET APPLICATIONS PRODUCT SUMMARY * Server and telecom power supplies VDS (V) at TJ max. RDS(on) typ. () at 25 C * Switch mode power supplies (SMPS) 850 VGS = 10 V 2.38 Qg max. (nC) 90 Qgs (nC) 11 Qgd (nC) 19 Configuration * Power factor correction power supplies (PFC) * Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting Single * Industrial - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) ORDERING INFORMATION Package IPAK (TO-251) Lead (Pb)-free and halogen-free SiHU2N80E-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 800 Gate-source voltage VGS 30 Continuous drain current (TJ = 150 C) VGS at 10 V TC = 25 C TC = 100 C Pulsed drain current a ID IDM Linear derating factor UNIT V 2.8 1.8 A 5 0.5 W/C Single pulse avalanche energy b EAS 14 mJ Maximum power dissipation PD 62.5 W TJ, Tstg -55 to +150 C Operating junction and storage temperature range Drain-source voltage slope TJ = 125 C Reverse diode dV/dt d Soldering recommendations (peak temperature) c For 10 s dV/dt 70 0.13 300 V/ns C Notes a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 140 V, starting TJ = 25 C, L = 28.2 mH, Rg = 25 , IAS = 0.9 A c. 1.6 mm from case d. ISD ID, dI/dt = 100 A/s, starting TJ = 25 C S18-0587-Rev. B, 18-Jun-2018 Document Number: 91986 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU2N80E www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Maximum junction-to-case (drain) RthJC - 2.0 UNIT C/W SPECIFICATIONS (TJ = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold Voltage (N) Gate-source leakage Zero gate voltage drain current VDS VGS = 0 V, ID = 250 A 800 - - V VDS/TJ Reference to 25 C, ID = 1 mA - 1.0 - V/C VGS(th) VDS = VGS, ID = 250 A 2.0 - 4.0 V VGS = 20 V - - 100 nA VGS = 30 V - - 1 A VDS = 800 V, VGS = 0 V - - 1 VDS = 640 V, VGS = 0 V, TJ = 125 C - - 10 IGSS IDSS A - 2.38 2.75 gfs VDS = 30 V, ID = 1.0 A - 1.0 - S Input capacitance Ciss VGS = 0 V, VDS = 100 V, f = 1 MHz - 315 - - 20 - - 6 - - 13 - - 45 - Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 1.0 A Dynamic Output capacitance Coss Reverse transfer capacitance Crss Effective output capacitance, energy related a Co(er) Effective output capacitance, time related b Co(tr) pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs Gate-drain charge Qgd Turn-on delay time Rise time Turn-off delay time - 9.8 19.6 - 2.4 - - 3.9 - td(on) - 11 22 tr - 7 14 - 19 38 td(off) Fall time tf Gate input resistance Rg VGS = 10 V ID = 1.0 A, VDS = 480 V VDD = 480 V, ID = 1.0 A, VGS = 10 V, Rg = 9.1 f = 1 MHz, open drain - 27 54 1.8 3.6 7.2 - - 2.8 nC ns Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G - - 5 TJ = 25 C, IS = 1 A, VGS = 0 V - - 1.2 - 278 556 ns TJ = 25 C, IF = IS = 1.0 A, dI/dt = 100 A/s, VR = 25 V - 0.9 1.8 C - 5 - A S V Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS S18-0587-Rev. B, 18-Jun-2018 Document Number: 91986 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU2N80E www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 3.0 6 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 4 RDS(on), Drain-to-Source On-Resistance (Normalized) 3 2 1 0 5 10 15 VDS, Drain-to-Source Voltage (V) 1.5 1.0 VGS = 10 V 0.5 -60 -40 -20 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (C) Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics 10 000 3 TOP 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 2 TJ = 150 C VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd 1000 C, Capacitance (pF) ID, Drain-to-Source Current (A) 2.0 0 0 1 Ciss 100 Coss 10 Crss 1 0 0 5 10 15 VDS, Drain-to-Source Voltage (V) 0 20 100 200 300 400 500 600 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 10 000 6 3.0 2.5 Coss, Output Capacitance (pF) 5 ID, Drain-to-Source Current (A) 2.5 TJ = 25 C 4 3 TJ = 150 C 2 1000 2.0 Eoss Coss 1.5 100 1.0 0.5 1 VDS = 31.6 V 10 0 0 5 10 15 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S18-0587-Rev. B, 18-Jun-2018 20 Eoss, Output Capacitance Stored Energy (J) ID, Drain-to-Source Current (A) 5 ID = 1 A TJ = 25 C 0 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 91986 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU2N80E www.vishay.com Vishay Siliconix 3.0 VDS = 480 V VDS = 300 V VDS = 120 V 2.5 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 12 6 1.0 0.5 0 0 3 6 9 Qg, Total Gate Charge (nC) 25 12 Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage 50 75 100 125 TC, Case Temperature (C) 150 Fig. 10 - Maximum Drain Current vs. Case Temperature 10 1050 TJ = 150 C 1 TJ = 25 C VGS = 0 V 0.1 0 0.3 0.6 0.9 1.2 VSD, Source-Drain Voltage (V) 1.5 Fig. 8 - Typical Source-Drain Diode Forward Voltage 10 Operation in this area limited by RDS(on) VDS, Drain-to-Source Breakdown Voltage (V) ISD, Reverse Drain Current (A) 1.5 3 0 ID, Drain Current (A) 2.0 1025 1000 975 950 925 900 875 850 825 ID = 250 A 800 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (C) Fig. 11 - Temperature vs. Drain-to-Source Voltage IDM limited 1 100 s Limited by RDS(on)* 0.1 1 ms TC = 25 C TJ = 150 C single pulse 0.01 1 10 ms BVDSS limited 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S18-0587-Rev. B, 18-Jun-2018 Document Number: 91986 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU2N80E www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty cycle = 0.5 0.2 0.1 0.05 0.02 0.1 Single pulse 0.01 0.0001 0.001 0.01 Pulse Time (s) 0.1 1 Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS D.U.T. VDD Rg + - VDD VDS 10 V Pulse width 1 s Duty factor 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS Qg 10 V 90 % Qgs 10 % VGS Qgd VG td(on) td(off) tr tf Charge Fig. 17 - Basic Gate Charge Waveform Fig. 14 - Switching Time Waveforms Current regulator Same type as D.U.T. L VDS Vary tp to obtain required IAS 50 k 12 V D.U.T. Rg 0.2 F 0.3 F + - VDD + D.U.T. IAS - VDS 10 V tp 0.01 VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S18-0587-Rev. B, 18-Jun-2018 Document Number: 91986 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHU2N80E www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg * * * * 1 Driver gate drive Period P.W. + V - DD dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current dI/dt waveform Diode recovery dV/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91986. S18-0587-Rev. B, 18-Jun-2018 Document Number: 91986 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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