16-Bit, 10 MHz Bandwidth, 30 MSPS to
160 MSPS Continuous Time Sigma-Delta ADC
AD9261
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.
FEATURES
SNR: 83 dB (85 dBFS) to 10 MHz input
SFDR: 87 dBc to 10 MHz input
Noise figure: 15 dB
Input impedance: 1 kΩ
Power: 340 mW
1.8 V analog supply operation
1.8 V to 3.3 V output supply
Selectable bandwidth
2.5 MHz/5 MHz/10 MHz
Output data rate: 30 MSPS to 160 MSPS
Integrated decimation filters
Integrated sample rate converter
On-chip PLL clock multiplier
On-chip voltage reference
Offset binary, Gray code, or twos complement data format
Serial control interface (SPI)
APPLICATIONS
Data acquisition
Automated test equipment
Instrumentation
Medical imaging
FUNCTIONAL BLOCK DIAGRAM
Σ-Δ
MODULATOR LOW-PASS
DECIMATION
FILTER
VIN+
VIN–
VREF
CFILT
AGND SDIO SCLK CSB
SAMPLE
RATE
CONVERTER
PHASE
LOCKED
LOOP
CMOS
BUFFER
DGND
A
V
DD
AD9261
DR
V
DD
D15
OR
D0
PLL_
LOCKED
CLK–
DCO
07803-001
SERIAL
INTERFACE
CLK+
Figure 1.
GENERAL DESCRIPTION
The AD9261 is a single 16-bit analog-to-digital converter
(ADC) based on a continuous time (CT) sigma-delta (Σ-Δ)
architecture that achieves 87 dBc of dynamic range over a 10 MHz
input bandwidth. The integrated features and characteristics
unique to the continuous time Σ-Δ architecture significantly
simplify its use and minimize the need for external components.
The AD9261 has a resistive input impedance that relaxes the
requirements of the driver amplifier. In addition, a 32× oversam-
pled fifth-order continuous time loop filter significantly attenuates
out-of-band signals and aliases, reducing the need for external
filters at the input.
An external clock input or the integrated integer-N PLL provides
the 640 MHz internal clock needed for the oversampled conti-
nuous time Σ-Δ modulator. On-chip decimation filters and sample
rate converters reduce the modulator data rate from 640 MSPS to a
user-defined output data rate from 30 MSPS to 160 MSPS,
enabling a more efficient and direct interface.
The digital output data is presented in offset binary, Gray code,
or twos complement format. A data clock output (DCO) is
provided to ensure proper timing with the receiving logic.
The AD9261 operates on a 1.8 V analog supply and a 1.8 V
to 3.3 V digital supply, consuming 340 mW. The AD9261 is
available in a 48-lead LFCSP and is specified over the industrial
temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. Continuous time Σ-Δ architecture efficiently achieves high
dynamic range and wide bandwidth.
2. Passive input structure reduces or eliminates the require-
ments for a driver amplifier.
3. An oversampling ratio of 32× and high order loop filter
provide excellent alias rejection reducing or eliminating the
need for antialiasing filters.
4. An integrated decimation filter, sample rate converter, PLL
clock multiplier, and voltage reference provide ease of use.
5. This part operates from a single 1.8 V analog power supply
and 1.8 V to 3.3 V output supply.
AD9261
Rev. 0 | Page 2 of 28
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications .......................................................................... 4
Digital Decimation Filtering Characteristics ............................ 4
Digital Specifications ................................................................... 5
Switching Specifications .............................................................. 6
Absolute Maximum Ratings ............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ..............................................9
Equivalent Circuits ......................................................................... 13
Theory of Operation ...................................................................... 14
Analog Input Considerations ................................................... 14
Clock Input Considerations ...................................................... 16
Power Dissipation and Standby Mode .................................... 18
Digital Engine ............................................................................. 19
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 21
Serial Port Interface (SPI) .............................................................. 23
Configuration Using the SPI ..................................................... 23
Hardware Interface ..................................................................... 24
Memory Map .................................................................................. 25
Memory Map Definitions ......................................................... 25
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
4/10—Revision 0: Initial Version
AD9261
Rev. 0 | Page 3 of 28
SPECIFICATIONS
DC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN1 = −2.0 dBFS,
unless otherwise noted.
Table 1.
Parameter Temp Min Typ Max Unit
RESOLUTION Full 16 Bits
ANALOG INPUT BANDWIDTH 10 MHz
ACCURACY
No Missing Codes Full Guaranteed
Offset Error Full ±0.02 ±0.15 % FSR
Gain Error Full ±0.7 ±3.0 % FSR
Integral Nonlinearity (INL)2 Full ±1.5 LSB
TEMPERATURE DRIFT
Offset Error Full ±1.5 ppm/°C
Gain Error Full ±50 ppm/°C
INTERNAL VOLTAGE REFERENCE 490 500 510 mV
ANALOG INPUT
Input Span, VREF = 0.5 V Full 2 V p-p diff
Common-Mode Voltage Full 1.7 1.8 1.9 V
Input Resistance Full 1 kΩ
POWER SUPPLIES
Supply Voltage
AVDD Full 1.7 1.8 1.9 V
CVDD Full 1.7 1.8 1.9 V
DVDD Full 1.7 1.8 1.9 V
DRVDD Full 1.7 1.8 3.6 V
Supply Current
IAVDD2 Full 74 83 mA
ICVDD2 PLL Enabled Full 57 654 mA
ICVDD2 PLL Disabled Full 8.0 8.8 mA
IDVDD2 Full 100 108 mA
IDRVDD2 (1.8 V) Full 5.5 5.8 mA
IDRVDD2 (3.3 V) Full 10 mA
POWER CONSUMPTION
Sine Wave Input2 PLL Disabled Full 340 370 mW
Sine Wave Input2 PLL Enabled Full 425 465 mW
Power-Down Power Full 20 mW
Standby Power2 Full 7 mW
Sleep Power Full 3 4 mW
1 Input power is referenced to full scale. Therefore, all measurements were taken with a 2 dB signal below full scale, unless otherwise noted.
2 Measured with a low input frequency, full-scale sine wave.
AD9261
Rev. 0 | Page 4 of 28
AC SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 2.
Parameter1 Temp Min Typ Max Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz Full 81 83 dB
fIN = 4.2 MHz 25°C 83 dB
fIN = 8.4 MHz 25°C 83 dB
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz 25°C 13.5 Bits
fIN = 4.2 MHz 25°C 13.5 Bits
fIN = 8.4 MHz 25°C 13.5 Bits
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz Full 87 80 dBc
fIN = 4.2 MHz 25°C 87 dBc
fIN = 8.4 MHz 25°C <120 dBc
NOISE SPECTRAL DENSITY (NSD)
AIN= −2 dBFS Full −155 −153 dB/Hz
AIN = −40 dBFS Full −156 −154.5 dB/Hz
NOISE FIGURE2 25°C 15 dB
TWO-TONE SFDR
fIN1 = 2.1 MHz at −8 dBFS, fIN2 = 2.4 MHz at −8 dBFS 25°C 93 dBc
fIN1 = 3.6 MHz at −8 dBFS, fIN2 = 4.2 MHz at −8 dBFS 25°C 92.5 dBc
fIN1 = 7.2 MHz at −8 dBFS, fIN2 = 8.4 MHz at −8 dBFS 25°C 92.5 dBc
ANALOG INPUT BANDWIDTH 25°C 10 MHz
APERTURE JITTER 25°C 1 ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Noise figure with respect to 50 Ω. AD9261 internal impedance is 1000 Ω differential. See the AN-835 Application Note for a definition.
DIGITAL DECIMATION FILTERING CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS, unless otherwise noted.
Table 3.
2.5 MHz BW 5 MHZ BW 10 MHz BW
Parameter1 Min Typ Max Min Typ Max Min Typ Max Unit
Pass-Band Transition 2.5 3.75 5 6.5 10 13 MHz
Pass-Band Ripple <0.1 <0.1 <0.1 dB
Stop Band 3.75 MHz − fS/2 6.5 MHz − fS/2 13 MHz − fS/2 MHz
Stop Band Attenuation >85 >85 >85 dB
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
AD9261
Rev. 0 | Page 5 of 28
DIGITAL SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 4.
Parameter1 Temp Min Typ Max Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVPECL
Differential Input Voltage Full 0.4 0.8 2 V p-p
Input Common-Mode Range Full 0.3 0.450 0.5 V
High Level Input Current Full −60 +60 µA
Low Level Input Current Full −60 +60 µA
Input Resistance Full 20 kΩ
Input Capacitance Full 1 pF
LOGIC INPUTS (SCLK)
High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −50 −75 µA
Low Level Input Current Full −10 +10 µA
Input Resistance Full 30 kΩ
Input Capacitance Full 2 pF
LOGIC INPUTS (SDIO, CSB, RESET)
High Level Input Voltage Full 1.2 DRVDD + 0.3 V
Low Level Input Voltage Full 0 0.8 V
High Level Input Current Full −10 +10 µA
Low Level Input Current Full +40 +135 µA
Input Resistance Full 26 kΩ
Input Capacitance Full 5 pF
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 µA) Full 3.29 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 3.25 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 µA) Full 1.79 V
High Level Output Voltage (VOH, IOH = 0.5 mA) Full 1.75 V
Low Level Output Voltage (VOL, IOL = 1.6 mA) Full 0.2 V
Low Level Output Voltage (VOL, IOL = 50 µA) Full 0.05 V
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
AD9261
Rev. 0 | Page 6 of 28
SWITCHING SPECIFICATIONS
All power supplies set to 1.8 V, 640 MHz sample rate, 0.5 V internal reference, PLL disabled, 40 MSPS output data rate, AIN = −2.0 dBFS,
unless otherwise noted.
Table 5.
Parameter1 Temp Min Typ Max Unit
CLOCK INPUT (USING CLOCK MULTIPLIER)
Conversion Rate Full 30 160 MSPS
CLK± Period Full 6.25 33 ns
CLK± Duty Cycle Full 40 50 60 %
CLOCK INPUT (DIRECT CLOCKING)
Conversion Rate Full 608 640 672 MSPS
CLK± Period Full 1.49 1.5625 1.64 ns
CLK± Duty Cycle Full 40 50 60 %
DATA OUTPUT PARAMETERS
Output Data Rate Full 20 168 MSPS
DCO to Data Skew (tSKEW)2 Full 3 ns
Sample Latency Full 960 Cycles
WAKE-UP TIME3 Full
Power Down Power Full 3 s
Standby Power Full 9 s
Sleep Power Full 15 s
OUT-OF-RANGE RECOVERY TIME Full 960 Cycles
SERIAL PORT INTERFACE4
SCLK Period Full 40 ns
SCLK Pulse Width High Time (tSHIGH) Full 16 ns
SCLK Pulse Width Low Time (tSLOW) Full 16 ns
SDIO to SCLK Setup Time (tSDS) Full 5 ns
SDIO to SCLK Hold Time (tSDH) Full 2 ns
CSB to SCLK Setup Time (tSS) Full 5 ns
CSB to SCLK Hold Time (tSH) Full 2 ns
1 See the AN-83 5 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Data skew is measured from DCO 50% transition to data (D0 to D15) 50% transition, with 5 pF load.
3 Wake-up time is dependent on the value of the decoupling capacitors. Values are shown with 10 µF capacitor on VREF and CFILT.
4 See Figure 50 and the Serial Port Interface (SPI) section.
Timing Diagram
07803-002
DCO
D0 TO D15
t
SKEW
Figure 2. Timing Diagram
AD9261
Rev. 0 | Page 7 of 28
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Rating
Electrical
AVDD to AGND −0.3 V to +2.0 V
DVDD to DGND −0.3 V to +2.0 V
DRVDD to DGND −0.3 V to +3.9 V
AGND to DGND −0.3 V to +0.3 V
AVDD to DRVDD −3.9 V to +2.0 V
CVDD to CGND −0.3 V to +2.0 V
CGND to DGND −0.3 V to +0.3 V
D0 to D15 to DGND −0.3 V to +2.0 V
DCO to DGND −0.3 V to +2.0 V
OR to DGND −0.3 V to +2.0 V
PDWN to GND −0.3 V to +2.0 V
PLLMULTx to DGND −0.3 V to +2.0 V
SDIO to DGND −0.3 V to +3.9 V
CSB to AGND −0.3 V to +3.9 V
SCLK to AGND −0.3 V to +3.9 V
VIN+, VIN− to AGND −0.3 V to +2.5 V
CLK+, CLK− to CGND −0.3 V to +2.0 V
Environmental
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 Sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.
Table 7. Thermal Resistance
Package Type θJA θ
JB θ
JC Unit
48-Lead LFCSP (CP-48-1) 27.7 11.8 1.1 °C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA.
ESD CAUTION
AD9261
Rev. 0 | Page 8 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
14
15
16
17
18
19
20
21
22
23
24
D4
D5
D6
D7
DRVDD
DGND
DVDD
D8
D9
D10
D11
D12
48
47
46
45
44
43
42
41
40
39
38
37
CLK+
CGND
AGND
AVDD
VIN–
VIN+
AVDD
CFILT
VREF
AVDD
AGND
CSB
1
2
3
4
5
6
7
8
9
10
11
12
CLK–
CVDD
PDWN
DVDD
DGND
DRVDD
PLL_LOCKED
DCO
D0
D1
D2
D3
NOTES
1. THE EXPOSED PAD MUST BE SOLDERED TO THE GROUND PLANE FOR
THE LFCSP PACKAGE. SO LDERI NG T HE EXPOSED PADDL E TO T HE P CB
INCREAS E S THE RELI ABIL ITY OF THE SOLDE R JOI NTS, MAXI MIZING
THE THERMAL CAPACIT Y O F T HE PACKAGE.
PLLMULT1/SDIO
PLLMULT2
PLLMULT3
PLLMULT4
DVDD
DGND
DRVDD
OR
D15
D14
D13
35 PLLMULT0/SCL
K
36
34
33
32
31
30
29
28
27
26
25
AD9261
TOP V IEW
(No t to Scal e)
PIN 1
INDICATOR
0
7803-003
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK− Clock Input (−).
2 CVDD Clock Supply (1.8 V).
3 PDWN External Power-Down Pin.
4, 19, 31 DVDD Digital Supply (1.8 V).
5, 18, 30 DGND Digital Ground.
6, 17, 29 DRVDD Digital Output Driver Supply (1.8 V to 3.3 V).
7 PLL_LOCKED PLL Lock Indicator.
8 DCO Data Clock Output.
9 to 16, 20 to 27 D0 to D15 Data Output Bits. D0 is the LSB and D15 is the MSB.
28 OR Overrange Indicator.
32, 33, 34 PLLMULT4, PLLMULT3, PLLMULT2 PLL Mode Selection Pins.
35 PLLMULT1/SDIO PLL Mode Selection Pin/Serial Port Interface Data Input/Output.
36 PLLMULT0/SCLK PLL Mode Selection Pin/Serial Port Interface Clock.
37 CSB Serial Port Interface Chip Select. Active low.
38, 46 AGND Analog Ground.
39, 42, 45 AVDD Analog Supply (1.8 V).
40 VREF Voltage Reference Input/Output.
41 CFILT Noise Limiting Filter Capacitor.
43 VIN+ Analog Input (+).
44 VIN– Analog Input (−).
47 CGND Clock Ground.
48 CLK+ Clock Input (+).
49 EPAD Analog Ground. Pin 49 is the exposed thermal pad on the bottom of the package.
AD9261
Rev. 0 | Page 9 of 28
TYPICAL PERFORMANCE CHARACTERISTICS
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
TA = 25°C, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-011
BANDWI DT H: 2.5MHz
DATA RATE: 40MSPS
f
IN
: 600kHz AT –2dBFS
SNR: 88.8dB
SFDR: 90dBc
Figure 4. Single-Tone FFT with fIN = 600 kHz and BW = 2.5 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-015
BANDWI DTH: 5MHz
DATA RAT E : 4 0MSPS
f
IN
: 1.2 M Hz AT –2dB F S
SNR: 86dB
SFDR: 90 .3dBc
Figure 5. Single-Tone FFT with fIN = 1.2 MHz and BW = 5 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-052
BANDWI DTH: 2.5MHz
DATA RAT E : 40M SPS
f
IN1
: 2. 1M Hz AT –8d BFS
f
IN2
: 2. 5M Hz AT –8d BFS
SFDR: 90.6d Bc
Figure 6. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.5 MHz, and BW = 2.5 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-053
BANDWIDTH: 5MHz
DATA RATE: 40M S P S
f
IN1
: 2. 1MHz AT –8d BFS
f
IN2
: 2. 4MHz AT –8d BFS
SF DR: 91.9d Bc
Figure 7. Two-Tone FFT with fIN1 = 2.1 MHz, fIN2 = 2.4 MHz and BW = 5 MHz
AD9261
Rev. 0 | Page 10 of 28
All power supplies set to 1.8 V, 640 MHz sample rate, 2 V p-p differential input, 0.5 V internal reference, PLL disabled, AIN = −2.0 dBFS,
10 MHz bandwidth, output data rate 40 MSPS, TA = 25°C, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-018
BANDWI DTH: 10MHz
DAT A RA TE: 40M SPS
f
IN
: 2. 4M Hz AT –2dBFS
SNR: 83.2dB
SF DR: 92.6dBc
Figure 8. Single-Tone FFT with fIN = 2.4 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-019
BANDWIDTH: 10 M Hz
DATA RATE: 40M S P S
f
IN
: 4. 2M Hz AT –2d BFS
SNR: 83.1d B
SF DR: 91.5d Bc
Figure 9. Single-Tone FFT with fIN = 4.2 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-020
BANDWI DTH: 10MHz
DAT A RA TE: 40M SPS
f
IN
: 8. 4M Hz AT –2d BFS
SNR: 83dB
SF DR: 105.7 dBc
Figure 10. Single-Tone FFT with fIN = 8.4 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-054
BANDWI DTH: 10MHz
DAT A RA TE: 40M SPS
f
IN1
: 2. 1MHz AT –8 dBFS
f
IN2
: 2. 4MHz AT –8 dBFS
SF DR: 91.2dBc
Figure 11. Two-Tone FFT with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-055
BANDWIDTH: 10 M Hz
DATA RATE: 40M S P S
f
IN1
: 3. 6MHz AT –8d BFS
f
IN2
: 4. 2MHz AT –8d BFS
SF DR: 92.2d Bc
Figure 12. Two-Tone FFT with fIN1 = 3.6 MHz and fIN2 = 4.2 MHz
0
–20
–40
–60
–80
–100
–120
–140
–1600 2 4 6 8101214161820
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-056
BANDWI DTH: 10MHz
DAT A RA TE: 40M SPS
f
IN1
: 7. 2MHz AT –8 dBFS
f
IN2
: 8. 4MHz AT –8 dBFS
SFDR: 93dBc
Figure 13. Two-Tone FFT with fIN1 = 7.2 MHz and fIN2 = 8.4 MHz
AD9261
Rev. 0 | Page 11 of 28
120
100
80
60
40
20
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT AMPLI T UDE (dBF S)
SNR/S FDR (d BFS AND d B)
07803-024
SFDR (dBFS)
SNR (dBFS)
SFDR (dB)
SNR (dB)
Figure 14. Single-Tone SNR and SFDR vs. Input Amplitude with fIN = 2.4 MHz
–
40
–60
–50
–70
–80
–90
–100
–110
–120
–60 –50 –40 –30 –20 –10
INPUT AMPLIT UDE (dBFS)
SFDR ( dBc AND dB)
07803-057
SFDR (dBc)
SFDR (d B)
Figure 15. Two-Tone SFDR/IMD3 vs. Input Amplitude
with fIN1 = 2.1 MHz and fIN2 = 2.4 MHz
94
92
90
88
86
84
82
8020 40 60 80 100 120 140 160
OUT P UT DATA RATE (M S P S )
SNR/ SFDR (d Bc)
07803-025
SFDR (d Bc)
SNR (dBc)
Figure 16: SNR/SFDR vs. Output Data Rate with fIN = 2.4 MHz
110
105
100
95
90
85
80012345678910
FREQUENCY ( M Hz )
AMPLITUDE (dBFS)
07803-023
SFDR (d Bc)
SNR (d B)
Figure 17. SNR/SFDR vs. Input Frequency
92
91
SNR
SFDR
90
89
88
87
86
85
84
83
82
81
–60 –40 –20 0 20 40 60 80 100
TEM P ERATURE (°C)
SNR (dB)/SFDR (dBc)
07803-059
1.9V
1.8V
1.7V
1.9V
1.8V
1.7V
Figure 18. SFDR/SNR vs. Temperature with fIN = 2.4 MHz
84.0
83.8
83.6
83.4
83.2
83.0
82.8
82.6
82.4
82.2
82.0
1.700 1.725 1.750 1.775 1.800 1.825 1.850 1.875 1.900
COMMON-MODE VOLTAGE (V)
SNR (d B)
07803-058
Figure 19. SNR vs. Input Common Mode Voltage with fIN = 2.4 MHz
AD9261
Rev. 0 | Page 12 of 28
84
83
82
81
80
79
78
771161412109825242120181715 4234323028
PLL DI VIDE RAT IO
SNR (d B)
07803-026
2.4MHz
8.4MHz
Figure 20. Single-Tone SNR vs. PLL Divide Ratio
1.0
0.5
0
–0.5
–1.0
–1.5
–2.008192 16,384 24,576 32,768 40,960 49,152 57,344 65,536
OUT P UT CODE
INL ERROR (LSB)
07803-021
Figure 21. INL with fIN = 2.4 MHz
AD9261
Rev. 0 | Page 13 of 28
EQUIVALENT CIRCUITS
2
V p-p DIFFERENTI
A
L
1.8V CM
500Ω
500Ω
07803-004
Figure 22. Equivalent Analog Input Circuit
CVDD
CLK+
10kΩ10kΩ
90kΩ30kΩ
CVDD
CLK–
07803-005
Figure 23. Equivalent Clock Input Circuit
S
DIO 1kΩ
DRVDD
07803-006
Figure 24. Equivalent SDIO Input Circuit
SCLK 30kΩ
1kΩ
07803-007
Figure 25. Equivalent SCLK Input Circuit
CSB
A
V
DD
1kΩ
26kΩ
07803-008
Figure 26. Equivalent CSB Input Circuit
DR
V
DD
DRGND
07803-009
Figure 27. Equivalent Digital Output Circuit
10kΩ
2.85kΩ8.5kΩ
3.5kΩ
0.5V
TO CURRENT
GENERATOR
10µF
07803-010
Figure 28. Equivalent VREF Circuit
AD9261
Rev. 0 | Page 14 of 28
THEORY OF OPERATION
The AD9261 uses a continuous time Σ-Δ modulator to convert
the analog input to a digital word. The digital word is processed
by the decimation filter and rate-adjusted by the sample rate
converter (see Figure 29). The modulator consists of a continuous
time loop filter preceding a quantizer that samples at fMOD =
640 MSPS. This produces an oversampling ratio (OSR) of 32 for
a 10 MHz input bandwidth. The output of the quantizer is fed
back to a DAC that ideally cancels the input signal. The incom-
plete input cancellation residue is filtered by the loop filter and
is used to form the next quantizer sample.
H(f)
LOOP FILTER QUANTIZER
+
–
DAC
ADC
MODULATOR DECIMATION
FILTER SAMPLE RATE
CONVERTER
SRC
07803-029
Figure 29. Σ-Δ Modulator Overview
The quantizer produces a nine-level digital word. The quantization
noise is spread uniformly over the Nyquist band (see Figure 30),
but the feedback loop causes the quantization noise present in
the nine-level output to have a nonuniform spectral shape. This
noise-shaping technique (see Figure 31) pushes the in-band
noise out of band; therefore, the amount of quantization noise
in the frequency band of interest is minimal.
The digital decimation filter that follows the modulator removes
the large out-of-band quantization noise (see Figure 32), while
also reducing the data rate from fMOD to fMOD/16. If the internal
PLL is enabled, the sample rate converter generates samples at
the same frequency as the input clock frequency. If the internal
PLL is disabled, the sample rate converter can be programmed
to give an output frequency that is a divide ratio of the modulator
clock. The sample rate converter is designed to attenuate images
outside the band of interest (see Figure 33).
QUANTIZATION NOISE
f
MOD/2
BAND OF INTE RE ST
07803-030
Figure 30. Quantization Noise
NOISE SHAPING
BAND OF I NT ERE ST
f
MOD
/2
07803-031
Figure 31. Noise Shaping
f
MOD
/32
f
MOD
/16
BAND OF INTE RE ST
DIGITAL FILTER CUTOFF FREQUENCY
07803-032
Figure 32. Digital Filter Cutoff Frequency
f
MOD
/16
f
OUT
/2
f
OUT
BAND OF INTE RES T
07803-033
Figure 33. Sample Rate Converter
ANALOG INPUT CONSIDERATIONS
The continuous time modulator removes the need for an anti-
alias filter at the input to the AD9261. A discrete time converter
aliases signals around the sample clock frequency and its multiples
to the band of interest (see Figure 34). Therefore, an external
antialias filter is needed to reject these signals.
DESIRED
INPUT UNDESIRED
SIGNAL
ADC
f
S
f
S
/2
07803-034
Figure 34. Discrete Time Converter
In contrast, the continuous time Σ-Δ modulator used within the
AD9261 has inherent antialiasing. The antialiasing property
results from sampling occurring at the output of the loop filter
(see Figure 35), and thus aliasing occurs at the same point in the
loop as quantization noise is injected; aliases are shaped by the
same mechanism as quantization noise. The quantization noise
transfer function, NTF(f), has zeros in the band of interest and in
all alias bands because NTF(f) is a discrete time transfer function,
whereas the loop filter transfer function, LF(f), is a continuous
time transfer function, which introduces poles only in the band
of interest. The signal transfer function, being the product of
NTF(f) and LF(f), only has zeros in alias bands and therefore
suppresses all aliases.
LF(f)
H(z)
QUANTIZATION
NOISE
INPUT
OUTPUT
LOOP FILTER
f
MOD
f
MOD
f
MOD
f
NTF(f)
LF(f)
07803-035
Figure 35. Continuous Time Converter
AD9261
Rev. 0 | Page 15 of 28
Input Common Mode
The analog inputs of the AD9261 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device such that VCM = AVDD is recommended for
optimum performance. The analog inputs are 500 Ω resistors,
and the internal reference loop aims to develop 0.5 V across
each input resistor (see Figure 36). With 0 V differential input,
the driver sources 1 mA into each analog input.
TO L OOP FILTER
STAGE 2
DAC
A
V
DD – 0.5V
500Ω
500Ω
VIN+
VIN–
FROM QUANTIZER
V
CM
=AVDD
V
IN
p-p = 2V
0
7803-036
Figure 36. Input Common Mode
Differential Input Configurations
The AD9261 can also be configured for differential inputs. The
ADA4937-1 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the ADA4937-1 is easily set by connecting AVDD to
the VOCM pin of the ADA4937-1 (see Figure 37). The noise and
linearity of the ADA4937-1 needs important consideration because
the system performance may be limited by the ADA4937-1.
9
2
3
11
10
8
15
200Ω
200Ω
200Ω
60.4Ω49.9Ω
50Ω
SIGNAL
SOURCE
2V p- p
R
T
60.4Ω
V
S
VIN–
VIN+
0.1µF
0.1µF
0.1µF
0.1µF
+5
V
AVDD
–5V
+1.8V
ADA4937-1
AD9261
V
OCM
07803-037
Figure 37. Differential Input Configuration Using the ADA4937-1
For frequencies offset from dc, where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 38. The center
tap of the secondary winding of the transformer is connected to
AVDD to bias the analog input.
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies
below a couple of megahertz (MHz), and excessive signal power
can cause core saturation, which leads to distortion.
50Ω
SIGNAL
SOURCE
2V p-p 1:1
R
T
50Ω
V
S
VIN–
VIN+
0.1µF
AVDD
AD9261
07803-038
Figure 38. Differential Transformer Configuration
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9261. The reference voltage should be decoupled to minimize
the noise bandwidth using a 10 μF capacitor. The reference is
used to generate a bias current into a matched resistor such that,
when used to bias the current in the feedback DAC, a voltage
of AVDD − 0.5 V is developed at the internal side of the input
resistors (see Figure 39). The current bias circuit should also be
decoupled on the CFILT pin with a 10 μF capacitor. For this
reason, the VREF voltage should always be 0.5 V.
AVDD
AVDD – 0.5V
CFILT
A
V
DD – 0.5V
500Ω
TO LOOP
FILTER
STAGE 2
500Ω
VIN+
V
CM
=AVDD
V
IN
p-p = 2V
VIN– 500Ω
10kΩ
10µF
0.5V
VREF
10µF
REF
0
7803-039
Figure 39. Voltage Reference Loop
Internal Reference Connection
To minimize thermal noise, the internal reference on the AD9261
is an unbuffered 0.5 V. It has an internal 10 kΩ series resistor,
which, when externally decoupled with a 10 μF capacitor, limits
the noise (see Figure 40). The unbuffered reference should not
be used to drive any external circuitry. The internal reference is
used by default.
10kΩ
2.85kΩ8.5kΩ
3.5kΩ
0.5V
TO CURRENT
GENERATOR
10µF
07803-040
Figure 40. Internal Reference Configuration
AD9261
Rev. 0 | Page 16 of 28
External Reference Operation
If an external reference is desired, the internal reference can be
disabled by setting Register 0x18[6] high. Figure 41 shows an
application using the ADR130B as a stable external reference.
0.5
V
ADR130B
TO CURRENT
GENERATOR
0.1µF 10µF
AVDD 10kΩ
07803-041
Figure 41. External Reference Configuration
CLOCK INPUT CONSIDERATIONS
The AD9261 offers two modes of sourcing the ADC sample
clock (CLK+ and CLK−). The first mode uses an on-chip clock
multiplier that accepts a reference clock operating at the lower
input frequency. The on-chip phase-locked loop (PLL) then
multiplies the reference clock up to a higher frequency, which is
then used to generate all the internal clocks required by the ADC
The clock multiplier provides a high quality clock that meets
the performance requirements of most applications. Using the
on-chip clock multiplier removes the burden of generating and
distributing the high speed clock.
The second mode bypasses the clock multiplier circuitry and
allows the clock to be directly sourced. This mode enables the
user to source a very high quality clock directly to the Σ-Δ
modulator. Sourcing the ADC clock directly may be necessary
in demanding applications that require the lowest possible ADC
output noise. Refer to Figure 20, which shows the degradation
in SNR performance for the various PLL settings.
In either case, when using the on-chip clock multiplier or
sourcing the high speed clock directly, it is necessary that the
clock source have low jitter to maximize the ADC noise
performance. High speed, high resolution ADCs are sensitive to
the quality of the clock input. As jitter increases, the SNR
performance of the AD9261 degrades from that specified in
Table 2. The jitter inherent to the part due to the PLL root sum
squares with any external clock jitter, thereby degrading
performance. To prevent jitter from dominating the performance
of the AD9261, the input clock source should be no greater than
1 ps rms of jitter.
The CLK± inputs are self-biased to 450 mV (see Figure 23); if
dc-coupled, it is important to maintain the specified 450 mV
input common-mode voltage. Each input pin can safely swing
from 200 mV p-p to 1 V p-p single-ended about the 450 mV
common-mode voltage. The recommended clock inputs are
CMOS or LVPECL.
The specified clock rate of the Σ-Δ modulator, fMOD, is 640 MHz.
The clock rate possesses a direct relationship with the available
input bandwidth of the ADC.
Bandwidth = fMOD ÷ 64
In either case, using the on-chip clock multiplier to generate the
Σ-Δ modulator clock rate or directly sourcing the clock, any
deviation from 640 MHz results in a change in input bandwidth.
The input range of the clock is limited to 640 MHz ± 5%.
Direct Clocking
The default configuration of the AD9261 is for direct clocking
where the PLL is bypassed. Figure 42 shows one preferred method
for clocking the AD9261. A low jitter clock source is converted
from a single-ended signal to a differential signal using an RF
transformer. The back-to-back Schottky diodes across the
secondary side of the transformer limits clock excursions into the
AD9261 to approximately 0.8 V p-p differential. This helps
prevent the large voltage swings of the clock from feeding
through to other portions of the AD9261 while preserving the
fast rise and fall times of the signal, which are critical to
achieving low jitter.
CLOCK
INPUT XFMR
MINI-CIRCUITS®
TC1- 1-13M+ , 1:1
SCHOTTKY
DIODES:
HSM2812
50Ω
CLK+
CLK–
0.1µF
0.1µF
ADC
AD9261
0.1µF
0.1µF
07803-042
Figure 42. Transformer-Coupled Differential Clock
If a differential clock is not available, the AD9261 can be driven
by a single-ended signal into the CLK+ terminal with the CLK−
terminal ac-coupled to ground. Figure 43 shows the circuit
configuration.
SCHOTTKY
DIODES:
HSM2812
50Ω
CLK+
CLK–
0.1µF
0.1µF
ADC
AD9261
CLOCK
INPUT
07803-043
Figure 43. Single-Ended Clock
Another option is to ac couple a differential LVPECL signal to
the sample clock input pins, as shown in Figure 44. The AD951x
family of clock drivers is recommended because it offers excellent
jitter performance.
100Ω
240Ω240Ω
50Ω
1
1
50Ω RESISTO RS ARE OPTIONAL.
50Ω
1
CLK+
CLK–
0.1µF
0.1µF
ADC
AD9261
CLOCK
INPUT
CLOCK
INPUT
0.1µF
0.1µF
CLK
AD951x
LVPECL
DRIVER
CLK
07803-044
Figure 44. Differential LVPECL Sample Clock
AD9261
Rev. 0 | Page 17 of 28
Internal PLL Clock Distribution
The alternative clocking option available on the AD9261 is to apply
a low frequency reference clock and use the on-chip clock multip-
lier to generate the high frequency fMOD rate. The internal clock
architecture is shown in Figure 45.
PHASE
DETECTOR
DIVIDER
PLL MULT
0x0A[5:0]
CLK+/CLK–
MODULATOR
CLOCK
640MSPS
PLLENABLE
0x09[2]
÷N
LOOP
FILTER 1.28GHz
VCO
PLL
÷2
07803-045
Figure 45. Internal Clock Architecture
The clock multiplication circuit operates such that the VCO
outputs a frequency, fVCO, equal to the reference clock input
multiplied by N
fVCO = (CLK±) × (N)
where N is the PLL multiplication (PLLMULT) factor.
The Σ-Δ modulator clock frequency, fMOD, is equal to
fMOD = fVCO ÷ 2
The reference clock, CLK±, is limited to 30 MHz to 160 MHz
when configured to use the on-chip clock multiplier. Given the
input range of the reference clock and the available multiplication
factors, the fVCO is approximately 1280 MHz. This results in the
desired fMOD rate of 640 MHz with a 50% duty cycle.
Before the PLL enable (PLLENABLE) register bit is set, the PLL
multiplication factor should be programmed into Register
0x0A[5:0]. After setting the PLLENABLE bit, the PLL locks and
reports a locked state in Register 0x0A[7]. If the PLL multiplica-
tion factor is changed, the PLL enable bit should be reset and set
again. Some common clock multiplication factors are shown in
Table 11.
The recommended sequence for enabling and programming the
on-chip clock multiplier is summarized in Table 9.
Table 9. Sequence for Enabling and Programming the PLL
Step Procedure
1 Apply a reference clock to the CLK± pins.
2 Program the PLL multiplication factor in
Register 0x0A[5:0]. See Table 10.
3 Enable the PLL; Register 0x09 = 04 (decimal).
4 Enable the PLL autoband select.
5 Initiate an SRC reset; Register 0x101[5:0] = 0.
6 Set SRC to the desired value via Register 0x101[5:0].
Table 10. Internal PLL Multiplication Factors
0x0A[5:0] PLLMULT (N) 0x0A[5:0] PLLMULT (N)
1 8 33 32
2 8 34 34
3 8 35 34
4 8 36 34
5 8 37 34
6 8 38 34
7 8 39 34
8 8 40 34
9 9 41 34
10 10 42 42
11 10 43 42
12 12 44 42
13 12 45 42
14 14 46 42
15 15 47 42
16 16 48 42
17 17 49 42
18 18 50 42
19 18 51 42
20 20 52 42
21 21 53 42
22 21 54 42
23 21 55 42
24 24 56 42
25 25 57 42
26 25 58 42
27 25 59 42
28 28 60 42
29 28 61 42
30 30 62 42
31 30 63 42
32 32 64 42
External PLL Control
At power-up, the serial interface is disabled until the first serial
port access. If the serial interface is disabled, the PLLMULTx
pins control the PLL multiplication factor. The five PLLMULTx
pins (Pin 32 to Pin 36) offer all the available multiplication
factors. If all PLLMULTx pins are tied high, the PLL is disabled
and the AD9261 assumes the high frequency modulator clock
rate that is applied to the CLK± pins. Table 12 shows the relation-
ship between PLLMULTx pins and the PLL multiplication factor.
AD9261
Rev. 0 | Page 18 of 28
PLL Autoband Select
The PLL VCO has a wide operating range that is covered by
overlapping frequency bands. For any desired VCO output
frequency, there are multiple valid PLL band select values. The
AD9261 possesses an automatic PLL band select feature on chip
that determines the optimal PLL band setting. This feature can be
enabled by writing to Register 0x0A[6] and is the recommended
configuration with the PLL clocking option. Follow the sequence
shown in Table 9 for enabling the autoband select and configur-
ing the PLL.
When the device is taken out of sleep or standby mode, Register
0x0A[6] must be toggled to reinitiate the autoband detect.
Table 11. Common Modulator Clock Multiplication Factors
CLK±
(MHz)
0x0A[5:0]
(PLLMULT) fVCO (MHz)
fMOD
(MHz)
BW
(MHz)
30.72 42 1290.24 645.12 10.08
39.3216 32 1258.29 629.15 9.83
52.00 25 1300.00 650.00 10.16
61.44 21 1290.24 645.12 10.08
76.80 17 1305.60 652.80 10.20
78.00 17 1326.00 663.00 10.36
78.6432 16 1258.29 629.15 9.83
89.60 15 1344.00 672.00 10.50
92.16 14 1290.24 645.12 10.08
122.88 10 1228.80 614.40 9.60
134.40 10 1344.00 672.00 10.50
153.60 8 1228.80 614.40 9.60
157.2864 8 1258.29 629.15 9.83
Table 12. External PLLMULTx Pins and PLL Multiplication
Factor
PLLMULTx[4:0] Pins PLL Multiplication Factors (N)
0 8
1 9
2 10
3 12
4 14
5 15
6 16
7 17
8 18
9 20
10 21
11 24
12 25
13 28
14 30
15 32
16 34
17 to 30 42
31 Direct clocking
Jitter Considerations
The aperture jitter requirements for continuous time Σ-Δ conver-
ters may be more forgiving than Nyquist rate converters. The
continuous time Σ-Δ architecture is an oversampled system,
and to accurately represent the analog input signal to the ADC,
a large number of output samples must be averaged together. As a
result, the jitter contribution from each sample is root sum
squared, resulting in a more subtle impact on noise perfor-
mance as compared to Nyquist converters where aperture jitter
has a direct impact on each sampled output.
In the block diagram of the continuous time Σ-Δ modulator
(see Figure 29), the two building blocks most susceptible to
jitter are the quantizer and the DAC. The error introduced
through the sampling process or quantizer is reduced by the
loop gain and shaped in the same way as the quantization noise
and, therefore, its effect can be neglected. On the contrary, the
jitter error associated to the DAC directly adds to the input
signal, thus increasing the in-band noise power and degrading
the modulator performance. The SNR degradation due to jitter
can be represented by the following equation:
SNR = −20 log (2πfanalogtjitter_rms) dB
where fanalog is the analog input frequency and tjitter_rms is the jitter.
The SNR performance of the AD9261 remains constant within
the input bandwidth of the converter, from dc to 10 MHz.
Therefore, the minimal jitter specification is determined at the
highest input frequency. From the calculation, the aperture
jitter of the input clock must be no greater than 1 ps to achieve
optimal SNR performance.
POWER DISSIPATION AND STANDBY MODE
The AD9261 power consumption can be further reduced by
configuring the chip in channel power-down, standby, or sleep
mode. The low power modes turn off internal blocks of the chip
including the reference. As a result, the wake-up time is depen-
dent on the amount of circuitry that is turned off. Fewer internal
circuits that are powered down result in proportionally shorter
wake-up time. The different low power modes are shown in
Table 13. In the standby mode, all clock related activity and the
output channels are disabled. Only the references and CMOS
outputs remain powered up to ensure a short recovery and link
integrity. During sleep mode, all internal circuits are powered
down, putting the device into its lowest power mode, and the
CMOS outputs are disabled.
If the serial port interface is not available, the AD9261 can be
configured in power-down mode by connecting Pin 3 (PDWN)
to AVDD.
AD9261
Rev. 0 | Page 19 of 28
Table 13. Low Power Modes
Mode 0x08[1:0] Analog Circuitry Clock Ref
Normal 0x0 On On On
Power-Down 0x1 Off On On
Standby 0x2 Off Off On
Sleep 0x3 Off Off Off
DIGITAL ENGINE
Bandwidth Selection
The digital engine (see Figure 46) selects the decimation signal
bandwidth by cascading third-order sinc (sinc3) decimate-by-2
filters. For a 10 MHz signal band, no filters are cascaded; for a
5 MHz signal band, a single filter is used; and for a 2.5 MHz
signal band, the 5 MHz filter is cascaded with a second filter.
Depending on the signal bandwidth, this drops the data rate
into the fixed decimation filter. As a result, lower signal bandwidth
options result in lower power. Bandwidth selection is determined
by setting Register 0x0F[6:5].
Decimation Filters
A fixed frequency low-pass filter is used to define the signal
band. This filter incorporates magnitude equalization for the
droop of the preceding sinc decimation filters and the sinc
filters of the sample rate converter. Table 14 and Table 15 detail
the coefficients for the DEC4 and LPF/EQZ filters. The preceding
sinc decimation filters are a standard sinc filter implementation.
Table 14. DEC4 Filter Coefficients
Coefficient
Number Coefficient
Coefficient
Number Coefficient
C0, C22 −21 C6, C16 1121
C1, C21 0 C7, C15 0
C2, C20 122 C8, C14 −2796
C3, C19 0 C9, C13 0
C4, C18 −418 C10, C12 10,184
C5, C17 0 C11 16,384
Table 15. LPF/EQZ Filter Coefficients
Coefficient
Number Coefficient
Coefficient
Number Coefficient
C0, C62 17 C16, C46 694
C1, C61 31 C17, C45 −744
C2, C60 −15 C18, C44 −677
C3, C59 −52 C19, C43 1271
C4, C58 36 C20, C42 450
C5, C57 78 C21, C41 −1909
C6, C56 −84 C22, C40 103
C7, C55 −98 C23, C39 2612
C8, C54 170 C24, C38 −1147
C9, C53 97 C25, C37 −3326
C10, C52 −291 C26, C36 3022
C11, C51 −42 C27, C35 4051
C12, C50 441 C28, C34 −6870
C13, C49 −98 C29, C33 −5305
C14, C48 −592 C30, C32 21,141
C15, C47 353 C31 38,956
10MHz
5MHz
2.5MHz
10MHz
5MHz
2.5MHz
DEC01
4
DEC02
SINC
3
2
SINC
3
2
SINC
4
2SINC
4
2SINC
6
2FIR
HB 2
DEC1 DEC2 DEC3 DEC4 LPF/EQZ
DECIM ATION FILTERSBANDWI DT H S ELE CT IO N
HB 2
INT1
HB 2
INT2
SINC
5
4
INT3
25MHz
2.5MHz
10MHz
SINC
5
8
INT4
NCO
SAMPLE RAT E CONVERTER
Σ-Δ
OUTPUT
16
DATA
OUTPUT
0
7803-046
Figure 46. Digital Engine
AD9261
Rev. 0 | Page 20 of 28
Sample Rate Converter
The sample rate converter (SRC) allows the flexibility of a user-
defined output sample rate, enabling a more efficient and direct
interface to the digital receiver blocks.
The sample rate converter performs an interpolation and
resampling procedure to provide an output data rate of
20 MSPS to 168 MSPS. Table 16 and Table 17 detail the coeffi-
cients for the INT1 and INT2 filters. The sinc filters are a
standard implementation.
Table 16. INT1 Filter Coefficients
Coefficient
Number Coefficient
Coefficient
Number Coefficient
C0, C26 15 C7, C19 0
C1, C25 0 C8, C18 2450
C2, C24 −97 C9, C17 0
C3, C23 0 C10, C16 −5761
C4, C22 361 C11, C15 0
C5, C21 0 C12, C14 20433
C6, C20 −1017 C13 32768
Table 17. INT2 Filter Coefficients
Coefficient
Number Coefficient
Coefficient
Number Coefficient
C0, C14 −27 C4, C10 −1032
C1, C13 0 C5, C9 0
C2, C12 227 C6, C8 4928
C3, C11 0 C7 8192
The relationship between the output sample rate and the Σ-Δ
modulator clock rate is expressed as follows:
fOUT = fMOD ÷ KOUT
Table 18 shows the available KOUT conversion factors.
If the main clocking source of the AD9261 is provided by the
PLL, it is important that once the PLL has been programmed
and locked, to initiate an SRC reset before programming the
desired KOUT factor. This is done by first writing 0x101[5:0] = 0
and then rewriting to the same register with the appropriate
KOUT value. In addition, if the AD9261 loses its clock source and
then later regains it, an SRC reset should be initiated.
Table 18. SRC Conversion Factors
0x101[5:0] KOUT 0x101[5:0] KOUT 0x101[5:0] KOUT
0 SRC reset 22 11 44 22
1 4 23 11.5 45 22.5
2 4 24 12 46 23
3 4 25 12.5 47 23.5
4 4 26 13 48 24
5 4 27 13.5 49 24.5
6 4 28 14 50 25
7 4 29 14.5 51 25.5
8 4 30 15 52 26
9 4.5 31 15.5 53 26.5
10 5 32 16 54 27
11 5.5 33 16.5 55 27.5
12 6 34 17 56 28
13 6.5 35 17.5 57 28.5
14 7 36 18 58 29
15 7.5 37 18.5 59 29.5
16 8 38 19 60 30
17 8.5 39 19.5 61 30.5
18 9 40 20 62 31
19 9.5 41 20.5 63 31.5
20 10 42 21
21 10.5 43 21.5
Cascaded Filter Responses
The cascaded filter responses for the three signal bandwidth
settings are for a 160 MSPS output data rate, as shown in Figure 47,
Figure 48, and Figure 49.
0 1020304050607080
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
0246810
–0.08
–0.04
0
0.04
0.08
FREQ UENCY (MHz)
07803-047
Figure 47. 10 MHz Signal Bandwidth, 160 MSPS
AD9261
Rev. 0 | Page 21 of 28
012345
–0.08
–0.04
0
0.04
0.08
FREQ UENCY (MHz)
0 1020304050607080
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY (MHz)
AMPL ITUDE ( dBFS )
07803-048
Figure 48. 5 MHz Signal Bandwidth, 160 MSPS
0.5 1.5 2.5
–0.08
–0.04
0
0.04
0.08
FREQUENCY (MHz)
0 1020304050607080
–160
–140
–120
–100
–80
–60
–40
–20
0
FREQUENCY ( M Hz )
AMPL ITUDE ( dBFS )
07803-049
Figure 49. 2.5 MHz Signal Bandwidth, 160 MSPS
DIGITAL OUTPUTS
Digital Output Format
The AD9261 offers a variety of digital output formats for ease of
system integration. The digital output consists of 16 data bits and
an output clock signal (DCO) for data latching. The data bits can
be configured for offset binary, twos complement, or Gray code
by writing to Register 0x14[1:0]. In addition, the voltage swing of
the digital outputs can be configured to 3.3 V TTL levels or a
reduced voltage swing of 1.8 V by accessing Register 0x14[7].
When 3.3 V voltage levels are desirable, the DRVDD power
supply must be set to 3.3 V.
Overrange (OR) Condition
The OR pin serves as an indicator for an overrange condition. The
OR pin is triggered by in-band signals that exceed the full-scale
range of the ADC. In addition, the AD9261 possesses out-of-
band gain above 10 MHz; therefore, a large out-of-band signal
may trip an overrange condition.
The OR pin is a synchronous output that is updated at the out-
put data rate. Ideally, OR should be latched on the falling edge of
DCO to ensure proper setup-and-hold time. However, because
an overrange condition typically extends well beyond one clock
cycle—that is, it does not toggle at the DCO rate—data can
usually be successfully detected on the rising edge of DCO or
monitored asynchronously.
The AD9261 has two trip points that can trigger an overrange
condition: analog and digital. The analog trip point is located
in the modulator, and the second trip point is in the digital
engine. In normal operation, it is possible for the analog trip
point to toggle the OR pin for a number of clock cycles as the
analog input approaches full scale. Because the OR pin is a pulse-
width modulated (PWM) signal, as the analog input increases
in amplitude, the duration of overrange pin toggling increases.
Eventually, when the OR pin is high for an extended period of
time, the ADC is overloaded, and there is little correspondence
between analog input and digital output.
The second trip point is in the digital block. If the input signal
is large enough to cause the data bits to clip to the maximum
full-scale level, an overrange condition occurs. The overrange
trip point can be adjusted by specifying a threshold level.
Table 19 shows the corresponding threshold level in dBFS vs.
register setting. If the input signal crosses this level, the OR pin
is set. In the case where 0x111[5:0] is set to all 0s, the threshold
level is set to the maximum code of 32,76710. This feature
provides a means of reporting the instantaneous amplitude as it
crosses a user-provided threshold. This gives the user a sense
for the signal level without needing to perform a full power
measurement.
The user has the ability to select how the overrange conditions
are reported, and this is controlled through Register 0x111 via
AUTORST, OR_IND, and ORTHRESH (see Table 20). By
enabling the AUTORST bit, Register 0x111[7], if an overrange
occurs, the ADC automatically resets itself. The OR pin remains
high until the automatic reset has completed. If an analog trip
occurs, the modulator resets itself after 16 consecutive clock
cycles of overrange.
If the AD9261 is used in a system that incorporates automatic
gain control (AGC), the OR signal can be used to indicate that
the signal amplitude should be reduced. This may be particularly
effective for use in maximizing the signal dynamic range if the
signal includes high occurrence components that occasionally
exceed full scale by a small amount.
TIMING
The AD9261 provides a data clock out (DCO) pin to assist
in capturing the data in an external register. The data outputs
are valid on the rising edge of DCO, unless changed by setting
Register 0x16[7]. See Figure 2 for a graphical timing description.
AD9261
Rev. 0 | Page 22 of 28
Table 19. OR Threshold Levels
0x111[5:0] Threshold (dBFS) 0x111[5:0] Threshold (dBFS) 0x111[5:0] Threshold (dBFS)
1 −36.12 16 −9.28 2B −3.45
2 −30.10 17 −8.89 2C −3.25
3 −26.58 18 −8.52 2D −3.06
4 −24.08 19 −8.16 2E −2.87
5 −22.14 1A −7.82 2F −2.68
6 −20.56 1B −7.50 30 −2.50
7 −19.22 1C −7.18 31 −2.32
8 −18.06 1D −6.88 32 −2.14
9 −17.04 1E −6.58 33 −1.97
A −16.12 1F −6.30 34 −1.80
B −15.29 20 −6.02 35 −1.64
C −14.54 21 −5.75 36 −1.48
D −13.84 22 −5.49 37 −1.32
E −13.20 23 −5.24 38 −1.16
F −12.60 24 −5.00 39 −1.00
10 −12.04 25 −4.76 3A −0.86
11 −11.51 26 −4.53 3B −0.71
12 −11.02 27 −4.30 3C −0.56
13 −10.56 28 −4.08 3D −0.42
14 −10.10 29 −3.87 3E −0.28
15 −9.68 2A −3.66 3F −0.14
Table 20. OR Conditions
OR Conditions AUTORST OR_IND ORTHRESH[5:0] ORTHRESH[4:0] Description
Normal, Reset Off 0 0 0 00000 Digital trip: if 16-bit output > 32,767, OR = 1, else OR = 0
Digital Threshold,
Reset Off
0 0 >0 Digital threshold: If 16-bit output > ORTHRESH, OR = 1,
else OR = 0
Full Overrange,
Reset Off
0 1 0 X1 If analog trip or digital trip, OR = 1, else OR = 0
Data Valid, No Reset 0 1 1 X1 If analog trip or digital trip or calibration, OR = 0, else OR = 1
Normal, Reset On 1 0 0 00000 Digital trip: if 16-bit output > 32,767, OR = 1, else OR = 0
Digital Threshold,
Reset On
1 0 >0 Digital threshold: if 16-bit output > ORTHRESH, OR = 1,
else OR = 0
Full Overrange,
Reset On
1 1 0 X1 If analog trip or digital trip, OR = 1, else OR = 0
Data Valid,
Reset On
1 1 1 X1 If analog trip or digital trip or calibration, OR = 0 else OR = 1
1 X = don’t care.
AD9261
Rev. 0 | Page 23 of 28
SERIAL PORT INTERFACE (SPI)
The AD9261 serial port interface (SPI) allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This provides
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that are further divided into fields, as documented in
the Memory Map section. For detailed operational information,
see the AN-877 Application Note, Interfacing to High Speed
ADCs via SPI.
CONFIGURATION USING THE SPI
As summarized in Table 21, three pins define the SPI of this ADC.
The SCLK pin synchronizes the read and write data presented
to the ADC. The SDIO pin allows data to be sent and read from
the internal ADC memory map registers. The CSB pin is an active
low control that enables or disables the read and write cycles.
Table 21. Serial Port Interface Pins
Pin Name Description
SCLK SCLK (serial clock) is the serial shift clock. SCLK
synchronizes serial interface reads and writes.
SDIO SDIO (serial data input/output) is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB CSB (chip select bar) is an active low control that
gates the read and write cycles.
The falling edge of CSB in conjunction with the rising edge of
SCLK determines the start of the framing. Figure 50 and Table 22
provide an example of the serial timing and its definitions.
Other modes involving CSB are available. CSB can be held low
indefinitely to permanently enable the device (this is called
streaming). CSB can stall high between bytes to allow for addi-
tional external timing. When CSB is tied high, SPI functions are
placed in a high impedance mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit words.
The first bit of each individual byte of serial data indicates whether
a read or write command is issued. This allows the serial data
input/output (SDIO) pin to change direction from an input to
an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as to read the
contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO) pin to change direction from an input to an output
at the appropriate point in the serial frame.
Data can be sent in MSB-first or in LSB-first mode. MSB first is
the default setting on power-up and can be changed via the
configuration register. For more information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
Table 22. SPI Timing Diagram Specifications
Parameter Description
tSDS Setup time between data and rising edge of SCLK
tSDH Hold time between data and rising edge of SCLK
tSCLK Period of the clock
tSS Setup time between CSB and SCLK
tSH Hold time between CSB and SCLK
tSHIGH Minimum period that SCLK should be in a logic
high state
tSLOW Minimum period that SCLK should be in a logic
low state
DON’ T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
SS
t
SDH
t
SHIGH
t
SCLK
t
SLOW
t
SDS
t
SH
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
0
7803-050
Figure 50. Serial Port Interface Timing Diagram
AD9261
Rev. 0 | Page 24 of 28
HARDWARE INTERFACE
The pins described in Table 21 comprise the physical interface
between the programming device of the user and the serial port
of the AD9261. The SCLK and CSB pins function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
such method is described in detail in the AN-812 Application
Note, MicroController-Based Serial Port Interface (SPI) Boot
Circuit.
When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power-on, the pins are associated with a specific function.
AD9261
Rev. 0 | Page 25 of 28
MEMORY MAP
Table 23. Memory Map
Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SPI Port Config 0x00 0 LSBFIRST SOFTRESET 1 1 SOFTRESET LSBFIRST 0
Chip ID 0x01 CHIPID[7:0]
Chip Grade 0x02 CHILDID[2:0]
Power Modes 0x08 PWRDWN[1:0]
PLLENABLE 0x09 PLLENABLE
PLL 0x0A PLLLOCKED PLLAUTO PLLMULT[5:0]
Analog Input 0x0F BW[1:0]
Output Modes 0x14 DRVSTD Interleave OUTENB OUTINV Format[1:0]
Output Adjust 0x15 DRVSTR33[1:0] DRVSTR18[1:0]
Output Clock 0x16 DCOINV
Reference 0x18 EXTREF
Output Data 0x101 KOUT[5:0]
Overrange 0x111 AUTORST OR_IND ORTHRESH[5:0]
MEMORY MAP DEFINITIONS
Table 24. Memory Map Definitions
Register Address Bit(s) Mnemonic Default Description
SPI Port Config 0x00 6, 1 LSBFIRST 0 0: serial interface uses MSB first format
1: serial interface uses LSB first format
5, 2 SOFTRESET 0 1: default all serial registers except 0x00, 0x09, and 0x0A
Chip ID 0x01 [7:0] CHIPID 0x26 0x26: AD9261
Chip Grade 0x02 [5:4] CHILDID 0 0x00: 10 MHz bandwidth
Power Modes 0x08 [1:0] PWRDWN 0 0x0: normal operation
0x1: power-down (local)
0x2: standby (everything except reference circuits)
0x3: sleep
PLLENABLE 0x09 2 PLLENABLE 0 1: enable PLL
PLL 0x0A 7 PLLLOCKED 0 0: PLL is not locked
1: PLL is locked
6 PLLAUTO 0 1: PLL autoband enabled
[5:0] PLLMULT 0 See Table 10
Analog Input 0x0F [6:5] BW 0 0x0: 10 MHz
0x1: 5 MHz
0x2: 2.5 MHz
0x3: 10 MHz
Output Modes 0x14 7 DRVSTD 0 0: 3.3 V
1: 1.8 V
5 Interleave 0 1: interleave both channels onto D[15:0]
4 OUTENB 0 1: data outputs tristated
2 OUTINV 0 1: data outputs bitwise inverted
[1:0] Format 0 0: offset binary
1: twos complement
2: Gray code
3: offset binary
AD9261
Rev. 0 | Page 26 of 28
Register Address Bit(s) Mnemonic Default Description
Output Adjust 0x15 [3:2] DRVSTR33 0 Typical output sink current to DGND
0: 33 mA
1: 63 mA
2: 93 mA
3: 120 mA
[1:0] DRVSTR18 2 Typical output sink current to DGND
0: 10 mA
1: 20 mA
2: 30 mA
3: 39 mA
Output Clock 0x16 7 DCOINV 0 1: invert DCO
Reference 0x18 6 EXTREF 0 1: use external reference
Output Data 0x101 [5:0] KOUT 0 Output data rate, see Table 18
Overrange 0x111 7 AUTORST 0 1: enable loop filter reset indicator on OR pin
6 OR_IND 0 See Table 20
[5:0] ORTHRESH 0 See Table 19
AD9261
Rev. 0 | Page 27 of 28
OUTLINE DIMENSIONS
PIN 1
INDICATOR
TOP
VIEW 6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° M AX
0.20 REF
0.80 M A X
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 M A X
0.02 NOM
0.60 M A X
0.60 MA X PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COM PLI ANT T O JEDEC S TANDARDS MO-220-V KKD-2
080108-A
FO R P ROPER CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE P IN CONFIGURATIO N AND
FUNCT I O N DES CRI PT I O NS
SECTIO N OF THIS DATA SHEE T .
Figure 51. 48-Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad (CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD9261BCPZ-10 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD9261BCPZRL7-10 −40°C to +85°C 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-48-1
AD9261-10EBZ Evaluation Board
1 Z = RoHS Compliant Part.
AD9261
Rev. 0 | Page 28 of 28
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07803-0-4/10(0)
