LT3055 Series 500mA, Linear Regulator with Precision Current Limit and Diagnostics DESCRIPTION FEATURES n n n n n n n n n n n n n n Output Current: 500mA Dropout Voltage: 350mV Input Voltage Range: 1.6V to 45V Programmable Precision Current Limit: 10% Output Current Monitor: 1/500th of IOUT Programmable Minimum IOUT Monitor Temperature Monitor: 10mV/C FAULT Indicator: Current Limit, Thermal Limit or Minimum IOUT Low Noise: 25VRMS (10Hz to 100kHz) Adjustable Output (VREF = VOUT(MIN) = 0.6V) Output Tolerance: 2% Over Load, Line and Temperature Stable with Low ESR, Ceramic Output Capacitors (3.3F Minimum) Shutdown Current: <1A Reverse Battery and Thermal Limit Protection 16-Lead 4mm x 3mm DFN and MSOP Packages APPLICATIONS n n n n n The LT(R)3055 series are micropower, low noise, low dropout voltage (LDO) linear regulators. The devices supply 500mA of output current with a dropout voltage of 350mV. A 10nF bypass capacitor reduces output noise to 25VRMS in a 10Hz to 100kHz bandwidth and soft starts the reference. The LT3055's 45V input voltage rating combined with its precision current limit and diagnostic functions make the IC an ideal choice for robust, high reliability applications. A single resistor programs the LT3055's current limit, accurate to 10% over a wide input voltage and temperature range. Another resistor programs the LT3055's minimum output current monitor, useful for detecting open-circuit conditions. The current monitor function sources a current equal to 1/500th of output current. Logic fault pins assert low if the LT3055 is in current limit (FAULT2), operating below its minimum output current (FAULT1) or is in thermal limit (both FAULT1 and FAULT2). PWRGD indicates output regulation. The TEMP pin indicates average die temperature. The LT3055 optimizes stability and transient response with low ESR ceramic capacitors, requiring a minimum of 3.3F. Internal protection circuitry includes current limiting, thermal limiting, reverse battery protection, reverse current protection and reverse output protection. Protected Antenna Supplies Automotive Telematics Industrial Applications (Trucks, Forklifts, etc.) High Reliability Applications Noise-Sensitive RF or DSP Supplies The LT3055 is available in fixed output voltages of 3.3V and 5V, and as an adjustable device with an output voltage range from 0.6V to 40V. All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION Precision Current Limit, RIMAX = 604 5V Supply with 497mA Precision Current Limit, 10mA IMIN VIN 6V + IN 10F 22nF 0.1F 200k 200k 200k 604 (THRESHOLD = 497mA) 120k (THRESHOLD = 10mA) LT3055-5 OUT SHDN FAULT1 FAULT2 PWRGD IMAX IMIN 5V 10nF SENSE 10F ADJ IMON TEMP REF/BYP GND 1k (ADC FULL-SCALE = 1V) 0.1F TO P ADC TO P ADC 10nF 3055 TA01a Document Feedback 550 CURRENT LIMIT FAULT THRESHOLD (mA) n 540 VOUT(NOMINAL) = 5V 530 520 510 500 490 VIN = 7V VIN = 5.6V 480 470 460 450 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 TA01b For more information www.analog.com Rev. B 1 LT3055 Series ABSOLUTE MAXIMUM RATINGS (Note 1) IN Pin Voltage..........................................................50V OUT Pin Voltage............................................ +40V, -50V Input-to-Output Differential Voltage...............+50V, -40V ADJ Pin Voltage.......................................................50V SENSE Pin Voltage...................................................50V SHDN Pin Voltage....................................................50V FAULT1, FAULT2, PWRGD Pin Voltage.............-0.3V, 50V IMON Pin Voltage...............................................-0.3V, 7V IMIN Pin Voltage................................................-0.3V, 7V IMAX Pin Voltage...............................................-0.3V, 7V TEMP Pin Voltage.............................................-0.3V, 7V REF/BYP Pin Voltage....................................................1V Output Short-Circuit Duration........................... Indefinite Operating Junction Temperature Range (Notes 2, 3) E-, I-Grades........................................ -40C to 125C MP-Grade........................................... -55C to 150C H-Grade.............................................. -40C to 150C Storage Temperature Range................... -65C to 150C Lead Temperature: (Soldering, 10 sec) MSOP Package Only.......................................... 300C PIN CONFIGURATION TOP VIEW TOP VIEW IN IN SHDN FAULT1 FAULT2 PWRGD TEMP IMON 1 2 3 4 5 6 7 8 17 GND 16 15 14 13 12 11 10 9 OUT OUT ADJ/SENSE** GND/ADJ* GND REF/BYP IMAX IMIN MSE PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 125C, JA = 37C/W, JC = 5C/W TO 10C/W TJMAX = 150C FOR H-GRADE EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB IN 1 IN 2 SHDN 3 FAULT1 4 FAULT2 5 PWRGD 6 TEMP 7 IMON 8 16 OUT 15 OUT 17 GND 14 ADJ/SENSE** 13 GND/ADJ* 12 GND 11 REF/BYP 10 IMAX 9 IMIN DE PACKAGE 16-LEAD (4mm x 3mm) PLASTIC DFN TJMAX = 125C, JA = 38C/W, JC = 4.3C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB *PIN 13 IS GND FOR LT3055; PIN 13 IS ADJ FOR LT3055-3.3 AND LT3055-5. **PIN 14 IS ADJ FOR LT3055; PIN 14 IS SENSE FOR LT3055-3.3 AND LT3055-5. Rev. B 2 For more information www.analog.com LT3055 Series ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3055EMSE#PBF LT3055EMSE#TRPBF 3055 16-Lead Plastic MSOP -40C to 125C LT3055IMSE#PBF LT3055IMSE#TRPBF 3055 16-Lead Plastic MSOP -40C to 125C LT3055MPMSE#PBF LT3055MPMSE#TRPBF 3055 16-Lead Plastic MSOP -55C to 150C LT3055HMSE#PBF LT3055HMSE#TRPBF 3055 16-Lead Plastic MSOP -40C to 150C LT3055EMSE-3.3#PBF LT3055EMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP -40C to 125C LT3055IMSE-3.3#PBF LT3055IMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP -40C to 125C LT3055MPMSE-3.3#PBF LT3055MPMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP -55C to 150C LT3055HMSE-3.3#PBF LT3055HMSE-3.3#TRPBF 305533 16-Lead Plastic MSOP -40C to 150C LT3055EMSE-5#PBF LT3055EMSE-5#TRPBF 30555 16-Lead Plastic MSOP -40C to 125C LT3055IMSE-5#PBF LT3055IMSE-5#TRPBF 30555 16-Lead Plastic MSOP -40C to 125C LT3055MPMSE-5#PBF LT3055MPMSE-5#TRPBF 30555 16-Lead Plastic MSOP -55C to 150C LT3055HMSE-5#PBF LT3055HMSE-5#TRPBF 30555 16-Lead Plastic MSOP -40C to 150C LT3055EDE#PBF LT3055EDE#TRPBF 3055 16-Lead (4mm x 3mm) Plastic DFN -40C to 125C LT3055IDE#PBF LT3055IDE#TRPBF 3055 16-Lead (4mm x 3mm) Plastic DFN -40C to 125C LT3055EDE-3.3#PBF LT3055EDE-3.3#TRPBF 05533 16-Lead (4mm x 3mm) Plastic DFN -40C to 125C LT3055IDE-3.3#PBF LT3055IDE-3.3#TRPBF 05533 16-Lead (4mm x 3mm) Plastic DFN -40C to 125C LT3055EDE-5#PBF LT3055EDE-5#TRPBF 30555 16-Lead (4mm x 3mm) Plastic DFN -40C to 125C LT3055IDE-5#PBF LT3055IDE-5#TRPBF 30555 16-Lead (4mm x 3mm) Plastic DFN -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix Rev. B For more information www.analog.com 3 LT3055 Series ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) PARAMETER CONDITIONS Minimum Input Voltage (Notes 3, 11, 17) ILOAD = 500mA Regulated Output Voltage (Note 4) LT3055-3.3: VIN = 3.9V, ILOAD = 1mA 3.9V < VIN < 45V, 1mA < ILOAD < 500mA ADJ Pin Voltage (Notes 3, 4) MIN TYP 1.6 2.2 V l 3.267 3.234 3.3 3.3 3.333 3.336 V V LT3055-5: VIN = 3.9V, ILOAD = 1mA 5.6V < VIN < 45V, 1mA < ILOAD < 500mA l 4.95 4.9 5 5 5.05 5.1 V V LT3055: VIN = 2.2V, ILOAD = 1mA 2.2V < VIN < 45V, 10mA < ILOAD < 500mA 594 588 600 l 606 612 mV mV l MAX UNITS Line Regulation (Note 3) LT3055: VIN = 2.2V to 45V, ILOAD = 1mA LT3055-3.3: VIN = 3.9V to 45V, ILOAD = 1mA LT3055-5: VIN = 5.6V to 45V, ILOAD = 1mA l l l 0.25 1.4 2 3 19.5 30 mV mV mV Load Regulation (Note 3) LT3055: VIN = 2.2V, ILOAD = 1mA to 500mA LT3055-3.3: VIN = 4.3V, ILOAD = 1mA to 500mA LT3055-5: VIN = 6V, ILOAD = 1mA to 500mA l l l 0.5 3.5 5.25 4 22 33 mV mV mV Dropout Voltage, VIN = VOUT(NOMINAL) (Notes 5, 6) ILOAD = 10mA 140 175 260 mV mV 200 250 370 mV mV 225 275 410 mV mV 350 400 590 mV mV 65 100 270 1.8 11 130 200 550 4.5 25 A A A mA mA 0.2 1 A 16 60 l ILOAD = 50mA l ILOAD = 100mA l ILOAD = 500mA l GND Pin Current, VIN = VOUT(NOMINAL) + 0.6V (Notes 6, 7) ILOAD = 0mA ILOAD = 1mA ILOAD = 10mA ILOAD = 100mA ILOAD = 500mA Quiescent Current in Shutdown VIN = 45V, VSHDN = 0V ADJ Pin Bias Current (Notes 3,12) VIN = 12V Output Voltage Noise COUT = 10F, ILOAD = 500mA, VOUT = 600mV, BW = 10Hz to 100kHz 90 VRMS COUT = 10F, CBYP = 10nF, ILOAD = 500mA, VOUT = 600mV, BW = 10Hz to 100kHz 25 VRMS l l l l l l Shutdown Threshold VOUT = Off to On VOUT = On to Off l l SHDN Pin Current (Note 13) VSHDN = 0V, VIN = 45V VSHDN = 45V, VIN = 45V l l Ripple Rejection VIN-VOUT = 2V, VRIPPLE = 0.5VP-P, fRIPPLE = 120Hz, ILOAD = 500mA LT3055, VOUT = 0.6V LT3055-3.3 LT3055-5 Input Reverse Leakage Current VIN = -45V, VOUT = 0 Reverse Output Current (Note 14) VOUT = 1.2V, VIN = 0 Internal Current Limit (Note 3) VIN = 2.2V, VOUT = 0, VIMAX = 0 VIN = 2.2V, VOUT = -5% External Programmed Current Limit, VOUT = 5V (Notes 6, 8) 0.9 1.3 1.1 0.5 70 55 51 1.42 V V 1 3 A A 85 70 66 dB dB dB 300 l 0 nA 10 900 A A mA mA l 520 5.6V < VIN < 10V, VOUT = 5V, RIMAX = 1.5k, FAULT2 Pin Threshold (IFAULT) l 180 200 220 mA 5.6V < VIN < 7V, VOUT = 5V, RIMAX = 604, FAULT2 Pin Threshold (IFAULT) l 445 495 545 mA Rev. B 4 For more information www.analog.com LT3055 Series ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 2) PARAMETER CONDITIONS FAULT, PWRGD Pins Logic Low Voltage Pull-Up Current = 50A MIN FAULT, PWRGD Pins Leakage Current VFAULT1, VFAULT2, VPWRGD = 5V IMIN Threshold Accuracy (Notes 6, 9) l TYP MAX UNITS 0.14 0.25 V 0.01 1 A 5.6V < VIN < 15V, VOUT = 5V, RIMIN = 1.2M 5.6V < VIN < 15V, VOUT = 5V, RIMIN = 120K l l 0.9 9 1 10 1.1 11 mA mA PWRGD Trip Point % of Nominal Output Voltage, Output Rising l 86 90 94 % PWRGD Trip Point Hysteresis % of Nominal Output Voltage Current Monitor Ratio (Notes 6,10), Ratio = IOUT/IMON ILOAD = 10mA, 250mA, 500mA TEMP Voltage (Note 16) 1 l 450 TJ = 25C TJ = 125C 550 0.25 1.25 TEMP Error (Note 16) l Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Absolute maximum input-to-output differential voltage is not achievable with all combinations of rated IN pin and OUT pin voltages. With the IN pin at 50V, the OUT pin may not be pulled below 0V. The total differential voltage from IN to OUT must not exceed +50V, -40V. If OUT is pulled above GND and IN, the total differential voltage from OUT to IN must not exceed 40V. Note 2: The LT3055 is tested and specified under pulse load conditions such that TJ ~ TA. The LT3055E is 100% production tested at TA = 25C and performance is guaranteed from 0C to 125C. Performance at -40C and 125C is assured by design, characterization and correlation with statistical process controls. The LT3055I is guaranteed over the full -40C to 125C operating junction temperature range. The LT3055MP is 100% tested over the -55C to 150C operating junction temperature range. The LT3055H is 100% tested at 150C operating junction temperature. Note 3: The LT3055 adjustable version is tested and specified for these conditions with ADJ pin connected to the OUT pin. Note 4: Maximum junction temperature limits operating conditions. Regulated output voltage specifications do not apply for all possible combinations of input voltage and output current. If operating at the maximum input voltage, limit the output current range. If operating at the maximum output current, limit the input voltage range. Current limit foldback limits the maximum output current as a function of input-tooutput voltage. See Current Limit vs VIN-VOUT in the Typical Performance Characteristics section. Note 5: Dropout voltage is the minimum differential IN-to-OUT voltage needed to maintain regulation at a specified output current. In dropout, the output voltage equals (VIN - VDROPOUT). For some output voltages, minimum input voltage requirements limit dropout voltage. Note 6: To satisfy minimum input voltage requirements, the LT3055 adjustable version is tested and specified for these conditions with an external resistor divider (60k bottom, 440k top) which sets VOUT to 5V. The external resistor divider adds 10A of DC load on the output. This external current is not factored into GND pin current. Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 0.6V and a current source load. GND pin current increases in dropout. For the fixed output voltage versions, an internal resistor divider adds about 10A to GND pin current. See GND pin current curves in the Typical Performance Characteristics section. 500 % -0.08 mA/mA V V 0.08 V Note 8: Current limit varies inversely with the external resistor value tied from the IMAX pin to GND. For detailed information on how to set the IMAX pin resistor value, please see the Operation section. If a programmed current limit is not needed, tie the IMAX pin to GND and internal protection circuitry implements short-circuit protection as specified. Note 9: The IMIN fault condition asserts if the output current falls below the IMIN threshold defined by an external resistor from the IMIN pin to GND. For detailed information on how to set the IMIN pin resistor value, please see the Operation section. If the IMIN fault condition is not needed, the IMIN pin must be left floating (unconnected). Note 10: Current monitor ratio is tested with the IMON pin fixed at VOUT - 0.5V and with the input range limited to VOUT + 0.6V < VIN < VOUT + 10V for IOUT = 10mA; VOUT + 0.6V < VIN < VOUT + 4V for IOUT = 250mA, and VOUT + 0.6V < VIN < VOUT + 2V for IOUT = 500mA. Input voltage range conditions are set to limit power dissipation in the IC to 1W maximum for test purposes. The current monitor ratio varies slightly when in current limit or when the IMON voltage exceeds VOUT - 0.5V. Please see the Operation section for more information. If the current monitor function is not needed, tie the IMON pin to GND. Note 11: To satisfy requirements for minimum input voltage, current limit is tested at VIN = VOUT(NOMINAL) + 1V or VIN = 2.2V, whichever is greater. Note 12: ADJ pin bias current flows out of the ADJ pin. Note 13: SHDN pin current flows into the SHDN pin. Note 14: Reverse output current is tested with the IN pin grounded and the OUT pin forced to the specified voltage. This current flows into the OUT pin and out of the GND pin. Note 15: 500mA of output current does not apply to the full range of input voltage due to the internal current limit foldback. Note 16: The TEMP output voltage represents the average temperature of the die while dissipating quiescent power. Due to the pass device power dissipation and temperature gradients across the die, the TEMP output voltage measurement does not guarantee that absolute maximum junction temperature is not exceeded. Note 17: Minimum Input Voltage is the input voltage at which the output voltage is decreased 1% from nominal. At elevated temperatures, an input voltage greater than this is necessary for correct operation of the TEMP pin. See Temp Pin Minimum Input Voltage in the Typical Performance Characteristics section. Rev. B For more information www.analog.com 5 LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS Guaranteed Dropout Voltage 600 550 500 TJ = 150C 400 DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 450 TJ = 125C 350 300 TJ = 25C 250 200 150 100 50 0 0 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) 700 650 600 550 500 450 400 350 300 250 200 150 100 50 0 550 500 TJ = 150C TJ = 25C 0 200 150 3055 G03 Output Voltage-LT3055-3.3 3.366 3.344 3.333 OUTPUT VOLTAGE (V) 608 606 604 602 600 598 596 594 3.322 3.311 3.300 3.289 3.278 3.267 592 3.256 590 3.245 588 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3.234 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 G06 4.96 4.94 4.92 4.90 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 GND Pin Current-LT3055-3.3 12 TJ = 25C IL = 0 11 RL = 6.6, IL = 500mA 10 GND PIN CURRENT (mA) IL = 1mA 4.98 IL = 1mA 3.355 Quiescent Current 5.00 IL = 10mA 3055 G05 QUIESCENT CURRENT (A) OUTPUT VOLTAGE (V) 250 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 50 100 150 200 250 300 350 400 450 500 OUTPUT CURRENT (mA) IL = 1mA 610 ADJ PIN VOLTAGE (mV) QUIESCENT CURRENT (A) 612 Output Voltage-LT3055-5 5.02 IL = 50mA 50 3055 G04 5.04 IL = 100mA 300 ADJ Pin Voltage 5.06 IL = 500mA 400 350 3055 G02 Quiescent Current 130 120 110 100 VIN = VSHDN = 12V 90 VOUT = 5V IL = 10A 80 70 60 50 40 30 20 VIN = 12V 10 ALL OTHER PINS = 0V 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 5.08 450 100 3055 G01 5.10 Dropout Voltage 600 = TEST POINTS DROPOUT VOLTAGE (mV) Typical Dropout Voltage TJ = 25C, unless otherwise noted. LT3055-5 LT3055-3.3 9 8 7 6 5 RL = 13.2, IL = 250mA 4 3 RL = 33, IL = 100mA 2 1 VSHDN = 0V, RL = 0 0 1 2 3 4 5 6 7 VIN (V) 8 9 10 11 12 3055 G07 3055 G08 0 RL = 330, IL = 10mA 0 1 2 3 4 5 6 7 VIN (V) 8 9 10 11 12 3055 G09 Rev. B 6 For more information www.analog.com LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS GND Pin Current-LT3055-5 GND Pin Current vs ILOAD 20 RL = 10, IL = 500mA 11 GND PIN CURRENT (mA) GND PIN CURRENT (mA) 9 8 7 6 5 RL = 20, IL = 250mA 4 3 16 14 12 10 8 6 2 RL = 50, IL = 100mA 4 1 RL = 500, IL = 10mA 2 0 0 1 2 3 4 5 6 7 VIN (V) 8 VIN = 5.6V VOUT = 5V 18 10 0 9 10 11 12 SHDN Pin Threshold SHDN PIN THRESHOLD (V) 12 TJ = 25C, unless otherwise noted. 0 50 100 150 200 250 300 350 400 450 500 ILOAD (mA) 3055 G10 3055 G11 SHDN Pin Input Current 3055 G12 SHDN Pin Input Current ADJ Pin Bias Current 50 3.0 2.5 2.0 1.5 1.0 0.5 45 2.5 ADJ PIN BIAS CURRENT (nA) SHDN = 45V SHDN PIN INPUT CURRENT (A) SHDN PIN INPUT CURRENT (A) 3.0 1.5 1.4 OFF TO ON 1.3 ON TO OFF 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 2.0 1.5 1.0 0.5 40 35 30 25 20 15 10 5 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 0 0 5 10 15 20 25 30 35 SHDN PIN VOLTAGE (V) 40 3055 G13 3055 G15 3055 G14 Internal Current Limit 1.0 Reverse Output Current TJ = -55C TJ = -40C TJ = 25C TJ = 125C TJ = 150C 0.9 0.8 CURRENT LIMIT (A) 1.5 1.4 VIN = 6V 1.3 VOUT = 0V 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 0.7 0.6 0.5 0.4 0.3 1.0 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.2 0.1 0.1 0 0 5 10 15 20 25 30 35 40 INPUT/OUTPUT DIFFERENTIAL (V) 3055 G16 45 3055 G17 VIN = 0 0.9 OUTPUT CURRENT (A) Internal Current Limit CURRENT LIMIT (A) 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 45 0 0 5 10 15 20 25 VOUT (V) 30 35 40 3055 G18 Rev. B For more information www.analog.com 7 LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS Input Ripple Rejection 90 VOUT = VADJ = 1.2V VIN = 0V RIPPLE REJECTION (dB) OUTPUT CURRENT (A) 80 70 60 50 40 30 IADJ 20 CREF/BYP = 0pF CREF/BYP = 100pF CREF/BYP = 10nF 80 60 50 40 30 ILOAD = 500mA COUT = 10F VOUT = 3.3V VIN = 4.3V + 50mVRMS RIPPLE 20 10 IOUT 10 70 0 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 10 1M Input Ripple Rejection 80 2.0 RIPPLE REJECTION (dB) 70 60 50 40 ILOAD = 500mA CREF/BYP = 10nF VOUT = 3.3V VIN = 4.3V + 50mVRMS RIPPLE f = 120Hz 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) ILOAD = 500mA VOUT = 5V VOUT = 3.3V VOUT = 2.5V VOUT = 1.2V VOUT = 0.6V 10 100 1k 10k FREQUENCY (Hz) 100k 1k 10k 100k FREQUENCY (Hz) 1M 10M IL = 1mA TO 500mA VIN = VOUT + 1V, 2.1V FOR LT3055 12 LT3055, VOUT = 0.6V LT3055-3.3 10 LT3055-5 8 14 1.6 1.4 1.2 1.0 0.8 0.6 6 4 3 2 0 0.4 -2 0.2 -4 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) -6 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 G24 3055 G23 OUTPUT NOISE SPECTRAL DENSITY (V/Hz) OUTPUT NOISE SPECTRAL DENSITY (V/Hz) COUT = 10F IL = 500mA 100 Load Regulation Output Noise Spectral Density vs CREF/BYP, CFF = 0 1 0.01 10 3055 G21 1.8 Output Noise Spectral Density CREF/BYP = 0, CFF = 0 0.1 ILOAD = 500mA CREF/BYP = 10nF VOUT = 3.3V VIN = 4.3V + 50mVRMS RIPPLE 20 16 3055 G22 10 40 30 0 10M LOAD REGULATION (mV) MINIMUM INPUT VOLTAGE (V) 2.2 10 50 Minimum Input Voltage 90 20 60 3055 G20 3055 G19 30 70 10 1k 10k 100k FREQUENCY (Hz) 100 COUT = 10F COUT = 3.3F 80 10 VOUT = 5V Output Noise Spectral Density vs CFF, CREF/BYP = 10nF COUT = 10F IL = 500mA 1 VOUT = 0.6V 0.1 0.01 CREF/BYP = 100pF CREF/BYP = 1nF CREF/BYP = 10nF 10 100 1k 10k FREQUENCY (Hz) 3055 G25 100k 3055 G26 OUTPUT NOISE SPECTRAL DENSITY (V/Hz) 90 Input Ripple Rejection 90 RIPPLE REJECTION (dB) Reverse Output Current 100 TJ = 25C, unless otherwise noted. 10 VOUT = 5V COUT = 10F IL = 500mA 1 0.1 0.01 CFF = 0pF CFF = 100pF CFF = 1nF CFF = 10nF 10 100 1k 10k FREQUENCY (Hz) 100k 3055 G27 Rev. B 8 For more information www.analog.com LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS CREF/BYP = 0pF 80 70 CREF/BYP = 100pF 60 50 40 CREF/BYP = 1nF 30 20 CREF/BYP = 10nF 10 0 0.01 0.1 1 10 100 LOAD CURRENT (mA) 1000 160 150 f = 10Hz TO 100kHz VOUT = 5V 140 COUT = 10F 130 120 VOUT = 3.3V 110 100 90 80 VOUT = 2.5V 70 60 50 40 VOUT = 1.2V 30 20 VOUT = 0.6V 10 0 0.01 0.1 1 10 100 1000 LOAD CURRENT (mA) RMS Output Noise vs Feedforward Capacitor (CFF) 120 110 OUTPUT NOISE VOLTAGE (VRMS) 110 f = 10Hz TO 100kHz 100 C OUT = 10F 90 RMS Output Noise vs Load Current, CREF/BYP = 10nF, CFF = 0 OUTPUT NOISE VOLTAGE (VRMS) OUTPUT NOISE VOLTAGE (VRMS) RMS Output Noise vs CREF/BYP, VOUT = 0.6V, CFF = 0 TJ = 25C, unless otherwise noted. VOUT = 5V 100 VOUT = 3.3V 90 80 f = 10Hz TO 100kHz CREF/BYP = 10nF COUT = 10F IFB-DIVIDER = 10A ILOAD = 500mA VOUT = 2.5V 70 60 50 40 30 VOUT = 1.2V 20 10 VOUT = 0.6V 0 0.01 0.1 1 FEEDFORWARD CAPACITOR, CFF (nF) 3055 G30 3055 G29 3055 G28 Start-Up Time vs REF/BYP Capacitor 10 10Hz to 100kHz Output Noise CREF/BYP = 10nF, CFF = 0 10Hz to 100kHz Output Noise CREF/BYP = 10nF, CFF = 10nF 60 START-UP TIME (ms) 50 40 VOUT 200V/DIV VOUT 200V/DIV 30 20 COUT = 10F ILOAD = 500mA VOUT = 5V 10 0 0 1ms/DIV 3055 G32 COUT = 10F ILOAD = 500mA VOUT = 5V 1ms/DIV 3055 G33 10 20 30 40 50 60 70 80 90 100 REF/BYP CAPACITOR (nF) 3055 G31 5V Transient Response CFF = 0, IOUT = 50mA to 500mA VOUT 200mV/DIV 5V Transient Response CFF = 10nF, IOUT = 50mA to 500mA VOUT 100mV/DIV Transient Response (Load Dump) VOUT 20mV/DIV 45V IOUT 500mA/DIV VIN 10V/DIV IOUT 500mA/DIV VIN = 6V 100s/DIV COUT = 10F IFB-DIVIDER = 10A VOUT = 5V 3055 G34 12V VIN = 6V 20s/DIV COUT = 10F IFB-DIVIDER = 10A VOUT = 5V 3055 G35 VOUT = 5V IOUT = 100mA COUT = 10F 1ms/DIV 3055 G36 Rev. B For more information www.analog.com 9 LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS SHDN Transient Response CREF/BYP = 0 TJ = 25C, unless otherwise noted. SHDN Transient Response CREF/BYP = 10nF Precision Current Limit, RIMAX = 1.5k OUT 5V/DIV IL=500mA OUT 5V/DIV IL = 500mA REF/BYP 500mV/DIV REF/BYP 500mV/DIV SHDN 2V/DIV SHDN 2V/DIV 2ms/DIV 2ms/DIV 3055 G37 3055 G38 CURRENT LIMIT FAULT THRESHOLD (mA) 220 VOUT(NOMINAL) = 5V 216 212 208 204 VIN = 10V 200 VIN = 5.6V 196 192 188 184 180 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 G39 Precision Current Limit, RIMAX = 604 IOUT/IMON Ratio, IOUT = 500mA 550 530 520 VIN = 7V 500 490 VIN = 5.6V 480 470 460 530 520 510 500 490 TJ = 150C TJ = 125C TJ = 25C TJ = -40C TJ = -55C 480 470 460 450 450 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) VOUT = 5V VIN = 5.6V 540 0 1 3 2 VIMON (V) 4 IOUT/IMON Current Ratio 500 490 TJ = 150C TJ = 125C TJ = 25C TJ = -40C TJ = -55C 450 0 50 100 150 200 250 300 350 400 450 500 IOUT (mA) IOUT/IMON CURRENT RATIO (mA/mA) IOUT/IMON CURRENT RATIO (mA/mA) 510 460 510 500 490 TJ = 150C TJ = 125C TJ = 25C TJ = -40C TJ = -55C 480 470 460 0 1 3 2 VIMON (V) 4 VOUT = 5V 540 VIMON = 3.5V I = 10mA at VIN = 15V 530 OUT IOUT = 250mA at VIN = 9V 520 IOUT = 500mA at VIN = 7V 510 500 490 TJ = 150C TJ = 125C TJ = 25C TJ = -40C TJ = -55C 480 470 460 450 0 5 3055 G41 Minimum Output Current Threshold, RIMIN = 1.2M 550 520 470 520 IOUT/IMON Current Ratio 550 480 530 3055 G41 3055 G40 VOUT = 5V 540 VIN = 5.6V VIMON = 3.5V 530 VOUT = 5V VIN = 7V 540 450 5 50 100 150 200 250 300 350 400 450 500 IOUT (mA) 3055 G43 3055 G44 MINIMUM OUTPUT CURRENT THRESHOLD (mA) 510 IOUT/IMON Ratio, IOUT = 500mA 550 IOUT/IMON CURRENT RATIO (mA/mA) VOUT(NOMINAL) = 5V 540 IOUT/IMON CURRENT RATIO (mA/mA) CURRENT LIMIT FAULT THRESHOLD (mA) 550 1.10 1.08 1.06 1.04 1.02 IMIN RISING THRESHOLD 1.00 0.98 IMIN FALLING THRESHOLD 0.96 0.94 0.92 0.90 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 G45 Rev. B 10 For more information www.analog.com LT3055 Series TYPICAL PERFORMANCE CHARACTERISTICS TJ = 25C, unless otherwise noted. TEMP Output Voltage vs Temperature 11.0 1.75 10.8 1.50 10.6 1.25 TEMP PIN VOLTAGE (V) MINIMUM OUTPUT CURRENT THRESHOLD (mA) Minimum Output Current Threshold RIMIN = 120k 10.4 10.2 IMIN RISING THRESHOLD 10.0 9.8 IMIN FALLING THRESHOLD 9.6 1.00 0.75 0.50 0.25 0 9.4 -0.25 9.2 -0.50 9.0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) -0.75 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 G46 3055 G47 TEMP Pin Minimum Input Voltage 2.2 MINIMUM INPUT VOLTAGE (V) 2.0 TEMP Pin Minimum Input Voltage 1.8 1.6 1.4 1.2 1.0 0.8 0.6 OUT Pin Minimum Input Voltage VOUT = 0.6V IL=500mA 0.4 0.2 0 25 100 75 50 TEMPERATURE (C) 125 0 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 150 3055 G49 3055 G48 PWRGD Threshold Voltage 590 580 570 ADJ PIN VOLTAGE (mV) TEMP PIN ERROR (C) TEMP Pin Error 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 560 550 540 530 ADJ PIN RISING THRESHOLD ADJ PIN FALLING THRESHOLD 520 510 500 490 -75 -50 -25 0 25 50 75 100 125 150 175 TEMPERATURE (C) 3055 G50 Rev. B For more information www.analog.com 11 LT3055 Series PIN FUNCTIONS IN (Pins 1, 2): Input. These pins supply power to the device. The LT3055 requires a local IN bypass capacitor if it is located more than six inches from the main input filter capacitor. In general, battery output impedance rises with frequency, so adding a bypass capacitor in batterypowered circuits is advisable. A bypass capacitor in the range of 1F to 10F is sufficient. See Input Capacitance and Stability in the Applications Information section for more information. TEMP (Pin 7): Temperature Output. The TEMP pin outputs a voltage proportional to the average junction temperature. The pin voltage is 250mV for 25C and has a slope of 10mV/C. The TEMP pin output impedance is approximately 1500. The TEMP pin is stable with no bypass capacitor or with a bypass capacitor with a value between 100pF and 1nF. A 100pF capacitor is recommended to improve TEMP pin power supply rejection. If not used, leave TEMP unconnected. The LT3055 regulator withstands reverse voltages on the IN pins with respect to ground and the OUT pins. In the case of a reverse input, which can happen if a battery is plugged in backwards, the device acts as if there is a diode in series with its input. No reverse current flows into the regulator and no reverse voltage appears at the load. The device protects both itself and the load. IMON (Pin 8): Output Current Monitor. This pin is the collector of a PNP current mirror that outputs 1/500th of the power PNP current. The IMON pin requires a small (22nF minimum) decoupling capacitor. In applications where the IMON pin is used in an external feedback network (current sharing, cable drop compensation, etc.) smaller bypass capacitance values may be used to ensure stability of the external feedback network. If not used, tie IMON to GND. SHDN (Pin 3): Shutdown. Pulling the SHDN pin low puts the LT3055 into a low power state and turns the output off. Drive the SHDN pin with either logic or an open-collector/ drain with a pull-up resistor. The resistor supplies the pull-up current to the open-collector/drain logic, normally several microamperes, and the SHDN pin current, typically less than 2A. If unused, connect the SHDN pin to IN. The LT3055 does not function if the SHDN pin is not connected. FAULT1 (Pin 4), FAULT2 (Pin 5): Fault Indicator Pins. FAULT1 and FAULT2 are open-collector logic pins. If the output current drops below the minimum current threshold, FAULT1 asserts low. If the output current exceeds the current limit threshold, FAULT2 asserts low. If the LT3055 enters thermal shutdown, both FAULT1 and FAULT2 assert low. The FAULT1 and FAULT2 pins are capable of sinking 50A. There is no internal pull-up resistor; an external pull-up resistor must be used. PWRGD (Pin 6): Power Good Pin. The PWRGD pin is an open-collector output that actively pulls low if the output is less than 90% of the nominal output value. The PWRGD pin is capable of sinking 50A. There is no internal pull-up resistor, an external pull-up resistor must be used. IMIN (Pin 9): Minimum Output Current Programming Pin. This pin is the collector of a PNP current mirror that outputs 1/2000th of the power PNP load current. This pin is also the input to the minimum output current fault comparator. Connecting a resistor between IMIN and GND sets the minimum output current fault threshold. For detailed information on how to set the IMIN pin resistor value, please see the Operation section. A small external decoupling capacitor (10nF minimum) is required to improve IMIN PSRR. If minimum output current programming is not required, float the IMIN pin (unconnected). IMAX (Pin 10): Precision Current Limit Programming Pin. This pin is the collector of a current mirror PNP that is 1/500th the size of the output power PNP. This pin is also the input to the current limit amplifier. Current limit threshold is set by connecting a resistor between the IMAX pin and GND. For detailed information on how to set the IMAX pin resistor value, please see the Operation section. The IMAX pin requires a 22nF decoupling capacitor to ground. If not used, tie IMAX to GND. Rev. B 12 For more information www.analog.com LT3055 Series PIN FUNCTIONS REF/BYP (Pin 11): Bypass/Soft-Start. Connecting a capacitor from this pin to GND bypasses the LT3055's reference noise and soft starts the reference. A 10nF bypass capacitor typically reduces output voltage noise to 25VRMS in a 10Hz to 100kHz bandwidth. Soft-start time is directly proportional to BYP/SS capacitor value. If the LT3055 is placed in shutdown, BYP/SS is actively pulled low by an internal device to reset soft-start. If low noise or soft-start performance is not required, this pin must be left floating (unconnected). Do not drive this pin with any active circuitry. Because the REF/BYP pin is the reference input to the error amplifier, stray capacitance at this point should be minimized. Special attention should be given to any stray capacitances that can couple external signals onto the REF/BYP pin producing undesirable output transients or ripple. A minimum REF/BYP capacitance of 100pF is recommended. GND (LT3055: Pin 12, Pin 13, Exposed Pad Pin 17): Ground. The exposed pad of the DFN and MSOP packages is an electrical connection to GND. To ensure proper electrical and thermal performance, solder Pin 17 to the PCB ground and tie it directly to Pins 12, 13. Connect the bottom of the output voltage setting resistor divider directly to GND (Pin 12) for optimum load regulation. GND (LT3055-3.3, LT3055-5: Pin 12, Exposed Pad Pin 17): Ground. The exposed pad of the DFN and MSOP packages is an electrical connection to GND. To ensure proper electrical and thermal performance, solder Pin 17 to the PCB ground and tie it directly to Pin 12. Connect the bottom of the output voltage setting resistor divider directly to GND (Pin 12) for optimum load regulation. IN OUT RP LT3055-5 + VIN + SHDN + SENSE LOAD GND RP 3055 F01 ADJ (LT3055: Pin 14): Adjust. This pin is the error amplifier's inverting terminal. The typical bias current of 16nA flows out of the pin (see the ADJ pin Bias Current vs Temperature curve in the Typical Performance Characteristics section). The ADJ pin voltage is 600mV referenced to GND. Connecting a capacitor from ADJ to OUT reduces output noise and improves transient response for output voltages greater than 600mV. See the Applications Information section for calculating the value of the feedforward capacitor. ADJ (LT3055-3.3, LT3055-5: Pin 13): Adjust. This pin is the error amplifier's inverting terminal. The typical bias current of 16nA flows out of the pin (see the ADJ pin Bias Current vs Temperature curve in the Typical Performance Characteristics section). The ADJ pin voltage is 600mV referenced to GND. Connecting a capacitor from ADJ to OUT reduces output noise and improves transient response for output voltages greater than 600mV. See the Applications Information section for calculating the value of the feedforward capacitor. SENSE (LT3055-3.3, LT3055-5: Pin 14): Sense. This pin is the top of the internal resistor divider network. SENSE should be connected directly to the load, as a Kelvin sense, for optimum load regulation and transient performance. Connecting this pin to the output pin, rather than directly to the load, can result in load regulation errors due to the current across the parasitic resistance of the PCB trace. OUT (Pins 15,16): Output. These pins supply power to the load. Stability requirements demand a minimum 3.3F ceramic output capacitor with an ESR < 1 to prevent oscillations. For output voltages less than 1.2V, a minimum 4.7F ceramic output capacitor is required. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for details on output capacitance and reverse output characteristics. Permissible output voltage range is 600mV to 40V. Figure 1. Kelvin Sense Connection Rev. B For more information www.analog.com 13 LT3055 Series BLOCK DIAGRAM IN R1 ADJ R5 30k R4 Q2 Q3 ERROR AMPLIFIER D2 CURRENT LIMIT AMPLIFIER + - IDEAL DIODE D3 SHDN QIMAX 1/500 THERMAL/ CURRENT LIMITS - + R6 QIMON 1/500 QIMIN 1/2000 D1 SENSE QPOWER 1 OUT 100k R3 IMAX IMON IMIN COMPARATOR + - 100k R2 + - 600mV REFERENCE IMIN FAULT1 IMIN QFAULT1 U1 THERMAL LIMIT FAULT2 CURRENT LIMITS QFAULT2 U2 THERMAL LIMIT - + + - PWRGD QPWRGD 540mV REFERENCE GND REF/BYP 3055 F02 Figure 2. OPERATION IMON Pin Operation (Current Monitor) The IMON pin is the collector of a PNP which mirrors the LT3055 output PNP at a ratio of 1:500 (see Block Diagram). There is additional circuitry which compensates for early voltage variation by regulating the collector of the IMON mirror PNP at the output voltage. This circuitry is active for VIMON (VOUT - 500mV). For the range where the early voltage compensation circuit is active, calculate the output current from the simple equation: V IOUT = 500 * IMON R IMON For VIMON > (VOUT-500mV), the IMON mirror PNP collector is VIMON + VDSSAT (500mV at 500mA). Early voltage effects increase the IOUT to IMON ratio as VIMON increases. Rev. B 14 For more information www.analog.com LT3055 Series OPERATION If the open-circuit detection function is not needed, the IMIN pin must be left floating (unconnected). A small decoupling capacitor (10nF minimum) from IMIN to GND is required to improve IMIN pin power supply rejection and to prevent FAULT1 pin glitches. See the Typical Performance Characteristics section for additional information. 525 IOUT:IIMON RATIO (mA/mA) 520 515 EARLY VOLTAGE EFFECTS 510 505 500 495 490 485 480 475 IMAX Pin Operation VIN = 6V VIMON = 2.5V IOUT = 500mA (IN CURRENT LIMIT) 1 0 3 2 VOUT (V) The IMAX pin is the collector of a PNP which mirrors the LT3055 output PNP at a ratio of 1:500 (see Block Diagram). The IMAX pin is also the input to the precision current limit amplifier. If the output load increases to the point where it causes the IMAX pin voltage to reach 0.6V, the current limit amplifier takes control of the output regulation so that the IMAX pin regulates at 0.6V, regardless of the output voltage. The current limit threshold (ILIMIT) is set by connecting a resistor (RIMAX) from IMAX to GND: 5 4 3055 F03a Figure 3a. IOUT:IIMON Ratio vs VOUT 525 VIN = 6V VOUT = 5V IOUT = 500mA IOUT:IIMON RATIO (mA/mA) 520 515 IMON MIRROR PNP SATURATING 510 505 R IMAX = 500 * 500 EARLY VOLTAGE EFFECTS 495 490 480 0 1 2 3 VIMON (V) 4 5 6 3055 F03b Figure 3. (b) IOUT:IIMON Ratio vs VIMON In addition, if VIN - VIMON < 1V, the IMON mirror PNP saturates at high loads, causing the IOUT-to-IMON ratio to increase quickly. The IMON mirror ratio is affected by power dissipation in the LT3055; it increases at a rate of approximately 0.5 percent per watt. Open-Circuit Detection (IMIN Pin) The IMIN pin is the collector of a PNP which mirrors the LT3055 output PNP at a ratio of 1:2000 (see Block Diagram). The IMIN fault comparator asserts the FAULT1 pin if the IMIN pin voltage is below 0.6V. This low output current fault threshold voltage (IOPEN) is set by attaching a resistor from IMIN to GND: R IMIN = 2000 * 0.6V IOPEN ILIMIT In cases where the IN to OUT differential voltage exceeds 10V, fold-back current limit lowers the internal current limit level, possibly causing it to override the external programmable current limit. See the Internal Current Limit vs VIN-VOUT graph in the Typical Performance Characteristics section. 485 475 0.6V The IMAX pin requires a 22nF decoupling capacitor. If the external programmable current limit is not needed, the IMAX pin must be connected to GND. The IMAX threshold is affected by power dissipation in the LT3055; it increases at a rate of approximately 0.5 percent per watt. FAULT Pins Operation The FAULT1 and FAULT2 pins are open-drain high voltage NMOS digital outputs. The FAULT1 pin asserts during a low current fault (open circuit). The FAULT2 pin asserts during a current limit fault (internal or externally programmed). Both FAULT1 and FAULT2 assert during thermal shutdown. There is no internal pull-up on the FAULT pins; an external pull-up resistor is required. The FAULT pins sink up to 50A of pull-down current. Off state logic may be as high as 45V, regardless of the input voltage used. Rev. B For more information www.analog.com 15 LT3055 Series OPERATION Table 1. FAULT Pins Truth Table STATUS Open Circuit Current Limit Thermal Shutdown FAULT1 Low High Low FAULT2 High Low Low Depending on the IMIN capacitance, BYP capacitance, and OUT capacitance, the FAULT pins may assert during start-up. Consideration should be given to masking the fault signals during start-up. The FAULT pin circuitry is inactive (not asserted) during shutdown and when the OUT pin is pulled above IN pin. PWRGD Pin Operation The PWRGD pin is an open-drain high voltage NMOS digital output. The PWRGD pin deasserts and becomes high impedance if the output rises above 90% of its nominal value. If the output falls below 89% of its nominal value for more than 25s, the PWRGD pin asserts low. The PWRGD comparator has 1% hysteresis and 25s of deglitching. The PWRGD comparator has a dedicated reference that does not soft-start when a capacitor is added to the REF/BYP pin. The use of a feed-forward capacitor, CFF, as shown in Figure 5, can result in the ADJ pin being pulled artificially high during start- up transients, which causes the PWRGD flag to assert early. To avoid this problem, ensure that the REF/ BYP capacitor is significantly larger than the feed-forward capacitor, causing REF/BYP time constant to dominate over the time constant of the resistor divider network. Operation in Dropout There may be some degradation of the current mirror accuracy for output currents less than 50mA when operating in dropout. APPLICATIONS INFORMATION The LT3055 is a micropower, low noise and low dropout voltage, 500mA linear regulator with micropower shutdown, programmable current limit, and diagnostic functions. The device supplies up to 500mA at a typical dropout voltage of 350mV and operates over a 1.6V to 45V input range. A single external capacitor provides low noise reference performance and output soft-start functionality. For example, connecting a 10nF capacitor from the REF/BYP pin to GND lowers output noise to 25VRMS over a 10Hz to 100kHz bandwidth. This capacitor also soft starts the reference and prevents output voltage overshoot at turn-on. The LT3055's quiescent current is merely 65A but provides fast transient response with a minimum low ESR 3.3F ceramic output capacitor. In shutdown, quiescent current is less than 1A and the reference soft-start capacitor is reset. The LT3055 optimizes stability and transient response with low ESR, ceramic output capacitors. The regulator does not require the addition of ESR as is common with other regulators. The LT3055 typically provides 0.1% line regulation and 0.1% load regulation. Internal protection circuitry includes reverse battery protection, reverse output protection, reverse current protection, current limit with fold-back and thermal shutdown. This "bullet-proof" protection set makes it ideal for use in battery-powered, automotive and industrial systems. In battery backup applications where the output is held up by a backup battery and the input is pulled to ground, the LT3055 acts like it has a diode in series with its output and prevents reverse current flow. Rev. B 16 For more information www.analog.com LT3055 Series APPLICATIONS INFORMATION Adjustable Operation + The adjustable LT3055 has an output voltage range of 0.6V to 40V. The output voltage is set by the ratio of two external resistors, as shown in Figure 4. The device servos the output to maintain the ADJ pin voltage at 0.6V referenced to ground. The current in R1 is then equal to 0.6V/R1, and the current in R2 is the current in R1 minus the ADJ pin bias current. The ADJ pin bias current, 16nA at 25C, flows from the ADJ pin through R1 to GND. Calculate the output voltage using the formula in Figure 4. The value of R1 should be no greater than 62k to provide a minimum 10A load current so that output voltage errors, caused by the ADJ pin bias current, are minimized. Note that in shutdown, the output is turned off and the divider current is zero. Curves of ADJ Pin Voltage vs Temperature and ADJ Pin Bias Current vs Temperature appear in the Typical Performance Characteristics section. The LT3055 is tested and specified with the ADJ pin tied to the OUT pin, yielding VOUT = 0.6V. Specifications for output voltages greater than 0.6V are proportional to the ratio of the desired output voltage to 0.6V: VOUT/0.6V. For example, load regulation for an output current change of 1mA to 500mA is 0.5mV (typical) at VOUT = 0.6V. At VOUT = 12V, load regulation is: 12V 0.6V * ( 0.5mV) = 10mV Table 2 shows 1% resistor divider values for some common output voltages with a resistor divider current of 10A. Table 2. Output Voltage Resistor Divider Values VOUT (V) 1.2 1.5 1.8 2.5 3 3.3 5 R1 (k) 60.4 59 59 60.4 59 61.9 59 R2 (k) 60.4 88.7 118 191 237 280 432 IN VIN VOUT OUT LT3055 SHDN R2 ADJ GND R1 3055 F04 R2 VOUT = 0.6V 1+ - (IADJ *R2) R1 VADJ = 0.6V IADJ = 16nA AT 25C OUTPUT RANGE = 0.6V TO 40V Figure 4. Adjustable Operation Bypass Capacitance and Output Voltage Noise The LT3055 regulator provides low output voltage noise over a 10Hz to 100kHz bandwidth while operating at full load with the addition of a bypass capacitor (CREF/BYP) from the REF/BYP pin to GND. A high quality low leakage capacitor is recommended. This capacitor bypasses the internal reference of the regulator, providing a low frequency noise pole for the internal reference. With the use of 10nF for CREF/BYP, output voltage noise decreases to as low as 25VRMS when the output voltage is set for 0.6V. For higher output voltages (generated by using a feedback resistor divider), the output voltage noise gains up proportionately when using CREF/BYP. To lower the higher output voltage noise, include a feedforward capacitor (CFF) from VOUT to the ADJ pin. A high quality, low leakage capacitor is recommended. This capacitor bypasses the error amplifier of the regulator, providing an additional low frequency noise pole. With the use of 10nF for both CFF and CREF/BYP, output voltage noise decreases to 25VRMS when the output voltage is set to 5V by a 10A feedback resistor divider. If the current in the feedback resistor divider is doubled, CFF must also be doubled to achieve equivalent noise performance. Higher values of output voltage noise can occur if care is not exercised with regard to circuit layout and testing. Crosstalk from nearby traces induces unwanted noise onto the LT3055's output. Power supply ripple rejection Rev. B For more information www.analog.com 17 LT3055 Series APPLICATIONS INFORMATION must also be considered. The LT3055 regulator does not have unlimited power supply rejection and passes a small portion of the input noise through to the output. Start-up time is also affected by the presence of a feedforward capacitor. Start-up time is directly proportional to the size of the feedforward capacitor and the output voltage, and is inversely proportional to the feedback resistor divider current, slowing to 15ms with a 10nF feedforward capacitor and a 10F output capacitor for an output voltage set to 5V by a 10A feedback resistor divider. Output Capacitance and Transient Response The LT3055 regulator is stable with a wide range of output capacitors. The ESR of the output capacitor affects stability, most notably with small capacitors. Use a minimum output capacitor of 3.3F with an ESR of 1 or less to prevent oscillations. If a feedforward capacitor is used with output voltages set for greater than 24V, use a minimum output capacitor of 10F. The LT3055 is a micropower device and output load transient response is a function of output capacitance. Larger values of output capacitance decrease the peak deviations and provide improved transient response for larger load current changes. Bypass capacitors, used to decouple individual components powered by the LT3055, increase the effective output capacitor value. For applications with large load current transients, a low ESR ceramic IN OUT LT3055 SHDN ADJ GND REF/BYP R2 CFF VOUT COUT R1 CREF/BYP 3055 F05 CFF 10nF * IFB _ DIVIDER 10A ( IFB _ DIVIDER = ) VOUT R1+R2 Figure 5. Feedforward Capacitor for Fast Transient Response 0 VOUT 100mV/DIV During start-up, the internal reference soft-starts when a bypass capacitor is present. Regulator start-up time is directly proportional to the size of the bypass capacitor (See Start-Up Time vs REF/BYP Capacitor in the Typical Performance Characteristics section). The reference bypass capacitor is actively pulled low during shutdown to reset the internal reference. VIN FEEDFORWARD CAPACITOR, CFF Using a feedforward capacitor (CFF) from VOUT to the ADJ pin has the added benefit of improving transient response for output voltages greater than 0.6V. With no feedforward capacitor, the settling time increases as the output voltage increases above 0.6V. Use the equation in Figure 5 to determine the minimum value of CFF to achieve a transient response that is similar to the 0.6V output voltage performance regardless of the chosen output voltage (See Figure 6 and Transient Response in the Typical Performance Characteristics section). + 100pF 1nF 10nF LOAD CURRENT 500mA/DIV 100s/DIV VOUT = 5V COUT = 10F IFB-DIVIDER = 10A 3055 F06 Figure 6. Transient Response vs Feedforward Capacitor capacitor in parallel with a bulk tantalum capacitor often provides an optimally damped response. Give extra consideration to the use of ceramic capacitors. Manufacturers make ceramic capacitors with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics provide high C-V products in a small package at low cost, but exhibit strong voltage and temperature coefficients, as shown in Figure 7 and Figure 8. When used with a 5V regulator, a 16V 10F Y5V capacitor can exhibit an effective value as low as 1F to 2F for the DC bias voltage applied, and over the operating temperature range. The X5R and X7R dielectrics yield much more stable characteristics and are more suitable for use as the output capacitor. The X7R type works over a wider temperature range and has better temperature stability, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R Rev. B 18 For more information www.analog.com LT3055 Series APPLICATIONS INFORMATION 20 0 CHANGE IN VALUE (%) of noise. A ceramic capacitor produced the trace in Figure 9 in response to light tapping from a pencil. Similar vibration induced behavior can masquerade as increased output voltage noise. BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F X5R -20 -40 -60 Y5V -80 -100 VOUT 1mV/DIV 0 2 4 14 8 6 10 12 DC BIAS VOLTAGE (V) 16 3055 F07 Figure 7. Ceramic Capacitor DC Bias Characteristics VOUT = 5V COUT = 10F CREF/BYP = 10nF 40 CHANGE IN VALUE (%) 20 -20 Stability and Input Capacitance -40 Y5V -60 -80 3055 F09 Figure 9. Noise Resulting from Tapping On a Ceramic Capacitor X5R 0 10ms/DIV BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10F -100 -50 -25 50 25 75 0 TEMPERATURE (C) 100 125 3055 F08 Figure 8. Ceramic Capacitor Temperature Characteristics and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric accelerometer or microphone works. For a ceramic capacitor, the stress is induced by vibrations in the system or thermal transients. The resulting voltages produced cause appreciable amounts Low ESR, ceramic input bypass capacitors are acceptable for applications without long input leads. However, applications connecting a power supply to an LT3055 circuit's IN and GND pins with long input wires combined with a low ESR, ceramic input capacitors are prone to voltage spikes, reliability concerns and application-specific board oscillations. The input wire inductance found in many battery-powered applications, combined with the low ESR ceramic input capacitor, forms a high QLC resonant tank circuit. In some instances this resonant frequency beats against the output current dependent LDO bandwidth and interferes with proper operation. Simple circuit modifications/solutions are then required. This behavior is not indicative of LT3055 instability, but is a common ceramic input bypass capacitor application issue. The self-inductance, or isolated inductance, of a wire is directly proportional to its length. Wire diameter is not a major factor on its self-inductance. For example, the self-inductance of a 2-AWG isolated wire (diameter = 0.26") is about half the self-inductance of a 30-AWG wire (diameter = 0.01"). One foot of 30-AWG wire has approximately 465nH of self-inductance. Rev. B For more information www.analog.com 19 LT3055 Series APPLICATIONS INFORMATION Two methods can reduce wire self-inductance. One method divides the current flowing towards the LT3055 between two parallel conductors. In this case, the farther apart the wires are from each other, the more the self-inductance is reduced; up to a 50% reduction when placed a few inches apart. Splitting the wires connects two equal inductors in parallel, but placing them in close proximity creates mutual inductance adding to the self-inductance. The second and most effective way to reduce overall inductance is to place both forward and return current conductors (the input and GND wires) in very close proximity. Two 30-AWG wires separated by only 0.02", used as forward- and returncurrent conductors, reduce the overall self-inductance to approximately one-fifth that of a single isolated wire. as 0.1 to 0.5 suffices. This impedance dampens the LC tank circuit at the expense of dropout voltage. A better alternative is to use higher ESR tantalum or electrolytic capacitors at the LT3055 input in place of ceramic capacitors. If a battery, mounted in close proximity, powers the LT3055, a 10F input capacitor suffices for stability. However, if a distant supply powers the LT3055, use a larger value input capacitor. Use a rough guideline of 1F (in addition to the 10F minimum) per 8 inches of wire length. The minimum input capacitance needed to stabilize the application also varies with power supply output impedance variations. Placing additional capacitance on the LT3055's output also helps. However, this requires an order of magnitude more capacitance in comparison with additional LT3055 input bypassing. Series resistance between the supply and the LT3055 input also helps stabilize the application; as little In Figure 10, this is implemented using inexpensive 2N3904 NPN devices. Precision 1k resistors provide 1V emitter degeneration at full load to guarantee good current mirror matching. The feedback resistors of the slave LT3055 are split into sections to ensure adequate headroom for the slave 2N3904. A 1nF capacitor added to the IMON pin of the slave device frequency compensates the feedback loop. REF + - + - This circuit architecture is scalable to as many LT3055s as are needed simply by extending the current mirror and adding slave LT3055 devices. 600mV 500x 1x IMON REF + - + - 600mV VOUT 5V 1A OUT ADJ 440k 500x 10F 60k LT3055 (SLAVE) IN 10F Higher output current is obtained by paralleling multiple LT3055 together. Tie the individual OUT pins together and tie the individual IN pins together. An external NPN or NMOS current mirror is used in combination with the LT3055 IMON pins to create a simple amplifier. This amplifier injects current into or out of the feedback divider of the slave LT3055 in order to ensure that the IMON currents from each LT3055 are equal. LT3055 (MASTER) IN VIN 5.6V Paralleling Devices 1x IMON 1nF OUT ADJ 300k 140k 60k 2N3904 1k 1k 3055 F10 Figure 10. Parallel Devices 20 For more information www.analog.com Rev. B LT3055 Series APPLICATIONS INFORMATION Spreading the devices on the PC board also spreads the heat. Series input resistors can further spread the heat if the input-to-output differential is high. Overload Recovery Like many IC power regulators, the LT3055 has safe operating area protection. The safe area protection decreases current limit as input-to-output voltage increases, and keeps the power transistor inside a safe operating region for all values of input-to-output voltage. The LT3055 provides some output current at all values of input-to-output voltage up to the device breakdown. When power is first applied, the input voltage rises and the output follows the input; allowing the regulator to start-up into very heavy loads. During start-up, as the input voltage is rising, the input-to-output voltage differential is small, allowing the regulator to supply large output currents. With a high input voltage, a problem can occur wherein the removal of an output short will not allow the output to recover. Other regulators, such as the LT1083/LT1084/ LT1085 family and LT1764A also exhibit this phenomenon, so it is not unique to the LT3055. The problem occurs with a heavy output load when the input voltage is high and the output voltage is low. Common situations are immediately after the removal of a short circuit or if the shutdown pin is pulled high after the input voltage is already turned on. The load line intersects the output current curve at two points. If this happens, there are two stable output operating points for the regulator. With this double intersection, the input power supply needs to be cycled down to zero and back up again to recover the output. Thermal Considerations The LT3055's maximum rated junction temperature of 125C (E-, I-grades) or 150C (MP-, H-grades) limits its power handling capability. Two components comprise the power dissipated by the device: GND pin current is determined using the GND Pin Current curves in the Typical Performance Characteristics section. Power dissipation equals the sum of the two components listed above. The LT3055 regulator has internal thermal limiting that protects the device during overload conditions. For continuous normal conditions, do not exceed the maximum junction temperature of 125C (E-, I-grades) or 150C (MP-, H-grades). Carefully consider all sources of thermal resistance from junction-to-ambient including other heat sources mounted in proximity to the LT3055. The undersides of the LT3055 DFN and MSE packages have exposed metal from the lead frame to the die attachment. These packages allow heat to directly transfer from the die junction to the printed circuit board metal to control maximum operating junction temperature. The dual-inline pin arrangement allows metal to extend beyond the ends of the package on the topside (component side) of a PCB. Connect this metal to GND on the PCB. The multiple IN and OUT pins of the LT3055 also assist in spreading heat to the PCB. For surface mount devices, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Copper board stiffeners and plated through-holes also can spread the heat generated by power devices. Table 3 and Table 4 list thermal resistance as a function of copper area in a fixed board size. All measurements were taken in still air on a 4-layer FR-4 board with 1oz solid internal planes, and 2oz external trace planes with a total board thickness of 1.6mm. For further information on thermal resistance and using thermal information, refer to JEDEC standard JESD51, notably JESD51-12. Table 3. MSOP Measured Thermal Resistance COPPER AREA THERMAL RESISTANCE BOARD AREA (JUNCTION-TO-AMBIENT) 1. Output current multiplied by the input/output voltage difference: IOUT * (VIN - VOUT), and 2500 sq mm 2500 sq mm 2500 sq mm 35C/W 1000 sq mm 2500 sq mm 2500 sq mm 36C/W 2. GND pin current multiplied by the input voltage: 225 sq mm 2500 sq mm 2500 sq mm 37C/W 100 sq mm 2500 sq mm 2500 sq mm 39C/W IGND * VIN TOPSIDE BACKSIDE Rev. B For more information www.analog.com 21 LT3055 Series APPLICATIONS INFORMATION Table 4. DFN Measured Thermal Resistance COPPER AREA TOPSIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500 sq mm 2500 sq mm 36C/W 1000 sq mm 2500 sq mm 37C/W 225 sq mm 2500 sq mm 38C/W 100 sq mm 2500 sq mm 40C/W Calculating Junction Temperature Example: Given an output voltage of 5V, an input voltage range of 12V 5%, a maximum output current range of 75mA and a maximum ambient temperature of 85C, what is the maximum junction temperature? The power dissipated by the device equals: IOUT(MAX) * (VIN(MAX) - VOUT) + IGND * VIN(MAX) where: IOUT(MAX) = 75mA VIN(MAX) = 12.6V IGND at (IOUT = 75mA, VIN = 12V) = 3.5mA So: P = 75mA * (12.6V - 5V) + 3.5mA * 12.6V = 0.614W Using a DFN package, the thermal resistance ranges from 36C/W to 40C/W depending on the copper area. So the junction temperature rise above ambient approximately equals: limiting, the device also protects against reverse input voltages, reverse output voltages and reverse output-toinput voltages. Current limit protection and thermal overload protection protect the device against current overload conditions at the output of the device. For normal operation, do not exceed a junction temperature of 125C (E-, I-grades) or 150C (MP-, H-grades). The LT3055 IN pin withstands reverse voltages of 50V. The device limits current flow to less than 1A (typically less than 25nA) and no negative voltage appears at OUT. The device protects both itself and the load against batteries that are plugged in backwards. The LT3055 incurs no damage if its output is pulled below ground. If the input is left open circuit or grounded, the output can be pulled below ground by 50V. No current flows through the pass transistor from the output. However, current flows in (but is limited by) the feedback resistor divider that sets the output voltage. Current flows from the bottom resistor in the divider and from the ADJ pin's internal clamp through the top resistor in the divider to the external circuitry pulling OUT below ground. If the input is powered by a voltage source, the output sources current equal to its current limit capability and the LT3055 protects itself by thermal limiting. In this case, grounding the SHDN pin turns off the device and stops the output from sourcing current. 1.0 0.614W * 40C/W = 24.6C VIN = 0 0.9 TJMAX = 85C + 24.6C = 110C Protection Features 0.8 OUTPUT CURRENT (A) The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient or: 0.7 0.6 0.5 0.4 0.3 0.2 The LT3055 incorporates several protection features that make it ideal for use in battery-powered circuits. In addition to the normal protection features associated with monolithic regulators, such as current limiting and thermal 0.1 0 0 5 10 15 20 25 VOUT (V) 30 35 40 3055 F11 Figure 11. Reverse Output Current Rev. B 22 For more information www.analog.com LT3055 Series PACKAGE DESCRIPTION MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev F) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 0.102 (.112 .004) 5.10 (.201) MIN 2.845 0.102 (.112 .004) 0.889 0.127 (.035 .005) 8 1 1.651 0.102 (.065 .004) 1.651 0.102 3.20 - 3.45 (.065 .004) (.126 - .136) 0.305 0.038 (.0120 .0015) TYP 16 0.50 (.0197) BSC 4.039 0.102 (.159 .004) (NOTE 3) RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 0.12 REF DETAIL "B" CORNER TAIL IS PART OF DETAIL "B" THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE 0.280 0.076 (.011 .003) REF 16151413121110 9 DETAIL "A" 0 - 6 TYP 3.00 0.102 (.118 .004) (NOTE 4) 4.90 0.152 (.193 .006) GAUGE PLANE 0.53 0.152 (.021 .006) DETAIL "A" 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 - 0.27 (.007 - .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD SHALL NOT EXCEED 0.254mm (.010") PER SIDE. 0.86 (.034) REF 0.1016 0.0508 (.004 .002) MSOP (MSE16) 0213 REV F Rev. B For more information www.analog.com 23 LT3055 Series PACKAGE DESCRIPTION DE Package 16-Lead Plastic DFN (4mm x 3mm) (Reference LTC DWG # 05-08-1732 Rev O) 0.70 0.05 3.30 0.05 3.60 0.05 2.20 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 0.10 (2 SIDES) R = 0.05 TYP 9 R = 0.115 TYP 0.40 0.10 16 3.30 0.10 3.00 0.10 (2 SIDES) 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 x 45 CHAMFER PIN 1 TOP MARK (SEE NOTE 6) (DE16) DFN 0806 REV O 8 0.200 REF 1 0.23 0.05 0.45 BSC 0.75 0.05 3.15 REF 0.00 - 0.05 BOTTOM VIEW--EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. B 24 For more information www.analog.com LT3055 Series REVISION HISTORY REV DATE DESCRIPTION A 6/14 Modified Minimum VIN to 1.8V Added 3.3V and 5V options, related specs, Typical Performance Characteristics and Pin Functions B 10/18 PAGE NUMBER 1 Throughout Added specification for absolute maximum SENSE pin voltage 2 Modified Pinouts to accommodate new fixed voltage options 2 Modified Note 7 5 Modified PWRGD applications section 16 Changed Typical Minimum Input Voltage from 1.8V to 1.6V 1, 4, 16, 26 Added Note 17 to Electrical Characteristics regarding Minimum Input Voltage 4, 5 Added new Typical Performance Curve TEMP Pin Minimum Input Voltage 11 Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications more by information www.analog.com subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. 25 LT3055 Series TYPICAL APPLICATION Cable Drop Compensation VIN 7V LT3055 IN 10F REF + - + - 600mV 1x 500x RCABLE/2 OUT IMON ADJ 100nF 10F RCABLE * 500 RCABLE/2 440k - RCABLE * 500 2N3904 1k 1k + 5V, COMPENSATED 10F FOR DROP ALONG RCABLE/2 RESISTORS - 10nF 60k 3055 TA02FF RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LT1761 100mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.8V to 20V, ThinSOTTM Package LT1762 150mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.8V to 20V, MS8 Package LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.8V to 20V, SO-8 Package LT1962 300mA, Low Noise LDO 270mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.8V to 20V, MS8 Package LT1964 200mA, Low Noise, Negative LDO 340mV Dropout Voltage, Low Noise: 30VRMS, VIN: -1.8V to -20V, ThinSOT Package LT1965 1.1A, Low Noise, Low Dropout Linear Regulator 290mV Dropout Voltage, Low Noise: 40VRMS, VIN: 1.8V to 20V, VOUT: 1.2V to 19.5V, Stable with Ceramic Capacitors, TO-220, DDPak, MSOP and 3mm x 3mm DFN Packages LT3008 20mA, 45V, 3A IQ Micropower LDO 300mV Dropout Voltage, Low IQ = 3A, VIN: 2.0V to 45V, VOUT: 0.6V to 39.5V, ThinSOT and 2mm x 2mm DFN-6 Packages LT3009 20mA, 3A IQ Micropower LDO 280mV Dropout Voltage, Low IQ = 3A, VIN: 1.6V to 20V, 2mm x 2mm DFN-6 and SC-70 Packages LT3010 50mA, High Voltage, Micropower LDO VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 30A, ISD < 1A, Low Noise: <100VRMSP-P, Stable with 1F Output Capacitor, Exposed MS8 Package LT3011 50mA, High Voltage, Micropower LDO with PWRGD VIN: 3V to 80V, VOUT: 1.275V to 60V, VDO = 0.3V, IQ = 46A, ISD < 1A, Low Noise: <100VRMS, PowerGood, Stable with 1F Output Capacitor, 3mm x 3mm DFN-10 and Exposed MS12E Packages LT3012 250mA, 4V to 80V, Low Dropout Micropower Linear Regulator VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 40A, ISD < 1A, TSSOP-16E and 4mm x 3mm DFN-12 Packages LT3013 250mA, 4V to 80V, Low Dropout Micropower Linear Regulator with PWRGD VIN: 4V to 80V, VOUT: 1.24V to 60V, VDO = 0.4V, IQ = 65A, ISD < 1A, PowerGood Feature, TSSOP-16E and 4mm x 3mm DFN-12 Packages LT3014/LT3014HV 20mA, 3V to 80V, Low Dropout Micropower Linear Regulator VIN: 3V to 80V (100V for 2ms, LT3014HV Version), VOUT: 1.22V to 60V, VDO = 0.35V, IQ = 7A, ISD < 1A, ThinSOT and 3mm x 3mm DFN-8 Packages LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply 0peration), Low Noise: 40VRMS, VIN: 1.2V to 36V, VOUT: 0V to 35.7V, Current-Based Reference with 1-Resistor VOUT Set, Directly Parallelable (No Op Amp Required), Stable with Ceramic Capacitors, TO-220, SOT-223, MSOP and 3mm x 3mm DFN Packages, LT3080-1 Version Has Integrated Internal Ballast Resistor LT3050 100mA LDO with Diagnostics and Precision Current Limit 340mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.6V to 45V, DFN and MSOP Packages LT3060 100mA, Low Noise LDO with Soft-Start 300mV Dropout Voltage, Low Noise: 20VRMS, VIN: 1.6V to 45V, DFN Package Rev. B 26 10/18 For more information www.analog.com www.analog.com ANALOG DEVICES, INC. 2013-2018