DATA SHEET 2G bits DDR3L SDRAM EDJ2104EDBG (512M words x 4 bits) EDJ2108EDBG (256M words x 8 bits) Specifications Features * Density: 2G bits * Organization 64M words x 4 bits x 8 banks (EDJ2104EDBG) 32M words x 8 bits x 8 banks (EDJ2108EDBG) * Package 78-ball FBGA Lead-free (RoHS compliant) and Halogen-free * Power supply: 1.35V (typ.) VDD, VDDQ = 1.283V to 1.45V Backward compatible for VDD, VDDQ = 1.5V 0.075V * Data rate 1600Mbps/1333Mbps/1066Mbps (max.) * 1KB page size Row address: A0 to A14 Column address: A0 to A9, A11 (EDJ2104EDBG) A0 to A9 (EDJ2108EDBG) * Eight internal banks for concurrent operation * Burst lengths (BL): 8 and 4 with Burst Chop (BC) * Burst type (BT): Sequential (8, 4 with BC) Interleave (8, 4 with BC) * /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11 * /CAS Write Latency (CWL): 5, 6, 7, 8 * Precharge: auto precharge option for each burst access * Driver strength: RZQ/7, RZQ/6 (RZQ = 240) * Refresh: auto-refresh, self-refresh * Refresh cycles Average refresh period 7.8s at 0C TC +85C 3.9s at +85C < TC +95C * Operating case temperature range TC = 0C to +95C * Double-data-rate architecture: two data transfers per clock cycle * The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture * Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver * DQS is edge-aligned with data for READs; centeraligned with data for WRITEs * Differential clock inputs (CK and /CK) * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Data mask (DM) for write data * Posted /CAS by programmable additive latency for better command and data bus efficiency * On-Die Termination (ODT) for better signal quality Synchronous ODT Dynamic ODT Asynchronous ODT * Multi Purpose Register (MPR) for pre-defined pattern read out * ZQ calibration for DQ drive and ODT * Programmable Partial Array Self-Refresh (PASR) * /RESET pin for Power-up sequence and reset function * SRT range: Normal/extended * Programmable Output driver impedance control Document No. E1797E41 (Ver. 4.1) Date Published February 2012 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2011-2012 EDJ2104EDBG, EDJ2108EDBG Ordering Information Part number EDJ2104EDBG-GN-F EDJ2104EDBG-DJ-F EDJ2104EDBG-AE-F EDJ2108EDBG-GN-F EDJ2108EDBG-DJ-F EDJ2108EDBG-AE-F Die revision D Organization (words x bits) 512M x 4 Internal banks JEDEC speed bin (CL-tRCD-tRP) Package DDR3L-1600K (11-11-11) DDR3L-1333H (9-9-9) DDR3L-1066F (7-7-7) DDR3L-1600K (11-11-11) DDR3L-1333H (9-9-9) DDR3L-1066F (7-7-7) 8 256M x 8 78-ball FBGA Note: 1. Please refer to the EDJ2104BDBG, EDJ2108BDBG datasheet (E1772E) when using this device at 1.5V operation, unless stated otherwise. Part Number E D J 21 04 E D BG - GN- F Elpida Memory Environment code F: Lead Free (RoHS compliant) and Halogen Free Type D: Packaged Device Speed GN: DDR3L-1600K (11-11-11) DJ: DDR3L-1333H (9-9-9) AE: DDR3L-1066F (7-7-7) Product Family J: DDR3 Density / Bank 21: 2Gb / 8-bank Organization 04: x4 08: x8 Package BG: FBGA Power Supply E: 1.35V Die Rev. Data Sheet E1797E41 (Ver. 4.1) 2 EDJ2104EDBG, EDJ2108EDBG Pin Configurations /xxx indicates active low signal. 78-ball FBGA (x4 configuration) 2 1 78-ball FBGA (x8 configuration) 3 7 8 9 NC NC VSS VDD 1 A 2 3 7 8 9 A VSS VDD VSS B VDD NC NU/(/TDQS) VSS VDD B VSS VSSQ DQ0 DM VSSQ VDDQ VSS VSSQ C DQ0 DM/TDQS VSSQ VDDQ C VDDQ DQ2 DQS DQ1 DQ3 VSSQ D VDDQ DQ2 DQS DQ1 DQ3 VSSQ VSSQ DQ6 /DQS VDD VSS VSSQ VREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ D VSSQ NC /DQS VDD VSS VSSQ E E VREFDQ VDDQ NC NC NC VDDQ F F NC VSS /RAS CK VSS NC G ODT VDD /CAS /CK VDD VSS /RAS CK VSS NC ODT VDD /CAS /CK VDD CKE NC /CS /WE A10(AP) ZQ NC VSS BA0 BA2 NC VDD A3 A0 VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD VSS /RESET A13 A14 A8 VSS CKE H H NC /CS A10(AP) /WE ZQ NC J J VSS BA0 BA2 NC VREFCA VSS K VREFCA VSS K A3 VDD A0 A12(/BC) BA1 VDD L M NC G A12(/BC) BA1 VDD L VSS A5 A2 A1 A4 VSS VDD A7 A9 A11 A6 VDD M N N VSS /RESET A13 A14 A8 VSS (Top view) Pin name (Top view) Function Pin name Address inputs A10 (AP): Auto precharge A12(/BC): Burst chop /RESET* Bank select VDD Supply voltage for internal circuit DQ0 to DQ7 Data input/output VSS Ground for internal circuit DQS, /DQS Differential data strobe VDDQ Supply voltage for DQ circuit TDQS, /TDQS Termination data strobe VSSQ Ground for DQ circuit Chip select VREFDQ Reference voltage for DQ Command input VREFCA Reference voltage Clock enable ZQ Reference pin for ZQ calibration A0 to A14* 3 BA0 to BA2* /CS* 3 3 /RAS, /CAS, /WE* CKE* 3 3 CK, /CK Differential clock input NC* 1 DM Write data mask NU* 2 ODT* 3 3 Function Active low asynchronous reset No connection Not usable ODT control Notes: 1. Not internally connected with die. 2. Don't connect. Internally connected. 3. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination. Data Sheet E1797E41 (Ver. 4.1) 3 EDJ2104EDBG, EDJ2108EDBG CONTENTS Specifications.................................................................................................................................................1 Features.........................................................................................................................................................1 Ordering Information......................................................................................................................................2 Part Number ..................................................................................................................................................2 Pin Configurations .........................................................................................................................................3 Electrical Conditions ......................................................................................................................................6 Absolute Maximum Ratings .........................................................................................................................6 Operating Temperature Condition ...............................................................................................................6 Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) ...............7 Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) ..................7 AC and DC Input Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V)...................8 VREF Tolerances ........................................................................................................................................9 Input Slew Rate Derating ........................................................................................................................... 10 AC and DC Logic Input Levels for Differential Signals ............................................................................... 16 AC and DC Output Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) .............. 21 AC Overshoot/Undershoot Specification.................................................................................................... 23 Output Driver Impedance........................................................................................................................... 24 On-Die Termination (ODT) Levels and I-V Characteristics ........................................................................26 ODT Timing Definitions.............................................................................................................................. 28 IDD Measurement Conditions (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) ............................... 32 Electrical Specifications...............................................................................................................................45 DC Characteristics 1 (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) ............................................. 45 Pin Capacitance (TC = 25C, VDD, VDDQ = 1.283V to 1.45V) ................................................................. 47 Standard Speed Bins ................................................................................................................................. 48 AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V, VSS, VSSQ = 0V)................... 51 Block Diagram .............................................................................................................................................64 Pin Function.................................................................................................................................................65 Command Operation ...................................................................................................................................67 Command Truth Table ............................................................................................................................... 67 CKE Truth Table ........................................................................................................................................ 71 Simplified State Diagram .............................................................................................................................72 RESET and Initialization Procedure ............................................................................................................73 Power-Up and Initialization Sequence ....................................................................................................... 73 Reset and Initialization with Stable Power ................................................................................................. 74 Programming the Mode Register.................................................................................................................75 Mode Register Set Command Cycle Time (tMRD) ....................................................................................75 MRS Command to Non-MRS Command Delay (tMOD) ............................................................................ 75 DDR3 SDRAM Mode Register 0 [MR0] ..................................................................................................... 76 DDR3 SDRAM Mode Register 1 [MR1] ..................................................................................................... 77 Data Sheet E1797E41 (Ver. 4.1) 4 EDJ2104EDBG, EDJ2108EDBG DDR3 SDRAM Mode Register 2 [MR2] ..................................................................................................... 78 DDR3 SDRAM Mode Register 3 [MR3] ..................................................................................................... 79 Burst Length (MR0) ................................................................................................................................... 80 Burst Type (MR0) ...................................................................................................................................... 80 DLL Enable (MR1) ..................................................................................................................................... 81 DLL-off Mode ............................................................................................................................................. 81 DLL on/off switching procedure ................................................................................................................. 82 Additive Latency (MR1).............................................................................................................................. 84 Write Leveling (MR1) ................................................................................................................................. 85 TDQS, /TDQS function (MR1) ................................................................................................................... 88 Extended Temperature Usage (MR2) ........................................................................................................ 89 Multi Purpose Register (MR3).................................................................................................................... 91 Operation of the DDR3 SDRAM ..................................................................................................................98 Read Timing Definition............................................................................................................................... 98 Read Operation ....................................................................................................................................... 103 Write Timing Definition............................................................................................................................. 110 Write Operation........................................................................................................................................ 112 Write Timing Violations ............................................................................................................................ 118 Write Data Mask ...................................................................................................................................... 119 Precharge ................................................................................................................................................ 120 Auto Precharge Operation ....................................................................................................................... 121 Auto-Refresh............................................................................................................................................ 122 Self-Refresh............................................................................................................................................. 123 Power-Down Mode .................................................................................................................................. 125 Input Clock Frequency Change during Precharge Power-Down.............................................................. 132 On-Die Termination (ODT)....................................................................................................................... 133 ZQ Calibration.......................................................................................................................................... 145 Package Drawing ......................................................................................................................................147 78-ball FBGA ........................................................................................................................................... 147 Recommended Soldering Conditions........................................................................................................148 Data Sheet E1797E41 (Ver. 4.1) 5 EDJ2104EDBG, EDJ2108EDBG Electrical Conditions * All voltages are referenced to VSS (GND) * Execute power-up and Initialization sequence before proper device operation is achieved. Absolute Maximum Ratings Parameter Symbol Rating Unit Notes Power supply voltage VDD -0.4 to +1.975 V 1, 3 Power supply voltage for output VDDQ -0.4 to +1.975 V 1, 3 Input voltage VIN -0.4 to +1.975 V 1 Output voltage VOUT -0.4 to +1.975 V 1 Reference voltage VREFCA -0.4 to 0.6 x VDD V 3 Reference voltage for DQ VREFDQ -0.4 to 0.6 x VDDQ V 3 Storage temperature Tstg -55 to +100 C 1, 2 Power dissipation PD 1.0 W 1 Short circuit output current IOUT 50 mA 1 Notes: 1. Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Storage temperature is the case surface temperature on the center/top side of the DRAM. 3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must be no greater than 0.6 x VDDQ, When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV. Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Operating Temperature Condition Parameter Symbol Rating Unit Notes Operating case temperature TC 0 to +95 C 1, 2, 3 Notes: 1. Operating temperature is the case surface temperature on the center/top side of the DRAM. 2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0C to +85C under all operating conditions. 3. Some applications require operation of the DRAM in the Extended Temperature Range between +85C and +95C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9s. (This double refresh requirement may not apply for some devices.) b) If Self-refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 bit [A6, A7] = [0, 1]) or enable the optional Auto Self-Refresh mode (MR2 bit [A6, A7] = [1, 0]). Data Sheet E1797E41 (Ver. 4.1) 6 EDJ2104EDBG, EDJ2108EDBG Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) [DDR3L Operation] Parameter Symbol min. typ. max. Unit Notes Supply voltage VDD 1.283 1.35 1.45 V 1, 2, 3, 4 Supply voltage for DQ VDDQ 1.283 1.35 1.45 V 1, 2, 3, 4 Notes: 1. Maximum DC value may not be greater than 1.425V. The DC value is the linear average of VDD/VDDQ(t) over a very long period of time (e.g. 1 sec). 2. If maximum limit is exceeded, input levels shall be governed by DDR3 specifications. 3. Under these supply voltages, the device operates to this DDR3L specifcation. 4. Once initialized for DDR3L operation, DDR3 operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3 operation shown as following timing wave form. Recommended DC Operating Conditions (TC = 0C to +85C, VDD, VDDQ = 1.5V 0.075V) [DDR3 Operation] Parameter Symbol min. typ. max. Unit Notes Supply voltage VDD 1.425 1.5 1.575 V 1, 2, 3 Supply voltage for DQ VDDQ 1.425 1.5 1.575 V 1, 2, 3 Notes: 1. If minimum limit is exceeded, input levels shall be governed by DDR3L specifications. 2. Under 1.5V operation, this DDR3L device operates to the DDR3 specifcations under the same speed timings as defined for this device. 3. Once initialized for DDR3 operation, DDR3L operation may only be used if the device is in reset while VDD and VDDQ are changed for DDR3L operation shown as below. Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, /CK tCKSRX T (min.) = 10ns VDD, VDDQ (DDR3) VDD, VDDQ (DDR3L) T (min.) = 10ns T (min.) = 200s T = 500s /RESET CKE tIS T (min.) = 10ns Valid tDLLK tXPR tIS Command *1 BA tMRD tMRD tMRD tMOD MRS MRS MRS MRS MR2 MR3 MR1 MR0 tZQinit ZQCL *1 Valid Valid tIS ODT Static low in case RTT_Nore is enabled at time Tg, otherwise static high or low Valid RTT : VIH or VIL Note: 1. From time point Td until Tk NOP or DESL commands must be applied between MRS and ZQCL commands. Data Sheet E1797E41 (Ver. 4.1) 7 EDJ2104EDBG, EDJ2108EDBG AC and DC Input Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) Single-Ended AC and DC Input Levels for Command and Address Parameter Symbol min. typ. max. Unit Notes DC input logic high VIHCA (DC90) VREF + 0.09 VDD V 1 DC input logic low VILCA (DC90) VSS VREF - 0.09 V 1 V 1, 2, 5 V 1, 2, 5 V 1, 2, 5 AC input logic high VIHCA (AC160) VREF + 0.160 AC input logic low VILCA (AC160) * AC input logic high VIHCA (AC135) 2 VREF + 0.135 2 AC input logic low VILCA (AC135) * Input reference voltage for address, command inputs VREFCA (DC) 0.49 x VDD 2 * VREF - 0.160 2 * VREF - 0.135 V 1, 2, 5 0.51 x VDD V 3, 4 Notes: 1. For input only pins except /RESET; VREF = VREFCA (DC). 2. See Overshoot and Undershoot Specifications section. 3. The AC peak noise on VREF may not allow VREF to deviate from VREFCA (DC) by more than 1% VDD (for reference: approx. 13.5mV). 4. For reference: approx. VDD/2 13.5mV. 5. These levels apply to 1.35V operation only. The 1.5V levels (e.g. VIH/VILCA of DC100, AC175 and AC150) do not apply to when the device is in 1.35V operation. Single-Ended AC and DC Input Levels for DQ and DM Parameter Symbol min. typ. max. Unit Notes DC input logic high VIHDQ (DC90) VREF + 0.09 VDD V 1 DC input logic low VILDQ (DC90) VSS VREF - 0.09 V 1 AC input logic high DDR3L-1600, 1333 VIHDQ (AC160) VREF + 0.160 DDR3L-1066 V 1, 2, 5 * 2 V 1, 2, 5 2 V 1, 2, 5 AC input logic high VIHDQ (AC135) VREF + 0.135 * AC input logic low DDR3L-1600, 1333 VILDQ (AC160) V 1, 2, 5 DDR3L-1066 * 2 VREF - 0.160 V 1, 2, 5 2 VREF - 0.135 V 1, 2, 5 0.51 x VDD V 3, 4 AC input logic low VILDQ (AC135) * Input reference voltage for DQ, DM inputs VREFDQ (DC) 0.49 x VDD Notes: 1. For DQ and DM: VREF = VREFDQ (DC). 2. See Overshoot and Undershoot Specifications section. 3. The AC peak noise on VREF may not allow VREF to deviate from VREFDQ (DC) by more than 1% VDD (for reference: approx. 13.5mV). 4. For reference: approx. VDD/2 13.5mV. 5. These levels apply to 1.35V operation only. The 1.5V levels (e.g. VIH/VILDQ of DC100, AC175 and AC150) do not apply to when the device is in 1.35V operation. Data Sheet E1797E41 (Ver. 4.1) 8 EDJ2104EDBG, EDJ2108EDBG VREF Tolerances The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are shown in Figure VREF(DC) Tolerance and VREF AC-Noise Limits. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for VREFCA and VREFDQ likewise). VREF(DC) is the linear average of VREF(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table of(Single-Ended AC and DC Input Levels for Command and Address). Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than +/- 1% VDD. VREF(DC) Tolerance and VREF AC-Noise Limits The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are dependent on VREF. VREF shall be understood as VREF(DC), as defined in figure above, VREF(DC) Tolerance and VREF AC-Noise Limits. This clarifies that DC-variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for VREF(DC) deviations from the optimum position within the data-eye of the input signals. This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with VREF AC-noise. Timing and voltage effects due to ac-noise on VREF up to the specified limit (1% of VDD) are included in DRAM timings and their associated deratings. Data Sheet E1797E41 (Ver. 4.1) 9 EDJ2104EDBG, EDJ2108EDBG Input Slew Rate Derating For all input signals the total tIS, tDS (setup time) and tIH, tDH (hold time) required is calculated by adding the data sheet tIS (base), tDS (base) and tIH (base), tDH (base) value to the tIS, tDS and tIH, tDH derating value respectively. Example: tDS (total setup time) = tDS (base) + tDS. Setup (tIS, tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIH (AC) min. Setup (tIS, tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF (DC) and the first crossing of VIL (AC) max. If the actual signal is always earlier than the nominal slew rate line between shaded `VREF (DC) to AC region', use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is later than the nominal slew rate line anywhere between shaded `VREF (DC) to AC region', the slew rate of a tangent line to the actual signal from the AC level to DC level is used for derating value (see the figure of Slew Rate Definition Tangent). Hold (tIH, tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL (DC) max. and the first crossing of VREF (DC). Hold (tIH, tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH (DC) min. and the first crossing of VREF (DC). If the actual signal is always later than the nominal slew rate line between shaded `DC level to VREF (DC) region', use nominal slew rate for derating value (See the figure of Slew Rate Definition Nominal). If the actual signal is earlier than the nominal slew rate line anywhere between shaded `DC to VREF (DC) region', the slew rate of a tangent line to the actual signal from the DC level to VREF (DC) level is used for derating value (see the figure of Slew Rate Definition Tangent). For a valid transition the input signal has to remain above/below VIH/VIL(AC) for some time tVAC (see the table of Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL (AC) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL (AC). For slew rates in between the values listed in the tables below, the derating values may obtained by linear interpolation. These values are typically not subject to production test. They are verified by design and characterization. [Address/Command Setup and Hold Base-Values for 1V/ns] DDR3L-1600 DDR3L-1333 DDR3L-1066 Unit Reference tIS(base) AC160 60 80 tIS(base) AC135 185 205 140 ps VIH/VILCA(AC) 290 ps VIH/VILCA(AC) tIH(base) DC90 130 150 210 ps VIH/VILCA(DC) Notes: 1. AC/DC referenced for 1V/ns Address/Command slew rate and 2V/ns differential CK, /CK slew rate. 2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125ps for DDR3L-1066 or 100ps for DDR3L-1600/1333 of derating to accommodate for the lower alternate threshold of 135mV and another 25ps to account for the earlier reference point [(160mV - 135mV)/1V/ns]. Data Sheet E1797E41 (Ver. 4.1) 10 EDJ2104EDBG, EDJ2108EDBG [Derating Values of tIS/tIH AC/DC based AC160 Threshold (DDR3L-1600, 1333, 1066)] tIS, tIH derating in [ps] AC/DC based AC160 Threshold -> VIH(AC)=VREF(DC)+160mV, VIL(AC)=VREF(DC)-160mV CK, /CK differential slew rate CMD, ADD slew rate (V/ns) 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIS tIS 2.0 +80 +45 +80 +45 +80 +45 +88 +53 +96 +61 +104 +69 +112 +79 +120 +95 ps 1.5 +53 +30 +53 +30 +53 +30 +61 +38 +69 +46 +77 +54 +85 +64 +93 +80 ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 +24 +24 +32 +34 +40 +50 ps 0.9 -1 -3 -1 -3 -1 -3 +7 +5 +15 +13 +23 +21 +31 +31 +39 +47 ps 0.8 -3 -8 -3 -8 -3 -8 +5 +1 +13 +9 +21 +17 +29 +27 +37 +43 ps 0.7 -5 -13 -5 -13 -5 -13 +3 -5 +11 +3 +19 +11 +27 +21 +35 +37 ps 0.6 -8 -20 -8 -20 -8 -20 0 -12 +8 -4 +16 +4 +24 +14 +32 +30 ps tIH tIH tIH Unit 0.5 -20 -30 -20 -30 -20 -30 -12 -22 -4 -14 +4 -6 +12 +4 +20 +20 ps 0.4 -40 -45 -40 -45 -40 -45 -32 -37 -24 -29 -16 -21 -8 -11 0 +5 ps [Derating Values of tIS/tIH AC/DC based-Alternate AC135 Threshold (DDR3L-1600, 1333, 1066)] tIS, tIH derating in [ps] AC/DC based Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV CK, /CK differential slew rate CMD, ADD slew rate (V/ns) 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIS 2.0 +68 +45 +68 +45 +68 +45 +76 +53 +84 +61 +92 +69 +100 +79 +108 +95 ps 1.5 +45 +30 +45 +30 +45 +30 +53 +38 +61 +46 +69 +54 +77 +64 +85 +80 ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 +24 +24 +32 +34 +40 +50 ps 0.9 +2 -3 +2 -3 +2 -3 +10 +5 +18 +13 +26 +21 +34 +31 +42 +47 ps 0.8 +3 -8 +3 -8 +3 -8 +11 +1 +19 +9 +27 +17 +35 +27 +43 +43 ps 0.7 +6 -13 +6 -13 +6 -13 +14 -5 +22 +3 +30 +11 +38 +21 +46 +37 ps 0.6 +9 -20 +9 -20 +9 -20 +17 -12 +25 -4 +33 +4 +41 +14 +49 +30 ps 0.5 +5 -30 +5 -30 +5 -30 +13 -22 +21 -14 +29 -6 +37 +4 +45 +20 ps 0.4 -3 -45 -3 -45 -3 -45 +6 -37 +14 -29 +22 -21 +30 -11 +38 +5 ps tIH [Required time tVAC above VIH(AC) {below VIL(AC)} for Valid Transition] tVAC @ AC160mV [ps] tVAC @ AC135mV [ps] Slew rate (V/ns) min. max. min. max. >2.0 TBD TBD 2.0 TBD TBD 1.5 TBD TBD 1.0 TBD TBD 0.9 TBD TBD 0.8 TBD TBD 0.7 TBD TBD 0.6 TBD TBD 0.5 TBD TBD <0.5 TBD TBD Data Sheet E1797E41 (Ver. 4.1) 11 tIH Unit EDJ2104EDBG, EDJ2108EDBG [Data Setup and Hold Base-Values] DDR3L-1600 DDR3L-1333 DDR3L-1066 Unit Reference tDS(base) AC160 40 ps VIH/VILDQ(AC) tDS(base) AC135 25 45 90 ps VIH/VILDQ(AC) tDH(base) DC90 55 75 110 ps VIH/VILDQ(DC) 1.2 V/ns 1.0 V/ns Note: 1 AC/DC referenced for 1V/ns DQ slew rate and 2V/ns DQS slew rate [Derating Values of tDS/tDH AC/DC based, AC160 (DDR3L-1066)] tDS, tDH derating in [ps] AC/DC based AC160 Threshold -> VIH(AC)=VREF(DC)+160mV, VIL(AC)=VREF(DC)-160mV DQS, /DQS differential slew rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH Unit DQ slew rate (V/ns) 2.0 +80 +45 +80 +45 +80 +45 ps 1.5 +53 +30 +53 +30 +53 +30 +61 +38 ps 1.0 0 0 0 0 0 0 +8 +8 +16 +16 ps 0.9 -1 -3 -1 -3 +7 +5 +15 +13 +23 +21 ps 0.8 -3 -8 +5 +1 +13 +9 +21 +17 +29 +27 ps 0.7 +3 -5 +11 +3 +19 +11 +27 +21 +35 +37 ps 0.6 +8 -4 +16 +4 +24 +14 +32 +30 ps 0.5 +4 -6 +12 +4 +20 +20 ps 0.4 -8 -11 0 +5 ps [Derating Values of tDS/tDH AC/DC based, AC135 (DDR3L-1600, 1333, 1066)] tDS, tDH derating in [ps] AC/DC based Alternate AC135 Threshold -> VIH(AC)=VREF(DC)+135mV, VIL(AC)=VREF(DC)-135mV DQS, /DQS differential slew rate 4.0 V/ns 3.0 V/ns 2.0 V/ns 1.8 V/ns 1.6 V/ns 1.4 V/ns 1.2 V/ns 1.0 V/ns tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH Unit +68 +45 +68 +45 +68 +45 1.5 +45 +30 +45 +30 +45 +30 +53 +38 1.0 0 0 0 0 0 0 +8 +8 0.9 +2 -3 +2 -3 +10 +5 0.8 +3 -8 +11 +1 0.7 +14 0.6 0.5 0.4 2.0 DQ slew rate (V/ns) ps ps +16 +16 ps +18 +13 +26 +21 ps +19 +9 +27 +17 +35 +27 ps -5 +22 +3 +30 +11 +38 +21 +46 +37 ps +25 -4 +33 +4 +41 +14 +49 +30 ps +29 -6 +37 +4 +45 +20 ps +30 -11 +38 +5 ps Data Sheet E1797E41 (Ver. 4.1) 12 EDJ2104EDBG, EDJ2108EDBG [Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition] DDR3L-1066 (AC160) DDR3L-1600, 1333, 1066 (AC135) tVAC [ps] tVAC [ps] Slew rate (V/ns) min. max. min. max. >2.0 TBD TBD 2.0 TBD TBD 1.5 TBD TBD 1.0 TBD TBD 0.9 TBD TBD 0.8 TBD TBD 0.7 TBD TBD 0.6 TBD TBD 0.5 TBD TBD <0.5 TBD TBD Data Sheet E1797E41 (Ver. 4.1) 13 EDJ2104EDBG, EDJ2108EDBG CK /CK tIS tIH tIS tIH VDD tVAC VIH (AC) min. VREF to AC region VIH (DC) min. VREF (DC) DC to VREF region nominal slew rate nominal slew rate DC to VREF region VIL (DC) max. VREF to AC region VIL (AC) max. tVAC VSS TFS TRH TRS TFH Slew Rate Definition Nominal (CK, /CK) /DQS DQS tDS tDH tDS tDH VDD tVAC VIH (AC) min. VREF to AC region VIH (DC) min. VREF (DC) DC to VREF region nominal slew rate nominal slew rate DC to VREF region VIL (DC) max. VREF to AC region VIL (AC) max. tVAC VSS TFS TRH TRS TFH Slew Rate Definition Nominal (DQS, /DQS) VIH (AC) min. - VREF (DC) Setup slew rate = Rising signal TRS VREF (DC) - VIL (AC) max. Setup slew rate = Falling signal TFS Hold slew rate Rising signal = VREF (DC) - VIL (DC) max. Hold slew rate Falling signal TRH Data Sheet E1797E41 (Ver. 4.1) 14 = VIH (DC) min. - VREF (DC) TFH EDJ2104EDBG, EDJ2108EDBG CK /CK tIS tIH tIS tIH VDD tVAC VIH (AC) min. VREF to AC region nominal line nominal line VIH (DC) min. DC to VREF region tangent line VREF (DC) tangent line DC to VREF region nominal line VIL (DC) max. VREF to AC region nominal line VIL (AC) max. tVAC VSS TFS TRH TRS TFH Slew Rate Definition Tangent (CK, /CK) /DQS DQS tDS tDH tDS tDH VDD tVAC VIH (AC) min. VREF to AC region nominal line nominal line VIH (DC) min. DC to VREF region tangent line VREF (DC) tangent line DC to VREF region nominal line VIL (DC) max. VREF to AC region nominal line VIL (AC) max. tVAC VSS TFS TRH TRS TFH Slew Rate Definition Tangent (DQS, /DQS) tangent line [VIH (AC) min. - VREF (DC)] Setup slew rate = Rising signal TRS tangent line [VREF (DC) - VIL (AC) max.] Setup slew rate = Falling signal TFS Hold slew rate Rising signal = tangent line [VREF (DC) - VIL (DC) max.] Hold slew rate Falling signal TRH Data Sheet E1797E41 (Ver. 4.1) 15 = tangent line [VIH (DC) min. - VREF (DC)] TFH EDJ2104EDBG, EDJ2108EDBG AC and DC Logic Input Levels for Differential Signals Differential signal definition ! "#" Definition of Differential AC-swing and "time above AC-level" tDVAC [Differential AC and DC Input Levels] Parameter min. typ. VIHdiff +0.180 * Differential input logic low VILdiff 3 -0.180 V 1 Differential input logic AC VIHdiff (AC) 2 x (VIH (AC) - VREF) 3 V 2 Differential input logic AC VILdiff (AC) V 2 Differential input logic high Symbol * * 3 max. * 3 2 x (VIL(AC) - VREF) Unit Notes V 1 Notes: 1. Used to define a differential signal slew-rate. 2. For CK, /CK use VIH/VIL(AC) of address/command and VREFCA; for strobes (DQS, /DQS) use VIH/VIL(AC) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single ended components of differential signal CK, /CK, DQS, /DQS to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Overshoot and Undershoot specifications. Data Sheet E1797E41 (Ver. 4.1) 16 EDJ2104EDBG, EDJ2108EDBG [Required time tDVAC above VIH(AC) {below VIL(AC)} for valid transition] @[VIH/Ldiff (AC)] = 320mV @[VIH/Ldiff (AC)] = 270mV tDVAC [ps] tDVAC [ps] Slew rate (V/ns) min. max. min. max. >4.0 TBD TBD 4.0 TBD TBD 3.0 TBD TBD 2.0 TBD TBD 1.8 TBD TBD 1.6 TBD TBD 1.4 TBD TBD 1.2 TBD TBD 1.0 TBD TBD <1.0 TBD TBD Data Sheet E1797E41 (Ver. 4.1) 17 EDJ2104EDBG, EDJ2108EDBG Single-Ended Requirements for Differential Signals Each individual component of a differential signal (CK, DQS, /CK, /DQS) has also to comply with certain requirements for single-ended signals. CK and /CK have to reach VSEH min. / VSEL max. (approximately equal to the AC-levels (VIH(AC) / VIL(AC)) for Address/command signals) in every half-cycle. DQS, /DQS have to reach VSEH min./VSEL max. (approximately equal to the AC-levels (VIH(AC) / VIL(AC)) for DQ signals) in every half-cycle preceding and following a valid transition. Note that the applicable ac-levels for Address/command and DQ's might be different per speed-bin etc. E.g. if VIH 135 (AC)/VIL 135 (AC) is used for Address/command signals, then these ac-levels apply also for the single ended components of differential CK and /CK. VDD or VDDQ VSEH min. VSEH VDD/2 or VDDQ/2 CK or DQS VSEL max. VSEL VSS or VSSQ time Single-Ended Requirement for Differential Signals. Note that while Address/command and DQ signal requirements are with respect to VREF, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. The transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSEL max, VSEH min has no bearing on timing, but adds a restriction on the common mode characteristics of these signals. Data Sheet E1797E41 (Ver. 4.1) 18 EDJ2104EDBG, EDJ2108EDBG [Single-ended levels for CK, DQS, /CK, /DQS] Parameter Symbol Single-ended high level for strobes Single-ended high level for CK, /CK Single-ended low level for strobes Single-ended low level for CK, /CK VSEH VSEL min. typ. max. Unit Notes V 1, 2 V 1, 2 (VDD/2) + 0.160 * 3 (VDD/2) + 0.160 * 3 * 3 (VDD/2) - 0.160 V 1, 2 * 3 (VDD/2) - 0.160 V 1, 2 Notes: 1. For CK, /CK use VIH/VIL(AC) of ADD/CMD; for strobes (DQS, /DQS) use VIH/VIL(AC) of DQs. 2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VIH(AC)/VIL(AC) for address/command is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here. 3. These values are not defined, however the single ended components of differential signals CK, /CK, DQS, /DQS need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to Overshoot and Undershoot specifications. To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, /CK and DQS, /DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signal to the midlevel between of VDD and VSS. VDD CK, DQS VIX VDD/2 VIX VIX /CK, /DQS VSEH VSEL VSS VIX Definition [Cross point voltage for differential input signals (CK, DQS)] Parameter Symbol pins min. max. Unit Note Differential input cross point voltage relative to VDD/2 VIX CK, /CK -150 150 mV 1 VIX DQS, /DQS -150 150 mV 1 Note: 1. The relation between VIX min./max. and VSEL/VSEH should satisfy the following. VDD/2 +VIX (min.) -VSEL 25mV VSEH - ((VDD/2) + VIX (max.)) 25mV Data Sheet E1797E41 (Ver. 4.1) 19 EDJ2104EDBG, EDJ2108EDBG [Differential Input Slew Rate Definition] Measured Description Differential input slew rate for rising edge (CK - /CK and DQS - /DQS) Differential input slew rate for falling edge (CK - /CK and DQS - /DQS) From To Defined by Applicable for VILdiff (max.) VIHdiff (min.) VIHdiff (min.) - VILdiff (max.) TRdiff VIHdiff (min.) VILdiff (max.) VIHdiff (min.) - VILdiff (max.) TFdiff Note: The differential signal (i.e. CK, /CK and DQS, /DQS) must be linear between these thresholds. VIHdiff(min.) 0 VILdiff (max.) TRdiff TFdiff Falling slew = VIHdiff (min.) - VILdiff (max.) Rising slew = TFdiff VIHdiff (min.) - VILdiff (max.) TRdiff Differential Input Slew Rate Definition for DQS, /DQS and CK, /CK Data Sheet E1797E41 (Ver. 4.1) 20 Note EDJ2104EDBG, EDJ2108EDBG AC and DC Output Measurement Levels (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) Parameter DC output high measurement level (for IV curve linearity) DC output middle measurement level (for IV curve linearity) DC output low measurement level (for IV curve linearity) AC output high measurement level (for output slew rate) AC output low measurement level (for output slew rate) AC differential output high measurement level (for output slew rate) AC differential output low measurement level (for output slew rate) AC differential cross point voltage Symbol Specification Unit VOH (DC) 0.8 x VDDQ V VOM (DC) 0.5 x VDDQ V VOL (DC) 0.2 x VDDQ V VOH (AC) VTT + 0.1 x VDDQ V 1 VOL (AC) VTT - 0.1 x VDDQ V 1 VOHdiff 0.2 x VDDQ V 2 VOLdiff -0.2 x VDDQ V 2 VOX (AC) TBD mV Notes: 1. The swing of 0.1 x VDDQ is based on approximately swing with a driver impedance of 34 and an effective differential outputs. 2. The swing of 0.2 x VDDQ is based on approximately swing with a driver impedance of 34 and an effective differential outputs. 50% of the static single-ended output high or low test load of 25 to VTT = VDDQ/2 at each of the 50% of the static single-ended output high or low test load of 25 to VTT = VDDQ/2 at each of the Output Slew Rate Definitions [Single-Ended Output Slew Rate Definition] Measured Description From To Output slew rate for rising edge VOL (AC) VOH (AC) Output slew rate for falling edge VOH (AC) VOL (AC) Defined by VOH (AC) - VOL (AC) TRse VOH (AC) - VOL (AC) TFse VOH (AC) VTT VOL (AC) TRse TFse Falling slew = VOH (AC) - VOL (AC) Rising slew = TFse VOH (AC) - VOL (AC) TRse Output Slew Rate Definition for Single-Ended Signals Data Sheet E1797E41 (Ver. 4.1) 21 Notes EDJ2104EDBG, EDJ2108EDBG [Differential Output Slew Rate Definition] Measured Description From To Defined by Differential output slew rate for rising edge VOLdiff (AC) VOHdiff (AC) Differential output slew rate for falling edge VOHdiff (AC) VOLdiff (AC) VOHdiff(AC) - VOLdiff (AC) TRdiff VOHdiff (AC) - VOLdiff (AC) TFdiff VOHdiff (AC) 0 VOLdiff (AC) TRdiff TFdiff Falling slew = VOHdiff (AC) - VOLdiff (AC) Rising slew = TFdiff VOHdiff (AC) - VOLdiff (AC) TRdiff Differential Output Slew Rate Definition for DQS, /DQS and CK, /CK Output Slew Rate (RON = RZQ/7 setting) Parameter Symbol Output slew rate (Single-ended) SRQse Output slew rate (Differential) SRQdiff Speed DDR3L-1600 DDR3L-1333 DDR3L-1066 DDR3L-1600 DDR3L-1333 DDR3L-1066 min. max. Unit Notes 1.75 5 V/ns 1 3.5 12 V/ns Remark: SR = slew rate. se = single-ended signals. diff = differential signals. Q = Query output Note: 1. In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane. (a) is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low). (b) is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the regular maximum limit of 5V/ns applies. Reference Load for AC Timing and Output Slew Rate VDDQ DUT CK, /CK DQ DQS, /DQS VTT = VDDQ/2 25 Reference Output Load Data Sheet E1797E41 (Ver. 4.1) 22 EDJ2104EDBG, EDJ2108EDBG AC Overshoot/Undershoot Specification Parameter Pins Specification Maximum peak amplitude allowed for overshoot Command, Address, CKE, ODT TBD Maximum peak amplitude allowed for undershoot TBD Maximum overshoot area above VDD DDR3L-1600 TBD DDR3L-1333 TBD DDR3L-1066 TBD Maximum undershoot area below VSS DDR3L-1600 TBD DDR3L-1333 TBD DDR3L-1066 TBD Maximum peak amplitude allowed for overshoot CK, /CK TBD Maximum peak amplitude allowed for undershoot TBD Maximum overshoot area above VDD DDR3L-1600 TBD DDR3L-1333 TBD DDR3L-1066 TBD Maximum undershoot area below VSS DDR3L-1600 TBD DDR3L-1333 TBD DDR3L-1066 TBD Maximum peak amplitude allowed for overshoot DQ, DQS, /DQS, DM TBD Maximum peak amplitude allowed for undershoot TBD Maximum overshoot area above VDDQ DDR3L-1600 TBD DDR3L-1333 TBD DDR3L-1066 TBD Maximum undershoot area below VSSQ DDR3L-1600 TBD DDR3L-1333 TBD DDR3L-1066 TBD Maximum amplitude Overshoot area Volts (V) VDD, VDDQ VSS, VSSQ Undershoot area Time (ns) Overshoot/Undershoot Definition Data Sheet E1797E41 (Ver. 4.1) 23 EDJ2104EDBG, EDJ2108EDBG Output Driver Impedance RON will be achieved by the DDR3 SDRAM after proper I/O calibration. Tolerance and linearity requirements are referred to the Output Driver DC Electrical Characteristics table. A functional representation of the output buffer is shown in the figure Output Driver: Definition of Voltages and Currents. RON is defined by the value of the external reference resistor RZQ as follows: * RON40 = RZQ/6 * RON34 = RZQ/7 The individual pull-up and pull-down resistors (RONPu and RONPd) are defined as follows: Parameter Symbol Output driver pull-up impedance RONPu Output driver pull-down impedance RONPd Definition Conditions VDDQ - VOUT IOUT VOUT IOUT RONPd is turned off RONPu is turned off Chip in Drive Mode Output Driver VDDQ IPu To other circuitry like RCV, ... RONPu DQ IOut RONPd VOut IPd VSSQ Output Driver: Definition of Voltages and Currents Data Sheet E1797E41 (Ver. 4.1) 24 EDJ2104EDBG, EDJ2108EDBG Output Driver DC Electrical Characteristics (RZQ = 240, entire operating temperature range; after proper ZQ calibration) RONnom Resistor 40 RON40Pd RON40Pu 34 RON34Pd RON34Pu Mismatch between pull-up and pull down, MMPuPd VOUT min. nom. max. VOL (DC) = 0.2 x VDDQ VOM (DC) = 0.5 x VDDQ VOH (DC) = 0.8 x VDDQ VOL (DC) = 0.2 x VDDQ VOM (DC) = 0.5 x VDDQ VOH (DC) = 0.8 x VDDQ VOL (DC) = 0.2 x VDDQ VOM (DC) = 0.5 x VDDQ VOH (DC) = 0.8 x VDDQ VOL (DC) = 0.2 x VDDQ VOM (DC) = 0.5 x VDDQ VOH (DC) = 0.8 x VDDQ 0.6 0.9 0.9 0.9 0.9 0.6 0.6 0.9 0.9 0.9 0.9 0.6 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.15 1.15 1.45 1.45 1.15 1.15 1.15 1.15 1.45 1.45 1.15 1.15 VOM (DC) = 0.5 x VDDQ -10 +10 Unit Notes RZQ/6 1, 2, 3 RZQ/6 1, 2, 3 RZQ/7 1, 2, 3 RZQ/7 1, 2, 3 % 1, 2, 4 Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. 4. Measurement definition for mismatch between pull-up and pull-down, MMPuPd: Measure RONPu and RONPd, both at 0.5 x VDDQ: MMPuPd = RONPu - RONPd x 100 RONnom Output Driver Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the table Output Driver Sensitivity Definition and Output Driver Voltage and Temperature Sensitivity. T = T - T (@calibration); V= VDDQ - VDDQ (@calibration); VDD = VDDQ Note: dRONdT and dRONdV are not subject to production test but are verified by design and characterization. [Output Driver Sensitivity Definition] RONPu@VOH (DC) min. max. unit 0.6 - dRONdTH x |T| - dRONdVH x |V| 1.1 + dRONdTH x |T| + dRONdVH x |V| RZQ/7 RON@ VOM (DC) 0.9 - dRONdTM x |T| - dRONdVM x |V| 1.1 + dRONdTM x |T| + dRONdVM x |V| RZQ/7 RONPd@VOL (DC) 0.6 - dRONdTL x |T| - dRONdVL x |V| 1.1 + dRONdTL x |T| + dRONdVL x |V| RZQ/7 [Output Driver Voltage and Temperature Sensitivity] DDR3L-1600 DDR3L-1333, 1066 min. max. max. Unit dRONdTM 0 1.5 1.5 %/C dRONdVM 0 0.13 0.15 %/mV dRONdTL 0 1.5 1.5 %/C dRONdVL 0 0.13 0.15 %/mV dRONdTH 0 1.5 1.5 %/C dRONdVH 0 0.13 0.15 %/mV Data Sheet E1797E41 (Ver. 4.1) 25 EDJ2104EDBG, EDJ2108EDBG On-Die Termination (ODT) Levels and I-V Characteristics On-Die Termination effective resistance RTT is defined by bits A9, A6 and A2 of the MR1 Register. ODT is applied to the DQ, DM, DQS, /DQS and TDQS, /TDQS (x8 devices only) pins. A functional representation of the on-die termination is shown in the figure On-Die Termination: Definition of Voltages and Currents. The individual pull-up and pull-down resistors (RTTPu and RTTPd) are defined as follows: Parameter Symbol ODT pull-up resistance RTTPu ODT pull-down resistance RTTPd Definition Conditions VDDQ - VOUT IOUT VOUT IOUT RTTPd is turned off RTTPu is turned off Chip in Termination Mode ODT VDDQ IPu To other circuitry like RCV, ... IOut = IPd - IPu RTTPu DQ IOut RTTPd VOut IPd VSSQ On-Die Termination: Definition of Voltages and Currents The value of the termination resistor can be set via MRS command to RTT60 = RZQ/4 (nom) or RTT120 = RZQ/2 (nom). RTT60 or RTT120 will be achieved by the DDR3 SDRAM after proper I/O calibration has been performed. Tolerances requirements are referred to the ODT DC Electrical Characteristics table. Measurement Definition for RTT Apply VIH (AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively. RTT = VIH( AC) - VIL( AC) I( VIH( AC)) - I( VIL( AC)) Measurement Definition for VM Measure voltage (VM) at test pin (midpoint) with no load. 2 x VM VM = - 1 x 100 VDDQ Data Sheet E1797E41 (Ver. 4.1) 26 EDJ2104EDBG, EDJ2108EDBG ODT DC Electrical Characteristics (RZQ = 240, entire operating temperature range; after proper ZQ calibration) MR1 [A9, A6, A2] RTT [0, 1, 0] Resistor VOUT min. nom. max. Unit Notes 120 RTT120Pd240 VOL (DC) VOM (DC) VOH (DC) 0.6 0.9 0.9 1.0 1.0 1.0 1.15 1.15 1.45 RZQ 1, 2, 3, 4 RTT120Pu240 VOL (DC) VOM (DC) VOH (DC) 0.9 0.9 0.6 1.0 1.0 1.0 1.45 1.15 1.15 RZQ 1, 2, 3, 4 RZQ/2 1, 2, 5 RZQ/2 1, 2, 3, 4 RZQ/2 1, 2, 3, 4 RZQ/4 1, 2, 5 RZQ/3 1, 2, 3, 4 RZQ/3 1, 2, 3, 4 RZQ/6 1, 2, 5 RZQ/4 1, 2, 3, 4 RZQ/4 1, 2, 3, 4 RZQ/8 1, 2, 5 RZQ/6 1, 2, 3, 4 RZQ/6 1, 2, 3, 4 RTT120 [0, 0, 1] 60 RTT60Pd120 RTT60Pu120 RTT60 [0, 1.1] 40 RTT40Pd80 RTT40Pu80 RTT40 [1, 0, 1] 30 RTT30Pd60 RTT30Pu60 RTT30 [1, 0, 0] 20 RTT20Pd40 RTT20Pu40 RTT20 VIL (AC) to VIH (AC) 0.9 1.0 1.65 VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) 0.6 0.9 0.9 0.9 0.9 0.6 1.0 1.0 1.0 1.0 1.0 1.0 1.15 1.15 1.45 1.45 1.15 1.15 VIL (AC) to VIH (AC) 0.9 1.0 1.65 VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) 0.6 0.9 0.9 0.9 0.9 0.6 1.0 1.0 1.0 1.0 1.0 1.0 1.15 1.15 1.45 1.45 1.15 1.15 VIL (AC) to VIH (AC) 0.9 1.0 1.65 VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) 0.6 0.9 0.9 0.9 0.9 0.6 1.0 1.0 1.0 1.0 1.0 1.0 1.15 1.15 1.45 1.45 1.15 1.15 VIL (AC) to VIH (AC) 0.9 1.0 1.65 VOL (DC) VOM (DC) VOH (DC) VOL (DC) VOM (DC) VOH (DC) 0.6 0.9 0.9 0.9 0.9 0.6 1.0 1.0 1.0 1.0 1.0 1.0 1.15 1.15 1.45 1.45 1.15 1.15 0.9 1.0 VIL (AC) to VIH (AC) Deviation of VM w.r.t. VDDQ/2, VM -5 1.65 RZQ/12 1, 2, 5 5 % 1, 2, 5, 6 Notes: 1. The tolerance limits are specified after calibration with stable voltage and temperature. For the behavior of the tolerance limits if temperature or voltage changes after calibration, see following section on voltage and temperature sensitivity. 2. The tolerance limits are specified under the condition that VDDQ = VDD and that VSSQ = VSS. 3. Pull-down and pull-up output resistors are recommended to be calibrated at 0.5 x VDDQ. Other calibration schemes may be used to achieve the linearity spec shown above, e.g. calibration at 0.2 x VDDQ and 0.8 x VDDQ. 4. Not a specification requirement, but a design guide line. 5. Measurement Definition for RTT: Apply VIH (AC) to pin under test and measure current I(VIH(AC)), then apply VIL(AC) to pin under test and measure current I(VIL(AC)) respectively. RTT = VIH( AC) - VIL( AC) I( VIH( AC)) - I( VIL( AC)) Data Sheet E1797E41 (Ver. 4.1) 27 EDJ2104EDBG, EDJ2108EDBG 6. Measurement Definition for VM and VM: Measure voltage (VM) at test pin (midpoint) with no load: 2 x VM VM = - 1 x 100 VDDQ ODT Temperature and Voltage Sensitivity If temperature and/or voltage change after calibration, the tolerance limits widen according to the table ODT Sensitivity Definition and ODT Voltage and Temperature Sensitivity. T = T - T (@calibration); V= VDDQ - VDDQ (@calibration); VDD = VDDQ Note: dRTTdT and dRTTdV are not subject to production test but are verified by design and characterization. [ODT Sensitivity Definition] RTT min. max. Unit 0.9 - dRTTdT x |T| - dRTTdV x |V| 1.6 + dRTTdTx|T| + dRTTdV x |V| RZQ/2, 4, 6, 8, 12 [ODT Voltage and Temperature Sensitivity] min. max. Unit dRTTdT 0 1.5 %/C dRTTdV 0 0.15 %/mV ODT Timing Definitions Test Load for ODT Timings Different than for timing measurements, the reference load for ODT timings are defined in ODT Timing Reference Load. VDDQ DUT CK, /CK DQ DQS, /DQS VTT = VSSQ RTT = 25 ODT Timing Reference Load Data Sheet E1797E41 (Ver. 4.1) 28 EDJ2104EDBG, EDJ2108EDBG ODT Measurement Definitions Definitions for tAON, tAONPD, tAOF, tAOFPD and tADC are provided in the following table and subsequent figures. Symbol tAON tAONPD tAOF tAOFPD tADC Begin Point Definition Rising edge of CK - /CK defined by the end point of ODTLon Rising edge of CK - /CK with ODT being first registered high Rising edge of CK - /CK defined by the end point of ODTLoff Rising edge of CK - /CK with ODT being first registered low Rising edge of CK - /CK defined by the end point of ODTLcnw, ODTLcwn4 or ODTLcwn8 End Point Definition Figure Extrapolated point at VSSQ Figure a) Extrapolated point at VSSQ Figure b) End point: Extrapolated point at VRTT_Nom Figure c) End point: Extrapolated point at VRTT_Nom Figure d) End point: Extrapolated point at VRTT_WR and VRTT_Nom respectively Figure e) Reference Settings for ODT Timing Measurements Measurement reference settings are provided in the following Table. Measured Parameter RTT_Nom Setting RTT_WR Setting VSW1 [V] VSW2 [V] tAON RZQ/4 N/A 0.05 0.10 RZQ/12 N/A 0.10 0.20 tAONPD tAOF tAOFPD tADC RZQ/4 N/A 0.05 0.10 RZQ/12 N/A 0.10 0.20 RZQ/4 N/A 0.05 0.10 RZQ/12 N/A 0.10 0.20 RZQ/4 N/A 0.05 0.10 RZQ/12 N/A 0.10 0.20 RZQ/12 RZQ/2 0.20 0.25 Begin point: Rising edge of CK - /CK defined by the end point of ODTLon CK VTT /CK tAON tSW2 DQ, DM DQS, /DQS TDQS, /TDQS tSW1 VSW2 VSSQ VSW1 VSSQ End point: Extrapolated point at VSSQ a) Definition of tAON Data Sheet E1797E41 (Ver. 4.1) 29 Note EDJ2104EDBG, EDJ2108EDBG Begin point: Rising edge of CK - /CK with ODT being first registered high CK VTT /CK tAONPD tSW2 DQ, DM DQS, /DQS TDQS, /TDQS tSW1 VSW2 VSW1 VSSQ VSSQ End point: Extrapolated point at VSSQ b) Definition of tAONPD Begin point: Rising edge of CK - /CK defined by the end point of ODTLoff CK VTT /CK tAOF VRTT_Nom End point: Extrapolated point at VRTT_Nom tSW2 DQ, DM DQS, /DQS TDQS, /TDQS tSW1 VSW2 VSW1 VSSQ c) Definition of tAOF Begin point: Rising edge of CK - /CK with ODT being first registered low CK VTT /CK tAOFPD VRTT_Nom End point: Extrapolated point at VRTT_Nom tSW2 DQ, DM DQS, /DQS TDQS, /TDQS tSW1 VSW2 VSW1 VSSQ d) Definition of tAOFPD Data Sheet E1797E41 (Ver. 4.1) 30 EDJ2104EDBG, EDJ2108EDBG Begin point: Rising edge of CK - /CK defined by the end point of ODTLcnw Begin point: Rising edge of CK - /CK defined by the end point of ODTLcwn4 or ODTLcwn8 CK VTT /CK tADC tADC VRTT_Nom End point: DQ, DM Extrapolated DQS, /DQS point at VRTT_Nom TDQS, /TDQS VRTT_Nom TSW21 TSW11 VSW2 TSW22 TSW12 VSW1 VRTT_Wr End point: Extrapolated point at VRTT_Wr VSSQ e) Definition of tADC Data Sheet E1797E41 (Ver. 4.1) 31 EDJ2104EDBG, EDJ2108EDBG IDD Measurement Conditions (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. The figure Measurement Setup and Test Load for IDD and IDDQ Measurements shows the setup and test load for IDD and IDDQ measurements. * IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R, IDD4W, IDD5B, IDD6, IDD6ET, IDD6TC and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents. * IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents. Note: IDDQ values cannot be directly used to calculate I/O power of the DDR3 SDRAM. They can be used to support correlation of simulated I/O power to actual I/O power as outlined in correlation from simulated channel I/O power to actual channel I/O power supported by IDDQ measurement. For IDD and IDDQ measurements, the following definitions apply: * L and 0: VIN VIL (AC)(max.) * H and 1: VIN VIH (AC)(min.) * FLOATING: is defined as inputs are VREF = VDDQ / 2 * Timings used for IDD and IDDQ measurement-loop patterns are provided in Timings used for IDD and IDDQ Measurement-Loop Patterns table. * Basic IDD and IDDQ measurement conditions are described in Basic IDD and IDDQ Measurement Conditions table. Note: The IDD and IDDQ measurement-loop patterns need to be executed at least one time before actual IDD or IDDQ measurement is started. * Detailed IDD and IDDQ measurement-loop patterns are described in IDD0 Measurement-Loop Pattern table through IDD7 Measurement-Loop Pattern table. * IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting. RON = RZQ/7 (34 in MR1); Qoff = 0B (Output Buffer enabled in MR1); RTT_Nom = RZQ/6 (40 in MR1); RTT_WR = RZQ/2 (120 in MR2); TDQS Feature disabled in MR1 * Define D = {/CS, /RAS, /CAS, /WE} : = {H, L, L, L} * Define /D = {/CS, /RAS, /CAS, /WE} : = {H, H, H, H} Data Sheet E1797E41 (Ver. 4.1) 32 EDJ2104EDBG, EDJ2108EDBG IDDQ IDD VDD /RESET CK, /CK CKE /CS /RAS, /CAS, /WE VDDQ DDR3 SDRAM Address, BA ODT ZQ VSS DQS, /DQS, DQ, DM, TDQS, /TDQS RTT = 25 VDDQ/2 VSSQ Measurement Setup and Test Load for IDD and IDDQ Measurements Application specific memory channel environment Channel I/O power simulation IDDQ Test load IDDQ simulation IDDQ measurement Correlation Correction Channel I/O power number Correlation from Simulated Channel I/O Power to Actual Channel I/O Power Supported by IDDQ Measurement. Data Sheet E1797E41 (Ver. 4.1) 33 EDJ2104EDBG, EDJ2108EDBG Timings used for IDD and IDDQ Measurement-Loop Patterns DDR3L-1600 DDR3L-1333 DDR3L-1066 Parameter 11-11-11 9-9-9 7-7-7 Unit CL 11 9 7 nCK tCK min. 1.25 1.5 1.875 ns nRCD min. 11 9 7 nCK nRC min. 39 33 27 nCK nRAS min. 28 24 20 nCK nRP min. 11 9 7 nCK nFAW 24 20 20 nCK nRRD 5 4 4 nCK nRFC 128 107 86 nCK Data Sheet E1797E41 (Ver. 4.1) 34 EDJ2104EDBG, EDJ2108EDBG Basic IDD and IDDQ Measurement Conditions Parameter Operating one bank active precharge current Operating one bank active-read-precharge current Precharge standby current Precharge standby ODT current Precharge standby ODT IDDQ current Symbol IDD0 IDD1 IDD2N IDD2NT IDDQ2NT Precharge power-down current slow exit IDD2P0 Precharge power-down current fast exit IDD2P1 Precharge quiet standby current IDD2Q Active standby current IDD3N Active power-down current IDD3P Description CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between ACT and PRE; Command, address, bank address inputs: partially toggling according to IDD0 Measurement-Loop Pattern table; Data I/O: FLOATING; DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see IDD0 Measurement2 Loop Pattern table); Output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; Pattern details: see IDD0 Measurement-Loop Pattern table CKE: H; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Timings used for IDD and 1, 6 IDDQ Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between ACT, READ and PRE; Command, address, bank address inputs, data I/O: partially toggling according to IDD1 Measurement-Loop Pattern table; DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... 2 (see IDD1 Measurement-Loop Pattern table); Output buffer and RTT: enabled in MR* ; ODT Signal: stable at 0; Pattern details: see IDD1 Measurement-Loop Pattern table CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ Measurement1 Loop patterns table BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: partially toggling according to IDD2N and IDD3N Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable at 0; bank activity: all 2 banks closed; output buffer and RTT: enabled in mode registers* ; ODT signal: stable at 0; pattern details: see IDD2N and IDD3N Measurement-Loop Pattern table CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ Measurement1 Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: partially toggling according to IDD2NT and IDDQ2NT Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable 2 at 0; bank activity: all banks closed; output buffer and RTT: enabled in MR* ; ODT signal: toggling according to IDD2NT and IDDQ2NT Measurement-Loop pattern table; pattern details: see IDD2NT and IDDQ2NT Measurement-Loop Pattern table Same definition like for IDD2NT, however measuring IDDQ current instead of IDD current CKE: L; External clock: on; tCK, CL: see Timings used for IDD and IDDQ Measurement1 Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address inputs: stable at 0; data I/O: FLOATING; DM: stable at 0; 2 bank activity: all banks closed; output buffer and RTT: EMR * ; ODT signal: stable at 0; 3 precharge power down mode: slow exit* CKE: L; External clock: on; tCK, CL: see Timings used for IDD and IDDQ Measurement1 Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: stable at 0; data I/O: FLOATING; DM:stable at 0; 2 bank activity: all banks closed; output buffer and RTT: enabled in MR* ; ODT signal: stable 3 at 0; precharge power down mode: fast exit* CKE: H; External clock: On; tCK, CL: see Timings used for IDD and IDDQ Measurement1 Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: stable at 0; data I/O: FLOATING; 2 DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in MR* ; ODT signal: stable at 0 CKE: H; External clock: on; tCK, CL: see Table Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address Inputs: partially toggling according to IDD2N and IDD3N Measurement-Loop Pattern; data I/O: FLOATING; DM: stable at 0; 2 bank activity: all banks open; output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD2N and IDD3N Measurement-Loop Pattern table CKE: L; External clock: on; tCK, CL: see Table Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: stable at 1; Command, address, bank address inputs: stable at 0; data I/O: FLOATING; DM:stable at 0; bank activity: all banks open; output buffer and RTT: 2 enabled in MR* ; ODT signal: stable at 0 Data Sheet E1797E41 (Ver. 4.1) 35 EDJ2104EDBG, EDJ2108EDBG Parameter Symbol Description Operating burst read current IDD4R CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ Measurement1, 6 Loop Patterns table; BL: 8* ; AL: 0; /CS: H between READ; Command, address, bank address Inputs: partially toggling according to IDD4R and IDDQ4R Measurement-Loop Pattern table; data I/O: seamless read data burst with different data between one burst and the next one according to IDD4R and IDDQ4R Measurement-Loop Pattern table; DM: stable at 0; bank activity: all banks open, READ commands cycling through banks: 0,0,1,1,2,2,... (see IDD4R and IDDQ4R Measurement-Loop Pattern table); Output buffer and RTT: enabled in 2 MR* ; ODT signal: stable at 0; pattern details: see IDD4R and IDDQ4R Measurement-Loop Pattern table Operating burst read IDDQ current IDDQ4R Same definition like for IDD4R, however measuring IDDQ current instead of IDD current Operating burst write current IDD4W Burst refresh current IDD5B Self-refresh current: normal IDD6 temperature range Self-refresh current: IDD6ET extended temperature range Auto self-refresh current (Optional) IDD6TC Operating bank interleave read current IDD7 RESET low current IDD8 CKE: H; External clock: on; tCK, CL: see Timings used for IDD and IDDQ Measurement1 Loop Patterns table; BL: 8* ; AL: 0; /CS: H between WR; command, address, bank address inputs: partially toggling according to IDD4W Measurement-Loop Pattern table; data I/O: seamless write data burst with different data between one burst and the next one according to IDD4W Measurement-Loop Pattern table; DM: stable at 0; bank activity: all banks open, WR commands cycling through banks: 0,0,1,1,2,2,.. (see IDD4W Measurement-Loop 2 Pattern table); Output buffer and RTT: enabled in MR* ; ODT signal: stable at H; pattern details: see IDD4W Measurement-Loop Pattern table CKE: H; External clock: on; tCK, CL, nRFC: see Timings used for IDD and IDDQ 1 Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS: H between REF; Command, address, bank address Inputs: partially toggling according to IDD5B Measurement-Loop Pattern table; data I/O: FLOATING; DM: stable at 0; bank activity: REF command every nRFC (IDD5B Measurement-Loop Pattern); output 2 buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD5B Measurement-Loop Pattern table 4 TC: 0 to 85C; ASR: disabled* ; SRT: 5 Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: see Timings used for 1 IDD and IDDQ Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable 2 at 0; bank activity: Self-refresh operation; output buffer and RTT: enabled in MR* ; ODT signal: FLOATING 4 5 TC: 0 to 95C; ASR: Disabled* ; SRT: Extended* ; CKE: L; External clock: off; CK and /CK: 1 L; CL: see Timings used for IDD and IDDQ Measurement-Loop Patterns table; BL: 8* ; AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable at 0; bank activity: Extended temperature self-refresh operation; output buffer 2 and RTT: enabled in MR* ; ODT signal: FLOATING 4 5 TC: 0 to 95C; ASR: Enabled* ; SRT: Normal* ; CKE: L; External clock: off; CK and /CK: L; CL: see Table Timings used for IDD and IDDQ Measurement-Loop 1 Patterns table; BL: 8* ; AL: 0; /CS, command, address, bank address, data I/O: FLOATING; DM: stable at 0; bank activity: Auto self-refresh operation; output buffer and RTT: enabled 2 in MR* ; ODT signal: FLOATNG CKE: H; External clock: on; tCK, nRC, nRAS, nRCD, nRRD, nFAW, CL: see Timings used for IDD and IDDQ Measurement-Loop Patterns table; 1, 6 BL: 8* ; AL: CL-1; /CS: H between ACT and READA; Command, address, bank address Inputs: partially toggling according to IDD7 Measurement-Loop Pattern table; data I/O: read data bursts with different data between one burst and the next one according to IDD7 Measurement-Loop Pattern table; DM: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ...7) with different addressing, see IDD7 Measurement-Loop 2 Pattern table; output buffer and RTT: enabled in MR* ; ODT signal: stable at 0; pattern details: see IDD7 Measurement-Loop Pattern table /RESET: low; External clock: off; CK and /CK: low; CKE: FLOATING; /CS, command, address, bank address, Data IO: FLOATING; ODT signal: FLOATING RESET low current reading is valid once power is stable and /RESET has been low for at least 1ms. Data Sheet E1797E41 (Ver. 4.1) 36 EDJ2104EDBG, EDJ2108EDBG Notes: 1. Burst Length: BL8 fixed by MRS: MR0 bits [1,0] = [0,0]. 2. MR: Mode Register Output buffer enable: set MR1 bit A12 = 1 and MR1 bits [5, 1] = [0,1]; RTT_Nom enable: set MR1 bits [9, 6, 2] = [0, 1, 1]; RTT_WR enable: set MR2 bits [10, 9] = [1,0]. 3. Precharge power down mode: set MR0 bit A12= 0 for Slow Exit or MR0 bit A12 = 1 for fast exit. 4. Auto self-refresh (ASR): set MR2 bit A6 = 0 to disable or 1 to enable feature. 5. Self-refresh temperature range (SRT): set MR0 bit A7= 0 for normal or 1 for extended temperature range. 6. Read burst type: nibble sequential, set MR0 bit A3 = 0. Data Sheet E1797E41 (Ver. 4.1) 37 EDJ2104EDBG, EDJ2108EDBG IDD0 Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number 0 Toggling Static H Command /CS /RAS /CAS /WE ODT BA* 0 ACT 0 0 1 1 0 1, 2 D, D 1 0 0 0 3, 4 /D, /D 1 1 1 1 ... Repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE 0 ... Repeat pattern 1...4 until nRC - 1, truncate if necessary 1 x nRC +0 1 x nRC +1, 2, 1 x nRC + 3, 4 0 1 0 A11 -A14 A10 A7 -A9 A3 -A6 A0 -A2 Data* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 ACT 0 0 1 1 0 0 0 0 0 F 0 D, D 1 0 0 0 0 0 0 0 0 F 0 /D, /D 1 1 1 1 0 0 0 0 0 F 0 ... Repeat pattern nRC + 1,...,4 until 1 x nRC + nRAS - 1, truncate if necessary 1 x nRC + nRAS PRE 0 ... Repeat nRC + 1,...,4 until 2 x nRC - 1, truncate if necessary 1 2 x nRC Repeat Sub-Loop 0, use BA= 1 instead 2 4 x nRC Repeat Sub-Loop 0, use BA= 2 instead 3 6 x nRC Repeat Sub-Loop 0, use BA= 3 instead 4 8 x nRC Repeat Sub-Loop 0, use BA= 4 instead 5 10 x nRC Repeat Sub-Loop 0, use BA= 5 instead 6 12 x nRC Repeat Sub-Loop 0, use BA= 6 instead 7 14 x nRC Repeat Sub-Loop 0, use BA= 7 instead 0 1 0 0 0 Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2. Data Sheet E1797E41 (Ver. 4.1) 38 0 0 0 F 0 2 EDJ2104EDBG, EDJ2108EDBG IDD1 Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number Command /CS /RAS /CAS /WE ODT BA* 0 ACT 0 0 1 1 0 1, 2 D, D 1 0 0 0 3, 4 /D, /D 1 1 1 1 ... Repeat pattern 1...4 until nRCD - 1, truncate if necessary nRCD READ 0 ... Repeat pattern 1...4 until nRAS - 1, truncate if necessary nRAS PRE ... Repeat pattern 1...4 until nRC - 1, truncate if necessary 0 Toggling Static H 1 x nRC +0 1 x nRC + 1, 2 1 x nRC + 3, 4 0 1 0 0 1 1 0 A11 -A14 A10 A7 -A9 A3 -A6 A0 -A2 Data* 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000000 0 0 0 0 0 0 0 3 0 0 0 0 2 ACT 0 0 1 1 0 0 0 0 0 F 0 D, D 1 0 0 0 0 0 0 0 0 F 0 /D, /D 1 1 1 1 0 0 0 0 0 F 0 0 00110011 0 ... Repeat pattern nRC + 1,..., 4 until nRC + nRCD - 1, truncate if necessary 1 x nRC + nRCD READ 0 ... Repeat pattern nRC + 1,..., 4 until nRC +nRAS - 1, truncate if necessary 1 x nRC + nRAS PRE 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 ... Repeat pattern nRC + 1,..., 4 until 2 * nRC - 1, truncate if necessary 1 2 x nRC Repeat Sub-Loop 0, use BA= 1 instead 2 4 x nRC Repeat Sub-Loop 0, use BA= 2 instead 3 6 x nRC Repeat Sub-Loop 0, use BA= 3 instead 4 8 x nRC Repeat Sub-Loop 0, use BA= 4 instead 5 10 x nRC Repeat Sub-Loop 0, use BA= 5 instead 6 12 x nRC Repeat Sub-Loop 0, use BA= 6 instead 7 14 x nRC Repeat Sub-Loop 0, use BA= 7 instead F F Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2. Data Sheet E1797E41 (Ver. 4.1) 39 EDJ2104EDBG, EDJ2108EDBG IDD2N and IDD3N Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number 0 Command /CS /RAS /CAS /WE ODT BA* 0 D 1 0 0 0 0 1 D 1 0 0 0 0 A11 -A14 A10 A7 -A9 A3 -A6 A0 -A2 Data* 0 0 0 0 0 0 0 0 0 0 0 0 3 2 /D 1 1 1 1 0 0 0 0 0 F 0 3 /D 1 1 1 1 0 0 0 0 0 F 0 4 to 7 Repeat Sub-Loop 0, use BA= 1 instead 8 to 11 Repeat Sub-Loop 0, use BA= 2 instead 3 12 to 15 Repeat Sub-Loop 0, use BA= 3 instead 4 16 to 19 Repeat Sub-Loop 0, use BA= 4 instead 5 20 to 23 Repeat Sub-Loop 0, use BA= 5 instead 6 24 to 27 Repeat Sub-Loop 0, use BA= 6 instead 7 28 to 31 Repeat Sub-Loop 0, use BA= 7 instead A11 -A14 A10 A7 -A9 A3 -A6 A0 -A2 Data* 1 Toggling Static H 2 2 Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2. IDD2NT and IDDQ2NT Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number Command /CS /RAS /CAS /WE ODT BA* 0 D 1 0 0 0 0 0 0 0 0 0 0 1 D 1 0 0 0 0 0 0 0 0 0 0 2 /D 1 1 1 1 0 0 0 0 0 F 0 3 /D 1 1 1 1 0 0 0 0 0 F 0 4 to 7 Repeat Sub-Loop 0, but ODT = 0 and BA= 1 8 to 11 Repeat Sub-Loop 0, but ODT = 1 and BA= 2 3 12 to 15 Repeat Sub-Loop 0, but ODT = 1 and BA= 3 4 16 to 19 Repeat Sub-Loop 0, but ODT = 0 and BA= 4 5 20 to 23 Repeat Sub-Loop 0, but ODT = 0 and BA= 5 6 24 to 27 Repeat Sub-Loop 0, but ODT = 1 and BA= 6 7 28 to 31 Repeat Sub-Loop 0, but ODT = 1 and BA= 7 0 1 Toggling Static H 2 3 Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2. Data Sheet E1797E41 (Ver. 4.1) 40 2 EDJ2104EDBG, EDJ2108EDBG IDD4R and IDDQ4R Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number Command /CS /RAS /CAS /WE ODT BA* 0 READ 0 1 0 1 0 1 D 1 0 0 0 0 2, 3 /D, /D 1 1 1 1 0 0 0 0 0 0 0 4 READ 0 1 0 1 0 0 0 0 0 F 0 00110011 0 Toggling Static H A11 -A14 A10 A7 A3 A0 -A9 -A6 -A2 Data* 0 0 0 0 0 0 00000000 0 0 0 0 0 0 3 5 D 1 0 0 0 0 0 0 0 0 F 0 6, 7 /D, /D 1 1 1 1 0 0 0 0 0 F 0 1 8 to 15 Repeat Sub-Loop 0, but BA= 1 2 16 to 23 Repeat Sub-Loop 0, but BA= 2 3 24 to 31 Repeat Sub-Loop 0, but BA= 3 4 32 to 39 Repeat Sub-Loop 0, but BA= 4 5 40 to 47 Repeat Sub-Loop 0, but BA= 5 6 48 to 55 Repeat Sub-Loop 0, but BA= 6 7 56 to 63 Repeat Sub-Loop 0, but BA= 7 Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2. Data Sheet E1797E41 (Ver. 4.1) 41 2 EDJ2104EDBG, EDJ2108EDBG IDD4W Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number Command /CS /RAS /CAS /WE ODT BA* 0 WRIT 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 F 0 00110011 1 D 1 0 0 0 A11 -A14 A7 A10 -A9 A3 -A6 A0 -A2 Data* 0 0 0 0 0 0 00000000 0 0 0 0 0 0 3 2, 3 /D, /D 1 1 1 1 1 4 WRIT 0 1 0 0 1 5 D 1 0 0 0 1 0 0 0 0 F 0 6, 7 /D, /D 1 1 1 1 1 0 0 0 0 F 0 8 to 15 Repeat Sub-Loop 0, but BA= 1 2 16 to 23 Repeat Sub-Loop 0, but BA= 2 3 24 to 31 Repeat Sub-Loop 0, but BA= 3 4 32 to 39 Repeat Sub-Loop 0, but BA= 4 5 40 to 47 Repeat Sub-Loop 0, but BA= 5 6 48 to 55 Repeat Sub-Loop 0, but BA= 6 7 56 to 63 Repeat Sub-Loop 0, but BA= 7 0 Toggling Static H 1 2 Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to write commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by write command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2. IDD5B Measurement-Loop Pattern CK, /CK CKE Sub Cycle -Loop number Command /CS /RAS /CAS /WE ODT BA* 0 Toggling Static H 1 2 3 A11 -A14 A10 A7 -A9 A3 -A6 A0 -A2 Data* 0 REF 0 0 0 1 0 0 0 0 0 0 0 1, 2 D 1 0 0 0 0 0 0 0 0 0 0 3, 4 /D, /D 1 1 1 1 0 0 0 0 0 F 0 5 to 8 Repeat cycles 1...4, but BA= 1 9 to 12 Repeat cycles 1...4, but BA= 2 13 to 16 Repeat cycles 1...4, but BA= 3 17 to 20 Repeat cycles 1...4, but BA= 4 21 to 24 Repeat cycles 1...4, but BA= 5 25 to 28 Repeat cycles 1...4, but BA= 6 29 to 32 Repeat cycles 1...4, but BA= 7 33 to Repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary. nRFC - 1 Notes: 1. DM must be driven low all the time. DQS, /DQS are FLOATING. 2. DQ signals are FLOATING. 3. BA: BA0 to BA2. Data Sheet E1797E41 (Ver. 4.1) 42 2 EDJ2104EDBG, EDJ2108EDBG IDD7 Measurement-Loop Pattern CK, /CK CKE Sub -Loop 0 1 Command /CS /RAS /CAS /WE ODT BA* 0 ACT 0 0 1 1 0 0 0 0 0 0 0 1 READA 0 1 0 1 0 0 0 1 0 0 0 00000000 2 D 1 0 0 0 0 0 0 0 0 0 0 ... Repeat above D Command until nRRD - 1 ACT 0 0 1 1 0 1 0 0 0 F 0 READA 0 1 0 1 0 1 0 1 0 F 0 00110011 nRRD + 2 D 1 0 0 0 0 1 0 0 0 F 0 0 0 0 F 0 F 0 Repeat above D Command until 2 x nRRD - 1 2 x nRRD Repeat Sub-Loop 0, but BA= 2 3 3 x nRRD Repeat Sub-Loop 1, but BA= 3 4 4 x nRRD 5 nFAW 8 9 Static H 10 nFAW + nRRD nFAW + 2 x nRRD nFAW + 3 x nRRD nFAW + 4nRRD 2 x nFAW +0 2 x nFAW +1 2 x nFAW +2 11 2 x nFAW + nRRD 2 x nFAW + nRRD + 1 2 x nFAW + nRRD + 2 12 13 A11 A7 A3 A0 2 Data* -A14 A10 -A9 -A6 -A2 nRRD + 1 ... 7 3 nRRD 2 6 Toggling Cycle number 2 x nFAW +2 x nRRD 2 x nFAW + 3 x nRRD D 1 0 0 0 0 3 Assert and repeat above D Command until nFAW - 1, if necessary Repeat Sub-Loop 0, but BA= 4 Repeat Sub-Loop 1, but BA= 5 Repeat Sub-Loop 0, but BA= 6 Repeat Sub-Loop 1, but BA= 7 D 1 0 0 0 0 7 0 0 0 Assert and repeat above D Command until 2 x nFAW - 1, if necessary ACT 0 0 1 1 0 0 0 0 0 F 0 READA 0 1 0 1 0 0 0 1 0 F 0 00110011 D 1 0 0 0 0 0 0 0 0 F 0 Repeat above D Command until 2 x nFAW + nRRD - 1 ACT 0 0 1 1 0 1 0 0 0 0 0 READA 0 1 0 1 0 1 0 1 0 0 0 00000000 D 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 Repeat above D Command until 2 x nFAW + 2 x nRRD - 1 Repeat Sub-Loop 10, but BA= 2 Repeat Sub-Loop 11, but BA= 3 D 1 0 0 0 0 3 0 0 14 2 x nFAW + 4 x nRRD Assert and repeat above D Command until 3 x nFAW - 1, if necessary 15 3 x nFAW Repeat Sub-Loop 10, but BA= 4 16 17 18 19 3 xnFAW +nRRD 3 x nFAW + 2 x nRRD 3 x nFAW + 3 x nRRD 3 x nFAW + 4 x nRRD Repeat Sub-Loop 11, but BA= 5 Repeat Sub-Loop 10, but BA= 6 Repeat Sub-Loop 11, but BA= 7 D 1 0 0 0 0 7 0 0 0 0 Assert and repeat above D Command until 4 x nFAW - 1, if necessary Data Sheet E1797E41 (Ver. 4.1) 43 EDJ2104EDBG, EDJ2108EDBG Notes: 1. DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise FLOATING. 2. Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are FLOATING. 3. BA: BA0 to BA2. Data Sheet E1797E41 (Ver. 4.1) 44 EDJ2104EDBG, EDJ2108EDBG Electrical Specifications DC Characteristics 1 (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) x4 Parameter Symbol Operating current (ACT-PRE) IDD0 Operating current (ACT-READ-PRE) IDD1 IDD2P1 Precharge power-down standby current IDD2P0 Precharge standby current IDD2N Precharge standby ODT current IDD2NT Precharge quiet standby current IDD2Q Active power-down current (Always fast exit) IDD3P Active standby current IDD3N Operating current (Burst read operating) IDD4R Operating current (Burst write operating) IDD4W Burst refresh current IDD5B All bank interleave read current IDD7 RESET low current IDD8 x8 Data rate (Mbps) max. max. 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 1600 1333 1066 55 50 45 65 60 55 20 18 18 12 12 12 33 30 27 33 30 27 33 30 27 30 27 27 43 40 37 105 95 85 110 100 90 175 170 170 175 165 145 55 50 45 65 60 55 20 18 18 12 12 12 33 30 27 33 30 27 33 30 27 30 27 27 43 40 37 110 100 90 115 105 95 175 170 170 180 170 150 12 12 Data Sheet E1797E41 (Ver. 4.1) 45 Unit Notes mA mA mA Fast PD Exit mA Slow PD Exit mA mA mA mA mA mA mA mA mA mA EDJ2104EDBG, EDJ2108EDBG Self-Refresh Current (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V) Parameter Self-refresh current normal temperature range Self-refresh current extended temperature range Auto self-refresh current (Optional) x4 x8 max. max. Unit IDD6 12 12 mA IDD6ET 18 18 mA IDD6TC mA Symbol Grade Data Sheet E1797E41 (Ver. 4.1) 46 Notes EDJ2104EDBG, EDJ2108EDBG Pin Capacitance (TC = 25C, VDD, VDDQ = 1.283V to 1.45V) Parameter Symbol Input pin capacitance, CK and /CK DDR3L-1600, 1333 CCK Pins CK, /CK DDR3L-1066 Delta input pin capacitance, CK and /CK CDCK Input pin capacitance, control pins DDR3L-1600, 1333 CIN_CTRL /CS, CKE, ODT DDR3L-1066 Input pin capacitance, address and command pins DDR3L-1600, 1333 /RAS, /CAS, /WE, Address CIN_ADD_CMD DDR3L-1066 Delta input pin capacitance, control pins DDR3L-1600, 1333 CDIN_CTRL /CS, CKE, ODT DDR3L-1066 Delta input pin capacitance, address and command pins DDR3L-1600, 1333 CDIN_ADD_CMD /RAS, /CAS, /WE, Address DDR3L-1066 Input/output pin capacitance DDR3L-1600, 1333 CIO DQ, DQS, /DQS, TDQS, /TDQS, DM DDR3L-1066 Delta input/output pin capacitance CDIO Delta input/output pin capacitance DDR3L-1600, 1333 CDDQS DQS, /DQS DDR3L-1066 Input/output pin capacitance of ZQ CZQ ZQ min. max. Unit Notes 0.8 1.4 pF 1, 3 0.8 1.6 pF 1, 3 0 0.15 pF 1, 2 0.75 1.3 pF 1 0.75 1.3 pF 1 0.75 1.3 pF 1 0.75 1.3 pF 1 -0.4 0.2 pF 1, 4 -0.5 0.3 pF 1, 4 -0.4 0.4 pF 1, 5 -0.5 0.5 pF 1, 5 1.5 2.3 pF 1, 6 1.5 2.5 pF 1, 6 -0.5 0.3 pF 1, 7, 8 0 0.15 pF 1, 10 0 0.2 pF 1, 10 3 pF 1, 9 Notes: 1. VDD, VDDQ, VSS, VSSQ applied and all other pins (except the pin under test) floating. VDD = VDDQ =1.35V, VBIAS=VDD/2. 2. Absolute value of CCK(CK-pin) - CCK(/CK-pin). 3. CCK (min.) will be equal to CIN (min.) 4. CDIN_CTRL = CIN_CTRL - 0.5 x (CCK(CK-pin) + CCK(/CK-pin)) 5. CDIN_ADD_CMD = CIN_ADD_CMD - 0.5 x (CCK(CK-pin) + CCK(/CK-pin)) 6. Although the DM, TDQS and /TDQS pins have different functions, the loading matches DQ and DQS. 7. DQ should be in high impedance state. 8. CDIO = CIO (DQ, DM) -0.5 x (CIO(DQS-pin) + CIO(/DQS-pin)). 9. Maximum external load capacitance on ZQ pin: 5pF. 10. Absolute value of CIO(DQS) - CIO(/DQS). Data Sheet E1797E41 (Ver. 4.1) 47 EDJ2104EDBG, EDJ2108EDBG Standard Speed Bins [DDR3L-1600 Speed Bins] Speed Bin DDR3L-1600K CL-tRCD-tRP Symbol 11-11-11 /CAS write latency min. max. Unit Notes tAA 13.125 20 ns 9 tRCD 13.125 ns 9 tRP 13.125 ns 9 tRC 48.125 ns 9 tRAS 35 9 x tREFI ns 8 tCK (avg) @CL=5 tCK (avg) @CL=6 tCK (avg) @CL=7 tCK (avg) @CL=8 tCK (avg) @CL=9 tCK (avg) @CL=10 tCK (avg) @CL=11 CWL = 5 3.0 3.3 ns 1, 2, 3, 4, 7 CWL = 6, 7, 8 Reserved Reserved ns 4 CWL = 5 2.5 3.3 ns 1, 2, 3, 7 CWL = 6 Reserved Reserved ns 4 CWL = 7, 8 Reserved Reserved ns 4 CWL = 5 Reserved Reserved ns 4 CWL = 6 1.875 < 2.5 ns 1, 2, 3, 4, 7 CWL = 7 Reserved Reserved ns 4 CWL = 8 Reserved Reserved ns 4 CWL = 5 Reserved Reserved ns 4 CWL = 6 1.875 < 2.5 ns 1, 2, 3, 7 CWL = 7 Reserved Reserved ns 4 CWL = 8 Reserved Reserved ns 4 CWL = 5, 6 Reserved Reserved ns 4 CWL= 7 1.5 < 1.875 ns 1, 2, 3, 4, 7 CWL= 8 Reserved Reserved ns 4 CWL = 5, 6 Reserved Reserved ns 4 CWL= 7 1.5 < 1.875 ns 1, 2, 3, 7 CWL= 8 Reserved Reserved ns 4 CWL = 5, 6, 7 Reserved Reserved ns 4 CWL= 8 1.25 < 1.5 ns 1, 2, 3 Supported CL settings Supported CWL settings 5, 6, 7, 8, 9, 10, 11 nCK 5, 6, 7, 8 nCK Data Sheet E1797E41 (Ver. 4.1) 48 EDJ2104EDBG, EDJ2108EDBG [DDR3L-1333 Speed Bins] Speed Bin DDR3L-1333H CL-tRCD-tRP Symbol 9-9-9 /CAS write latency min. max. Unit Notes tAA 13.125 20 ns 9 tRCD 13.125 ns 9 tRP 13.125 ns 9 tRC 49.125 ns 9 tRAS 36 9 x tREFI ns 8 tCK (avg) @CL=5 tCK (avg) @CL=6 tCK (avg) @CL=7 tCK (avg) @CL=8 tCK (avg) @CL=9 tCK (avg) @CL=10 CWL = 5 3.0 3.3 ns 1, 2, 3, 4, 6 CWL = 6, 7 Reserved Reserved ns 4 CWL = 5 2.5 3.3 ns 1, 2, 3, 6 CWL = 6 Reserved Reserved ns 4 CWL = 7 Reserved Reserved ns 4 CWL = 5 Reserved Reserved ns 4 CWL = 6 1.875 < 2.5 ns 1, 2, 3, 4, 6 CWL = 7 Reserved Reserved ns 4 CWL = 5 Reserved Reserved ns 4 CWL = 6 1.875 < 2.5 ns 1, 2, 3, 6 CWL = 7 Reserved Reserved ns 4 CWL = 5, 6 Reserved Reserved ns 4 CWL= 7 1.5 < 1.875 ns 1, 2, 3, 4 CWL = 5, 6 Reserved Reserved ns 4 CWL= 7 1.5 < 1.875 ns 1, 2, 3 Supported CL settings Supported CWL settings 5, 6, 7, 8, 9, 10 nCK 5, 6, 7 nCK Data Sheet E1797E41 (Ver. 4.1) 49 EDJ2104EDBG, EDJ2108EDBG [DDR3L-1066 Speed Bins] Speed Bin DDR3L-1066F CL-tRCD-tRP 7-7-7 Symbol /CAS write latency min. max. Unit Notes tAA 13.125 20 ns 9 tRCD 13.125 ns 9 tRP 13.125 ns 9 tRC 50.625 ns 9 tRAS 37.5 9 x tREFI ns 8 CWL = 5 3.0 3.3 ns 1, 2, 3, 4, 5 CWL = 6 Reserved Reserved ns 4 CWL = 5 2.5 3.3 ns 1, 2, 3, 5 CWL = 6 Reserved Reserved ns 4 tCK (avg) @CL=5 tCK (avg) @CL=6 tCK (avg) @CL=7 tCK (avg) @CL=8 CWL = 5 Reserved Reserved ns 4 CWL = 6 1.875 < 2.5 ns 1, 2, 3, 4 CWL = 5 Reserved Reserved ns 4 1.875 < 2.5 ns 1, 2, 3 CWL = 6 Supported CL settings 5, 6, 7, 8 nCK Supported CWL settings 5, 6 nCK Notes: 1. The CL setting and CWL setting result in tCK (avg) (min.) and tCK (avg) (max.) requirements. When making a selection of tCK (avg), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting. 2. tCK (avg) (min.) limits: Since /CAS latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK (avg) value (2.5, 1.875, 1.5, or 1.25ns) when calculating CL (nCK) = tAA (ns) / tCK (avg)(ns), rounding up to the next `Supported CL'. 3. tCK (avg) (max.) limits: Calculate tCK (avg) + tAA (max.)/CL selected and round the resulting tCK (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875ns or 1.25ns). This result is tCK (avg) (max.) corresponding to CL selected. 4. Reserved' settings are not allowed. User must program a different value. 5. Any DDR3L-1066 speed bin also supports functional operation at lower frequencies as shown in the table DDR3L-1066 Speed Bins which are not subject to production tests but verified by design/characterization. 6. Any DDR3L-1333 speed bin also supports functional operation at lower frequencies as shown in the table DDR3L-1333 Speed Bins which is not subject to production tests but verified by design/characterization. 7. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table DDR3L-1600 Speed Bins which is not subject to production tests but verified by design/characterization. 8. tREFI depends on operating case temperature (TC). 9. For devices supporting optional down binning to CL = 7 and CL = 9, tAA/tRCD/tRP(min.) must be 13.125 ns or lower. SPD settings must be programmed to match. Data Sheet E1797E41 (Ver. 4.1) 50 EDJ2104EDBG, EDJ2108EDBG AC Characteristics (TC = 0C to +85C, VDD, VDDQ = 1.283V to 1.45V, VSS, VSSQ = 0V) * New units tCK(avg) and nCK, are introduced in DDR3. tCK(avg): actual tCK(avg) of the input clock under operation. nCK: one clock cycle of the input clock, counting the actual clock edges. AC Characteristics [DDR3L-1600, 1333] Data rate (Mbps) -GN -DJ 1600 1333 Parameter Symbol min. max. min. max. Unit Average clock cycle time tCK (avg) 1250 3333 1500 3333 ps Minimum clock cycle time (DLL-off mode) tCK (DLL-off) 8 8 ns Average CK high-level width tCH (avg) 0.47 0.53 0.47 0.53 tCK (avg) Average CK low-level width tCL (avg) 0.47 0.53 0.47 0.53 tCK (avg) Active to read or write command delay tRCD 13.125 13.125 ns 26 Precharge command period tRP 13.125 13.125 ns 26 Active to active/auto-refresh command time tRC 48.125 49.125 ns 26 Active to precharge command tRAS 35 9 x tREFI 36 9 x tREFI ns 26 Active bank A to active bank B command period tRRD 6 26, 27 tRRD 4 4 nCK 26, 27 Four active window tFAW 30 30 ns 26 Address and control input hold time (VIH/VIL (DC90) levels) Address and control input setup time (VIH/VIL (AC160) levels) Address and control input setup time (VIH/VIL (AC135) levels) DQ and DM input hold time (VIH/VIL (DC90) levels) DQ and DM input setup time (VIH/VIL (AC160) levels) DQ and DM input setup time (VIH/VIL (AC135) levels) Control and Address input pulse width for each input DQ and DM input pulse width for each input tIH (base) DC90 130 150 ps 16, 23 tIS (base) AC160 60 80 ps 16, 23 tIS (base) AC135 185 205 ps 16, 23, 31 55 75 ps 17, 25 ps 17, 25 25 45 ps 17, 25 tIPW 560 620 ps 32 tDIPW 360 400 ps 32 DQ high-impedance time tHZ (DQ) 225 250 ps DQ low-impedance time tLZ (DQ) -450 225 -500 250 ps tDH (base) DC90 tDS (base) AC160 tDS (base) AC135 6 ns DQS, /DQS high-impedance time (RL + BL/2 reference) DQS, /DQS low-impedance time (RL - 1 reference) DQS, /DQS to DQ skew, per group, per access tHZ (DQS) 225 250 ps tLZ (DQS) -450 225 -500 250 ps tDQSQ 100 125 ps /CAS to /CAS command delay tCCD 4 4 nCK tQH 0.38 0.38 tCK (avg) tDQSCK -225 225 -255 255 ps DQ output hold time from DQS, /DQS DQS, /DQS rising edge output access time from rising CK, /CK Data Sheet E1797E41 (Ver. 4.1) 51 Notes 6 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13 12, 13, 38 12, 13, 37 EDJ2104EDBG, EDJ2108EDBG Data rate (Mbps) Parameter -GN -DJ 1600 1333 Symbol min. max. min. max. Unit Notes tDQSS -0.27 0.27 -0.25 0.25 tCK (avg) 24 tDSH 0.18 0.2 tCK (avg) 24, 36 tDSS 0.18 0.2 tCK (avg) 24, 36 DQS input high pulse width tDQSH 0.45 0.55 0.45 0.55 tCK (avg) 34, 35 DQS input low pulse width tDQSL 0.45 0.55 0.45 0.55 tCK (avg) DQS latching rising transitions to associated clock edges DQS falling edge hold time from rising CK DQS falling edge setup time to rising CK DQS output high time tQSH 0.40 0.40 tCK (avg) DQS output low time tQSL 0.40 0.40 tCK (avg) Mode register set command cycle time tMRD 4 4 nCK tMOD 15 15 ns tMOD 12 12 nCK Mode register set command update delay 33, 35 12, 13, 38 12, 13, 38 27 27 13, 19, 38 11, 13, 38 Read preamble tRPRE 0.9 0.9 tCK (avg) Read postamble tRPST 0.3 0.3 tCK (avg) Write preamble tWPRE 0.9 0.9 tCK (avg) 1 Write postamble tWPST 0.3 0.3 tCK (avg) 1 Write recovery time tWR 15 15 ns 26 tDAL WR + RU (tRP/tCK (avg)) WR + RU (tRP/tCK (avg)) nCK tMPRR 1 1 nCK Auto precharge write recovery + precharge time Multi-Purpose register recovery time Read to write command delay (BC4MRS, BC4OTF) tRTW RL + tCCD/2 + 2nCK - WL RL + tCCD + 2nCK - WL RL + tCCD/2 + 2nCK - WL RL + tCCD + 2nCK - WL (BL8MRS, BL8OTF) tRTW Internal write to read command delay tWTR 7.5 7.5 ns tWTR 4 4 nCK Internal read to precharge command delay Active to READ with auto precharge command delay Minimum CKE low width for selfrefresh entry to exit timing Valid clock requirement after selfrefresh entry or power-down entry 18, 26, 27 18, 26, 27 tRTP 7.5 7.5 ns 26, 27 tRTP 4 4 nCK 26, 27 tRAP tRCD min tRCD min tCKESR tCKE (min.) + 1nCK tCKE (min.) + 1nCK tCKSRE 10 10 ns 27 tCKSRE 5 5 nCK 27 10 10 ns 27 5 tCKSRX Valid clock requirement before self-refresh exit or power-down exit tCKSRX Exit self-refresh to commands not requiring a locked DLL 29 28 5 nCK 27 tXS tRFC (min.) + 10 tRFC (min.) + 10 ns 27 tXS 5 5 nCK 27 Data Sheet E1797E41 (Ver. 4.1) 52 EDJ2104EDBG, EDJ2108EDBG Data rate (Mbps) Parameter Symbol Exit self-refresh to commands requiring tXSDLL a locked DLL Auto-refresh to active/auto-refresh tRFC command time Average periodic refresh interval tREFI (0C TC +85C) -GN -DJ 1600 1333 min. max. min. max. Unit tDLLK (min.) tDLLK (min.) nCK 160 160 ns 7.8 7.8 s Notes (+85C < TC +95C) tREFI 3.9 3.9 s CKE minimum pulse width (high and low pulse width) tCKE 5 5.625 ns 27 tCKE 3 3 nCK 27 tXPR tRFC (min.)+10 tRFC (min.)+10 ns 27 tXPR 5 5 nCK 27 DLL locking time tDLLK 512 512 nCK Power-down entry to exit time tPD Exit reset from CKE high to a valid command tCKE (min.) 9 x tREFI tCKE (min.) 9 x tREFI Exit precharge power-down with DLL frozen to commands requiring a locked tXPDLL DLL 24 24 ns 2 tXPDLL 10 10 nCK 2 tXP 6 6 ns 27 tXP 3 3 nCK 27 tCPDED 1 1 nCK tACTPDEN 1 1 nCK 20 tPRPDEN 1 1 nCK 20 tRDPDEN RL + 4 + 1 RL + 4 + 1 nCK tWRPDEN WL + 4 + tWR/tCK (avg) WL + 4 + tWR/tCK (avg) nCK 9 (BC4MRS) tWRPDEN WL + 2 + tWR/tCK (avg) WL + 2 + tWR/tCK (avg) nCK 9 Timing of last WRITA command to power-down entry (BL8MRS, BL8OTF, BC4OTF) tWRAPDEN WL + 4 + WR + 1 WL + 4 + WR + 1 nCK 10 (BC4MRS) tWRAPDEN WL + 2 + WR + 1 WL + 2 + WR + 1 nCK 10 1 1 nCK 20, 21 tMOD (min.) tMOD (min.) Exit power-down with DLL on to any valid command; Exit precharge power- down with DLL frozen to commands not requiring a locked DLL Command pass disable/enable delay Timing of last ACT command to powerdown entry Timing of last PRE command to powerdown entry Timing of last READ/READA command to power-down entry Timing of last WRIT command to power-down entry (BL8MRS, BL8OTF, BC4OTF) Timing of last REF command to powertREFPDEN down entry Timing of last MRS command to tMRSPDEN power-down entry Data Sheet E1797E41 (Ver. 4.1) 53 15 EDJ2104EDBG, EDJ2108EDBG ODT AC Electrical Characteristics [DDR3L-1600, 1333] Data rate (Mbps) -GN -DJ 1600 1333 Parameter Symbol min. max. min. max. Unit Notes RTT turn-on tAON -225 225 -250 250 ps 7, 12, 37 tAONPD 2 8.5 2 8.5 ns tAOF 0.3 0.7 0.3 0.7 tCK (avg) tAOFPD 2 8.5 2 8.5 ns tANPD WL - 1 WL - 1 nCK ODT turn-on Latency ODTLon WL - 2 WL - 2 WL - 2 WL - 2 nCK ODT turn-off Latency ODTLoff WL - 2 WL - 2 WL - 2 WL - 2 nCK ODTLcnw WL - 2 WL - 2 WL - 2 WL - 2 nCK ODTLcwn4 4 + ODTLoff 4 + ODTLoff nCK ODTLcwn8 6 + ODTLoff 6 + ODTLoff nCK ODTH4 4 4 nCK ODTH8 6 6 nCK tADC 0.3 0.7 0.3 0.7 tCK (avg) tZQinit 512 512 nCK tZQoper 256 256 nCK tZQCS 64 64 nCK Asynchronous RTT turn-on delay (Power-down with DLL frozen) RTT_Nom and RTT_WR turn-off time from ODTLoff reference Asynchronous RTT turn-off delay (Power-down with DLL frozen) ODT to power-down entry/exit latency ODT Latency for changing from RTT_Nom to RTT_WR ODT Latency for change from RTT_WR to RTT_Nom (BC4) ODT Latency for change from RTT_WR to RTT_Nom (BL8) ODT high time without WRIT command or with WRIT command and BC4 ODT high time with WRIT command and BL8 RTT dynamic change skew Power-up and reset calibration time Normal operation full calibration time Normal operation short calibration time 8, 12, 37 12, 37 30 Write Leveling Characteristics [DDR3L-1600, 1333] Data rate (Mbps) Parameter -GN -DJ 1600 1333 Symbol min. max. min. max. Unit Notes tWLMRD 40 40 nCK 3 tWLDQSEN 25 25 nCK 3 tWLS 165 195 ps tWLH 165 195 ps Write leveling output delay tWLO 0 7.5 0 9 ns Write leveling output error tWLOE 0 2 0 2 ns First DQS pulse rising edge after write leveling mode is programmed DQS, /DQS delay after write leveling mode is programmed Write leveling setup time from rising CK, /CK crossing to rising DQS, /DQS crossing Write leveling hold time from rising DQS, /DQS crossing to rising CK, /CK crossing Data Sheet E1797E41 (Ver. 4.1) 54 EDJ2104EDBG, EDJ2108EDBG AC Characteristics [DDR3L-1066] -AE Data rate (Mbps) 1066 Parameter Symbol min. max. Unit Clock cycle time Average CL = X tCK(avg) 1875 3333 ps Minimum clock cycle time (DLL-off mode) tCK (DLL-off) 8 ns Average duty cycle high-level tCH (avg) 0.47 0.53 tCK (avg) Average duty cycle low-level tCL (avg) 0.47 0.53 tCK (avg) Active to read or write command delay tRCD 13.125 ns 26 Precharge command period tRP 13.125 ns 26 Active to active/auto-refresh command time tRC 50.625 ns 26 Active to precharge command tRAS 37.5 9 x tREFI ns 26 Active bank A to active bank B command period tRRD 7.5 ns 26, 27 tRRD 4 nCK 26, 27 Four active window tFAW 37.5 ns 26 Address and control input hold time (VIH/VIL (DC90) levels) Address and control input setup time (VIH/VIL (AC160) levels) Address and control input setup time (VIH/VIL (AC135) levels) DQ and DM input hold time (VIH/VIL (DC90) levels) DQ and DM input setup time (VIH/VIL (AC160) levels) DQ and DM input setup time (VIH/VIL (AC135) levels) Control and Address input pulse width for each input tIH (base) DC90 210 ps 16, 23 tIS (base) AC160 140 ps 16, 23 tIS (base) AC135 290 ps 16, 23, 31 110 ps 17, 25 40 ps 17, 25 90 ps 17, 25 tIPW 780 ps 32 DQ and DM input pulse width for each input tDIPW 490 ps 32 DQ high-impedance time tHZ (DQ) 300 ps DQ low-impedance time tLZ (DQ) -600 300 ps tHZ (DQS) 300 ps tLZ (DQS) -600 300 ps DQS, /DQS -DQ skew, per group, per access tDQSQ 150 ps /CAS to /CAS command delay tCCD 4 nCK DQ output hold time from DQS, /DQS tQH 0.38 tCK (avg) 12, 13, 38 tDQSCK -300 +300 ps 12, 13, 37 tDQSS -0.25 0.25 tCK (avg) 24 DQS falling edge hold time from rising CK tDSH 0.2 tCK (avg) 24, 36 DQS falling edge setup time to rising CK tDSS 0.2 tCK (avg) 24, 36 DQS, /DQS high-impedance time (RL + BL/2 reference) DQS, /DQS low-impedance time (RL - 1 reference) DQS, /DQS rising edge output access time from rising CK, /CK DQS latching rising transitions to associated clock edges tDH (base) DC90 tDS (base) AC160 tDS (base) AC135 Notes 6 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13, 14, 37 12, 13 DQS input high pulse width tDQSH 0.45 0.55 tCK (avg) 34, 35 DQS input low pulse width tDQSL 0.45 0.55 tCK (avg) 33, 35 Data Sheet E1797E41 (Ver. 4.1) 55 EDJ2104EDBG, EDJ2108EDBG -AE Data rate (Mbps) 1066 Parameter Symbol min. max. Unit Notes DQS output high time tQSH 0.38 tCK (avg) 12, 13, 38 DQS output low time tQSL 0.38 tCK (avg) 12, 13, 38 Mode register set command cycle time tMRD 4 nCK Mode register set command update delay tMOD 15 ns 27 tMOD 12 nCK 27 Read preamble tRPRE 0.9 tCK (avg) 13, 19, 38 Read postamble tRPST 0.3 tCK (avg) 11, 13, 38 Write preamble tWPRE 0.9 tCK (avg) 1 Write postamble tWPST 0.3 tCK (avg) 1 Write recovery time ns 26 tWR 15 Auto precharge write recovery + precharge time tDAL WR + RU (tRP/tCK (avg)) nCK Multi-Purpose register recovery time tMPRR 1 nCK 29 Read to write command delay (BC4MRS, BC4OTF) tRTW (BL8MRS, BL8OTF) tRTW Internal write to read command delay tWTR 7.5 ns 18, 26, 27 tWTR 4 nCK 18, 26, 27 tRTP 7.5 ns 26, 27 tRTP 4 nCK 26, 27 tRCD min tCKE (min.) +1nCK 10 ns 27 tCKSRE 5 nCK 27 tCKSRX 10 ns 27 tCKSRX 5 nCK 27 tXS tRFC (min.) + 10 ns 27 tXS 5 nCK 27 tXSDLL tDLLK (min.) nCK tRFC 160 ns tREFI 7.8 s tREFI 3.9 s Internal read to precharge command delay Active to READ with auto precharge command tRAP delay Minimum CKE low width for self-refresh entry tCKESR to exit timing Valid clock requirement after self-refresh entry tCKSRE or power-down entry Valid clock requirement before self-refresh exit or power-down exit Exit self-refresh to commands not requiring a locked DLL Exit self-refresh to commands requiring a locked DLL Auto-refresh to active/auto-refresh command time Average periodic refresh interval (0C TC +85C) (+85C < TC +95C) RL + tCCD/2 + 2nCK - WL RL + tCCD + 2nCK - WL Data Sheet E1797E41 (Ver. 4.1) 56 28 EDJ2104EDBG, EDJ2108EDBG -AE Data rate (Mbps) 1066 Parameter Symbol min. max. Unit Notes CKE minimum pulse width (high and low pulse width) tCKE 5.625 ns 27 tCKE 3 nCK 27 Exit reset from CKE high to a valid command tXPR tRFC(min.)+10 ns 27 tXPR 5 nCK 27 DLL locking time tDLLK 512 nCK Power-down entry to exit time tPD tCKE (min.) 9 x tREFI Exit precharge power-down with DLL frozen to tXPDLL commands requiring a locked DLL 24 ns 2 tXPDLL 10 nCK 2 tXP 7.5 ns 27 tXP 3 nCK 27 tCPDED 1 nCK tACTPDEN 1 nCK 20 tPRPDEN 1 nCK 20 tRDPDEN RL + 4 + 1 nCK tWRPDEN WL + 4 + tWR/tCK (avg) nCK 9 (BC4MRS) tWRPDEN WL + 2 + tWR/tCK (avg) nCK 9 Timing of last WRITA command to power-down entry (BL8MRS, BL8OTF, BC4OTF) tWRAPDEN WL + 4 + WR + 1 nCK 10 (BC4MRS) tWRAPDEN WL + 2 + WR + 1 nCK 10 tREFPDEN 1 nCK 20, 21 tMRSPDEN tMOD (min.) Fast exit/active precharge power down to any command Command pass disable/enable delay Timing of last ACT command to power-down entry Timing of last PRE command to power-down entry Timing of last READ/READA command to power-down entry Timing of last WRIT command to power-down entry (BL8MRS, BL8OTF, BC4OTF) Timing of last REF command to power-down entry Timing of last MRS command to power-down entry Data Sheet E1797E41 (Ver. 4.1) 57 15 EDJ2104EDBG, EDJ2108EDBG ODT AC Electrical Characteristics [DDR3L-1066] -AE Data rate (Mbps) 1066 Parameter Symbol min. max. Unit Notes RTT turn-on tAON -300 300 ps 7, 12, 37 2 8.5 ns 0.3 0.7 tCK (avg) Asynchronous RTT turn-on delay (Power-down tAONPD with DLL frozen) RTT_Nom and RTT_WR turn-off time from tAOF ODTLoff reference 8, 12, 37 ODT turn-off (Power-down mode) tAOFPD 2 8.5 ns ODT to power-down entry/exit latency tANPD WL - 1 nCK ODT turn-on Latency ODTLon WL - 2 WL - 2 nCK ODT turn-off Latency ODTLoff WL - 2 WL - 2 nCK ODTLcnw WL - 2 WL - 2 nCK ODTLcwn4 4 + ODTLoff nCK ODTLcwn8 6 + ODTLoff nCK ODTH4 4 nCK ODT high time with WRIT command and BL8 ODTH8 6 nCK RTT dynamic change skew tADC 0.3 0.7 tCK (avg) Power-up and reset calibration time tZQinit 512 nCK Normal operation full calibration time tZQoper 256 nCK Normal operation short calibration time tZQCS 64 nCK 30 ODT Latency for changing from RTT_Nom to RTT_WR ODT Latency for change from RTT_WR to RTT_Nom (BC4) ODT Latency for change from RTT_WR to RTT_Nom (BL8) ODT high time without WRIT command or with WRIT command and BC4 12, 37 Write Leveling Characteristics [DDR3L-1066] -AE Data rate (Mbps) Parameter 1066 Symbol min. max. Unit Notes tWLMRD 40 nCK 3 tWLDQSEN 25 nCK 3 tWLS 245 ps tWLH 245 ps Write leveling output delay tWLO 0 9 ns Write leveling output error tWLOE 0 2 ns First DQS pulse rising edge after write leveling mode is programmed DQS, /DQS delay after write leveling mode is programmed Write leveling setup time from rising CK, /CK crossing to rising DQS, /DQS crossing Write leveling hold time from rising DQS, /DQS crossing to rising CK, /CK crossing Data Sheet E1797E41 (Ver. 4.1) 58 EDJ2104EDBG, EDJ2108EDBG Notes for AC Electrical Characteristics Notes: 1. Actual value dependant upon measurement level definitions. See Figure Method for Calculating tWPRE Transitions and Endpoints and see Figure Method for Calculating tWPST Transitions and Endpoints. 2. Commands requiring locked DLL are: READ (and READA) and synchronous ODT commands. 3. The max values are system dependent. 4. WR as programmed in mode register. 5. Value must be rounded-up to next integer value. 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI. 7. ODT turn on time (min.) is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time (max.) is when the ODT resistance is fully on. Both are measured from ODTLon. 8. ODT turn-off time (min.) is when the device starts to turn-off ODT resistance. ODT turn-off time (max.) is when the bus is in high impedance. Both are measured from ODTLoff. 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR/tCK to the next integer. 10. WR in clock cycles as programmed in MR0. 11. The maximum read postamble is bound by tDQSCK (min.) plus tQSH (min.) on the left side and tHZ (DQS) (max.) on the right side. See Figure Clock to Data Strobe Relationship. 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this parameter needs to be derated by TBD. 13. Value is only valid for RON34. 14. Single ended signal parameter. Refer to the section of tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Notes for definition and measurement method. 15. tREFI depends on operating case temperature (TC). 16. tIS(base) and tIH(base) values are for 1V/ns command/address single-ended slew rate and 2V/ns CK, /CK differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except /RESET, VREF(DC) = VREFCA(DC). See Address / Command Setup, Hold and Derating section 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, /DQS differential slew rate. Note for DQ and DM signals, VREF(DC) = VREFDQ(DC). For input only pins except /RESET, VREF(DC) = VREFCA(DC). See Data Setup, Hold and Slew Rate Derating section. 18. Start of internal write transaction is definited as follows: For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (on-the-fly): Rising clock edge 4 clock cycles after WL. For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL. 19. The maximum read preamble is bound by tLZ(DQS)(min.) on the left side and tDQSCK(max.) on the right side. 20. CKE is allowed to be registered low while operations such as row activation, precharge, auto precharge or refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. 21. Although CKE is allowed to be registered low after a refresh command once tREFPDEN(min.) is satisfied, there are cases where additional time such as tXPDLL(min.) is also required. See Figure Power-Down Entry/Exit Clarifications - Case 2. 22. tJIT(duty) = { 0.07 x tCK(avg) - [(0.5 - (min (tCH(avg), tCL(avg))) x tCK(avg)] }. For example, if tCH/tCL was 0.48/0.52, tJIT(duty) would calculate out to 125ps for DDR3-800. The tCH(avg) and tCL(avg) values listed must not be exceeded. 23. These parameters are measured from a command/address signal (CKE, /CS, /RAS, /CAS, /WE, ODT, BA0, A0, A1, etc.) transition edge to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should be met whether clock jitter is present or not. 24. These parameters are measured from a data strobe signal (DQS, /DQS) crossing to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should be met whether clock jitter is present or not. 25. These parameters are measured from a data signal (DM, DQ0, DQ1, etc.) transition edge to its respective data strobe signal (DQS, /DQS) crossing. Data Sheet E1797E41 (Ver. 4.1) 59 EDJ2104EDBG, EDJ2108EDBG 26. For these parameters, the DDR3 SDRAM device is characterized and verified to support tnPARAM [nCK] = RU{tPARAM [ns] / tCK(avg)}, which is in clock cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK(avg)}, which is in clock cycles, if all input clock jitter specifications are met. This means: For DDR3-800 6-6-6, of which tRP = 15ns, the device will support tnRP =RU{tRP / tCK(avg)} = 6, i.e. as long as the input clock jitter specifications are met, precharge command at Tm and active command at Tm+6 is valid even if (Tm+6 - Tm) is less than 15ns due to input clock jitter. 27. These parameters should be the larger of the two values, analog (ns) and number of clocks (nCK). 28. The tRAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. 29. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function. 30. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64nCK for all speed bins assuming the maximum sensitivities specified in the `Output Driver Voltage and Temperature Sensitivity' and `ODT Voltage and Temperature Sensitivity' tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: x x where TSens = max.(dRTTdT, dRONdTM) and VSens = max.(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as: 0.5 = 0.133 128ms (1.5 x 1) + (0.15 x 15) 31. The tIS(base) AC135 specifications are adjusted from the tIS(base) specification by adding an additional 125ps of derating to accommodate for the lower alternate threshold of 135mV and another 25ps to account for the earlier reference point [(160mV - 135mV)/1V/ns]. 32. Pulse width of a input signal is defined as the width between the first crossing of VREF(DC) and the consecutive crossing of VREF(DC). 33. tDQSL describes the instantaneous differential input low pulse width on DQS - /DQS, as measured from one falling edge to the next consecutive rising edge. 34. tDQSH describes the instantaneous differential input high pulse width on DQS -/DQS, as measured from one rising edge to the next consecutive falling edge. 35. tDQSH,act + tDQSL,act = 1tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 36. tDSH,act + tDSS,act = 1tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in the application. 37. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(mper),act of the input clock, where 2 m 12. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tERR(mper),act,min = -172ps and tERR(mper),act,max = +193ps, then tDQSCK,min(derated) = tDQSCK,min - tERR(mper),act,max = -400ps - 193ps = -593ps and tDQSCK,max(derated) =tDQSCK,max - tERR(mper),act,min = 400ps + 172ps = +572ps. Similarly, tLZ(DQ) for DDR3-800 derates to tLZ(DQ),min(derated) = -800ps - 193ps = -993ps and tLZ(DQ),max(derated) = 400ps + 172ps = +572ps. Note that tERR(mper),act,min is the minimum measured value of tERR(nper) where 2 n 12, and tERR(mper),act,max is the maximum measured value of tERR(nper) where 2 n 12. 38. When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR3-800 SDRAM has tCK(avg),act = 2500ps, tJIT(per),act,min = - 72ps and tJIT(per),act,max = +93ps, then tRPRE,min(derated) = tRPRE,min + tJIT(per),act,min = 0.9 x tCK(avg),act + tJIT(per),act,min = 0.9 x 2500ps - 72ps = +2178ps. Similarly, tQH,min(derated) = tQH,min + tJIT(per),act,min = 0.38 x tCK(avg),act + tJIT(per),act,min = 0.38 x 2500ps - 72ps = + 878ps. Data Sheet E1797E41 (Ver. 4.1) 60 EDJ2104EDBG, EDJ2108EDBG Clock Jitter [DDR3L-1600, 1333] Data rate (Mbps) -GN -DJ 1600 1333 Parameter Symbol min. max. min. max. Unit Notes Average clock period tCK (avg) 1250 3333 1500 3333 ps 1 Absolute clock period tCK (abs) tCK(avg)min + tCK(avg)max+ tCK(avg)min + tCK(avg)max+ ps tJIT(per)min tJIT(per)max tJIT(per)min tJIT(per)max 2 Clock period jitter tJIT (per) -70 70 -80 80 ps 6 Clock period jitter during DLL locking period tJIT (per, lck) -60 60 -70 70 ps 6 Cycle to cycle period Jitter tJIT (cc) 140 160 ps 7 Cycle to cycle clock period jitter during DLL locking period tJIT (cc, lck) 120 140 ps 7 Cumulative error across 2 cycles tERR (2per) -103 103 -118 118 ps 8 Cumulative error across 3 cycles tERR (3per) -122 122 -140 140 ps 8 Cumulative error across 4 cycles tERR (4per) -136 136 -155 155 ps 8 Cumulative error across 5 cycles tERR (5per) -147 147 -168 168 ps 8 Cumulative error across 6 cycles tERR (6per) -155 155 -177 177 ps 8 Cumulative error across 7 cycles tERR (7per) -163 163 -186 186 ps 8 Cumulative error across 8 cycles tERR (8per) -169 169 -193 193 ps 8 Cumulative error across 9 cycles tERR (9per) -175 175 -200 200 ps 8 Cumulative error across 10 cycles tERR (10per) -180 180 -205 205 ps 8 Cumulative error across 11 cycles tERR (11per) -184 184 -210 210 ps 8 Cumulative error across 12 cycles tERR (12per) -188 188 -215 215 ps 8 ps 9 Cumulative error across n = 13, 14...49, 50 cycles tERR (nper) tERR (nper) min. = (1+0.68ln(n)) x tJIT(per) min. tERR (nper) max. = (1+0.68ln(n)) x tJIT(per) max. Average high pulse width tCH (avg) 0.47 0.53 0.47 0.53 Average low pulse width tCL (avg) 0.47 0.53 0.47 0.53 Absolute clock high pulse width tCH (abs) 0.43 0.43 Absolute clock low pulse width tCL (abs) 0.43 0.43 Duty cycle jitter tJIT (duty) Data Sheet E1797E41 (Ver. 4.1) 61 tCK (avg) tCK (avg) tCK (avg) tCK (avg) ps 3 4 10, 11 10, 12 5 EDJ2104EDBG, EDJ2108EDBG Clock Jitter [DDR3L-1066] -AE Data rate (Mbps) 1066 Parameter Symbol min. max. Unit Notes Average clock period tCK (avg) 1875 3333 ps 1 Absolute clock period tCK (abs) tCK(avg)min + tJIT(per)min tCK(avg)max+ tJIT(per)max ps 2 Clock period jitter tJIT (per) -90 90 ps 6 Clock period jitter during DLL locking period tJIT (per, lck) -80 80 ps 6 Cycle to cycle period jitter tJIT (cc) 180 ps 7 Cycle to cycle clock period jitter during DLL locking period tJIT (cc, lck) 160 ps 7 Cumulative error across 2 cycles tERR (2per) -132 132 ps 8 Cumulative error across 3 cycles tERR (3per) -157 157 ps 8 Cumulative error across 4 cycles tERR (4per) -175 175 ps 8 Cumulative error across 5 cycles tERR (5per) -188 188 ps 8 Cumulative error across 6 cycles tERR (6per) -200 200 ps 8 Cumulative error across 7 cycles tERR (7per) -209 209 ps 8 Cumulative error across 8 cycles tERR (8per) -217 217 ps 8 Cumulative error across 9 cycles tERR (9per) -224 224 ps 8 Cumulative error across 10 cycles tERR (10per) -231 231 ps 8 Cumulative error across 11 cycles tERR (11per) -237 237 ps 8 Cumulative error across 12 cycles tERR (12per) -242 242 ps 8 Cumulative error across n=13, 14...49,50 cycles tERR (nper) tERR (nper) min. = (1+0.68ln(n)) x tJIT(per) min. tERR (nper) max. = (1+0.68ln(n)) x tJIT(per) max. ps 9 Average high pulse width tCH (avg) 0.47 0.53 tCK (avg) 3 Average low pulse width tCL (avg) 0.47 0.53 tCK (avg) 4 Absolute clock high pulse width tCH (abs) 0.43 tCK (avg) 10, 11 Absolute clock low pulse width tCL (abs) 0.43 tCK (avg) 10, 12 Duty cycle jitter tJIT (duty) ps 5 Notes: 1. tCK (avg) is calculated as the average clock period across any consecutive 200cycle window, where each clock period is calculated from rising edge to rising edge. N tCKj N j=1 N = 200 2. tCK (abs) is the absolute clock period, as measured from one rising edge to the next consecutive rising edge. tCK (abs) is not subject to production test. 3. tCH (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. N (N x tCK(avg)) tCHj j=1 N = 200 Data Sheet E1797E41 (Ver. 4.1) 62 EDJ2104EDBG, EDJ2108EDBG 4. tCL (avg) is defined as the average low pulse width, as calculated across any consecutive 200 low pulses. N (N x tCK(avg)) tCLj j=1 N = 200 5. tJIT (duty) is defined as the cumulative set of tCH jitter and tCL jitter. tCH jitter is the largest deviation of any single tCH from tCH (avg). tCL jitter is the largest deviation of any single tCL from tCL (avg). tJIT (duty) is not subject to production test. tJIT (duty) = Min./Max. of {tJIT (CH), tJIT (CL)}, where: tJIT (CH) = {tCHj- tCH (avg) where j = 1 to 200} tJIT (CL) = {tCLj- tCL (avg) where j = 1 to 200} 6. tJIT (per) is defined as the largest deviation of any single tCK from tCK (avg). tJIT (per) = Min./Max. of { tCKj - tCK (avg) where j = 1 to 200} tJIT (per) defines the single period jitter when the DLL is already locked. tJIT (per, lck) uses the same definition for single period jitter, during the DLL locking period only. tJIT (per) and tJIT (per, lck) are not subject to production test. 7. tJIT (cc) is defined as the absolute difference in clock period between two consecutive clock cycles: tJIT (cc) = Max. of {tCKj+1 - tCKj} tJIT (cc) is defines the cycle when the DLL is already locked. tJIT (cc, lck) uses the same definition for cycle-to-cycle jitter, during the DLL locking period only. tJIT (cc) and tJIT (cc, lck) are not subject to production test. 8. tERR (nper) is defined as the cumulative error across n multiple consecutive cycles from tCK (avg). tERR (nper) is not subject to production test. 9. n = from 13 cycles to 50 cycles. This row defines 38 parameters. 10. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing hold at all times. (minimum and maximum of spec values are to be used for calculations in the table below.) Parameter Symbol Absolute clock period tCK (abs) Absolute clock high pulse width Absolute clock low pulse width tCH (abs) tCL (abs) min. max. Unit tCK (avg)min. + tJIT (per)min. tCK (avg)max. + tJIT (per)max. ps tCH (avg)min. x tCK (avg)min. + tJIT (duty)min. tCL (avg)min. x tCK (avg)min. + tJIT (duty)min. tCH (avg)max. x tCK (avg)max. ps + tJIT (duty)max. tCL (avg)max. x tCK (avg)max. ps + tJIT (duty)max. 11. tCH (abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following falling edge. 12. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising edge. Data Sheet E1797E41 (Ver. 4.1) 63 EDJ2104EDBG, EDJ2108EDBG Bank 7 Bank 6 Bank 5 Bank 4 Bank 3 Bank 2 Bank 1 Address, BA0, BA1, BA2 Mode register Row address buffer and refresh counter Row decoder CK /CK CKE Clock generator Block Diagram Memory cell array Bank 0 Control logic /CS /RAS /CAS /WE Command decoder Sense amp. Column decoder Column address buffer and burst counter Data control circuit Latch circuit CK, /CK DLL Input & Output buffer DQS, /DQS TDQS, /TDQS ODT DM DQ Data Sheet E1797E41 (Ver. 4.1) 64 EDJ2104EDBG, EDJ2108EDBG Pin Function CK, /CK (input pins) CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). /CS (input pin) All commands are masked when /CS is registered high. /CS provides for external rank selection on systems with multiple ranks. /CS is considered part of the command code. /RAS, /CAS, /WE (input pins) /RAS, /CAS and /WE (along with /CS) define the command being entered. A0 to A14 (input pins) Provided the row address for active commands and the column address for read/write commands to select one location out of the memory array in the respective bank. (A10(AP) and A12(/BC) have additional functions, see below) The address inputs also provide the op-code during mode register set commands. [Address Pins Table] Address (A0 to A14) Part number Page size Row address (RA) Column address (CA) EDJ2104EDBG 1KB AX0 to AX14 AY0 to AY9, AY11 AX0 to AX14 AY0 to AY9 EDJ2108EDBG Note A10(AP) (input pin) A10 is sampled during read/write commands to determine whether auto precharge should be performed to the accessed bank after the read/write operation. (high: auto precharge; low: no auto precharge) A10 is sampled during a precharge command to determine whether the precharge applies to one bank (A10 = low) or all banks (A10 = high). If only one bank is to be precharged, the bank is selected by bank addresses (BA). A12(/BC) (input pin) A12 is sampled during read and write commands to determine if burst chop (on-the-fly) will be performed. (A12 = high: no burst chop, A12 = low: burst chopped.) See command truth table for details. BA0 to BA2 (input pins) BA0, BA1 and BA2 define to which bank an active, read, write or precharge command is being applied. BA0 and BA1 also determine which Mode Register (MR0 to MR3) is to be accessed during a MRS cycle. [Bank Select Signal Table] BA0 BA1 BA2 Bank 0 L L L Bank 1 H L L Bank 2 L H L Bank 3 H H L Bank 4 L L H Bank 5 H L H Bank 6 L H H Bank 7 H H H Remark: H: VIH. L: VIL. Data Sheet E1797E41 (Ver. 4.1) 65 EDJ2104EDBG, EDJ2108EDBG CKE (input pin) CKE high activates, and CKE low deactivates, internal clock signals and device input buffers and output drivers. Taking CKE low provides precharge power-down and self-refresh operation (all banks idle), or active power-down (row active in any bank). CKE is asynchronous for self-refresh exit. After VREF has become stable during the power-on and initialization sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout read and write accesses. Input buffers, excluding CK, /CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are disabled during self-refresh. DM (input pins) DM is an input mask signal for write data. Input data is masked when DM is sampled high coincident with that input data during a write access. DM is sampled on both edges of DQS. For x8 configuration, the function of DM or TDQS, /TDQS is enabled by mode register A11 setting in MR1. DQ (input/output pins) Bi-directional data bus. DQS, /DQS (input/output pins) Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data. The data strobe DQS is paired with differential signal /DQS to provide differential pair signaling to the system during READs and WRITEs. TDQS, /TDQS (output pins) TDQS and /TDQS is applicable for x8 configuration only. When enabled via mode register A11 = 1 in MR1, DRAM will enable the same termination resistance function on TDQS, /TDQS as is applied to DQS, /DQS. When disabled via mode register A11 = 0 in MR1, DM/TDQS will provide the data mask function and /TDQS is not used. In x4 configuration, the TDQS function must be disabled via mode register A11 = 0 in MR1. /RESET (input pin) /RESET is a CMOS rail to rail signal with DC high and low at 80% and 20% of VDD (1.20V for DC high and 0.30V for DC low). It is negative active signal (active low) and is referred to GND. There is no termination required on this signal. It will be heavily loaded across multiple chips. /RESET is destructive to data contents. ODT (input pin) ODT (registered high) enables termination resistance internal to the DDR3 SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, DM/TDQS, NU(/TDQS) (when TDQS is enabled via mode register A11 = 1 in MR1) signal for x4/x8 configuration. The ODT pin will be ignored if the Mode Register (MR1) is programmed to disable ODT. ZQ (supply) Reference pin for ZQ calibration. VDD, VSS, VDDQ, VSSQ (power supply pins) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. VREFCA, VREFDQ (power supply pins) Reference voltage Data Sheet E1797E41 (Ver. 4.1) 66 EDJ2104EDBG, EDJ2108EDBG Command Operation Command Truth Table The DDR3 SDRAM recognizes the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. CKE Function Symbol Previous cycle Mode register set MRS H H L L L L BA op-code Auto-refresh REF H H L L L H V Self-refresh entry SELF H L L L L H Self-refresh exit SREX L H H x x L H L H H H L L Single bank precharge PRE Current cycle /CS /RAS /CAS /WE BA0 to BA2 A12 (/BC) A10 (AP) Address V V V V V V V x x x x x H H V V V V H L BA V L V H V Precharge all banks PALL H H L L H L V V Bank activate ACT H H L L H H BA RA Write (Fixed BL) WRIT H H L H L L BA V L CA WRS4 H H L H L L BA L L CA Write (BL8, on the fly) WRS8 H H L H L L BA H L CA WRITA H H L H L L BA V H CA WRAS4 H H L H L L BA L H CA WRAS8 H H L H L L BA H H CA READ H L H L H BA V L CA Read (Fixed BL) H 6, 8, 11 6, 7, 8, 11 12 Write (BC4, on the fly) Write with auto precharge (Fixed BL) Write with auto precharge (BC4, on the fly) Write with auto precharge (BL8, on the fly) Notes Read (BC4, on the fly) RDS4 H H L H L H BA L L CA Read (BL8, on the fly) RDS8 H H L H L H BA H L CA READA H H L H L H BA V H CA RDAS4 H H L H L H BA L H CA RDAS8 H H L H L H BA H H CA No operation NOP H H L H H H V V V V 9 Device deselect DESL H H H x x x x x x x 10 Power-down mode entry PDEN H L H x x x x x x x 5, 11 H L L H H H V V V V H H x x x x x x x Read with auto precharge (Fixed BL) Read with auto precharge (BC4, on the fly) Read with auto precharge (BL8, on the fly) Power-down mode exit PDEX L L H L H H H V V V V ZQ calibration long ZQCL H H L H H L x x H x ZQ calibration short ZQCS H H L H H L x x L x 5, 11 Remark: H = VIH. L = VIL. x = Don't care (defined or undefined (including floating around VREF)) logic level. V = VIH or VIL (defined logic level). BA = Bank addresses. RA = Row Address. CA = Column Address. /BC = Burst Chop. Data Sheet E1797E41 (Ver. 4.1) 67 EDJ2104EDBG, EDJ2108EDBG Notes: 1. All DDR3 commands are defined by states of /CS, /RAS, /CAS, /WE and CKE at the rising edge of the clock. The most significant bit (MSB) of BA, RA, and CA are device density and configuration dependent. 2. /RESET is an active low asynchronous signal that must be driven high during normal operation 3. Bank Addresses (BA) determine which bank is to be operated upon. For MRS, BA selects an mode register. 4. Burst READs or WRITEs cannot be terminated or interrupted and fixed/on the fly BL will be defined by MRS. 5. The power-down mode does not perform any refresh operations. 6. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 7. Self-refresh exit is asynchronous. 8. VREF (both VREFDQ and VREFCA) must be maintained during self-refresh operation. VREFDQ supply may be turned off and VREFDQ may take any value between VSS and VDD during self-refresh operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first write operation or first write leveling activity may not occur earlier than 512 nCK after exit from self-refresh. 9. The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 10. The DESL command performs the same function as a NOP command. 11. Refer to the CKE Truth Table for more detail with CKE transition. 12. No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. No Operation Command [NOP] The No Operation command (NOP) should be used in cases when the DDR3 SDRAM is in an idle or a wait state. The purpose of the NOP command is to prevent the DDR3 SDRAM from registering any unwanted commands between operations. A NOP command will not terminate a previous operation that is still executing, such as a burst read or write cycle. The no operation (NOP) command is used to instruct the selected DDR3 SDRAM to perform a NOP (/CS low, /RAS, /CAS, /WE high). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Device Deselect Command [DESL] The deselect function (/CS high) prevents new commands from being executed by the DDR3 SDRAM. The DDR3 SDRAM is effectively deselected. Operations already in progress are not affected. Mode Register Set Command [MR0 to MR3] The mode registers are loaded via row address inputs. See mode register descriptions in the Programming the Mode Register section. The mode register set command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. Bank Activate Command [ACT] This command is used to open (or activate) a row in a particular bank for a subsequent access. The values on the BA inputs select the bank, and the address provided on row address inputs selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A precharge command must be issued before opening a different row in the same bank. Note: No more than 4 banks may be activated in a rolling tFAW window. Converting to clocks is done by dividing tFAW (ns) by tCK (ns) and rounding up to next integer value. As an example of the rolling window, if (tFAW/tCK) rounds up to 10 clocks, and an activate command is issued in clock N, no more than three further activate commands may be issued in clock N+1 through N+9. Data Sheet E1797E41 (Ver. 4.1) 68 EDJ2104EDBG, EDJ2108EDBG Read Command [READ, RDS4, RDS8, READA, RDAS4, RDAS8] The read command is used to initiate a burst read access to an active row. The values on the BA inputs select the bank, and the address provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Write Command [WRIT, WRS4, WRS8, WRITA, WRAS4, WRAS8] The write command is used to initiate a burst write access to an active row. The values on the BA inputs select the bank, and the address provided on column address inputs selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered low, the corresponding data will be written to memory; if the DM signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. Precharge Command [PRE, PALL] The precharge command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA select the bank. Otherwise BA are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. A precharge command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. Auto precharge Command [READA, WRITA] Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the read or write command is issued, then the auto precharge function is engaged. During auto precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is (AL* + tRTP) cycles later from the read with auto precharge command. Auto precharge can also be implemented during write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The tRAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Note: AL (Additive Latency), refer to Posted /CAS description in the Register Definition section. Auto-Refresh Command [REF] Auto-refresh is used during normal operation of the DDR3 SDRAM and is analogous to /CAS-before-/RAS (CBR) refresh in FPM/EDO DRAM. This command is nonpersistent, so it must be issued each time a refresh is required. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an auto-refresh command. A maximum of eight auto-refresh commands can be posted to any given DDR3, meaning that the maximum absolute interval between any auto-refresh command and the next auto-refresh command is 9 x tREFI. This maximum absolute interval is to allow DDR3 output drivers and internal terminators to automatically recalibrate compensating for voltage and temperature changes. Data Sheet E1797E41 (Ver. 4.1) 69 EDJ2104EDBG, EDJ2108EDBG Self-Refresh Command [SELF] The self-refresh command can be used to retain data in the DDR3, even if the rest of the system is powered down. When in the self-refresh mode, the DDR3 retains data without external clocking. The self-refresh command is initiated like an auto-refresh command except CKE is disabled (low). The DLL is automatically disabled upon entering self-refresh and is automatically enabled and reset upon exiting self-refresh. The active termination is also disabled upon entering self-refresh and enabled upon exiting self-refresh. (512 clock cycles must then occur before a read command can be issued). Input signals except CKE are "Don't Care" during self-refresh. The procedure for exiting self-refresh requires a sequence of commands. First, CK and /CK must be stable prior to CKE going back high. Once CKE is high, the DDR3 must have NOP commands issued for tXSDLL because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh, DLL requirements and out-put calibration is to apply NOPs for 512 clock cycles before applying any other command to allow the DLL to lock and the output drivers to recalibrate. ZQ calibration Command [ZQCL, ZQCS] ZQ calibration command (short or long) is used to calibrate DRAM RON and ODT values over PVT. ZQ Calibration Long (ZQCL) command is used to perform the initial calibration during power-up initialization sequence. ZQ Calibration Short (ZQCS) command is used to perform periodic calibrations to account for VT variations. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh. Data Sheet E1797E41 (Ver. 4.1) 70 EDJ2104EDBG, EDJ2108EDBG CKE Truth Table CKE Current state* 2 Power-down Self-refresh Bank Active *3 Previous 1 cycle (n-1)* Current *1 cycle (n) Command (n) /CS, /RAS, /CAS, /WE Operation (n) L L x Maintain power-down 14, 15 L H DESL or NOP Power-down exit 11, 14 L L x Maintain self-refresh 15, 16 L H DESL or NOP Self-refresh exit 8, 12, 16 H L DESL or NOP Active power-down entry 11, 13, 14 *3 Notes Reading H L DESL or NOP Power-down entry 11, 13, 14, 17 Writing H L DESL or NOP Power-down entry 11, 13, 14, 17 Precharging H L DESL or NOP Power-down entry 11, 13, 14, 17 Refreshing H L DESL or NOP Precharge power-down entry 11 All banks idle H L DESL or NOP Precharge power-down entry 11, 13, 14, 18 H L REFRESH Self-refresh entry 9, 13, 18 H H Refer to the Command Truth Table Any state other than listed above 10 Remark: H = VIH. L = VIL. x = Don't care Notes: 1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) is the state of CKE at the previous clock edge. 2. Current state is the state of the DDR3 SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and operation (n) is a result of Command (n). ODT is not included here. 4. All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document. 5. The state of ODT does not affect the states described in this table. The ODT function is not available during self-refresh. 6. CKE must be registered with the same value on tCKE (min.) consecutive positive clock edges. CKE must remain at the valid input level the entire time it takes to achieve the tCKE (min.) clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during the time period of tIS + tCKE (min.) + tIH. 7. DESL and NOP are defined in the Command Truth Table. 8. On self-refresh exit, DESL or NOP commands must be issued on every clock edge occurring during the tXS period. Read or ODT command may be issued only after tXSDLL is satisfied. 9. Self-refresh mode can only be entered from the all banks idle state. 10. Must be a legal command as defined in the Command Truth Table. 11. Valid commands for power-down entry and exit are NOP and DESL only. 12. Valid commands for self-refresh exit are NOP and DESL only. 13. Self-refresh can not be entered while read or write operations, (extended) mode register set operations or precharge operations are in progress. See section Power-Down and self-refresh Command for a detailed list of restrictions. 14. The power-down does not perform any refresh operations. 15. "x" means "don't care" (including floating around VREF) in self-refresh and power-down. It also applies to address pins. 16. VREF (both VREFDQ and VREFCA) must be maintained during self-refresh operation. VREFDQ supply may be turned off and VREFDQ may take any value between VSS and VDD during self-refresh operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first write operation or first write leveling activity may not occur earlier than 512 nCK after exit from self-refresh. 17. If all banks are closed at the conclusion of the read, write or precharge command, the precharge powerdown is entered, otherwise active power-down is entered. 18. Idle state means that all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress. CKE is high and all timings from previous operation are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) as well as all self-refresh exit and power-down exit parameters are satisfied (tXS, tXP, tXPDLL, etc). Data Sheet E1797E41 (Ver. 4.1) 71 EDJ2104EDBG, EDJ2108EDBG Simplified State Diagram CKE_L POWER APPLIED POWER ON RESET PROCEDURE MRS, MPR, WRITE LEVELING INITIALIZATION MRS FROM ANY STATE SELFX ZQCL ZQCS RESET SELF REFRESH SELF REF ZQ CALIBRATION IDLE ACT ACTIVE POWER DOWN REFRESHING PDEN PDEX ACTIVATING PRECHARGE POWER DOWN CKE_L PDEX CKE_L PDEN BANK ACTIVE READ WRIT WRIT READ WRITA READA READ WRITING READING WRIT READA WRITA WRITA READA PRE, PALL WRITING READING PRE, PALL PRE, PALL PRECHARGING Automatic sequence Command sequence Data Sheet E1797E41 (Ver. 4.1) 72 EDJ2104EDBG, EDJ2108EDBG RESET and Initialization Procedure Power-Up and Initialization Sequence 1. Apply power (/RESET is recommended to be maintained below 0.2 x VDD, (all other inputs may be undefined). ) /RESET needs to be maintained for minimum 200s with stable power. CKE is pulled low anytime before /RESET being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDD (min.) must be no greater than 200ms; and during the ramp, VDD > VDDQ and (VDD - VDDQ) < 0.3V. * VDD and VDDQ are driven from a single power converter output AND * The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is limited to 0.95V max once power ramp is finished, AND * VREF tracks VDDQ/2. OR * Apply VDD without any slope reversal before or at the same time as VDDQ. * Apply VDDQ without any slope reversal before or at the same time as VTT and VREF. * The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. 2. After /RESET is de-asserted, wait for another 500s until CKE become active. During this time, the DRAM will start internal state initialization; this will be done independently of external clocks. 3. Clocks (CK, /CK) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be met. Also a NOP or DESL command must be registered (with tIS set up time to clock) before CKE goes active. Once the CKE registered "high" after Reset, CKE needs to be continuously registered high until the initialization sequence is finished, including expiration of tDLLK and tZQinit. 4. The DDR3 SDRAM will keep its on-die termination in high-impedance state during /RESET being asserted at least until CKE being registered high. Therefore, the ODT signal may be in undefined state until tIS before CKE being registered high. After that, the ODT signal must be kept inactive (low) until the power-up and initialization sequence is finished, including expiration of tDLLK and tZQinit. 5. After CKE being registered high, wait minimum of tXPR, before issuing the first MRS command to load mode register. (tXPR = max. (tXS ; 5 x tCK) 6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide low to BA0 and BA2, high to BA1.) 7. Issue MRS command to load MR3 with all application settings. (To issue MRS command for MR3, provide low to BA2, high to BA0 and BA1.) 8. Issue MRS command to load MR1 with all application settings and DLL enabled. (To issue DLL Enable command, provide low to A0, high to BA0 and low to BA1 and BA2). 9. Issue MRS command to load MR0 with all application settings and DLL reset. (To issue DLL reset command, provide high to A8 and low to BA0 to BA2). 10. Issue ZQCL command to start ZQ calibration. 11. Wait for both tDLLK and tZQinit completed. 12. The DDR3 SDRAM is now ready for normal operation. Data Sheet E1797E41 (Ver. 4.1) 73 EDJ2104EDBG, EDJ2108EDBG Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, /CK tCKSRX max. (10 ns; 5tCK) VDD, VDDQ 200ms 500ms /RESET tIS 10ns CKE 2 tXPR* tIS Command *1 BA tDLLK tMRD tMRD tMRD tZQinit tMOD MRS MRS MRS MRS MR2 MR3 MR1 MR0 ZQcal tIS ODT DRAM_RTT Notes: 1. From time point "Td" until "Tk", NOP or DESL commands must be applied between MRS and ZQcal commands. 2. tXPR = max. (tXS; 5tCK) : VIH or VIL Reset and Initialization Sequence at Power-On Ramping Reset and Initialization with Stable Power The following sequence is required for /RESET at no power interruption initialization. 1. Assert /RESET below 0.2 x VDD anytime when reset is needed (all other inputs may be undefined). /RESET needs to be maintained for minimum 100ns. CKE is pulled low before /RESET being de-asserted (minimum time 10ns). 2. Follow Power-Up Initialization Sequence steps 2 to 11. 3. The reset sequence is now completed; DDR3 SDRAM is ready for normal operation. Ta Tb Tc Td Te Tf Tg Th Ti Tj Tk CK, /CK tCKSRX max. (10 ns; 5tCK) VDD, VDDQ 500ms 100ns /RESET 10ns tIS CKE 2 * tXPR tIS Command *1 BA tDLLK tMRD tMRD tMRD tMOD MRS MRS MRS MRS MR2 MR3 MR1 MR0 tZQinit ZQCL tIS ODT DRAM_RTT Notes: 1. From time point "Td" until"Tk", NOP or DESL commands must be applied between MRS and ZQCL commands. 2. tXPR = max. (tXS; 5tCK) Reset Procedure at Power Stable Condition Data Sheet E1797E41 (Ver. 4.1) 74 : VIH or VIL EDJ2104EDBG, EDJ2108EDBG Programming the Mode Register For application flexibility, various functions, features and modes are programmable in four mode registers, provided by the DDR3 SDRAM, as user defined variables, and they must be programmed via a Mode Register Set (MRS) command. As the default values of the Mode Registers (MR#) are not defined, content of mode registers must be fully initialized and/or re-initialized, i.e. written, after Power-up and/or reset for proper operation. Also the contents of the mode registers can be altered by re-executing the MRS command during normal operation. When programming the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset does not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents. The mode register set command cycle time, tMRD is required to complete the write operation to the mode register and is the minimum time required between two MRS commands. The MRS command to non-MRS command delay, tMOD, is required for the DRAM to update the features except DLL reset and is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL. The mode register contents can be changed using the same command and timing requirements during normal operation as long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed and CKE is already high prior to writing into the mode register. The mode registers are divided into various fields depending on the functionality and/or modes. Mode Register Set Command Cycle Time (tMRD) tMRD is the minimum time required from an MRS command to the next MRS command. As DLL enable and DLL reset are both MRS commands, tMRD is applicable between MRS to MR1 for DLL enable and MRS to MR0 for DLL reset, and not tMOD. /CK CK Command MRS NOP MRS NOP tMRD tMRD Timing MRS Command to Non-MRS Command Delay (tMOD) tMOD is the minimum time required from an MRS command to a non-MRS command excluding NOP and DESL. Note that additional restrictions may apply, for example, MRS to MR0 for DLL reset followed by read. /CK CK Command MRS NOP non-MRS NOP tMOD Old setting Updating New Setting tMOD Timing Data Sheet E1797E41 (Ver. 4.1) 75 EDJ2104EDBG, EDJ2108EDBG DDR3 SDRAM Mode Register 0 [MR0] The Mode Register MR0 stores the data for controlling various operating modes of DDR3 SDRAM. It controls burst length, read burst type, /CAS latency, test mode, DLL reset, WR and DLL control for precharge power-down, which include various vendor specific options to make DDR3 SDRAM useful for various applications. The mode register is written by asserting low on /CS, /RAS, /CAS, /WE, BA0 and BA1, while controlling the states of address pins according to the table below. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 0*1 BA1 BA0 0 0*1 0 PPD A8 A7 DLL TM WR A6 A5 A4 /CAS latency A3 A2 A1 RBT CL A0 BL Address field Mode register 0 Burst length A8 DLL reset A7 Mode A3 Read burst type 0 No 0 Normal 0 Nibble sequential 1 Yes 1 Test 1 Interleave A1 A0 BL 0 0 8 (Fixed) 4 or 8 (on the fly) 0 1 MRS mode 1 0 4 (Fixed) 1 1 Reserved 0 0 MR0 0 1 MR1 Write recovery for autoprecharge /CAS latency A10 A9 WR A6 A5 A4 A2 Latency Reserved 0 0 0 0 Reserved 1 0 MR2 A11 1 1 MR3 0 0 0 0 0 1 5*2 0 0 1 0 5 0 1 0 6*2 0 1 0 0 6 0 1 1 7*2 0 1 1 0 7 1 0 0 8*2 1 0 0 0 8 1 0 1 10*2 1 0 1 0 9 1 1 0 12*2 1 1 0 0 10 1 1 1 Reserved 1 1 1 0 11 A12 DLL Control for Precharge PD 0 Slow exit (DLL off) 1 Fast exit (DLL on) Notes: 1. BA2, A13 and A14 are reserved for future use and must be programmed to 0 during MRS. 2. WR (min.) (Write Recovery for autoprecharge) is determined by tCK (max.) and WR (max.) is determined by tCK (min.). WR in clock cycles is calculated by dividing tWR (in ns) by tCK (in ns) and rounding up to the next integer (WR (min.) [cycles] = roundup tWR (ns) / tCK (ns)). (The WR value in the mode register must be programmed to be equal or larger than WR (min.) This is also used with tRP to determine tDAL. MR0 Programming Data Sheet E1797E41 (Ver. 4.1) 76 EDJ2104EDBG, EDJ2108EDBG DDR3 SDRAM Mode Register 1 [MR1] The Mode Register MR1 stores the data for enabling or disabling the DLL, output driver strength, RTT_Nom impedance, additive latency, write leveling enable, TDQS enable and Qoff. The Mode Register 1 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA0 and low on BA1, while controlling the states of address pins according to the table below. BA2 BA1 BA0 A14 A13 A12 A11 A10 A9 0*1 0 0*1 1 Qoff TDQS 0*1 Rtt_Nom A11 TDQS enable 0 Disabled 1 Enabled A8 A7 A6 A5 0*1 Level Rtt_Nom D.I.C A4 A3 AL A2 Rtt_Nom A9 A6 A2 RTT_Nom*5 0 0 0 ODT Disabled 0 0 1 RZQ/4 0 1 0 RZQ/2 0 1 1 RZQ/6 1 0 0 RZQ/12*4 A7 Write leveling enable 1 0 1 RZQ/8*4 0 Disabled 1 1 0 Reserved 1 Enabled 1 1 1 Reserved Qoff A12 0 Output buffers enabled 1 Output buffers disabled*2 Notes: 1. 2. 3. 4. 5. A1 A0 Address field D.I.C DLL Mode register 1 A0 DLL enable 0 Enable 1 Disable Output driver A4 A3 Additive Latency A5 A1 impedance control 0 0 0 (AL disabled) 0 0 RZQ/6 CL-1 0 1 RZQ/7 0 1 1 0 CL-2 1 0 Reserved 1 1 Reserved 1 1 Reserved BA2, A8, A10, A13 and A14 are reserved for future use (RFU) and must be programmed to 0 during MRS. Outputs disabled - DQ, DQS, /DQS. RZQ = 240 If RTT_Nom is used during writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed. In write leveling mode (MR1[bit7] = 1) with MR1[bit12] = 1, all RTT_Nom settings are allowed; in write leveling mode (MR1[bit7] = 1) with MR1[bit12] = 0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed MR1 Programming Data Sheet E1797E41 (Ver. 4.1) 77 EDJ2104EDBG, EDJ2108EDBG DDR3 SDRAM Mode Register 2 [MR2] The Mode Register MR2 stores the data for controlling refresh related features, RTT_WR impedance and /CAS write latency (CWL). The Mode Register 2 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and low on BA0, while con-trolling the states of address pins according to the table below. BA2 BA1 BA0 A14 A13 0*1 1 A12 A11 A10 1 0 0* A7 Self-refresh range 0 Normal self-refresh 1 Extend temperature self-refresh A9 A8 Rtt_WR*2 0*1 A7 A6 A5 SRT ASR A4 A3 A2 A1 A0 PASR* 2 CWL Address field Mode register 2 Partial array self-refresh Refresh array A2 A1 A0 0 0 0 Full 0 0 1 Half 0 1 0 Quarter: Bank 0 and Bank 1 (BA [2:0] = 000, 001) : Bank 0 to Bank 3 (BA [2:0] = 000, 001, 010, 011) A6 Auto self-refresh method 0 1 1 1/8 : Bank 0 (BA [2:0] = 000) 0 Manual SR reference (SRT) 1 0 0 3/4 : Bank 2 to Bank 7 (BA [2:0] = 010, 011, 100, 101,110 ,111) 1 0 1 Half : Bank 4 to Bank 7 (BA [2:0] = 100, 101, 110, 111) 1 1 0 Quarter: Bank 6 and Bank 7 (BA [2:0] = 110, 111) 1 1 1 1/8 1 ASR enable (Optional) : Bank 7 A5 A4 A3 A10 A9 Rtt_WR 0 0 0 0 0 5 (tCK 2.5ns) Dynamic ODT off (write does not affect Rtt value) 0 0 1 6 (2.5ns > tCK 1.875ns) 0 1 0 0 1 7 (1.875ns > tCK 1.5ns) RZQ/4 0 1 1 1 0 8 (1.5ns > tCK 1.25ns) RZQ/2 1 0 0 Reserved 1 1 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved (BA [2:0] = 111) CAS write Latency (CWL) Notes: 1. BA2, A8, and A11 to A14 are RFU and must be programmed to 0 during MRS. 2. The Rtt_WR value can be applied during writes even when Rtt_Nom is desabled. During write leveling, Dynamic ODT is not available. 3. Optional in DDR3 SDRAM: If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range will be lost if self-refresh is entered. Data integrity will be maintained if tREF conditions are met and no self-refresh command is issued. MR2 Programming Data Sheet E1797E41 (Ver. 4.1) 78 EDJ2104EDBG, EDJ2108EDBG DDR3 SDRAM Mode Register 3 [MR3] The Mode Register MR3 controls Multi Purpose Registers (MPR). The Mode Register 3 is written by asserting low on /CS, /RAS, /CAS, /WE, high on BA1 and BA0, while controlling the states of address pins according to the table below. BA2 BA1 BA0 A14 A13 0* 1 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 0*1 1 A2 A1 MPR A0 MPR Loc Address field Mode register 3 MPR Address MPR location A1 A0 MPR Operation 0 0 Predefined pattern*2 A2 MPR 0 1 RFU 0 Normal operation*3 1 0 RFU 1 Data flow from MPR 1 1 RFU Notes : 1. BA2, A3 to A14 are reserved for future use (RFU) and must be programmed to 0 during MRS. 2. The predefined pattern will be used for read synchronization. 3 . When MPR control is set for normal operation, MR3 A[2]=0, MR3 A[1:0] will be ignored. MR3 Programming Data Sheet E1797E41 (Ver. 4.1) 79 EDJ2104EDBG, EDJ2108EDBG Burst Length (MR0) Read and write accesses to the DDR3 are burst oriented, with the burst length being programmable, as shown in the figure MR0 Programming. The burst length determines the maximum number of column locations that can be accessed for a given read or write command. Burst length options include fixed BC4, fixed BL8, and on the fly which allows BC4 or BL8 to be selected coincident with the registration of a read on write command Via A12 (/BC). Reserved states should not be used, as unknown operation or incompatibility with future versions may result. Burst Chop In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected on the fly via A12(/BC), the internal write operation starts at the same point in time like a burst of 8 write operation. This means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks. Burst Type (MR0) [Burst Length and Sequence] Burst length Operation Starting address (A2, A1, A0) Sequential addressing (decimal) Interleave addressing (decimal) 4 (Burst chop) READ 000 0, 1, 2, 3, T, T, T, T 0, 1, 2, 3, T, T, T, T 001 1, 2, 3, 0, T, T, T, T 1, 0, 3, 2, T, T, T, T 010 2, 3, 0, 1, T, T, T, T 2, 3, 0, 1, T, T, T, T 011 3, 0, 1, 2, T, T, T, T 3, 2, 1, 0, T, T, T, T 100 4, 5, 6, 7, T, T, T, T 4, 5, 6, 7, T, T, T, T 101 5, 6, 7, 4, T, T, T, T 5, 4, 7, 6, T, T, T, T 110 6, 7, 4, 5, T, T, T, T 6, 7, 4, 5, T, T, T, T 111 7, 4, 5, 6, T, T, T, T 7, 6, 5, 4, T, T, T, T 0VV 0, 1, 2, 3, X, X, X, X 0, 1, 2, 3, X, X, X, X 1VV 4, 5, 6, 7, X, X, X, X 4, 5, 6, 7, X, X, X, X WRITE 8 READ WRITE 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 VVV 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 Remark: T: Output driver for data and strobes are in high impedance. V: A valid logic level (0 or 1), but respective buffer input ignores level on input pins. X: Don't Care. Notes: 1. Page length is a function of I/O organization and column addressing 2. 0...7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst. Data Sheet E1797E41 (Ver. 4.1) 80 EDJ2104EDBG, EDJ2108EDBG DLL Enable (MR1) The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having the DLL disabled. The DLL is automatically disabled when entering selfrefresh operation and is automatically re-enabled upon exit of self-refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON or tAOF parameters. During tDLLK, CKE must continuously be registered high. DDR3 SDRAM does not require DLL for any write operation. DDR3 does not require DLL to be locked prior to any write operation. DDR3 requires DLL to be locked only for read operation and to achieve synchronous ODT timing. DLL-off Mode DDR3 DLL-off mode is entered by setting MR1 bit A0 to 1; this will disable the DLL for subsequent operations until A0 bit set back to 0. The MR1 A0 bit for DLL control can be switched either during initialization or later. The DLL-off mode operations listed below are an optional feature for DDR3. The maximum clock frequency for DLLoff mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to satisfy the refresh interval, tREFI. Due to latency counter and timing restrictions, only one value of /CAS Latency (CL) in MR0 and CAS Write Latency (CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL = 6 and CWL = 6. DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the Data Strobe to Data relationship (tDQSQ, tQH, tQHS). Special attention is needed to line up Read data to controller time domain. Comparing with DLL-on mode, where tDQSCK starts from the rising clock edge (AL + CL) cycles after the Read command, the DLL-off mode tDQSCK starts (AL + CL - 1) cycles after the read command. Another difference is that tDQSCK may not be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCK (min.). and tDQSCK (max.) is significantly larger than in DLL-on mode. The timing relations on DLL-off mode READ operation are shown at following Timing Diagram (CL = 6, BL8): T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK, /CK Command BA READ A DQSdiff_DLL-on RL = AL + CL = 6 (CL = 6, AL = 0) CL = 6 DQ_DLL-on CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 RL (DLL-off) = AL + (CL - 1) = 5 tDQSCK(DLL-off)_min DQSdiff_DLL-off CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 DQ_DLL-off tDQSCK(DLL-off)_max DQSdiff_DLL-off CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 DQ_DLL-off DLL-Off Mode Read Timing Operation Data Sheet E1797E41 (Ver. 4.1) 81 EDJ2104EDBG, EDJ2108EDBG DLL on/off switching procedure DDR3 DLL-off mode is entered by setting MR1 bit A0 to "1"; this will disable the DLL for subsequent operations until A0 bit set back to "0". DLL "on" to DLL "off" Procedure To switch from DLL "on" to DLL "off" requires the frequency to be changed during self-refresh outlined in the following procedure: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled, and DRAMs On-die Termination resistors, RTT, must be in high impedance state before MRS to MR1 to disable the DLL.) 2. Set MR1 Bit A0 to "1" to disable the DLL. 3. Wait tMOD. 4. Enter self-refresh mode; wait until (tCKSRE) satisfied. 5. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section. 6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. After stable clock, wait tCKSRX before issuing SRX command. 7. Starting with the self-refresh exit command, CKE must continuously be registered high until all tMOD timings from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when selfrefresh mode was entered, the ODT signal must continuously be registered low until all tMOD timings from any MRS command are satisfied. If both ODT features were disabled in the mode registers when self-refresh mode was entered, ODT signal can be registered low or high. 8. Wait tXS, then set mode registers with appropriate values (especially an update of CL, CWL and WR may be necessary. A ZQCL command may also be issued after tXS). 9. Wait for tMOD, then DRAM is ready for next command. Ta Tb Tc Tc+1 Tc+2 Td Te Tf Tf+1 Tf+2 Tg Tg+1 Th CK /CK tMOD tCKSRE tCKSRX tXS Command MRS SRE NOP SRX tCKESR CKE ODT Change Frequency DLL Switch Sequence from DLL-on to DLL-off Data Sheet E1797E41 (Ver. 4.1) 82 tMOD MRS Valid EDJ2104EDBG, EDJ2108EDBG DLL "off" to DLL "on" Procedure To Switch from DLL "off" to DLL "on" (with required frequency change) during Self-Refresh: 1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT) must be in high impedance state before Self-Refresh mode is entered.) 2. Enter Self-refresh Mode, wait until tCKSRE satisfied. 3. Change frequency, in guidance with Input Clock Frequency Change during Precharge Power-Down section. 4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs. 5. Starting with the self-refresh exit command, CKE must continuously be registered high until all tDLLK timing from subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers when self-refresh mode was entered, the ODT signal must continuously be registered low until tDLLK timings from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when Self-refresh mode was entered, ODT signal can be registered low or high. 6. Wait tXS, then set MR1 bit A0 to "0" to enable the DLL. 7. Wait tMRD, then set MR0 bit A8 to "1" to start DLL Reset. 8. Wait tMRD, and then set mode registers with appropriate values (especially an update of CL, CWL and WR may be necessary. After tMOD is satisfied from any proceeding MRS command, a ZQCL command may also be issued during or after tDLLK.) 9. Wait for tMOD, and then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying command requiring a locked DLL). In addition, wait also for tZQoper in case a ZQCL command was issued. Ta Tb Tc Tc+1Tc+2 Td Te Tf Tf+1 Tf+2 Tg CK /CK tCKSRE tCKSRX tDLLK tXS Command SRX SRE NOP tMRD MRS tCKESR CKE ODTLoff + 1x tCK ODT Change Frequency DLL Switch Sequence from DLL-Off to DLL-On Data Sheet E1797E41 (Ver. 4.1) 83 tMRD MRS MRS Valid EDJ2104EDBG, EDJ2108EDBG Additive Latency (MR1) A posted /CAS read or write command when issued is held for the time of the Additive Latency (AL) before it is issued inside the device. The read or write posted /CAS command may be issued with or without auto precharge. The Read Latency (RL) is controlled by the sum of AL and the /CAS latency (CL). The value of AL is also added to compute the overall Write Latency (WL). MRS (1) bits A4 and A3 are used to enable Additive latency. MRS1 A4 A3 AL* 0 0 0 (posted CAS disabled) 0 1 CL - 1 1 0 CL - 2 1 1 Reserved Note: AL has a value of CL - 1 or CL - 2 as per the CL value programmed in the /CAS latency MRS setting. Data Sheet E1797E41 (Ver. 4.1) 84 EDJ2104EDBG, EDJ2108EDBG Write Leveling (MR1) For better signal integrity, DDR3 memory module adopts fly by topology for the commands, addresses, control signals and clocks. The fly by topology has benefits for reducing number of stubs and their length but in other aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes Controller hard to maintain tDQSS, tDSS and tDSH specification. Therefore, the controller should support 'write leveling' in DDR3 SDRAM to compensate the skew. Write leveling is a scheme to adjust DQS to CK relationship by the controller, with a simple feedback provided by the DRAM. The memory controller involved in the leveling must have adjustable delay setting on DQS to align the rising edge of DQS with that of the clock at the DRAM pin. DRAM asynchronously feeds back CK, sampled with the rising edge of DQS, through the DQ bus. The controller repeatedly delays DQS until a transition from 0 to 1 is detected. The DQS delay established through this exercise would ensure tDQSS, tDSS and tDSH specification. A conceptual timing of this scheme is shown as below. diff_Clock Source diff_DQS Destination diff_Clock diff_DQS DQ X 0 0 Push DQS to capture 0-1 transition DQ X 1 1 Write Leveling Concept DQS, /DQS driven by the controller during leveling mode must be terminated by the DRAM, based on the ranks populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller. One or more data bits should carry the leveling feedback to the controller across the DRAM configurations x4, x8. DRAM Setting for Write Leveling and DRAM Termination Function in That Mode DRAM enters into write leveling mode if A7 in MR1 set 1. And after finishing leveling, DRAM exits from write leveling mode if A7 in MR1 set 0 (MR1 Setting Involved in the Leveling Procedure table). Note that in write leveling mode, only DQS/DQS terminations are activated and deactivated via ODT pin, not like normal operation (refer to the DRAM Termination Function in The Leveling Mode table) [MR1 Setting Involved in the Leveling Procedure] Function MR1 bit Enable Disable Write leveling enable A7 1 0 Output buffer mode (Qoff) A12 0 1 Note 1 Note: 1. Output buffer mode definition is consistent with DDR2 [DRAM Termination Function in The Leveling Mode] ODT pin@DRAM DQS, /DQS termination DQs termination De-asserted Off Off Asserted On Off Note: In write leveling mode with its output buffer disabled (MR1 [bit7] = 1 with MR1 [bit12] = 1) all RTT_Nom settings are allowed; in write leveling mode with its output buffer enabled (MR1 [bit7] = 1 with MR1 [bit12] = 0) only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed. Data Sheet E1797E41 (Ver. 4.1) 85 EDJ2104EDBG, EDJ2108EDBG Write Leveling Procedure Memory controller initiates leveling mode of all DRAMs by setting bit 7 of MR1 to 1. Since the controller levelizes rank at a time, the output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at which DRAM is ready to accept the ODT signal. Controller may drive DQS low and /DQS high after a delay of tWLDQSEN, at which time DRAM has applied on-die termination on these signals. After tWLMRD, controller provides a single DQS, /DQS edge which is used by the DRAM to sample CK driven from controller. tWLMRD timing is controller dependent. DRAM samples CK status with rising edge of DQS and provides feedback on all the DQ bits asynchronously after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no read strobes (DQS, /DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or decrement DQS delay setting and launches the next DQS, /DQS pulse after some time, which is controller dependent. Once a 0 to 1 transition is detected, the controller locks DQS delay setting and write leveling is achieved for the device. The below figure describes detailed timing diagram for overall procedure and the timing parameters are shown in below figure. tWLS T1 tWLH CK*5 /CK Command T2 tWLS **22 MRS tWLH **34 NOP *3 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP tMOD 6 *6(min.) tDQSL (min.) tDQSL* (min.) tDQSH ODT tDQSH (min.) tWLDQSEN diff_DQS*4 tWLOE All DQs*1 tWLO tWLMRD tWLO Notes:1. DDR3 SDRAM drives leveling feedback on all DQs. 2. MRS : Load MR1 to enter write leveling mode. 3. NOP : NOP or deselec 4. diff_DQS is the differential data strobe (DQS, /DQS). Timing reference points are the zero crossing. DQS is shown with solid line, /DQS is shown with dotted line. 5. CK, /CK : CK is shown with solid dark line, where as /CK is drawn with dotted line. 6. DQS needs to fulfill minimum pulse width requirements tDQSH (min.) and tDQSL (min.) as defined for regular writes; the max pulse width is system dependent. Timing Details Write Leveling Sequence Data Sheet E1797E41 (Ver. 4.1) 86 EDJ2104EDBG, EDJ2108EDBG Write Leveling Mode Exit The following sequence describes how the write leveling mode should be exited: 1. After the last rising strobe edge(see T111), stop driving the strobe signals (see ~T128). Note: From now on, DQ pins are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (T145). 2. Drive ODT pin low (tIS must be satisfied) and continue registering low (see T128). 3. After the RTT is switched off: disable Write Level Mode via MR command (see T132). 4. After tMOD is satisfied (T145), any valid commands may be registered. (MR commands may already be issued after tMRD (T136). T111 T112 T116 T117 T128 T131 T132 T136 T145 MRS Valid CK, /CK Command WL_off tMOD BA 1 tIS ODT tODTL_off RTT_DQS-/DQS DQS-/DQS RTT_DQ tWLO + tWLOE DQ Result = 1 Timing Details Write Leveling Exit Data Sheet E1797E41 (Ver. 4.1) 87 Valid tMRD Valid Valid EDJ2104EDBG, EDJ2108EDBG TDQS, /TDQS function (MR1) TDQS (Termination Data Strobe) is a feature of x8 DDR3 SDRAM that provides additional termination resistance outputs that may be useful in some system configurations. TDQS is not supported in x4 configurations. When enabled via the mode register, the same termination resistance function is applied to the TDQS and /TDQS pins that are applied to the DQS and /DQS pins. In contrast to the RDQS function of DDR2 SDRAM, TDQS provides the termination resistance function only. The data strobe function of RDQS is not provided by TDQS. The TDQS and DM functions share the same pin. When the TDQS function is enabled via the mode register, the DM function is not supported. When the TDQS function is disabled, the DM function is provided and the /TDQS pin is not used. See Table TDQS, /TDQS function for details. The TDQS function is available in x8 DDR3 SDRAM only and must be disabled via the mode register A11 = 0 in MR1 for x4 configurations. [TDQS, /TDQS function] A11@MR1 TDQS enable 0 Disable 1 Enable Notes: 1. If TDQS is enabled, the DM function is disabled. 2. When not used, TDQS function can be disabled to save termination power. 3. TDQS function is only available for x8 DRAM and must be disabled for x4. [Function matrix] A11@MR1 (TDQS enable) DM/TDQS NU/ /TDQS 0 DM High-Z 1 TDQS /TDQS Data Sheet E1797E41 (Ver. 4.1) 88 EDJ2104EDBG, EDJ2108EDBG Extended Temperature Usage (MR2) [Mode Register Description] Field Bits Description ASR A6 0 1 Manual SR Reference (SRT) ASR enable (Optional) SRT A7 0 1 Normal operating temperature range Extended operating temperature range Description Auto self-refresh (ASR) (Optional) when enabled, DDR3 SDRAM automatically provides self-refresh power management functions for all supported operating temperature values. If not enabled, the SRT bit must be programmed to indicate TC during subsequent self-refresh operation Self-Refresh Temperature (SRT) Range If ASR = 0, the SRT bit must be programmed to indicate TC during subsequent self-refresh operation If ASR = 1, SRT bit must be set to 0 Partial Array Self-Refresh (PASR) Optional in DDR3 SDRAM: Users should refer to the DRAM supplier data sheet and/or the DIMM SPD to determine if DDR3 SDRAM devices support the following options or requirements referred to in this material. If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address range shown in figure of MR2 programming will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-Refresh command is issued. /CAS Write Latency (CWL) The /CAS Write Latency is defined by MR2 bits [A3, A5], as shown in figure of MR2 programming. /CAS Write Latency is the delay, in clock cycles, between the internal Write command and the availability of the first bit of input data. DDR3 SDRAM does not support any half-clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + /CAS Write Latency (CWL); WL = AL + CWL. For more information on the sup-ported CWL and AL settings based on the operating clock frequency, refer to "Standard Speed Bins". For detailed Write operation refer to "WRITE Operation". Auto Self-Refresh Mode - ASR Mode (optional) DDR3 SDRAM provides an Auto Self-Refresh mode (ASR) for application ease. ASR mode is enabled by setting MR2 bit A6 = 1 and MR2 bit A7 = 0. The DRAM will manage self-refresh entry in either the Normal or Extended (optional) Temperature Ranges. In this mode, the DRAM will also manage self-refresh power consumption when the DRAM operating temperature changes, lower at low temperatures and higher at high temperatures. If the ASR option is not supported by the DRAM, MR2 bit A6 must be set to 0. If the ASR mode is not enabled (MR2 bit A6 = 0), the SRT bit (MR2 A7) must be manually programmed with the operating temperature range required during self-refresh operation. Support of the ASR option does not automatically imply support of the Extended Temperature Range. Self- Refresh Temperature Range - SRT If ASR = 0, the Self-Refresh Temperature (SRT) Range bit must be programmed to guarantee proper self-refresh operation. If SRT = 0, then the DRAM will set an appropriate refresh rate for self-refresh operation in the Normal Temperature Range. If SRT = 1 then the DRAM will set an appropriate, potentially different, refresh rate to allow self-refresh operation in either the Normal or Extended Temperature Ranges. The value of the SRT bit can effect self-refresh power consumption, please refer to the IDD table for details. For parts that do not support the Extended Temperature Range, MR2 bit A7 must be set to 0 and the DRAM should not be operated outside the Normal Temperature Range. Data Sheet E1797E41 (Ver. 4.1) 89 EDJ2104EDBG, EDJ2108EDBG [Self-Refresh Mode Summary] MR2 A6 A7 Self-refresh operation Allowed operating temperature range for self-refresh mode 0 0 Self-refresh rate appropriate for the Normal Temperature Range Normal (0C to +85C) 0 1 1 0 1 0 1 1 Self-refresh rate appropriate for either the Normal or Extended Temperature Ranges. The DRAM must support Extended Temperature Range. The value of the SRT bit can effect selfrefresh power consumption, please refer to the Self- refresh Current for details. ASR enabled (for devices supporting ASR and Normal Temperature Range). Self-refresh power consumption is temperature dependent ASR enabled (for devices supporting ASR and Extended Temperature Range). Self-refresh power consumption is temperature dependent Normal and Extended (0C to +95C) Normal (0C to +85C) Normal and Extended (0C to +95C) Illegal Dynamic ODT (Rtt_WR) DDR3 SDRAM introduces a new feature "Dynamic ODT". In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. MR2 register locations A9 and A10 configure the Dynamic ODT settings. In write leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to "Dynamic ODT". Data Sheet E1797E41 (Ver. 4.1) 90 EDJ2104EDBG, EDJ2108EDBG Multi Purpose Register (MR3) The Multi Purpose Register (MPR) function is used to read out predefined system timing calibration bit sequence. ( $%" $ " $%&" '$%& * ! " ! #$ #$ ! ! * Conceptual Block Diagram of Multi Purpose Register To enable the MPR, a Mode Register Set (MRS) command must be issued to MR3 register with bit A2 = 1. Prior to issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP/tRPA met). Once the MPR is enabled, any subsequent READ or READA commands will be redirected to the multi purpose register. The resulting operation when a READ or READA command is issued is defined by MR3 bits [A1: A0] when the MPR is enabled. When the MPR is enabled, only READ or READA commands are allowed until a subsequent MRS command is issued with the MPR disabled (MR3 bit A2=0). Power-down mode, self-refresh, and any other nonREAD/READA command are not allowed during MPR enable mode. The /RESET function is supported during MPR enable mode. [Functional Description of MR3 Bits for MPR] MR3 A2 A [1:0] MPR MPR-Loc 0 Don't care (0 or 1) 1 MR3 A [1:0] Function Notes Normal operation, no MPR transaction. All subsequent reads will come from DRAM array. All subsequent WRITEs will go to DRAM array. Enable MPR mode, subsequent READ/READA commands defined by MR3 A [1:0] 1 bits. Note: 1. See Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register table Data Sheet E1797E41 (Ver. 4.1) 91 EDJ2104EDBG, EDJ2108EDBG * One bit wide logical interface via all DQ pins during READ operation Register Read on x4: DQ [0] drives information from MPR. DQ [3:1] drive the same information as DQ [0]. Register Read on x8: DQ [0] drives information from MPR. DQ [7:1] drive the same information as DQ [0]. Note: A standardization of which DQ is used by DDR3 SDRAM for MPR reads is strongly recommended to ensure functionality also for AMB2 on DDR3 FB-DIMM. * Addressing during Multi Purpose Register reads for all MPR agents: BA [2:0]: don't care. A [1:0]: A [1:0] must be equal to `00'b. Data read burst order in nibble is fixed A [2]: For BL8, A [2] must be equal to 0. 1 Burst order is fixed to [0,1,2,3,4,5,6,7] * For Burst Chop 4 cases, the burst order is switched on nibble base A [2] = 0, Burst order: 0,1,2,3 *1 1 A [2] = 1, Burst order: 4,5,6,7 * A [9:3]: don't care A10(AP): don't care A12(/BC): Selects burst chop mode on-the-fly, if enabled within MR0 A11: don't care * Regular interface functionality during register reads: Support two burst ordering which are switched with A2 and A [1:0] = 00. Support of read burst chop (MRS and on-the-fly via A12(/BC). All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the DDR3 SDRAM. Regular read latencies and AC timings apply. DLL must be locked prior to MPR Reads. Note: Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Data Sheet E1797E41 (Ver. 4.1) 92 EDJ2104EDBG, EDJ2108EDBG Functional Block Diagrams Figures below provide functional block diagrams for the multi purpose register in x4, x8 DDR3 SDRAM. Memory Array 4x8 4x8 32 Copy to DQ[3:0] DQ[3:0] 8 Q Read Path MPR DQS /DQS DM NibbleLane Functional Block Diagram of Multi Purpose Register in x4 DDR3 SDRAM Memory Array 8x8 8x8 64 Copy to DQ[7:0] DQ[7:0] 8 Q Read Path MPR DQS /DQS DM ByteLane Functional Block Diagram of Multi Purpose Register in x8 DDR3 SDRAM Data Sheet E1797E41 (Ver. 4.1) 93 EDJ2104EDBG, EDJ2108EDBG Register Address Table The table below provides an overview of the available data locations, how they are addressed by MR3 A [1:0] during a MR0 to MR3, and how their individual bits are mapped into the burst order bits during a multi purpose register read. [Available Data Locations and Burst Order Bit Mapping for Multi Purpose Register] MR3 A [2] 1 1 1 1 Function 000 00 BL8 Read predefined pattern for BC4 system calibration BC4 BL8 000 Burst order 0,1,2,3,4,5,6,7 1 BC4 000 Burst order 0,1,2,3 1 BC4 100 Burst order 4,5,6,7 1 BL8 000 Burst order 0,1,2,3,4,5,6,7 1 BC4 000 Burst order 0,1,2,3 1 BC4 100 Burst order 4,5,6,7 1 BL8 000 Burst order 0,1,2,3,4,5,6,7 1 BC4 000 Burst order 0,1,2,3, 1 BC4 100 Burst order 4,5,6,7 1 01 10 11 RFU RFU RFU Burst Length Read Address Burst Order and Data Pattern A [2:0] MR3 A [1:0] 000 100 Burst order 0,1,2,3,4,5,6,7 Pre-defined pattern [0,1,0,1,0,1,0,1] Burst order 0,1,2,3, Pre-defined pattern [0,1,0,1] Burst order 4,5,6,7 Pre-defined pattern [0,1,0,1] Notes 1 1 1 Note: 1. Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent. Relevant Timing Parameters The following AC timing parameters are important for operating the Multi Purpose Register: tRP, tMRD, tMOD and tMPRR. Besides these timings, all other timing parameters needed for proper operation of the DDR3 SDRAM need to be observed. [MPR Recovery Time tMPRR] Symbol Description tMPRR Multi Purpose Register Recovery Time, defined between end of MPR read burst and MRS which reloads MPR or disables MPR function Data Sheet E1797E41 (Ver. 4.1) 94 EDJ2104EDBG, EDJ2108EDBG Protocol Examples Protocol Example: Read Out Predetermined Read-Calibration Pattern Multiple reads from Multi Purpose Register, in order to do system level read timing calibration based on predetermined and standardized pattern. Protocol Steps: * Precharge All * Wait until tRP is satisfied * MRS MR3, op-code "A2 = 1 " and "A[1:0] = 00" Redirect all subsequent reads into the Multi Purpose Register, and load Pre-defined pattern into MPR. * Wait until tMRD and tMOD are satisfied (Multi Purpose Register is then ready to be read). During the period MR3 A2 =1, no data write operation is allowed. * Read: A [1:0] = `00' (Data burst order is fixed starting at nibble, always 00 here) A [2] = `0' (For BL8, burst order is fixed as 0,1,2,3,4,5,6,7) A12(/BC) = 1 (use regular burst length of 8) All other address pins (including BA [2:0] and A10(AP)): don't care. * After RL = AL + CL, DRAM bursts out the predefined Read Calibration Pattern. * Memory controller repeats these calibration reads until read data capture at memory controller is optimized. * After end of last MPR read burst wait until tMPRR is satisfied. * MRS MR3, op-code "A2 = 0" and "A[1:0] = valid data but value are don't care" All subsequent read and write accesses will be regular READs and WRITEs from/to the DRAM array. * Wait until tMRD and tMOD are satisfied * Continue with "regular" DRAM commands, like activate a memory bank for regular read or write access, T0 T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T39 CK /CK tMOD tMRD Command *1 PALL NOP MRS tRP NOP READ NOP MRS tMOD tMPRR BA 3 Valid A[1:0] 0 0 3 *2 Valid *2 A[2] 1 0 A[9:3] 00 Valid 00 0 Valid 0 0 Valid 0 A10(AP) 1 A[11] NOP 0 *1 A12(/BC) 0 Valid 0 A[15:13] 0 Valid 0 DQS, /DQS RL DQ Notes: 1. READ with BL8 either by MRS or OTF 2. Memory Control must drive 0 on A[2:0] VIH or VIL MPR Readout of Predefined Pattern, BL8 fixed Burst Order, Single Readout Data Sheet E1797E41 (Ver. 4.1) 95 EDJ2104EDBG, EDJ2108EDBG T0 T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T43 CK /CK tMRD Command PALL NOP MRS tRP tMOD NOP tMOD 3 BA A[1:0] *1 READ *1 READ NOP MRS NOP tCCD Valid 0 0 3 Valid *2 0 *2 *2 Valid *2 A[2] 1 0 A[9:3] 00 Valid Valid 00 1 0 0 0 Valid Valid 0 A[11] 0 Valid Valid 0 A12(/BC) 0 Valid Valid 0 A[15:13] 0 Valid Valid 0 A10, AP NOP tMPRR *1 *1 DQS, /DQS RL RL DQ Notes: 1. READ with BL8 either by MRS or OTF 2. Memory Control must drive 0 on A[2:0] VIH or VIL MPR Readout of Predefined Pattern, BL8 Fixed Burst Order, Back-to-Back Readout T0 T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T43 CK /CK tMOD tMRD Command PALL NOP MRS tRP 0 A[1:0] A[2] A[9:3] A10(AP) 1 *1 READ NOP NOP tCCD tMOD 3 BA NOP *1 READ NOP tMPRR Valid 0 MRS 3 Valid *2 0 *3 *2 Valid *4 1 0 00 Valid Valid 00 0 Valid Valid 0 1 0 A[11] 0 Valid A12(/BC) 0 Valid Valid 0 A[15:13] 0 Valid Valid 0 0 Valid *1 *1 DQS, /DQS RL RL DQ VIH or VIL Notes:1. READ with BC4 either by MRS or OTF 2. Memory Control must drive 0 on A[1:0] 3. A[2] = 0 selects lower 4 nibble bits 0 ... 3 4. A[2] = 1 selects upper 4 nibble bits 4 ... 7 MPR Readout Predefined Pattern, BC4, Lower Nibble Then Upper Nibble Data Sheet E1797E41 (Ver. 4.1) 96 EDJ2104EDBG, EDJ2108EDBG T0 T4 T5 T9 T17 T18 T19 T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T43 CK, /CK tMOD tMRD Command PALL NOP MRS tRP NOP *1 READ *1 READ NOP NOP tCCD tMOD BA 3 Valid A[1:0] 0 0 MRS tMPRR 3 Valid *2 0 *4 *2 Valid *3 A[2] 1 1 A[9:3] 00 Valid Valid 00 0 Valid Valid 0 A10, AP 1 NOP 0 0 A[11] 0 Valid A12(/BC) 0 Valid Valid 0 A[15:13] 0 Valid Valid 0 0 Valid *1 *1 DQS, /DQS RL RL DQ Notes:1. READ with BC4 either by MRS or OTF 2. Memory Control must drive 0 on A[1:0] 3. A[2] = 0 selects lower 4 nibble bits 0 ... 3 4. A[2] = 1 selects upper 4 nibble bits 4 ... 7 VIH or VIL MPR Readout of Predefined Pattern, BC4, Upper Nibble Then Lower Nibble Data Sheet E1797E41 (Ver. 4.1) 97 EDJ2104EDBG, EDJ2108EDBG Operation of the DDR3 SDRAM Read Timing Definition Read timing is shown in the following Figure and is applied when the DLL is enabled and locked. Rising data strobe edge parameters: * tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, /CK. * tDQSCK is the actual position of a rising strobe edge relative to CK, /CK. * tQSH describes the DQS, /DQS differential output high time. * tDQSQ describes the latest valid transition of the associated DQ pins. * tQH describes the earliest invalid transition of the associated DQ pins. Falling data strobe edge parameters: * tQSL describes the DQS, /DQS differential output low time. * tDQSQ describes the latest valid transition of the associated DQ pins. * tQH describes the earliest invalid transition of the associated DQ pins. tDQSQ; both rising/falling edges of DQS, no tAC defined. /CK CK tDQSCK(min.) tDQSCK(min.) tDQSCK(max.) tDQSCK(max.) Rising Strobe Region Rising Strobe Region tDQSCK tDQSCK tQSH tQSL tQH tQH tDQSQ tDQSQ /DQS DQS Associated DQ Pins Read Timing Definition Data Sheet E1797E41 (Ver. 4.1) 98 EDJ2104EDBG, EDJ2108EDBG * * * * * CK, /CK crossing to DQS, /DQS crossing tDQSCK; rising edges only of CK and DQS tQSH; rising edges of DQS to falling edges of DQS tQSL; rising edges of / DQS to falling edges of /DQS tLZ (DQS), tHZ (DQS) for preamble/postamble (see tHZ (DQS), tLZ (DQS) RL Measured to this point CK /CK tDQSCK(min.) tDQSCK(min.) tDQSCK(min.) tDQSCK(min.) tLZ(DQS)(min.) tQSH tQSL tRPRE tRPST DQS, /DQS Early strobe Bit0 Bit1 Bit2 tDQSCK(max.) Bit3 tDQSCK(max.) Bit4 Bit5 tDQSCK(max.) Bit6 Bit7 tDQSCK(max.) tLZ(DQS)(max.) tHZ(DQS)(max.) tQSL tQSH tRPRE tRPST DQS, /DQS Late strobe Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Notes: 1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK (min.) or tDQSCK (max.). Instead, rising strobe edge can vary between tDQSCK (min.) and tDQSCK (max.). 2. Notwithstanding note 1, a rising strobe edge with tDQSCK (max) at T (n) can not be immediately followed by a rising strobe edge with tDQSCK (min.) at T (n+1). This is because other timing relationships (tQSH, tQSL) exist: if tDQSCK(n+1) < 0: tDQSCK(n) < 1.0 tCK - (tQSHmin + tQSLmin) - | tDQSCK (n+1) | 3. The DQS, /DQS differential output high time is defined by tQSH and the DQS, /DQS differential output low time is defined by tQSL. 4. Likewise, tLZ (DQS)min and tHZ (DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ (DQS) max and tHZ (DQS) max are not tied to tDQSCKmax (late strobe case). 5. The minimum pulse width of read preamble is defined by tRPRE (min). 6. The maximum read postamble is bound by tDQSCK(min.) plus tQSH (min.) on the left side and tHZ(DQS)(max.) on the right side. 7. The minimum pulse width of read postamble is defined by tRPST (min.). 8. The maximum read preamble is bound by tLZ (DQS)(min.) on the left side and tDQSCK (max.) on the right side. DDR3 Clock to Data Strobe Relationship Data Sheet E1797E41 (Ver. 4.1) 99 EDJ2104EDBG, EDJ2108EDBG * DQS, /DQS crossing to Data Output * tDQSQ; both rising/falling edges of DQS, no tAC defined T0 T4 T5 T6 T7 T8 T9 T10 /CK CK Command*3 NOP READ RL = AL + CL Address*4 Bank Coln tRPRE tQH tQH tRPST DQS, /DQS tDQSQ(max.) tDQSQ(max.) tLZ(DQ)(max.) DQ*2 (Last data valid) DQ*2 (First data no longer valid) All DQS collectively tLZ(DQ)(min.) tHZ(DQ)(max.) Dout n Dout n Dout n+1 Dout n+1 Dout n Dout n+2 Dout n+2 Dout n+1 Data valid Dout n+2 Dout n+3 Dout n+3 Dout n+4 Dout n+4 Dout n+3 Dout n+4 Dout n+5 Dout n+5 Dout n+5 Dout n+6 Dout n+6 Dout n+6 Dout n+7 Dout n+7 Dout n+7 Data valid Notes: 1. BL8, RL = 5(AL = 0, CL = 5). 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] and A12 = 1 during READ command at T0. 5. Output timings are referenced to VDDQ/2, and DLL on for locking. 6. tDQSQ defines the skew between DQS, /DQS to data and does not define DQS, /DQS to clock. 7. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary(either early or late) within a busy. DDR3 Data Strobe to Data Relationship Data Sheet E1797E41 (Ver. 4.1) 100 VIH or VIL EDJ2104EDBG, EDJ2108EDBG tLZ (DQS), tLZ (DQ), tHZ (DQS), tHZ (DQ) Notes tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level which specifies when the device output is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ). The figure below shows a method to calculate the point when device is no longer driving tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistent. The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as singled ended. tLZ(DQS): CK-/CK rising crossing at RL - 1 tLZ(DQ): CK-/CK rising crossing at RL tHZ(DQS), tHZ(DQ) with BL8: CK-/CK rising crossing at RL + 4nCK tHZ(DQS), tHZ(DQ) with BL4: CK-/CK rising crossing at RL + 2nCK CK CK /CK /CK tLZ tHZ VTT + 2x mV VOH - x mV VTT + x mV VOH - 2x mV tLZ(DQS), tLZ(DQ) tHZ(DQS), tHZ(DQ) VOL + 2x mV VTT - x mV VTT - 2x mV T2 T1 VOL + x mV T1 T2 tHZ(DQS), tHZ(DQ) end point = 2 x T1 - T2 tLZ(DQS), tLZ(DQ) begin point = 2 x T1 - T2 Method for Calculating Transitions and Endpoints tRPRE Calculation The method for calculating differential pulse widths for tRPRE is shown as follows. CK VTT /CK tA tB DQS VTT Single ended signal, provided as background information tD tC VTT /DQS Single ended signal, provided as background information t1 tRPRE_begin DQS - /DQS tRPRE 0V Resulting differential signal, relevant for tRPRE specification t2 tRPRE_end Method for Calculating tRPRE Transitions and Endpoint Data Sheet E1797E41 (Ver. 4.1) 101 EDJ2104EDBG, EDJ2108EDBG tRPST Calculation The method for calculating differential pulse widths for tRPST is shown as follows. CK VTT /CK tA DQS VTT Single ended signal, provided as background information tB tC tD VTT /DQS Single ended signal, provided as background information tRPST DQS - /DQS Resulting differential signal, relevant for tRPST specification 0V t1 tRPST_begin t2 tRPST_end Method for Calculating tRPST Transitions and Endpoint Data Sheet E1797E41 (Ver. 4.1) 102 EDJ2104EDBG, EDJ2108EDBG Read Operation During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (auto precharge can be enabled or disabled). * A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) * A12 = 1, BL8 A12 will be used only for burst length control, not a column address. The Burst Read command is initiated by having /CS and /CAS low while holding /RAS and /WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output (DQS) is driven low 1 clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus /CAS latency (CL). The CL is defined by the Mode Register 0 (MR0), similar to the existing SDR and DDR-I SDRAMs. The AL is defined by the Mode Register 1. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK /CK Command*3 READ Address*4 Bank Col n NOP tRPST tRPRE DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ*2 CL = 5 RL = AL + CL VIH or VIL Notes: 1. BL8, AL = 0, RL = 5, CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Operation, RL = 5 Data Sheet E1797E41 (Ver. 4.1) 103 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK Command*3 READ Address*4 Bank Col n NOP tRPST tRPRE DQS, /DQS*2 Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ AL = 4 CL = 5 RL = AL + CL VIH or VIL Notes: 1. BL8, RL = 9, AL = (CL - 1), CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Operation, RL = 9 T0 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 READ NOP NOP READ tCCD Address*4 Bank Col n Bank Col b tRPST tRPRE DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 b+4 b+5 b+6 b+7 DQ*2 RL = 5 RL = 5 VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and T4. Read (BL8) to Read (BL8) Data Sheet E1797E41 (Ver. 4.1) 104 EDJ2104EDBG, EDJ2108EDBG T0 T3 READ NOP T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command* 3 NOP NOP READ tCCD = 5 Address* 4 Bank Col n Bank Col b tRPST tRPRE DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ*2 Dout Dout Dout Dout Dout Dout Dout Dout b b+1 b+2 b+3 b+4 b+5 b+6 b+7 RL = 5 RL = 5 VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0), tCCD = 5. 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and T4. 5. DQS-/DQS is held logic low at T9. Nonconsecutive Read (BL8) to Read (BL8), tCCD = 5 T0 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 READ NOP NOP READ tCCD Address*4 Bank Col b Bank Col n tRPRE tRPST tRPRE tRPST DQS, /DQS Dout Dout Dout Dout n n+1 n+2 n+3 DQ*2 Dout Dout Dout Dout b b+1 b+2 b+3 RL = 5 RL = 5 VIH or VIL Notes: 1. BC4, RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and T4. Read (BC4) to Read (BC4) Data Sheet E1797E41 (Ver. 4.1) 105 EDJ2104EDBG, EDJ2108EDBG T0 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK /CK Command*3 READ NOP WRIT NOP tWR READ to WRIT command delay = RL + tCCD + 2tCK - WL tBL = 4 clocks tWTR Address*4 Bank Col n Bank Col b tRPST tRPRE tWPRE tWPST DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ*2 RL = 5 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 VIH or VIL Notes: 1. BL8, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0 and WRIT command T6. Read (BL8) to Write (BL8) T0 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK /CK Command*3 READ NOP NOP WRIT READ to WRIT Command delay = RL + tCCD/2 + 2tCK - WL tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tRPRE tRPST tWPST tWPRE DQS, /DQS Dout Dout Dout Dout n n+1 n+2 n+3 DQ*2 RL = 5 Din b Din b+1 Din b+2 Din b+3 WL = 5 VIH or VIL Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0 and WRIT command T4. Read (BC4) to Write (BC4) OTF Data Sheet E1797E41 (Ver. 4.1) 106 EDJ2104EDBG, EDJ2108EDBG T0 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 READ NOP NOP READ tCCD Bank Col n Address*4 Bank Col b tRPST tRPRE DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 b b+1 b+2 b+3 DQ*2 RL = 5 RL = 5 VIH or VIL Notes: 1. RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Read (BL8) to Read (BC4) OTF T0 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 READ NOP NOP READ tCCD Address*4 Bank Col n Bank Col b tRPRE tRPST tRPRE tRPST DQS, /DQS Dout Dout Dout Dout n n+1 n+2 n+3 DQ*2 Dout Dout Dout Dout Dout Dout Dout Dout b b+1 b+2 b+3 b+4 b+5 b+6 b+7 RL = 5 RL = 5 Notes: 1. RL = 5 (CL = 5, AL = 0). 2. Dout n (or b) = data-out from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T4. Read (BC4) Read (BL8) OTF Data Sheet E1797E41 (Ver. 4.1) 107 VIH or VIL EDJ2104EDBG, EDJ2108EDBG T0 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK /CK Command*3 READ NOP WRIT NOP tWR READ to WRIT command delay = RL + tCCD/2 + 2tCK - WL tBL = 4 clocks tWTR Address*4 Bank Col n Bank Col b tRPST tRPRE tWPST tWPRE DQS, /DQS Dout Dout Dout Dout n n+1 n+2 n+3 DQ*2 RL = 5 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 VIH or VIL Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n , Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during READ command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4. Read (BC4) to Write (BL8) OTF T0 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 CK /CK Command*3 READ NOP WRIT NOP READ to WRIT command delay = RL + tCCD + 2tCK - WL tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tRPST tRPRE tWPRE tWPST DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ*2 RL = 5 Din b Din b+1 Din b+2 Din b+3 WL = 5 VIH or VIL Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0). 2. Dout n = data-out from column n, n Din b= data-in from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T6. Read (BL8) to Write (BC4) OTF Data Sheet E1797E41 (Ver. 4.1) 108 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK /CK Command*3 READ NOP NOP PRE tRTP = 4 nCK Address*4 tRP Bank Col n tRPST tRPRE DQS, /DQS Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ*2 CL = 5 RL = AL + CL VIH or VIL Notes: 1. BL8, AL = 0, RL = 5, CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Precharge Operation, RL = 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK Command*3 tRTP = 4 nCK Address*4 NOP PRE NOP READ tRP Bank Col n tRPRE tRPST DQS, /DQS*2 Dout Dout Dout Dout Dout Dout Dout Dout n n+1 n+2 n+3 n+4 n+5 n+6 n+7 DQ AL = 4 CL = 5 RL = AL + CL Internal Read command starls here VIH or VIL Notes: 1. BL8, RL = 9, AL = (CL - 1), CL = 5 2. Dout n = data-out from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during READ command at T0. Burst Read Precharge Operation, RL = 9 Data Sheet E1797E41 (Ver. 4.1) 109 EDJ2104EDBG, EDJ2108EDBG Write Timing Definition /CK*1 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRIT NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK Command*3 WL = AL + CWL Address*4 Bank, Col n tDQSS tDSH tWPRE (min) tDSH tDSH tDSH tWPST (min) tDQSS(min) DQS, /DQS tDQSL tDQSH tDQSH tDQSH tDQSH tDQSL tDQSL tDQSL tDQSL (min) tDQSH (min) tDSS tDSS Din n+1 Din n DQ*2 tWPRE (min) Din n+2 tDSH tDSS Din n+3 Din n+4 tDSH tDSS Din n+5 Din n+6 tDSH tDSS Din n+7 tDSH tWPST (min) DQS, /DQS tDQSH tDQSH tDQSH tDQSH tDQSL tDQSL tDQSL tDQSL (min) tDQSL tDQSH (min) tDSS tDSS Din n+1 Din n DQ*2 tDSS Din n+2 Din n+3 tDSS Din n+4 Din n+5 tDSS Din n+6 Din n+7 tDQSS tDSH tDQSS(max) tDSH tDSH tDSH tWPST (min) tWPRE (min) DQS, /DQS tDQSLtDQSHtDQSLtDQSHtDQSLtDQSHtDQSLtDQSH tDQSL (min) tDQSH (min) tDSS tDSS Din n DQ*2 Notes: 1. 2. 3. 4. 5. Din n+1 tDSS Din n+2 Din n+3 tDSS tDSS Din n+4 Din n+5 Din n+6 Din n+7 BL8, WL = 5 (AL = 0, CWL = 5) VIH or VIL Din n = data-in from column n. NOP commands are shown for ease of illustration; other commands may be valid at these times. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. tDQSS must be met at each rising clock edge. Write Timing Definition Data Sheet E1797E41 (Ver. 4.1) 110 EDJ2104EDBG, EDJ2108EDBG tWPRE Calculation The method for calculating differential pulse widths for tWPRE is shown as follows. CK VTT /CK t1 tWPRE_begin DQS - /DQS Resulting differential signal, relevant for tWPRE specification 0V tWPRE t2 tWPRE_end Method for Calculating tWPRE Transitions and Endpoints tWPST Calculation The method for calculating differential pulse widths for tWPST is shown as follows. CK VTT /CK tWPST DQS - /DQS Resulting differential signal, relevant for tWPST specification 0V t1 tWPST_begin t2 tWPST_end Method for Calculating tWPST Transitions and Endpoints Data Sheet E1797E41 (Ver. 4.1) 111 EDJ2104EDBG, EDJ2108EDBG Write Operation During read or write command DDR3 will support BC4 and BL8 on the fly using address A12 during the READ or WRITE (auto precharge can be enabled or disabled). * A12 = 0, BC4 (BC4 = burst chop, tCCD = 4) * A12 = 1, BL8 A12 will be used only for burst length control, not a column address. The Burst Write command is initiated by having /CS, /CAS and /WE low while holding /RAS high at the rising edge of the clock. The address inputs determine the starting column address. Write latency (WL) is equal to (AL + CWL). A data strobe signal (DQS) should be driven low (preamble) one clock prior to the WL. The first data bit of the burst cycle must be applied to the DQ pins at the first rising edge of the DQS following the preamble. The tDQSS specification must be satisfied for write cycles. The subsequent burst bit data are issued on successive edges of the DQS until the burst length of 4 is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. The DQ Signal is ignored after the burst write operation is complete. The time from the completion of the burst write to bank precharge is the write recovery time (tWR). T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK Command*3 NOP WRIT WL = AL + CWL Address*4 Bank Col n tWPRE tWPST DQS, /DQS DQ*2 Din n Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 VIH or VIL Notes: 1. BL8, WL = 5 (AL = 0, CWL = 5) 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. Burst Write Operation, WL = 5 Data Sheet E1797E41 (Ver. 4.1) 112 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK Command*3 WRIT Address*4 Bank Col n NOP tWPST tWPRE DQS, /DQS Din n DQ*2 AL = 4 Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 CWL = 5 WL = AL + CWL VIH or VIL Notes: 1. BL8, WL = 9 (AL = (CL - 1), CL = 5, CWL = 5) 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRITcommand at T0. Burst Write Operation, WL = 9 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Tn Tn+1 Tn+2 CK /CK Command*3 NOP WRIT READ tWTR*5 Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS Din n DQ*2 Din n+1 Din n+2 Din n+3 WL = 5 Notes: RL = 5 1. BC4, WL = 5, RL = 5. 2. Din n = data-in from column n; Dout b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0 and READ command at Tn. 5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7. Write (BC4) to Read (BC4) Operation Data Sheet E1797E41 (Ver. 4.1) 113 VIH or VIL EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Tn Tn+1 Tn+2 CK /CK Command*3 NOP WRIT PRE tWR*5 Address*4 Bank Col n tWPRE tWPST DQS, /DQS Din n DQ*2 Din n+1 Din n+2 Din n+3 WL = 5 Notes: VIH or VIL 1. BC4, WL = 5, RL = 5. 2. Din n = data-in from column n. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [1, 0] during WRIT command at T0. 5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7. tWR specifies the last burst write cycle until the precharge command can be issued to the same bank . Write (BC4) to Precharge Operation T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK Command*3 WRIT NOP NOP WRIT tCCD tWR tBL = 4 clocks tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS DQ*2 Din n Din n+1 Din n+2 WL = 5 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 Notes: 1. BL8, WL = 5 (CWL = 5, AL = 0) VIH or VIL 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by either MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0 and T4. Write (BL8) to Write (BL8) OTF Data Sheet E1797E41 (Ver. 4.1) 114 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CK /CK Command*3 NOP WRIT NOP WRIT tCCD tWR tBL = 4 clocks tWTR Address*4 Bank Col n Bank Col b tWPRE tWPRE tWPST tWPST DQS, /DQS DQ*2 Din n WL = 5 Din n+1 Din n+2 Din b Din n+3 Din b+1 Din b+2 Din b+3 WL = 5 Notes: 1. BC4, WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by either MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0 and T4. VIH or VIL Write (BC4) to Write (BC4) OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 READ NOP CK /CK Command*3 NOP WRIT tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS Din n DQ*2 Din n+1 Din n+2 Din n+3 Din n+4 Din n+5 Din n+6 Din n+7 RL = 5 WL = 5 Notes: 1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0) VIH or VIL 2. Din n = data-in from column n; DOUT b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 0] or MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13. Write (BL8) to Read (BC4/BL8) OTF Data Sheet E1797E41 (Ver. 4.1) 115 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 READ NOP CK /CK Command*3 NOP WRIT tBL = 4 clocks Address*4 tWTR Bank Col b Bank Col n tWPRE tWPST DQS, /DQS Din n DQ*2 Din n+1 Din n+2 Din n+3 RL = 5 WL = 5 Notes: 1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0) 2. Din n = data-in from column n; Dout b = data-out from column b. 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0. READ command at T13 can be either BC4 or BL8 depending on MR0 bit [A1, A0] and A12 status at T13. VIH or VIL Write (BC4) to Read (BC4/BL8) OTF T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 WRIT NOP NOP WRIT tCCD tBL = 4 clocks tWR tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST DQS, /DQS Din n DQ*2 Din n+1 Din n+2 Din n+3 WL = 5 Din n+4 Din n+5 Din n+6 Din n+7 Din b Din b+1 Din b+2 Din b+3 WL = 5 Notes: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T0. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T4. Write (BL8) to Write (BC4) OTF Data Sheet E1797E41 (Ver. 4.1) 116 VIH or VIL EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 WRIT NOP NOP WRIT tCCD tWR tBL = 4 clocks tWTR Address*4 Bank Col n Bank Col b tWPRE tWPST tWPRE tWPST DQS, /DQS Din n DQ*2 WL = 5 Din n+1 Din n+2 Din n+3 Din b Din b+1 Din b+2 Din b+3 Din b+4 Din b+5 Din b+6 Din b+7 WL = 5 Notes: 1. WL = 5 (CWL = 5, AL = 0) 2. Din n (or b) = data-in from column n (or column b). 3. NOP commands are shown for ease of illustration; other commands may be valid at these times. 4. BC4 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 0 during WRIT command at T0. BL8 setting activated by MR0 bit [A1, A0] = [0, 1] and A12 = 1 during WRIT command at T4. Write (BC4) to Write (BL8) OTF Data Sheet E1797E41 (Ver. 4.1) 117 VIH or VIL EDJ2104EDBG, EDJ2108EDBG Write Timing Violations Motivation Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure the DRAM works properly. However it is desirable for certain minor violations, that the DRAM is guaranteed not to "hang up" and error to be limited to that particular operation. For the following it will be assumed that there are no timing violations w.r.t to the write command itself (including ODT etc.) and that it does satisfy all timing requirements not mentioned below. Data Setup and Hold Violations Should the data to strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with this write command. In the example (Figure Write Timing Parameters) the relevant strobe edges for write burst A are associated with the clock edges: T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. Strobe to Strobe and Strobe to Clock Violations Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements (tDSS, tDSH tDQSS) be violated for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offending write command. Subsequent reads from that location might result in unpredictable read data, however the DRAM will work properly otherwise. In the example (Figure Write (BL8) to Write (BL8) OTF) the relevant strobe edges for write burst n are associated with the clock edges: T4, T4.5, T5, T5.5, T6, T6.5, T7, T7.5, T8, T8.5 and T9. Any timing requirements starting and ending on one of these strobe edges are T8, T8.5, T9, T9.5, T10, T10.5, T11, T11.5, T12, T12.5 and T13. Some edges are associated with both bursts. T0 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 CK /CK Command*3 WRIT Address*4 A NOP WRIT NOP B /CS ODTL BL/2 + 2 + ODTL WL tDQSS tDSS tDSH tDQSL tWPRE tDQSH tWPST DQS, /DQS tDH tDS DQ*2 VIH or VIL Write Timing Parameters Data Sheet E1797E41 (Ver. 4.1) 118 EDJ2104EDBG, EDJ2108EDBG Write Data Mask One write data mask (DM) pin for each 8 data bits (DQ) will be supported on DDR3 SDRAMs, Consistent with the implementation on DDR-I SDRAMs. It has identical timings on write operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to ensure matched system timing. DM is not used during read cycles. T1 T2 T3 T4 in in T5 T6 DQS /DQS DQ in in in in in in DM Write mask latency = 0 Data Mask Timing /CK CK [tDQSS(min.)] Command tWR WRIT NOP WL tDQSS DQS, /DQS DQ in0 in2 in3 DM WL [tDQSS(max.)] tDQSS DQS, /DQS DQ in0 in2 in3 DM Data Mask Function, WL = 5, AL = 0 shown Data Sheet E1797E41 (Ver. 4.1) 119 EDJ2104EDBG, EDJ2108EDBG Precharge The precharge command is used to precharge or close a bank that has been activated. The precharge command is triggered when /CS, /RAS and /WE are low and /CAS is high at the rising edge of the clock. The precharge command can be used to precharge each bank independently or all banks simultaneously. Four address bits A10, BA0, BA1 and BA2 are used to define which bank to precharge when the command is issued. [Bank Selection for Precharge by Address Bits] A10 BA0 BA1 BA2 Precharged Bank(s) L L L L Bank 0 only L H L L Bank 1 only L L H L Bank 2 only L H H L Bank 3 only L L L H Bank 4 only L H L H Bank 5 only L L H H Bank 6 only L H H H Bank 7 only H x x x All banks 0 to 7 Remark: H: VIH, L: VIL, x: VIH or VIL Data Sheet E1797E41 (Ver. 4.1) 120 EDJ2104EDBG, EDJ2108EDBG Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the precharge command or the auto precharge function. When a read or a write command is given to the DDR3 SDRAM, the /CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the read or write Command is issued, then normal read or write burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is issued, then the auto precharge function is engaged. During auto precharge, a read Command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is /CAS latency (CL) clock cycles before the end of the read burst. Auto precharge can also be implemented during Write commands. The precharge operation engaged by the Auto precharge command will not begin until the last data of the burst write sequence is properly stored in the memory array. This feature allows the precharge operation to be partially or completely hidden during burst read cycles (dependent upon /CAS latency) thus improving system performance for random data access. The /RAS lockout circuit internally delays the Precharge operation until the array restore operation has been completed so that the auto precharge command may be issued with any read or write command. Burst Read with Auto Precharge If A10 is high when a Read Command is issued, the Read with Auto precharge function is engaged. The DDR3 SDRAM starts an auto precharge operation on the rising edge which is (AL + tRTP) cycles later from the read with AP command when tRAS (min.) is satisfied. If tRAS (min.) is not satisfied at the edge, the start point of auto precharge operation will be delayed until tRAS (min.) is satisfied. A new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) The /RAS precharge time (tRP) has been satisfied from the clock at which the auto precharge begins. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. Burst Write with Auto precharge If A10 is high when a write command is issued, the Write with auto precharge function is engaged. The DDR3 SDRAM automatically begins precharge operation after the completion of the burst writes plus write recovery time (tWR). The bank-undergoing auto precharge from the completion of the write burst may be reactivated if the following two conditions are satisfied. (1) The data-in to bank activate delay time (tWR + tRP) has been satisfied. (2) The /RAS cycle time (tRC) from the previous bank activation has been satisfied. Data Sheet E1797E41 (Ver. 4.1) 121 EDJ2104EDBG, EDJ2108EDBG Auto-Refresh The refresh command (REF) is used during normal operation of the DDR3 SDRAMs. This command is non persistent, so it must be issued each time a refresh is required. The DDR3 SDRAM requires refresh cycles at an average periodic interval of tREFI. When /CS, /RAS and /CAS are held low and /WE high at the rising edge of the clock, the chip enters a refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of the precharge time tRP(min) before the refresh command can be applied. The refresh addressing is generated by the internal refresh controller. This makes the address bits "Don't Care" during a refresh command. An internal address counter supplies the addresses during the refresh cycle. No control of the external address bus is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the refresh command and the next valid command, except NOP or DESL, must be greater than or equal to the minimum refresh cycle time tRFC(min) as shown in the following figure. Note that the tRFC timing parameter depends on memory density. In general, a refresh command needs to be issued to the DDR3 SDRAM regularly every tREFI interval. To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of 8 refresh commands can be postponed during operation of the DDR3 SDRAM, meaning that at no point in time more than a total of 8 refresh commands are allowed to be postponed. In case that 8 refresh commands are postponed in a row, the resulting maximum interval between the surrounding refresh commands is limited to 9 x tREFI. A maximum of 8 additional refresh commands can be issued in advance ("pulled in"), with each one reducing the number of regular refresh commands required later by one. Note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 x tREFI. At any given time, a maximum of 16 REF commands can be issued within 2 x tREFI. Self-refresh mode may be entered with a maximum of eight refresh commands being postponed. After exiting self-refresh mode with one or more refresh commands postponed, additional refresh commands may be postponed to the extent that the total number of postponed refresh commands (before and after the self-refresh) will never exceed eight. During self-refresh mode, the number of postponed or pulled-in REF commands does not change. T0 T1 T2 T3 /CK CK VIH tRP CKE Command PRE tRFC tRFC REF NOP NOP REF Refresh Command Timing tREFI 9 x tREFI t tRFC 8 x REF-Commands postponed Postponing Refresh Command tREFI 9 x tREFI t tRFC 8 x REF-Commands pulled-in Pulling-in Refresh Command Data Sheet E1797E41 (Ver. 4.1) 122 Any Command EDJ2104EDBG, EDJ2108EDBG Self-Refresh The self-refresh command can be used to retain data in the DDR3 SDRAM, even if the rest of the system is powered down. When in the self-refresh mode, the DDR3 SDRAM retains data without external clocking. The DDR3 SDRAM device has a built-in timer to accommodate self-refresh operation. The self-refresh entry (SELF) command is defined by having /CS, /RAS, /CAS and CKE held low with /WE high at the rising edge of the clock. Before issuing the self-refresh entry command, the DDR3 SDRAM must be idle with all bank precharge state with tRP satisfied. `Idle state' is defined as all banks are closed (tRP, tDAL, etc. satisfied), no data bursts are in progress, CKE is high, and all timings from previous operations are satisfied (tMRD, tMOD, tRFC, tZQinit, tZQoper, tZQCS, etc.) Also, on-die termination must be turned off before issuing self-refresh entry command, by either registering ODT pin low "ODTL + 0.5tCK" prior to the self-refresh entry command or using MRS to MR1 command. Once the self-refresh entry command is registered, CKE must be held low to keep the device in self-refresh mode. During normal operation (DLL on), MR1 (A0 = 0), the DLL is automatically disabled upon entering self-refresh and is automatically enabled (including a DLL-Reset) upon exiting self-refresh. When the DDR3 SDRAM has entered self-refresh mode all of the external control signals, except CKE and /RESET, are "don't care". For proper self-refresh operation, all power supply and reference pins (VDD, VDDQ, VSS, VSSQ, VREFCA and VREFDQ) must be at valid levels. VREFDQ supply may be turned OFF and VREFDQ may take any value between VSS and VDD during self-refresh operation, provided that VREFDQ is valid and stable prior to CKE going back high and that first write operation or first write leveling activity may not occur earlier than 512 nCK after exit from self-refresh. The DRAM initiates a minimum of one refresh command internally within tCKESR period once it enters self-refresh mode. The clock is internally disabled during self-refresh operation to save power. The minimum time that the DDR3 SDRAM must remain in self-refresh mode is tCKESR. The user may change the external clock frequency or halt the external clock tCKSRE cycles after self-refresh entry is registered, however, the clock must be restarted and stable tCKSRX clock cycles before the device can exit self-refresh operation. To protect DRAM internal delay on CKE line to block the input signals, one NOP (or DESL) command is needed after self-refresh entry. The procedure for exiting self-refresh requires a sequence of events. First, the clock must be stable prior to CKE going back high. Once a self-refresh exit command (SREX, combination of CKE going high and either NOP or DESL on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command that requires a locked DLL can be applied, a delay of at least tXSDLL must be satisfied. Depending on the system environment and the amount of time spent in self-refresh, ZQ calibration commands may be required to compensate for the voltage and temperature drift as described in ZQ Calibration section. To issue ZQ calibration commands, applicable timing requirements must be satisfied (See Figure ZQ Calibration). CKE must remain high for the entire self-refresh exit period tXSDLL for proper operation except for self-refresh re-entry. Upon exit from self-refresh, the DDR3 SDRAM can be put back into self-refresh mode after waiting at least tXS period and issuing one refresh command (refresh period of tRFC). NOP or DESL commands must be registered on each positive clock edge during the self-refresh exit interval tXS. ODT must be turned off during tXSDLL. The use of self-refresh mode introduces the possibility that an internally timed refresh event can be missed when CKE is raised for exit from self-refresh mode. Upon exit from self-refresh, the DDR3 SDRAM requires a minimum of one extra refresh command before it is put back into self-refresh mode. Data Sheet E1797E41 (Ver. 4.1) 123 EDJ2104EDBG, EDJ2108EDBG Ta Tb Tc Tc+1Tc+2 Td Te Tf Tf+1 Tf+2 Tg Tg+1 Th Th+1 CK, /CK tCKSRE tRP tCKSRX tXSDLL tXS *4 Command PALL SELF NOP SREX tCKESR CKE ODTLoff + 0.5 x tCK ODT Notes: 1. 2. 3. 4. Only NOP or DESL commands. Valid commands not requiring a locked DLL. Valid commands requiring a locked DLL. One NOP or DESL commands. Self-Refresh Entry and Exit Timing Data Sheet E1797E41 (Ver. 4.1) 124 *1 *2 *2 Valid Valid *3 *3 Valid Valid EDJ2104EDBG, EDJ2108EDBG Power-Down Mode Power-down is synchronously entered when CKE is registered low (along with NOP or DESL command). CKE is not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or read/write operation are in progress. CKE is allowed to go low while any of other operations such as row activation, precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing those operations. The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM specifications. During power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after in-progress commands are completed, the device will be in active power-down mode. Entering power-down deactivates the input and output buffers, excluding CK, /CK, ODT, CKE and /RESET. To protect DRAM internal delay on CKE line to block the input signals, multiple NOP or DESL commands are needed during the CKE switch off and cycle(s) after this timing period are defined as tCPDED. CKE_low will result in deactivation of command and address receivers after tCPDED has expired. [Power-Down Entry Definitions] Status of DRAM MR0 bit A12 DLL PD Exit Relevant Parameters Active (A bank or more open) Don't Care On Fast tXP to any valid command Precharged (All banks precharged) 0 Off Slow tXP to any valid command. Since it is in precharge state, commands here will be ACT, AR, MRS, PRE or PALL . tXPDLL to commands who need DLL to operate, such as READ, READA or ODT control line. Precharged (All banks precharged) 1 On Fast tXP to any valid command Also the DLL is disabled upon entering precharge power-down for slow exit mode, but the DLL is kept enabled during precharge power-down for fast exit mode or active power-down. In power-down mode, CKE low, RESET high and a stable clock signal must be maintained at the inputs of the DDR3 SDRAM, and ODT should be in a valid state but all other input signals are "Don't Care" (If RESET goes low during power-down, the DRAM will be out of PD mode and into reset state). CKE low must be maintained until tPD has been satisfied. Power-down duration is limited by 9 times tREFI of the device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or DESL command). CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at AC Characteristics table of this data sheet. Data Sheet E1797E41 (Ver. 4.1) 125 EDJ2104EDBG, EDJ2108EDBG Timing Diagrams for Proposed CKE with Power-Down Entry, Power-Down Exit T0 /CK CK Command T1 T5 T6 T7 T8 T9 READ BA T10 T11 NOP NOP Tx Tx+1 Valid tCPDED tRDPDEN CKE T12 tIS VIH RL = CL + AL = 5 (AL = 0) tPD DQ(BL8) out 0 out 1 out 2 DQ(BC4) out 0 out out 1 2 out out 3 4 out out 5 6 out 7 out 3 Power-Down Entry after Read and Read with Auto Precharge T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T14 T15 T16 T17 T18 CK /CK Command BA NOP WRITA NOP NOP Valid tCPDED tIS CKE tWRAPDEN tPD tWR* WL=5 DQ(BL8) in 0 in 1 in 2 in 3 DQ(BC4) in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 Start Internal Precharge Note: tWR is programmed through MRS. Power-Down Entry After Write with Auto Precharge Data Sheet E1797E41 (Ver. 4.1) 126 Tn EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 Tx Tx+1 Tx+2 Tx+3 CK /CK Command WRITE BA NOP NOP Valid tCPDED tIS CKE tWRPDEN tPD tWR WL=5 DQ(BL8) in 0 in 1 in 2 in 3 DQ(BC4) in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 Power-Down Entry after Write T0 T1 Tn Tn+1 Tx Ty CK /CK tPD tIH tIH CKE tIS tIS tCPDED Command Valid NOP NOP tCKE (min.) NOP NOP NOP NOP NOP Valid NOP NOP NOP NOP N tXP Enter power-down mode Exit power-down Note: Valid command at T0 is ACT, NOP, DESL or precharge with still one bank remaining open after completion of precharge command. Active Power-Down Entry and Exit Timing Diagram T0 T1 Tn Tn+1 Tx Ty CK /CK tPD tIH tIH CKE tIS tIS tCPDED Command Valid NOP NOP tCKE (min.) NOP NOP NOP NOP NOP Valid NOP NOP NOP NOP N tXP Exit power-down Enter power-down mode Precharge Power-Down (Fast Exit Mode) Entry and Exit Data Sheet E1797E41 (Ver. 4.1) 127 EDJ2104EDBG, EDJ2108EDBG T0 T1 Tn Tx Tn+1 Ty CK /CK tIH tIH CKE tIS tIS tPD tCPDED Command Valid NOP tCKE (min.) NOP NOP NOP NOP NOP NOP NOP Valid NOP Valid NOP NO tXP tXPDLL Exit power-down Enter power-down mode Precharge Power-Down (Slow Exit Mode) Entry and Exit T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 T8 T9 T10 T11 CK /CK Valid Command tCPDED tREFPDEN tIS CKE Refresh Command to Power-Down Entry T0 T1 T2 T3 Valid NOP NOP T4 Tn Tn+1 Tn+2 CK /CK Command tCPDED tPD tACTPDEN tIS CKE Active Command to Power-Down Entry Data Sheet E1797E41 (Ver. 4.1) 128 End EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 T8 T9 T10 T11 Tn+6 Tn+7 CK /CK Command Valid tCPDED tPREPDEN tIS CKE Precharge/Precharge All Command to Power-Down Entry T0 T1 T2 T3 Tn Tn+1 Tn+2 MRS NOP NOP NOP NOP NOP Tn+3 CK /CK Command tCPDED tMRSPDEN tIS CKE MRS Command to Power-Down Entry Data Sheet E1797E41 (Ver. 4.1) 129 Tn+4 Tn+5 End EDJ2104EDBG, EDJ2108EDBG Timing Values tXXXPDEN Parameters Status of DRAM Last Command before CKE_low Parameter Parameter Value Unit Idle or Active Activate tACTPDEN 1 nCK Idle or Active Precharge tPRPDEN 1 nCK Active READ/READA tRDPDEN RL + 4 + 1 Active WRIT for BL8MRS, BL8OTF, BC4OTF tWRPDEN WL + 4 + (tWR/tCK (avg)) * 1 nCK tWRPDEN 1 nCK Active WRIT for BC4MRS nCK WL + 2 + (tWR/tCK (avg))* 2 nCK 2 Active WRITA for BL8MRS, BL8OTF, BC4OTF tWRAPDEN WL + 4 + WR* + 1 Active WRITA for BC4MRS tWRAPDEN WL + 2 + WR* + 1 nCK Idle Refresh tREFPDEN 1 nCK Idle Mode Register Set tMRSPDEN tMOD Notes: 1. tWR is defined in ns, for calculation of tWRPDEN, it is necessary to round up tWR / tCK to next integer. 2. WR in clock cycles as programmed in mode register. Power-Down Entry and Exit Clarification Case 1: When CKE registered low for power-down entry, tPD must be satisfied before CKE can be registered high for powerdown exit. Case 1a: After power-down exit, tCKE must be satisfied before CKE can be registered low again. T0 T1 Tn Tn+1 Tx Ty CK /CK tIH tIH CKE tIS tIS tPD tCKE tCPDED Command Valid NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP N Exit power-down Enter power-down Power-Down Entry/Exit Clarifications (1) Data Sheet E1797E41 (Ver. 4.1) 130 EDJ2104EDBG, EDJ2108EDBG Case 2: For certain CKE intensive operations, for example, repeated "PD Exit - Refresh - PD Entry" sequence, the number of clock cycles between PD Exit and PD Entry may be insufficient to keep the DLL updated. Therefore the following conditions must be met in addition to tPD in order to maintain proper DRAM operation when Refresh commands is issued in between PD Exit and PD Entry. Power-down mode can be used in conjunction with Refresh command if the following conditions are met: 1. tXP must be satisfied before issuing the command 2. tXPDLL must be satisfied (referenced to registration of PD exit) before next power-down can be entered. CK T0 T1 Tn Tn+1 Tx Ty /CK tIH tIH CKE tIS tIS tCPDED tXPDLL (min.) tCKE (min.) tPD Command Valid NOP NOP NOP NOP REF NOP NOP NOP NOP NOP NOP NOP tXP Enter power-down Exit power-down Power-Down Entry/Exit Clarifications (2) Case 3: If an early PD Entry is issued after Refresh command, once PD Exit is issued, NOP or DESL with CKE high must be issued until tRFC from the refresh command is satisfied. This means CKE cannot be de-asserted twice within tRFC window. T0 T1 Tn Tn+1 Tx Ty CK /CK tIH tIH CKE tIS tIS tPD tXPDLL tCPDED Command REF NOP NOP tCKE (min.) NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP N tRFC (min.) Enter power-down Exit power-down Note: * Synchronous ODT Timing starts at the end of tXPDLL (min.) Power-Down Entry/Exit Clarifications (3) Data Sheet E1797E41 (Ver. 4.1) 131 EDJ2104EDBG, EDJ2108EDBG Input Clock Frequency Change during Precharge Power-Down Once the DDR3 SDRAM is initialized, the DDR3 SDRAM requires the clock to be "stable" during almost all states of normal operation. This means once the clock frequency has been set and is to be in the "stable state", the clock period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (Spread Spectrum Clocking) specifications. The input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self-refresh mode and (2) precharge power-down mode. Outside of these two modes, it is illegal to change the clock frequency. For the first condition, once the DDR3 SDRAM has been successfully placed in to SelfRefresh mode and tCKSRE has been satisfied, the state of the clock becomes a don't care. Once a don't care, changing the clock frequency is permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh mode for the sole purpose of changing the clock frequency, the self-refresh entry and exit specifications must still be met as outlined in Self-Refresh section. The second condition is when the DDR3 SDRAM is in Precharge Power-down mode (either fast exit mode or slow exit mode.) ODT must be at a logic low ensuring RTT is in an off state prior to entering Precharge Power-down mode and CKE must be at a logic low. A minimum of tCKSRE must occur after CKE goes low before the clock frequency may change. The DDR3 SDRAM input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed grade. During the input clock frequency change, ODT and CKE must be held at stable low levels. Once the input clock frequency is changed, stable new clocks must be provided to the DRAM tCKSRX before Precharge Power-down may be exited; after Precharge Power-down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL with CKE continuously registered high. During DLL relock period, ODT must remain low. After the DLL lock time, the DRAM is ready to operate with new clock frequency. This process is depicted in the figure Clock Frequency Change in Precharge Power-Down Mode. Previous clock frequency T0 T1 T2 Ta New clock frequency Tb Tc Tc+1 Td Td+1 Te Te+1 NOP MRS NOP Valid /CK CK tIS tIH tCKSRE tCKSRX CKE tCPDED Command NOP NOP NOP NOP DLL RESET Address Valid tXP tAOFPD/tAOF ODT DQS, /DQS DQ tDLLK High-Z High-Z DM Enter precharge power-down mode Frequency change Exit precharge power-down mode Notes: 1. Applicable for both slow exit and fast exit precharge power-down. 2. tCKSRE and tCKSRX are self-refresh mode specifications but the values they represent are applicable here. 3. tAOFPD and tAOF must be satisfied and outputs high-z prior to T1; refer to ODT timing for exact requirements. Clock Frequency Change in Precharge Power-Down Mode Data Sheet E1797E41 (Ver. 4.1) 132 EDJ2104EDBG, EDJ2108EDBG On-Die Termination (ODT) ODT (On-Die Termination) is a feature of the DDR3 SDRAM that allows the DRAM to turn on/off termination resistance for each DQ, DQS, /DQS and DM for x4 and x8 configuration (and TDQS, /TDQS for x8 configuration, when enabled via A11=1 in MR1) via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices. The ODT feature is turned off and not supported in Self-Refresh mode. A simple functional representation of the DRAM ODT feature is shown in figure Functional Representation of ODT. ODT To other circuitry like RCV, ... VDDQ/2 RTT Switch DQ, DQS, DM, TDQS Functional Representation of ODT The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control information, see below. The value of RTT is determined by the settings of mode register bits (see MR1 programming figure in the section Programming the Mode Register). The ODT pin will be ignored if the Mode Register MR1 is programmed to disable ODT and in self-refresh mode. ODT Mode Register and ODT Truth Table The ODT Mode is enabled if either of MR1 bits A2 or A6 or A9 are non-zero. In this case the value of RTT is determined by the settings of those bits. Application: Controller sends WRIT command together with ODT asserted. * One possible application: The rank that is being written to provide termination. * DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR) * DRAM does not use any write or read command decode information * The Termination Truth Table is shown in the Termination Truth Table [Termination Truth Table] ODT pin DRAM Termination State 0 OFF 1 ON, (OFF, if disabled by MR1 bits A2, A6 and A9 in general) Data Sheet E1797E41 (Ver. 4.1) 133 EDJ2104EDBG, EDJ2108EDBG Synchronous ODT Mode Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition, these modes are: * Active mode * Idle mode with CKE high * Active power-down mode (regardless of MR0 bit A12) * Precharge power-down mode if DLL is enabled during precharge power-down by MR0 bit A12. In synchronous ODT mode, RTT will be turned on or off ODTLon clock cycles after ODT is sampled high by a rising clock edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL - 2. ODT Latency and Posted ODT In Synchronous ODT mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency (AL) relative to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to DDR3 SDRAM latency definitions. [ODT Latency Table] Parameter Symbol Value Unit ODT turn-on Latency ODTLon WL - 2 = CWL + AL - 2 nCK ODT turn-off Latency ODTLoff WL - 2 = CWL + AL - 2 nCK Synchronous ODT Timing Parameters In synchronous ODT mode, the following timing parameters apply (see Synchronous ODT Timing Examples (1)): ODTLLow, ODTLLoff, tAON,(min.), (max.), tAOF,(min.),(max.) Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is fully on. Both are measured from ODTLon. Minimum RTT turn-off time (tAOF min ) is the point in time when the device starts to turn-off the ODT resistance. Maximum RTT turn-off time (tAOF max) is the point in time when the on-die termination has reached high impedance. Both are measured from ODTLoff. When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BL4) or ODTH8 (BL8) after the Write command (see figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a Write command until ODT is registered low. Data Sheet E1797E41 (Ver. 4.1) 134 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 END CK /CK CKE ODTH4 (min.) ODT AL = 3 AL = 3 IntODT ODTLon = CWL + AL - 2 ODTLoff = CWL + AL - 2 CWL - 2 tAOF (max.) tAOF (min.) tAON (max.) tAON (min.) RTT RTT Synchronous ODT Timing Examples (1): AL=3, CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 CK /CK CKE Command WRS4 ODTH4 ODTH4 ODTH4 ODT ODTLoff = WL - 2 ODTLoff = WL - 2 ODTLon = WL - 2 ODTLon = WL - 2 tAON (max.) tAON (min.) DRAM_RTT RTT tAOF (max.) tAOF (min.) tAOF (max.) tAOF (min.) RTT tAON (max.) tAON (min.) Synchronous ODT Timing Examples (2)*: BC4, WL = 7 ODT must be held high for at least ODTH4 after assertion (T1); ODT must be kept high ODTH4 (BC4) or ODTH8 (BL8) after write command (T7). ODTH is measured from ODT first registered high to ODT first registered low, or from registration of write command with ODT high to ODT registered low. Note that although ODTH4 is satisfied from ODT registered high at T6 ODT must not go low before T11 as ODTH4 must also be satisfied from the registration of the write command at T7. Data Sheet E1797E41 (Ver. 4.1) 135 EDJ2104EDBG, EDJ2108EDBG ODT during Reads As the DDR3 SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock cycle before the read preamble by driving the ODT pin low appropriately. RTT may nominally not be enabled until one clock cycle after the end of the post-amble as shown in the example in the figure below. Note that ODT may be disabled earlier before the Read and enabled later after the Read than shown in this example in the figure below. ODT must be disabled externally during Reads by driving ODT low. (example: CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTLon = CWL + AL -2 = 8; ODTLoff = CWL + AL - 2 = 8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 End CK /CK Command Address READ A RL = AL + CL ODT ODTLoff = WL - 2 = CWL + AL - 2 ODTLon = WL - 2 = CWL + AL - 2 tAOF (max.) tAOF (min.) DRAM_RTT tAON (min.) tAON (max.) RTT RTT DQS, /DQS out out out out out out out out 0 1 2 3 4 5 6 7 DQ Example of ODT during Reads Data Sheet E1797E41 (Ver. 4.1) 136 EDJ2104EDBG, EDJ2108EDBG Dynamic ODT In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination strength of the DDR3 SDRAM can be changed without issuing an MRS command. This requirement is supported by the "Dynamic ODT" feature as described as follows: Functional Description: The Dynamic ODT mode is enabled if bit A9 or A10 of MR2 is set to '1'. The function and is described as follows: * Two RTT values are available: RTT_Nom and RTT_WR. The value for RTT_Nom is pre-selected via bits A[9,6,2] in MR1 The value for RTT_WR is pre-selected via bits A[10,9] in MR2 * During operation without write commands, the termination is controlled as follows: Nominal termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff. * When a write command (WRIT, WRITA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is enabled, the termination is controlled as follows: A latency ODTLcnw after the write command, termination strength RTT_WR is selected. A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected OTF) after the write command, termination strength RTT_Nom is selected. Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff. Table Latencies and Timing Parameters Relevant for Dynamic ODT shows latencies and timing parameters, which are relevant for the on-die termination control in Dynamic ODT mode: When ODT is asserted, it must remain high until ODTH4 is satisfied. If a write command is registered by the SDRAM with ODT high, then ODT must remain high until ODTH4 (BC4) or ODTH8 (BL8) after the write command (see the figure Synchronous ODT Timing Examples (2)). ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a write command until ODT is registered low. [Latencies and Timing Parameters Relevant for Dynamic ODT] Parameters Symbols ODT turn-on Latency ODTLon ODT turn-off Latency ODTLoff ODT latency for changing from RTT_Nom to RTT_WR ODT latency for change from RTT_WR to RTT_Nom (BC4) ODT latency for change from RTT_WR to RTT_Nom (BL8) Minimum ODT high time after ODT assertion Minimum ODT high time after Write (BC4) Minimum ODT high time after Write (BL8) RTT change skew ODTLcnw Defined from Registering external ODT signal high Registering external ODT signal low Registering external write command Defined to Definition for all DDR3 speed bins Unit Turning termination on ODTLon = WL - 2 nCK Turning termination off ODTLoff = WL - 2 nCK Change RTT strength from ODTLcnw = WL - 2 RTT_Nom to RTT_WR nCK ODTLcwn4 Registering external write command Change RTT strength from ODTLcwn4 = RTT_WR to RTT_Nom 4 + ODTLoff nCK ODTLcwn8 Registering external write command Change RTT strength from ODTLcwn8 = RTT_WR to RTT_Nom 6 + ODTLoff nCK ODTH4 registering ODT high ODT registered low ODTH4 ODTH8 tADC registering Write with ODT registered low ODT high registering Write with ODT registered low ODT high ODTLcnw RTT valid ODTLcwn Data Sheet E1797E41 (Ver. 4.1) 137 ODTH4 (min.) = 4 nCK ODTH4 (min.) = 4 nCK ODTH8 (min.) = 6 nCK 0.3 to 0.7 tCK (avg) EDJ2104EDBG, EDJ2108EDBG Mode Register Settings for Dynamic ODT Mode: The table Mode Register for RTT Selection shows the mode register bits to select RTT_Nom and RTT_WR values. [Mode Register for RTT Selection] MR1 MR2 A9 A6 A2 RTT_Nom (RZQ) 0 0 0 off off 0 0 1 RZQ/4 60 0 1 RZQ/4 60 0 1 0 RZQ/2 120 1 0 RZQ/2 120 0 1 1 RZQ/6 40 1 1 Reserved Reserved 2 RTT_Nom () A10 A9 0 0 RTT_WR (RZQ) RTT_WR* () Dynamic ODT OFF: Write does not affect RTT value 20 30 Reserved Reserved Reserved Reserved 1 0 0 RZQ/12* 1 0 1 RZQ/8* 1 1 0 1 1 1 2 1 Notes: 1. RZQ = 240. 2. If RTT_Nom is used during WRITEs, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed. ODT Timing Diagrams T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 CK /CK ODTLcnw Command WRS4 ODTH4 ODTH4 ODT ODTLon RTT ODTLoff tAON (min.) tADC (min.) RTT_Nom RTT_WR tAON (max.) tADC (max.) tADC (min.) tAOF (min.) RTT_Nom tADC (max.) tAOF (max.) ODTLcwn4 DQS, /DQS in in in in 0 1 2 3 DQ WL Dynamic ODT: Behavior with ODT Being Asserted Before and after the Write* Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the write command. In this example ODTH4 would be satisfied if ODT is low at T8 (4 clocks after the write command). Data Sheet E1797E41 (Ver. 4.1) 138 EDJ2104EDBG, EDJ2108EDBG T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK /CK Command ODTH4 ODT ODTLon ODTLoff tAON (min.) tAOF (min.) RTT_Nom RTT tAON (max.) tAOF (max.) DQS, /DQS DQ Dynamic ODT*: Behavior without Write Command; AL = 0, CWL = 5 Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 CK /CK ODTLcnw Command WRS8 ODTH8 ODT ODTLon ODTLoff tAON (min.) tAOF (min.) RTT RTT_WR tADC (max.) tAOF (max.) ODTLcwn8 DQS, /DQS in 0 DQ in 1 in 2 in 3 in 4 in 5 in 6 in 7 WL Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for Duration of 6 Clock Cycles Note: Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH8 = 6 is exactly satisfied. Data Sheet E1797E41 (Ver. 4.1) 139 EDJ2104EDBG, EDJ2108EDBG T0 CK /CK T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 ODTLcnw Command WRS4 ODTH4 ODT ODTLon ODTLoff tAON (min.) tAOF (min.) tADC (min.) RTT RTT_WR RTT_Nom tADC (max.) tADC (max.) tAOF (max.) ODTLcwn4 DQS, /DQS in 0 DQ in 1 in 2 in 3 WL Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for a Duration of 6 Clock Cycles, Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. Note: ODTH4 is defined from ODT registered high to ODT registered low, so in this example ODTH4 is satisfied; ODT registered low at T5 would also be legal. T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 CK /CK ODTLcnw Command WRS4 ODTH4 ODT ODTLon ODTLoff tAON (min.) tAOF (min.) RTT RTT_WR tAOF (max.) tADC (max.) ODTLcwn4 DQS, /DQS in 0 DQ in 1 in 2 in 3 WL Dynamic ODT*: Behavior with ODT Pin Being Asserted Together with Write Command for Duration of 4 Clock Cycles Note: Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example ODTH4 = 4 is exactly satisfied. Data Sheet E1797E41 (Ver. 4.1) 140 EDJ2104EDBG, EDJ2108EDBG Asynchronous ODT Mode Asynchronous ODT mode is selected when DRAM runs in DLL-on mode, but DLL is temporarily disabled (i.e. frozen) in precharge power-down (by MR0 bit A12). Precharge power-down mode if DLL is disabled during precharge power-down by MR0 bit A12. In asynchronous ODT timing mode, internal ODT command is not delayed by Additive Latency (AL) relative to the external ODT command. In asynchronous ODT mode, the following timing parameters apply (see figure Asynchronous ODT Timings): tAONPD (min.), (max.), tAOFPD (min.),(max.) Minimum RTT turn-on time (tAONPD (min.)) is the point in time when the device termination circuit leaves high impedance state and ODT resistance begins to turn on. Maximum RTT turn-on time (tAONPD (max.)) is the point in time when the ODT resistance is fully on. tAONPD (min.) and tAONPD (max.) are measured from ODT being sampled high. Minimum RTT turn-off time (tAOFPD (min.)) is the point in time when the devices termination circuit starts to turn off the ODT resistance. Maximum ODT turn-off time (tAOFPD (max.)) is the point in time when the on-die termination has reached high impedance. tAOFPD (min.) and tAOFPD (max.) are measured from ODT being sampled low. CK /CK CKE tIH tIH tIS tIS ODT tAOFPD (min.) tAONPD (max.) RTT DRAM_RTT tAONPD (min.) tAOFPD (max.) Asynchronous ODT Timings on DDR3 SDRAM with Fast ODT Transition: AL is Ignored In precharge power-down, ODT receiver remains active, however no read or write command can be issued, as the respective address/command receivers may be disabled. [Asynchronous ODT Timing Parameters for All Speed Bins] Symbol Parameters min. max. Unit tAONPD Asynchronous RTT turn-on delay (power-down with DLL frozen) 2 8.5 ns tAOFPD Asynchronous RTT turn-off delay (power-down with DLL frozen) 2 8.5 ns [ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period] Description min. max. ODT to RTT turn-on delay min {ODTLon x tCK + tAON(min.); tAONPD(min.) } min { (WL - 2) x tCK + tAON(min.); tAONPD(min.) } min { ODTLoff x tCK +tAOF(min.); tAOFPD(min.) } min { (WL - 2) x tCK +tAOF(min.); tAOFPD(min.) } max {ODTLon x tCK + tAON(max.); tAONPD(max.) } max {(WL - 2) x tCK + tAON(max.); tAONPD(max.) } max { ODTLoff x tCK + tAOF(max.); tAOFPD(max.) } max {(WL - 2) x tCK + tAOF(max.); tAOFPD(max.) } ODT to RTT turn-off delay WL - 1 tANPD Data Sheet E1797E41 (Ver. 4.1) 141 EDJ2104EDBG, EDJ2108EDBG Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0 there is a transition period around power-down entry, where the DDR3 SDRAM may show either synchronous or asynchronous ODT behavior. This transition period ends when CKE is first registered low and starts tANPD before that. If there is a Refresh command in progress while CKE goes low, then the transition period ends tRFC after the refresh command. tANPD is equal to (WL - 1) and is counted (backwards) from the clock cycle where CKE is first registered low. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.) and (ODTLon x tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon x tCK + tAON(max.)). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.) and (ODTLoff x tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff x tCK + tAOF(max.)). Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows the three different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition period; ODT_C shows a state change after the transition period. CK /CK Command REF NOP NOP CKE PD entry transition period tANPD ODT tRFC ODT_A_sync ODTLoff tAOF (max.) tAOF (min.) DRAM_RTT_A_sync RTT ODT_B_tran ODTLoff + tAOFPD (max.) tAOFPD (max.) ODTLoff + tAOFPD (min.) tAOFPD (min.) DRAM_RTT_B_tran ODT_C_async tAOFPD (max.) tAOFPD (min.) DRAM_RTT_C_async RTT Synchronous to Asynchronous Transition During Precharge Power-Down (with DLL Frozen) Entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4) Data Sheet E1797E41 (Ver. 4.1) 142 EDJ2104EDBG, EDJ2108EDBG Asynchronous to Synchronous ODT Mode Transition during Power-Down Exit If DLL is selected to be frozen in precharge power-down mode by the setting of bit A12 in MR0 to 0, there is also a transition period around power-down exit, where either synchronous or asynchronous response to a change in ODT must be expected from the DDR3 SDRAM. This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered high. tANPD is equal to (WL - 1) and is counted backward from the clock cycle where CKE is first registered high. ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPD(min.) and (ODTLon x tCK + tAON(min.)) and as late as the larger of tAONPD(max.) and (ODTLon x tCK + tAON(max.)). ODT de-assertion during the transition period may result in an RTT change as early as the smaller of tAOFPD(min.) and (ODTLoff x tCK + tAOF(min.)) and as late as the larger of tAOFPD(max.) and (ODTLoff x tCK + tAOF(max.)). See ODT for Power-Down (with DLL Frozen) Entry and Exit Transition Period table. Note that, if AL has a large value, the range where RTT is uncertain becomes quite large. The figure below shows the three different cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition period; ODT_A shows a state change of ODT after the transition period with synchronous response. T1 T3 T5 T7 T9 T11 T13 T15 T17 T19 T21 T23 T25 T27 T29 T31 T33 T35 CK /CK Command NOP NOP CKE PD exit transition period tANPD ODT_C_async tXPDLL tAOFPD (max.) tAOFPD (min.) DRAM_RTT_C_async RTT ODT_B_tran tAOFPD (min.) ODTLoff + tAOF (min.) ODTLoff + tAOF (max.) tAOFPD (max.) DRAM_RTT_B_tran ODT_A_sync ODTLoff tAOF (max.) tAOF (min.) DRAM_RTT_A_sync RTT Asynchronous to Synchronous Transition during Precharge Power-Down (with DLL Frozen) Exit (CL = 6; AL = CL - 1; CWL = 5; tANPD= WL - 1 = 9) Data Sheet E1797E41 (Ver. 4.1) 143 EDJ2104EDBG, EDJ2108EDBG Asynchronous to Synchronous ODT Mode during Short CKE high and Short CKE Low Periods If the total time in precharge power-down state or idle state is very short, the transition periods for power-down entry and power-down exit may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the power-down entry transition period to the end of the PD exit transition period (even if the entry period ends later than the exit period). If the total time in idle state is very short, the transition periods for power-down exit and power-down entry may overlap. In this case the response of the DDR3 SDRAM RTT to a change in ODT state at the input may be synchronous OR asynchronous from the start of the power-down exit transition period to the end of the power-down entry transition period. Note that in the bottom part of figure below it is assumed that there was no refresh command in progress when idle state was entered. CK /CK Command CKE REF NOP NOP NOP NOP tANPD tRFC PD entry transition period PD exit transition period tANPD tXPDLL short CKE low transition period CKE tANPD tANPD tXPDLL tXPDLL short CKE high transition period Transition Period for Short CKE Cycles with Entry and Exit Period Overlapping (AL = 0, WL = 5, tANPD = WL - 1 = 4) Data Sheet E1797E41 (Ver. 4.1) 144 EDJ2104EDBG, EDJ2108EDBG ZQ Calibration ZQ calibration command is used to calibrate DRAM RON and ODT values. DDR3 SDRAM needs longer time to calibrate RON and ODT at initialization and relatively smaller time to perform periodic calibrations. ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may be issued at any time by the controller depending on the system environment. ZQCL command triggers the calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from calibration engine to DRAM I/O which gets reflected as updated RON and ODT values. The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a timing period of tZQoper. ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS. One ZQCS command can effectively correct a minimum of 0.5% (ZQCorrection) of RON and RTT impedance error within 64nCK for all speed bins assuming the maximum sensitivities specified in the `Output Driver Voltage and Temperature Sensitivity' and `ODT Voltage and Temperature Sensitivity' tables. The appropriate interval between ZQCS commands can be determined from these tables and other application-specific parameters. One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage (Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the following formula: x x where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature and voltage sensitivities. For example, if TSens = 1.5%/C, VSens = 0.15%/mV, Tdriftrate = 1C/sec and Vdriftrate = 15mV/sec, then the interval between ZQCS commands is calculated as: 0.5 = 0.133 128ms (1.5 x 1) + (0.15 x 15) No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper or tZQCS. The quiet time on the DRAM channel allows in accurate calibration of RON and ODT. Once DRAM calibration is achieved the DRAM should disable ZQ current consumption path to reduce power. All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller. ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self-refresh. Upon selfrefresh exit, DDR3 SDRAM will not perform an I/O calibration without an explicit ZQ calibration command. The earliest possible time for ZQ Calibration command (short or long) after self-refresh exit is tXS. In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit or tZQCS between the devices. CK Command A10 ZQCL NOP/DESL Valid ZQCS A10 = H A10 = L X X Address NOP/DESL Valid CKE tZQinit or tZQ oper DQ Bus*2 tZQCS Hi-Z Activities Notes: 1. CKE must be continuously registered high during the calibration procedure. 2. ODT must be disabled via ODT signal or MRS during calibration procedure. 3. All device connected to DQ bus should be High impedance during calibration. ZQ Calibration Data Sheet E1797E41 (Ver. 4.1) 145 Hi-Z Activities EDJ2104EDBG, EDJ2108EDBG ZQ External Resistor Value and Tolerance DDR3 SDRAM has a 240 1% tolerance external resistor connecting from the DDR3 SDRAM ZQ pin to ground. The resister can be used as single DRAM per resistor. Data Sheet E1797E41 (Ver. 4.1) 146 EDJ2104EDBG, EDJ2108EDBG Package Drawing 78-ball FBGA Solder ball: Lead free (Sn-Ag-Cu) Unit: mm 7.50 0.10 0.20 S B 10.60 0.10 INDEX MARK 0.20 S A 0.20 S 1.20 max. S 0.35 0.05 0.10 S 0.8 A INDEX MARK 1.6 6.4 0.15 M S A B 9.6 78-0.45 0.05 B 0.8 ECA-TS2-0306-01 Data Sheet E1797E41 (Ver. 4.1) 147 EDJ2104EDBG, EDJ2108EDBG Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDJ2104EDBG, EDJ2108EDBG. Type of Surface Mount Device EDJ2104EDBG, EDJ2108EDBG: 78-ball FBGA < Lead free (Sn-Ag-Cu) > Data Sheet E1797E41 (Ver. 4.1) 148 EDJ2104EDBG, EDJ2108EDBG NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 Data Sheet E1797E41 (Ver. 4.1) 149 EDJ2104EDBG, EDJ2108EDBG The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. 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[Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] Usage in environments with special characteristics as listed below was not considered in the design. Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. Example: 1) Usage in liquids, including water, oils, chemicals and organic solvents. 2) Usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 , SO 2 , and NO x . 4) Usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) Usage in places where dew forms. 6) Usage in environments with mechanical vibration, impact, or stress. 7) Usage near heating elements, igniters, or flammable items. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E1007 Data Sheet E1797E41 (Ver. 4.1) 150