PL138-48 2.5V to 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer Features General Description * * * * The PL138-48 is a high performance low-cost 1:4 outputs differential LVPECL fanout buffer. * * * * * * * Four Differential 2.5V/3.3V LVPECL Output Pairs Output Frequency: 800 MHz Two Selectable Differential Input Pairs Translates Any Standard Single-Ended or Differential Input Format to LVPECL Output. It Can Accept the Following Standard Input Formats and More: - LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML Output Skew: 25 ps (typ.) Part-to-Part Skew: 140 ps (typ.) Propagation Delay: 1.5 ns (typ.) Additive Jitter: <100 fs (max.) Operating Supply Voltage: 2.375V ~ 3.63V Operating Temperature Range from -40C to +85C Package Availability: 16-Pin QFN and 20-Pin TSSOP 2016 Microchip Technology Inc. Microchip's family of differential LVPECL buffers are designed to operate from a single power supply of 2.5V 5% or 3.3V 10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to-lot skew. Designed to fit in a small form-factor package, the PL138-48 offers up to 800 MHz of output operation with very low-power consumption and lowest additive jitter of any comparable device. Block Diagram DS20005543B-page 1 PL138-48 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Supply Voltage (VDD) ...............................................................................................................................................+4.6V Input Voltage, DC (VI)..........................................................................................................................-0.5V to VDD+0.5V Output Voltage, DC (VO) .....................................................................................................................-0.5V to VDD+0.5V ESD Protection (HBM) ...............................................................................................................................................2 kV Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS Specifications: VCC = 3.3V; VEE = 0V. Input and output parameters vary 1:1 with VCC when VCC varies 10%. Parameters Output High Voltage, (Note 1) Output Voltage Low, (Note 1) Input High Voltage Input Low Voltage Output Voltage Reference, (Note 2) Input High Voltage Common Mode Range, (Note 3, Note 4) Input High Current, (Note 5) Input Low Current, (Note 5) Note 1: 2: 3: 4: 5: Symbol VOH VOL VIH VIL VBB VCMR IIH IIL Min. Typ. Max. Units Conditions 2.215 2.320 2.420 2.275 2.350 2.420 2.275 2.350 2.420 At +85C 1.470 1.610 1.745 At -40C 1.490 1.585 1.680 1.490 1.585 1.680 At +85C 2.075 -- 2.420 At -40C 2.135 -- 2.420 2.135 -- 2.420 At +85C 1.470 -- 1.890 At -40C 1.490 -- 1.825 1.490 -- 1.825 At +85C 1.86 -- 1.98 At -40C 1.92 -- 2.04 1.92 -- 2.04 At +85C 1.2 -- 3.3 At -40C 1.2 -- 3.3 1.2 -- 3.3 At +85C -- -- 75 At -40C -- -- 75 -- -- 75 At +85C -75 -- -- At -40C -75 -- -- -75 -- -- At -40C V V V V V V A A At +25C At +25C At +25C At +25C At +25C At +25C At +25C At +25C At +85C Outputs terminated with 50 to VCCO-2V. Single-ended input operation is limited to VCC 3V in LVPECL mode. Common mode voltage is defined as VIH. For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC+0.3V. CLK-IN0, CLK-IN1; CLK-IN0B, CLK-IN1B. DS20005543B-page 2 2016 Microchip Technology Inc. PL138-48 DC ELECTRICAL CHARACTERISTICS Specifications: VCC = 2.5V; VEE = 0V. Input and output parameters vary 1:1 with VCC when VCC varies 5%. Parameters Symbol Output High Voltage, (Note 1) VOH Output Voltage Low, (Note 1) Input High Voltage Input Low Voltage Input High Voltage Common Mode Range, (Note 2, Note 3) Input High Current, (Note 4) Input Low Current, (Note 4) Note 1: 2: 3: 4: VOL VIH VIL VCMR IIH IIL Min. Typ. Max. 1.415 1.520 1.620 1.475 1.550 1.620 Units Conditions At -40C V At +25C 1.475 1.550 1.620 At +85C 0.670 0.810 0.945 At -40C 0.690 0.785 0.880 0.690 0.785 0.880 At +85C 1.275 -- 1.620 At -40C 1.335 -- 1.620 1.335 -- 1.620 At +85C 0.670 -- 1.090 At -40C 0.690 -- 1.025 0.690 -- 1.025 At +85C 1.2 -- 2.5 At -40C 1.2 -- 2.5 1.2 -- 2.5 At +85C -- -- 60 At -40C -- -- 60 -- -- 60 At +85C -60 -- -- At -40C -60 -- -- -60 -- -- V V V V A A At +25C At +25C At +25C At +25C At +25C At +25C At +85C Outputs terminated with 50 to VCCO-2V. Common mode voltage is defined as VIH. For single-ended applications, the maximum input voltage for CLK-INx, CLK-INxB is VCC+0.3V. CLK-IN0, CLK-IN1; CLK-IN0B, CLK-IN1B. 2016 Microchip Technology Inc. DS20005543B-page 3 PL138-48 AC ELECTRICAL CHARACTERISTICS VCC = -3.8V to -2.375 or VCC = 2.375V to 3.8V; VEE = 0V; TA = -40C to +85C. All parameters are measured at f 800 MHz unless otherwise noted. Parameters Output Frequency Propagation Delay, (Note 1) Symbol fMAX tPD Min. Typ. Max. Units MHz -- -- 800 600 680 750 650 725 790 690 790 890 Conditions At all temperatures At -40C ps At +25C At +85C Output Skew, (Note 2, Note 4) tSK(O) -- 25 37 ps At all temperatures Part-to-Part Skew, (Note 3, Note 4) tSK(PP) -- 85 225 ps At all temperatures tAPJ -- -- 0.10 ps At all temperatures; refer to Noise Characteristics section VPP 150 800 1200 mV At all temperatures 470 800 950 VSWING 600 800 930 600 800 930 200 -- 550 Buffer Additive Phase Jitter, RMS Peak-to-Peak Input Voltage (Differential Configuration) Peak-to-Peak Output Voltage Output Rise/Fall Time Note 1: 2: 3: 4: tR/tF At -40C mV At +25C ps At all temperatures; 20% to 80% at full output swing. At +85C Measured from the differential input crossing point to the differential output crossing point. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. This parameter is defined in accordance with JEDEC Standard 65. DS20005543B-page 4 2016 Microchip Technology Inc. PL138-48 TEMPERATURE SPECIFICATIONS (Note 1) Parameters Sym. Min. Typ. Max. Units Conditions TA -40 -- +85 C Note 2 Temperature Ranges Ambient Operating Temperature Junction Temperature TJ -- -- +110 C -- Storage Temperature Range TS -65 -- +150 C -- Soldering Temperature -- -- -- +260 C 10 sec. Note 1: 2: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature, and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +125C rating. Sustained junction temperatures above +125C can impact the device reliability. Operating temperature is guaranteed by design for all parts (commercial and industrial), but tested for commercial grade only. 2016 Microchip Technology Inc. DS20005543B-page 5 PL138-48 2.0 PIN DESCRIPTIONS FIGURE 2-1: Pin Configuration, 16-Pin QFN. FIGURE 2-2: Pin Configuration, 20-Pin TSSOP. The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Pin Number QFN-16 Pin Number TSSOP-20 Pin Name Type 4 1 VEE P Power supply pin connection. 16 2 CLK-EN I Synchronizing clock enable. When HIGH, clock outputs follow clock input. When LOW, Q outputs are forced low, QB outputs are forced high. LVTTL/LVCMOS interface levels. 50 k internal pull-up resistor. -- 3 CLK-SEL I Clock select input. When HIGH, selects CLK1 input. When LOW, selects CLK0 input. LVTTL/LVCMOS interface levels. 50 k internal pull-down resistor. 2 4 CLK-IN0 I True part of differential clock input signal. 75 k internal pull-down resistor. 3 5 CLK-IN0B I Complementary part of differential clock input signal. 100 k internal pull-up and pull-down resistors. DS20005543B-page 6 Description 2016 Microchip Technology Inc. PL138-48 TABLE 2-1: PIN FUNCTION TABLE (CONTINUED) Pin Number QFN-16 Pin Number TSSOP-20 Pin Name Type -- 6 CLK-IN1 I True part of differential clock input signal. 75 k internal pull-down resistor. -- 7 CLK-IN1B I Complementary part of differential clock input signal. 100 k internal pull-up and pull-down resistors. Description 1, 5 8, 9 DNC -- 8, 13 10, 13, 18 VCC P Power supply pin connection. 6, 9, 11 ,14 11, 14, 16, 19 QB0 ~ QB3 O LVPECL Complementary output. 7, 10, 12, 15 12, 15, 17, 20 Q0 ~ Q3 O LVPECL True output. 2016 Microchip Technology Inc. Do Not Connect. DS20005543B-page 7 PL138-48 3.0 NOISE CHARACTERISTICS When a buffer is used to pass a signal, the buffer adds a little bit of its own noise. The phase noise on the output of the buffer will be a little bit more than the phase noise of the input signal. To quantify the noise addition in the buffer we compare the Phase Jitter numbers from the input and the output. The difference is called "Additive Phase Jitter". The formula for the Additive Phase Jitter is as follows: EQUATION 3-1: AdditivePhaseJitter = TABLE 3-1: 2 OutputPhaseJitter - InputPhaseJitter 2 PL138-48 NOISE CHARACTERISTICS Parameters Additive Phase Jitter FIGURE 3-1: DS20005543B-page 8 Symbol tAPJ Min. Typ. Max. Units -- 20 40 VDD = 3.3V, Frequency = 622.08 MHz Offset = 12 kHz ~ 20 MHz -- 50 100 VDD = 3.3V, Frequency = 156.25 MHz Offset = 12 kHz ~ 20 MHz -- 50 100 -- 50 100 fs Conditions VDD = 3.3V, Frequency = 50 MHz Offset = 1 kHz ~ 1 MHz VDD = 3.3V, Frequency = 25 MHz Offset = 1 kHz ~ 1 MHz PL138-48 Additive Phase Jitter Plot, 622 MHz. 2016 Microchip Technology Inc. PL138-48 4.0 PARAMETER MEASUREMENT INFORMATION FIGURE 4-1: Circuit. Output Waveform Test FIGURE 4-2: Part-to-Part Skew. FIGURE 4-3: Output Rise/Fall Time. 2016 Microchip Technology Inc. FIGURE 4-4: Differential Input Level. FIGURE 4-5: Output Skew. FIGURE 4-6: Propagation Delay. DS20005543B-page 9 PL138-48 5.0 APPLICATION INFORMATION 5.1 Input Logic Configurations The following circuits show different configurations for different input logic type signals. For good signal integrity at the PL138 input, the signals need to be properly terminated according to the logic type requirements. The signals need to be presented at the PL138 input according to VCMR, VPP, and other input requirements. FIGURE 5-1: CLK-IN Input Driven by a 3.3V LVPECL Driver. FIGURE 5-2: 3.3V LVPECL Driver, Alternative Termination. FIGURE 5-3: CML Driver. FIGURE 5-5: LVDS Driver. CLK-IN Input Driven by an FIGURE 5-6: AC-Coupling. LVDS Driver, Alternative This circuit is for compatibility only. AC-coupling is not really required for LVDS. The VCMR range of the PL138 reaches low enough that LVDS signals can be connected directly to the PL138 input like in the circuit in Figure 5-5. CLK-IN Input Driven by a FIGURE 5-7: CMOS Driver. FIGURE 5-4: SSTL Driver. DS20005543B-page 10 CLK-IN Input Driven by a CLK-IN Input Driven by an 2016 Microchip Technology Inc. PL138-48 TABLE 5-2: INPUT CLOCK CONTROL SELECTION CLK_SEL Selected Source 0 CLK-IN0 1 CLK-IN1 TABLE 5-3: FIGURE 5-8: CLK-IN Input Driven by a Single-Ended LVPECL. FIGURE 5-9: HCSL Driver. CLK-IN Input Driven by an HCSL presents its signals very close to the ground rail, below the VCMR range, so the HCSL signals cannot be connected to the PL138 input directly. AC-coupling is required for HCSL signals on the PL138 input. INPUT CLOCK FUNCTION Inputs CLK-EN CLKSEL 5.2 TABLE 5-1: Input Logic Block Diagram. INPUT PIN CHARACTERISTICS Input Parameter Min. Typ. Max. Units CLK-IN0, CLK-IN1 Pull-Down Resistor -- 75 -- CLK-IN0B, CLK_IN1B Pull-Up & Pull-Down Resistors -- 100 -- CLK-EN Pull-Up Resistor -- 50 -- CLKSEL Pull-Down Resistor -- 50 -- Source Q0:Q3 Q0B:Q3B 0 0 CLK-IN0 Disabled Low Disabled High 0 1 CLK-IN1 Disabled Low Disabled High 1 0 CLK-IN0 Enabled Enabled 1 1 CLK-IN1 Enabled Enabled Termination for LVPECL Outputs The required termination for LVPECL is 50 to a VCC-2V DC voltage level. Below are two schematics to implement this termination. FIGURE 5-11: Schematic #1. FIGURE 5-10: Outputs LVPECL Termination * VCC = 3.3V - Ideal values: R1 = 127, R2 = 82.5 - Commercial values (E24): R1 = 130, R2 = 82 * VCC = 2.5V - Ideal values: R1 = 250, R2 = 62.5 - Commercial values (E24): R1 = 240, R2 = 62 k 2016 Microchip Technology Inc. DS20005543B-page 11 PL138-48 ambient". The thermal resistance depends upon the type of package, how the package is assembled to the PCB and if there is additional air flow for improved cooling. TABLE 5-4: FIGURE 5-12: Schematic #2. LVPECL Termination Schematic #2 is an alternative simplified termination. * VCC = 3.3V - Ideal value: RT = 48.7 - Commercial value: RT = 50 (E24: 51) * VCC = 2.5V - Ideal value: RT = 18.7 - Commercial value: RT = 18 5.3 Power Considerations Driving LVPECL outputs requires an amount of power that can warm up the chip significantly. The general requirement for the chip is that the junction temperature should not exceed +110C. The power consumption can be divided into two parts: 1. 2. Core power dissipation Output buffer power dissipation 5.3.1 20-PIN TSSOP THERMAL RESISTANCE Air Flow Velocity in Linear Feet/Minute JA Value for JEDEC Standard Multi-Layer PCB 0 73C/W 200 67C/W 500 64C/W The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to JA x Power. For an ambient temperature of +85C, all outputs loaded and no air flow, the junction temperature TJ = 85C + 73 x 0.291 = 106C. TABLE 5-5: 16-PIN QFN THERMAL RESISTANCE Air Flow Velocity in Linear Feet/Minute JA Value for JEDEC Standard Multi-Layer PCB 0 60C/W 200 53C/W 500 46C/W The temperature of the chip (junction) will be higher than the environment (ambient) with an amount equal to JA x Power. For an ambient temperature of +85C, all outputs loaded and no air flow, the junction temperature TJ = 85C + 60 x 0.291 = 102C. CORE POWER DISSIPATION The chip core power is equal to VCC x IEE. With a worst case VCC and IEE, the power dissipation in the core is 3.63V x 45 mA = 163 mW. 5.3.2 OUTPUT BUFFER POWER DISSIPATION The output buffers are not exposed to the full VCC - VEE voltage. On the differential output, one line is at logic 1 with a small voltage across the buffer and a large output current. The other line is at logic 0 with a larger voltage across the buffer and a smaller output current. The power dissipation per output buffer is 32 mW. Only buffers that are loaded will have power dissipation. With all 4 buffers loaded the worst case output buffer power dissipation will be 128 mW. Total chip power dissipation, worst case, is 163 mW + 128 mW = 291 mW. 5.3.3 JUNCTION TEMPERATURE How much the chip is warmed up from the power dissipation depends upon the thermal resistance from the chip to the environment, also known as "junction to DS20005543B-page 12 2016 Microchip Technology Inc. PL138-48 6.0 PACKAGE MARKING INFORMATION 16-Lead QFN 3.0 mm x 3.5 mm Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2016 Microchip Technology Inc. DS20005543B-page 13 PL138-48 20-Lead TSSOP Package Outline and Recommended Land Pattern Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005543B-page 14 2016 Microchip Technology Inc. PL138-48 APPENDIX A: REVISION HISTORY Revision A (May 2016) * Converted Micrel data sheet PL138-48 to Microchip DS20005543A. * Minor text changes throughout. Revision B (June 2016) * Updated output frequency tolerances to 800 MHz. 2016 Microchip Technology Inc. DS20005543B-page 15 PL138-48 NOTES: DS20005543B-page 16 2016 Microchip Technology Inc. PL138-48 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. Examples: PART NO. X Device Package X -X a) PL138-48OC-R: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer, 20-Pin TSSOP, Commercial Temperature Range, Tape & Reel b) PL138-48QI: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer, 16-Pin QFN, Industrial Temperature Range, Tube c) PL138-48OI-R: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer, 20-Pin TSSOP, Industrial Temperature Range, Tape & Reel d) PL138-48QC: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer, 16-Pin QFN, Commercial Temperature Range, Tube Temperature Packing Option Range Device: PL138-48: 2.5V - 3.3V, Low-Skew, 1:4 Differential PECL Fanout Buffer Package: O Q = = 20-Pin TSSOP 16-Pin QFN Temperature Range: C I = = 0C to +70C (Commercial) -40C to +85C (Industrial) Packing Option: Blank R = = Tube Tape & Reel 2016 Microchip Technology Inc. DS20005543B-page 17 PL138-48 NOTES: DS20005543B-page 18 2016 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2016 Microchip Technology Inc. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. (c) 2016, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-0540-5 DS20005543B-page 19 Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Germany - Dusseldorf Tel: 49-2129-3766400 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Hong Kong Tel: 852-2943-5100 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8569-7000 Fax: 86-10-8528-2104 Austin, TX Tel: 512-257-3370 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Canada - Toronto Tel: 905-673-0699 Fax: 905-673-6509 China - Dongguan Tel: 86-769-8702-9880 China - Guangzhou Tel: 86-20-8755-8029 China - Hangzhou Tel: 86-571-8792-8115 Fax: 86-571-8792-8116 China - Hong Kong SAR Tel: 852-2943-5100 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8864-2200 Fax: 86-755-8203-1760 India - Pune Tel: 91-20-3019-1500 Japan - Osaka Tel: 81-6-6152-7160 Fax: 81-6-6152-9310 Japan - Tokyo Tel: 81-3-6880- 3770 Fax: 81-3-6880-3771 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Italy - Venice Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Poland - Warsaw Tel: 48-22-3325737 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-5778-366 Fax: 886-3-5770-955 Taiwan - Kaohsiung Tel: 886-7-213-7828 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Taipei Tel: 886-2-2508-8600 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 06/17/16 DS20005543B-page 20 2016 Microchip Technology Inc.