Qualcomm Technologies International, Ltd. Confidential and Proprietary - Qualcomm Technologies International, Ltd. (formerly known as Cambridge Silicon Radio Ltd.) NO PUBLIC DISCLOSURE PERMITTED: Please report postings of this document on public servers or websites to: DocCtrlAgent@qualcomm.com. Restricted Distribution: Not to be distributed to anyone who is not an employee of either Qualcomm Technologies International, Ltd.or its affiliated companies without the express approval of Qualcomm Configuration Management. Not to be used, copied, reproduced, or modified in whole or in part, nor its contents revealed in any manner to others without the express written permission of Qualcomm Technologies International, Ltd. Any software provided with this notice is governed by the Qualcomm Technologies International, Ltd. Terms of Supply or the applicable license agreement at https://www.csrsupport.com/CSRTermsandConditions. Qualcomm is a trademark of Qualcomm Incorporated, registered in the United States and other countries. All Qualcomm Incorporated trademarks are used with permission. Other product and brand names may be trademarks or registered trademarks of their respective owners. This technical data may be subject to U.S. and international export, re-export, or transfer ("export") laws. Diversion contrary to U.S. and international law is strictly prohibited. (c) 2015 Qualcomm Technologies International, Ltd. All rights reserved. Qualcomm Technologies International, Ltd. Churchill House Cambridge Business Park Cambridge, CB4 0WZ United Kingdom CSR Energy(R) CSR1012 QFN Features Bluetooth Smart IC Production Information CSR1012A05 Issue 5 General Description Applications CSR1012 QFN is a CSR Energy platform device. CSR Energy are CSR's single-mode Bluetooth low energy products for the Bluetooth Smart market. CSR1012 QFN is a small footprint variant of CSR1010 QFN. CSR Energy enables ultra low-power connectivity and basic data transfer for applications previously limited by the power consumption, size constraints and complexity of other wireless standards. CSR1012 QFN provides everything required to create a Bluetooth low energy product with RF, baseband, MCU, qualified Bluetooth v4.1 specification stack and customer application running on a single IC. Building an ecosystem using Bluetooth low energy CSR is the industry leader for Bluetooth low energy, also known as Bluetooth Smart. Bluetooth Smart enables connectivity and data transfer to leading smartphone, tablet and personal computing devices including Apple iPhone, iPad, iPod and Mac products and leading Android devices. Bluetooth low energy takes less time to make a connection than conventional Bluetooth wireless technology and can consume approximately 1/20th of the power of Bluetooth Basic Rate. CSR1012 QFN supports profiles for health and fitness sensors, watches, keyboards, mice and remote controls. Typical Bluetooth Smart applications: HID: keyboards, mice, touchpads, remote controls Sports and fitness sensors: heart rate, runner speed and cadence, cycle speed and cadence Health sensors: blood pressure, thermometer and glucose meters Mobile accessories: watches, proximity tags, alert tags and camera controls Smart home: heating control and lighting control Bluetooth LE Radio and Modem MCU I/O UART LED PWM PIO 16MHz 32kHz ROM AIO RAM Debug Clock Generation I 2C / SPI Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 1 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Bluetooth(R) v4.1 specification compliant Bluetooth Smart 128KB memory: 64KB RAM and 64KB ROM Support for Bluetooth v4.1 specification host stack including ATT, GATT, SMP, L2CAP, GAP RSSI monitoring for proximity applications <900nA current consumption in dormant mode 32kHz and 16MHz crystal or system clock Switch-mode power supply Programmable general purpose PIO controller 10-bit ADC 12 digital PIOs 3 analogue AIOs UART IC / SPI for EEPROM / flash memory ICs and peripherals Debug SPI 4 PWM modules Wake-up interrupt and watchdog timer QFN 32-lead, 4 x 4 x 0.65mm, 0.4mm pitch Ordering Information Package Device CSR1012 QFN Type Size Shipment Method QFN32-lead (Pb free) 4 x 4 x 0.65mm 0.4mm pitch Tape and reel Order Number CSR1012A05-IQQP-R Note: The minimum order quantity is 4kpcs taped and reeled. Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative. Contacts Production Information (c) Cambridge Silicon Radio Limited 2013-2015 www.csr.com sales@csr.com www.csrsupport.com product.compliance@csr.com comments@csr.com CSR1012 QFN Data Sheet General information Information on this product Customer support for this product Details of compliance and standards Help with this document Page 2 of 48 CS-238833-DSP5 www.csr.com Device Details Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Synthesiser Fully integrated synthesiser requires no external VCO varactor diode, resonator or loop filter Baseband and Software Hardware MAC for all packet types enables packet handling without the need to involve the MCU Physical Interfaces SPI master interface SPI programming and debug interface IC 12 digital PIOs 3 analogue AIOs UART Auxiliary Features Battery monitor Power management features include software shutdown and hardware wake-up CSR1012 QFN can run in low power modes from an external 32.768kHz clock signal Integrated switch-mode power supply Linear regulator (internal use only) Power-on-reset cell detects low supply voltage Package 32-lead 4 x 4 x 0.65mm, 0.4mm pitch QFN Page 3 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Bluetooth Radio On-chip balun (50 impedance in TX and RX modes) No external trimming is required in production Bluetooth v4.1 specification compliant Bluetooth Transmitter 9dBm RF transmit power with level control from integrated 6-bit DAC over a dynamic range >25dB No external power amplifier or TX/RX switch required Bluetooth Receiver -94dBm sensitivity Integrated channel filters Digital demodulator for improved sensitivity and cochannel rejection Fast AGC for enhanced dynamic range Bluetooth Stack CSR's protocol stack runs on the integrated MCU: Support for Bluetooth v4.1 specification features: Master and slave operation Including encryption Software stack in firmware includes: GAP L2CAP Security manager Attribute protocol Attribute profile Bluetooth low energy profile support Functional Block Diagram RF XTAL_16M XTAL_32K Bluetooth Radio Clock Generation I/O Bluetooth LE Modem and LC Wake-up UART I2C / SPI Serial Flash DMA CSR1012 QFN Data Sheet RAM 64KB I2C / SPI Serial Flash I2C EEPROM SPI Serial Flash PIO and LED PWM RAM Arbiter AES-CCS and AES Encryption PIO AUX / CLK / PSU Control Memory Protection VDD_PADS Control State Machine Code Data MCU Interrupt ROM Debug Debug Production Information (c) Cambridge Silicon Radio Limited 2013-2015 LDO SMPU VDDREG_IN VDD_BAT G-TW-0005362.9.2 Timer Page 4 of 48 CS-238833-DSP5 www.csr.com Document History Date Change Reason 1 18 APR 13 Original publication of this document. 2 21 DEC 13 Updates include: Pre-production Information added. Status Information. 4.4V operation added. Absolute maximum ratings value for battery operation. Package Information. UART hardware flow control removed. PIO definitions clarified. Sleep clock maximum load capacitance. Non-confidential information. VDD_DIG corrected to VDD_CORE. Hibernate current. Correction to Performance Specification document number in Document References. Bluetooth 4.1 specification added. Example Application Schematic. Dev kit details removed. 3 03 FEB 14 Updates include: Production Information added. RF parameters. Minimum order quantity. 4.3V Performance Specification document reference added. Copyright years. Minimum operating temperature in Recommended Operating Conditions. Machine Model removed from ESD as it is not required by CSR or the latest JEDEC standards . 4 03 FEB 14 Confidentiality Status added to Status Information. 5 06 JAN 15 Updates include: Section 3 Clock Generation Section 4 Operating Modes. Section 5 Microcontroller, Memory and Baseband Logic. Section 6 Serial Interfaces. Section 7 Power Control and Regulation. Section 8 Example Application Schematic. Section 9 Electrical Characteristics. Section 10 Current Consumption. Section 14 Document References. Other minor updates. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 5 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Revision Status Information Device Implementation Important Note: As the feature-set of the CSR1012 QFN is firmware build-specific, see the relevant software release note for the exact implementation of features on the CSR1012 QFN. Life Support Policy and Use in Safety-critical Applications CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications. CSR Green Semiconductor Products and RoHS Compliance CSR1012 QFN devices meet the requirements of Directive 2011/65/EU of the European Parliament and of the Council on the Restriction of Hazardous Substance (RoHS). CSR1012 QFN devices are free from halogenated or antimony trioxide-based flame retardants and other hazardous chemicals. For more information, see CSR's Environmental Compliance Statement for CSR Green Semiconductor Products. Confidentiality Status This document is non-confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by CSR plc and the party that CSR plc delivered this document to. Trademarks, Patents and Licences Unless otherwise stated, words and logos marked with TM or (R) are trademarks registered or owned by CSR plc or its affiliates. Bluetooth (R) and the Bluetooth (R) logos are trademarks owned by Bluetooth (R) SIG, Inc. and licensed to CSR. Other products, services and names used in this document may have been trademarked by their respective owners. The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc and/or its affiliates. CSR reserves the right to make technical changes to its products as part of its development programme. While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any errors. Refer to www.csrsupport.com for compliance and conformance to standards information. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 6 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format: Advance Information: Information for designers concerning CSR product in development. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. Engineering Sample: Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice. Pre-production Information: Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values. All electrical specifications may be changed by CSR without notice. Production Information: Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications. Production Data Sheets supersede all previous document versions. Contents 1 2 4 5 6 Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 7 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet 3 Ordering Information ........................................................................................................................................... 2 Contacts ..................................................................................................................................................... 2 Device Details ..................................................................................................................................................... 3 Functional Block Diagram .................................................................................................................................. 4 Package Information ......................................................................................................................................... 10 1.1 Pinout Diagram ........................................................................................................................................ 10 1.2 Device Terminal Functions ....................................................................................................................... 11 1.3 Package Dimensions ............................................................................................................................... 14 1.4 PCB Design and Assembly Considerations ............................................................................................. 15 1.5 Typical Solder Reflow Profile ................................................................................................................... 15 Bluetooth Modem .............................................................................................................................................. 16 2.1 RF Ports ................................................................................................................................................... 16 2.2 RF Receiver ............................................................................................................................................. 16 2.2.1 Low Noise Amplifier .................................................................................................................... 16 2.2.2 RSSI Analogue to Digital Converter ........................................................................................... 16 2.3 RF Transmitter ......................................................................................................................................... 16 2.3.1 IQ Modulator ............................................................................................................................... 16 2.3.2 Power Amplifier .......................................................................................................................... 16 2.4 Bluetooth Radio Synthesiser .................................................................................................................... 16 2.5 Baseband ................................................................................................................................................. 16 2.5.1 Physical Layer Hardware Engine ............................................................................................... 16 Clock Generation ............................................................................................................................................... 17 3.1 Clock Architecture .................................................................................................................................... 17 3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT .......................................................................... 17 3.2.1 Crystal Specification ................................................................................................................... 17 3.2.2 Frequency Trim .......................................................................................................................... 18 3.3 Sleep Clock .............................................................................................................................................. 18 3.3.1 Crystal Specification ................................................................................................................... 18 Operating Modes ............................................................................................................................................... 20 4.1 Run Mode ................................................................................................................................................. 20 4.2 Idle Mode ................................................................................................................................................. 20 4.3 Deep Sleep Mode .................................................................................................................................... 20 4.4 Hibernate Mode ........................................................................................................................................ 20 4.5 Dormant Mode ......................................................................................................................................... 20 Microcontroller, Memory and Baseband Logic .................................................................................................. 21 5.1 System RAM ............................................................................................................................................ 21 5.2 Internal ROM ........................................................................................................................................... 21 5.3 Microcontroller .......................................................................................................................................... 21 5.4 Programmable I/O Ports, PIO and AIO .................................................................................................... 21 5.5 LED Flasher / PWM Module ..................................................................................................................... 22 5.6 Temperature Sensor ................................................................................................................................ 23 5.7 Battery Monitor ......................................................................................................................................... 24 Serial Interfaces ................................................................................................................................................ 25 6.1 Application Interface ................................................................................................................................. 25 6.1.1 UART Interface ........................................................................................................................... 25 6.2 IC Interface ............................................................................................................................................. 25 6.3 SPI Master Interface ................................................................................................................................ 27 6.4 Programming and Debug Interface .......................................................................................................... 29 6.4.1 Instruction Cycle ......................................................................................................................... 29 6.4.2 Multi-slave Operation .................................................................................................................. 30 Power Control and Regulation .......................................................................................................................... 31 7.1 Switch-mode Regulator ............................................................................................................................ 31 7.2 Low-voltage VDD_CORE Linear Regulator ............................................................................................. 31 7.3 Reset ........................................................................................................................................................ 31 7.3.1 Digital Pin States on Reset ......................................................................................................... 31 7.3.2 Power-on Reset .......................................................................................................................... 32 8 Example Application Schematic ........................................................................................................................ 33 9 Electrical Characteristics ................................................................................................................................... 34 9.1 Absolute Maximum Ratings ..................................................................................................................... 34 9.2 Recommended Operating Conditions ...................................................................................................... 34 9.3 Input/Output Terminal Characteristics ...................................................................................................... 35 9.3.1 Switch-mode Regulator .............................................................................................................. 35 9.3.2 Low-voltage Linear Regulator ..................................................................................................... 35 9.3.3 Digital Terminals ......................................................................................................................... 35 9.3.4 AIO ............................................................................................................................................. 36 9.4 Junction Temperature .............................................................................................................................. 38 9.5 ESD Protection ......................................................................................................................................... 38 10 Current Consumption ........................................................................................................................................ 39 11 CSR Green Semiconductor Products and RoHS Compliance .......................................................................... 40 12 CSR1012 QFN Software Stack ......................................................................................................................... 41 13 Tape and Reel Information ................................................................................................................................ 42 13.1 Tape Orientation ...................................................................................................................................... 42 13.2 Tape Dimensions ..................................................................................................................................... 43 13.3 Reel Information ....................................................................................................................................... 44 13.4 Moisture Sensitivity Level ......................................................................................................................... 44 14 Document References ....................................................................................................................................... 45 Terms and Definitions ................................................................................................................................................ 46 7 Figure 1.1 Figure 3.1 Figure 3.2 Figure 3.3 Figure 5.1 Figure 5.2 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 7.1 Figure 12.1 Figure 13.1 Figure 13.2 Figure 13.3 Pinout Diagram .................................................................................................................................... 10 Clock Architecture ................................................................................................................................ 17 Crystal Driver Circuit ............................................................................................................................ 17 Sleep Clock Crystal Driver Circuit ........................................................................................................ 18 Baseband Digits Block Diagram .......................................................................................................... 21 Typical PWM Signal on a PIO ............................................................................................................. 23 Example of an IC Interface EEPROM Connection ............................................................................. 26 IC Standard Mode 100 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) ............................. 26 IC Fast Mode 400 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) .................................... 27 SPI Timing Diagram ............................................................................................................................. 28 Memory Boot-up Sequence ................................................................................................................. 29 Voltage Regulator Configuration .......................................................................................................... 31 Software Architecture .......................................................................................................................... 41 Tape Orientation .................................................................................................................................. 42 Tape Dimensions ................................................................................................................................. 43 Reel Dimensions .................................................................................................................................. 44 Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 8 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet List of Figures List of Tables Table 3.1 Table 3.2 Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2 Table 6.3 Table 6.4 Table 6.5 Table 7.1 Table 7.2 Table 9.1 Table 9.2 Table 10.1 Crystal Specification ............................................................................................................................. 18 Sleep Clock Specification ..................................................................................................................... 19 Wake Options for Sleep Modes ............................................................................................................ 22 Alternative PIO Functions ..................................................................................................................... 22 PWM Operating Range ......................................................................................................................... 23 Possible UART Settings ....................................................................................................................... 25 IC Standard Mode 100 kHz Timing Definition ..................................................................................... 26 IC Fast Mode 400 kHz Timing Definition ............................................................................................. 27 SPI Master Serial Flash Memory Interface ........................................................................................... 28 Instruction Cycle for a SPI Transaction ................................................................................................ 30 Pin States on Reset .............................................................................................................................. 32 Power-on Reset .................................................................................................................................... 32 Junction Temperature within Recommended Operating Conditions .................................................... 38 ESD Handling Ratings .......................................................................................................................... 38 Current Consumption ............................................................................................................................ 39 CSR1012 QFN Data Sheet Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 9 of 48 CS-238833-DSP5 www.csr.com 1 1.1 Package Information Pinout Diagram Orientation from Top of Device 32 31 30 29 28 27 26 25 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 10 11 12 13 14 15 16 G-TW-0005350.6.1 24 CSR1012 QFN Data Sheet 1 Figure 1.1: Pinout Diagram Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 10 of 48 CS-238833-DSP5 www.csr.com 1.2 Device Terminal Functions Radio RF Lead 7 (a) Pad Type Supply Domain Description RF VDD_RADIO(a) Bluetooth transmitter / receiver. The VDD_RADIO domain is generated from VDD_REG_IN, see Figure 7.1. Synthesiser and Oscillator Lead Pad Type Supply Domain Description XTAL_32K_OUT 2 Analogue VDD_BAT Drive for sleep clock crystal. XTAL_32K_IN 3 Analogue VDD_BAT 32.768kHz sleep clock input. XTAL_16M_OUT 9 Analogue VDD_ANA(b) Drive for crystal. XTAL_16M_IN 10 Analogue VDD_ANA Reference clock input. The VDD_ANA domain is generated from VDD_REG_IN, see Figure 7.1. IC Interface Lead Pad Type Supply Domain Description VDD_PADS IC data input / output or SPI serial flash data output (SF_DOUT). If connecting to SPI serial flash, connect this pin to SO on the serial flash. See Section 6.3. I2C_SDA 29 Bidirectional, tristate, with weak internal pull-up I2C_SCL 28 Input with weak internal pull-up VDD_PADS IC clock or SPI serial flash clock output (SF_CLK), see Section 6.3. PIO Port Lead Pad Type Supply Domain Description PIO[11] 25 PIO[10] 24 VDD_PADS Programmable I/O line. PIO[9] 23 Bidirectional with programmable strength internal pullup/down PIO[8] / DEBUG_MISO 22 PIO[7] / DEBUG_MOSI 20 PIO[6] / DEBUG_CS# 19 PIO[5] / DEBUG_CLK 18 Programmable I/O line or debug SPI MISO selected by SPI_PIO#. Bidirectional with programmable strength internal pullup/down Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Programmable I/O line or debug SPI MOSI selected by SPI_PIO#. VDD_PADS Programmable I/O line or debug SPI chip select (CS#) selected by SPI_PIO#. Programmable I/O line or debug SPI CLK selected by SPI_PIO#. Page 11 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet (b) PIO Port Lead PIO[4] / SF_CS# 17 PIO[3] / SF_DIN 16 27 PIO[1] / UART_RX 15 PIO[0] / UART_TX 14 AIO[2] 11 AIO[1] 12 AIO[0] 13 (c) Supply Domain Description Programmable I/O line or SPI serial flash chip select (SF_CS#), see Section 6.3. Bidirectional with programmable strength internal pullup/down VDD_PADS Programmable I/O line or SPI serial flash data (SF_DIN) input. If connecting to SPI serial flash, this pin connects to SI on the serial flash. See Section 6.3. Bidirectional with programmable strength internal pullup/down VDD_PADS Programmable I/O line or IC power. Programmable I/O line or UART RX. Bidirectional with programmable strength internal pullup/down VDD_PADS Bidirectional analogue VDD_AUX(c) Programmable I/O line or UART TX. Analogue programmable I/O line. The VDD_AUX domain is generated from VDD_REG_IN, see Figure 7.1. Test and Debug Lead SPI_PIO# 26 Wake-up Lead WAKE 4 Pad Type Supply Domain Description Input with strong internal pull-down VDD_PADS Selects SPI debug on PIO[8:5]. Pad Type Supply Domain Description Input has no internal pull-up or pull-down, use external pulldown. VDD_BAT Input to wake CSR1012 QFN from hibernate or dormant. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 12 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet PIO[2] Pad Type Power Supplies and Control Lead Description VDD_BAT 1 Battery input and regulator enable (active high). VDD_BAT_SMPS 32 Input to high-voltage switch-mode regulator. SMPS_LX 31 High-voltage switch-mode regulator output. VDD_CORE 5, 30 VDD_PADS 21 Positive supply for all digital I/O ports PIO[11:0]. VDD_REG_IN 6 Positive supply for Bluetooth radio and digital linear regulator. VDD_XTAL 8 Decouple with 470nF capacitor to ground. VSS Exposed pad Positive supply for digital domain. Ground connections. CSR1012 QFN Data Sheet Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 13 of 48 CS-238833-DSP5 www.csr.com 1.3 Package Dimensions Top View ccc C D A bbb C B C Seating Plane M 32 Dimension Min Typ Max Dimension Min Typ Max A 0.55 0.6 0.65 J 2.24 2.34 2.44 A1 0 0.035 0.05 K 2.24 2.34 2.44 A2 - 0.4 - L 0.25 0.30 0.35 A3 - 0.203 - aaa - 0.1 - b 0.15 0.20 0.25 bbb - 0.1 - D - 4.0 - ccc - 0.08 - E - 4.0 - ddd - 0.1 - e - 0.4 - eee - 0.1 - d1/e1 - 0.118 - P 0.43 - - 1 E M aaa C A2 A A1 (A3) Bottom View J e1 eee C A B 25 32 Pin 1 ID P Notes 1. Description 32-lead Quad-flat No-lead Package Size 4 x 4 x 0.65mm JEDEC MO-220 Pitch 0.4 Units mm Coplanarity applies to leads, corner leads and die attach pad. 1 24 e/2 e 8 17 d1 16 32 x L Production Information (c) Cambridge Silicon Radio Limited 2013-2015 9 32 x b ddd M C A B Exposed Die Attach Pad G-TW-0012803.3.3 eee C A B Page 14 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Pin 1 Corner 1.4 PCB Design and Assembly Considerations This section lists recommendations to achieve maximum board-level reliability of the 4 x 4 x 0.65mm QFN 32-lead package: 1.5 NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation. CSR recommends that the PCB land pattern is in accordance with IPC standard IPC-7351. Solder paste must be used during the assembly process. Typical Solder Reflow Profile For information, see Typical Solder Reflow Profile for Lead-free Devices Information Note. CSR1012 QFN Data Sheet Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 15 of 48 CS-238833-DSP5 www.csr.com 2 2.1 Bluetooth Modem RF Ports CSR1012 QFN contains an integrated balun which provides a single-ended RF TX / RX port pin. No matching components are needed as the receive mode impedance is 50 and the transmitter has been optimised to deliver power in to a 50 load. 2.2 RF Receiver The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and WCDMA cellular phone transmitters without being significantly desensitised. An ADC digitises the IF received signal. 2.2.1 Low Noise Amplifier The LNA operates in differential mode and takes its input from the balanced port of the integrated balun. 2.2.2 RSSI Analogue to Digital Converter 2.3 RF Transmitter 2.3.1 IQ Modulator The transmitter features a direct IQ modulator to minimise frequency drift during a transmit packet, which results in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping. 2.3.2 Power Amplifier The internal PA has a maximum 9dBm output power without needing an external RF PA. 2.4 Bluetooth Radio Synthesiser The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the guaranteed temperature range to meet the Bluetooth v4.1 specification. 2.5 Baseband 2.5.1 Physical Layer Hardware Engine Dedicated logic performs: Cyclic redundancy check Encryption Data whitening Access code correlation The hardware supports all optional and mandatory features of Bluetooth v4.1 specification. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 16 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet The ADC samples the RSSI voltage on a packet-by-packet basis and implements a fast AGC. The front-end LNA gain is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the dynamic range of the receiver, improving performance in interference-limited environments. 3 Clock Generation The Bluetooth reference clock for the system is generated from an external 16MHz clock source, see Figure 3.1. All the CSR1012 QFN internal digital clocks are generated using a phase locked loop, which is locked to the frequency of either the external reference clock source or a sleep clock frequency of 32.768kHz, see Figure 3.1. Clock Architecture Bluetooth PLL Fast XTAL Clock for System Core Digits (16MHz) 32kHz Embedded Digits (32kHz) Figure 3.1: Clock Architecture 3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT CSR1012 QFN contains crystal driver circuits. This operates with an external crystal and capacitors to form a Pierce oscillator. Figure 3.2 shows the external crystal is connected to pins XTAL_16M_IN and XTAL_16M_OUT. - CLOAD1 CLOAD2 G-TW-0005348.1.1 XTAL_16M_IN XTAL_16M_OUT CTRIM Figure 3.2: Crystal Driver Circuit Note: CTRIM is the internal trimmable capacitance in Table 3.1. CLOAD1 and CLOAD2 in combination with CTRIM and any parasitic capacitance provide the load capacitance required by the crystal. 3.2.1 Crystal Specification Table 3.1 shows the specification for an external crystal. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 17 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Slow XTAL Clock for Sleep 16MHz Bluetooth LO (~4.8GHz) G-TW-0005266.2.2 3.1 Parameter Min Typ Max Unit Frequency - 16 - MHz Frequency tolerance (without trimming)(a) - - 25 ppm Frequency trim range(b) - 50 - ppm Drive level - 0.4 - V Equivalent series resistance - - 60 Load capacitance - 9 - pF 10 - - ppm/pF Pullability Table 3.1: Crystal Specification Use integrated load capacitors to trim initial frequency tolerance in production or to trim frequency over temperature, increasing the allowable frequency tolerance. (b) Frequency trim range is dependent on crystal load capacitor values and crystal pullability. 3.2.2 Frequency Trim CSR1012 QFN contains variable integrated capacitors to allow for fine-tuning of the crystal resonant frequency. This firmware-programmable feature allows accurate trimming of crystals on a per-device basis on the production line. The resulting trim value is stored in non-volatile memory. 3.3 Sleep Clock The sleep clock is an externally provided 32.768kHz clock that is used during deep sleep and in other low-power modes. Figure 3.3 shows the sleep clock crystal driver circuit. CLOAD1 CLOAD2 G-TW-0005349.2.2 XTAL_32K_IN XTAL_32K_OUT - Figure 3.3: Sleep Clock Crystal Driver Circuit Note: CLOAD1 and CLOAD2 in combination with any parasitic capacitance provide the load capacitance required by the crystal. 3.3.1 Crystal Specification Table 3.2 shows the requirements for the sleep clock. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 18 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet (a) Sleep Clock Min Typ Max Units Frequency 30 32.768 35 kHz Frequency tolerance(a) (b) - - 250 ppm Frequency trim range - 50 - ppm Drive level - 0.4 - V Load capacitance - - 10 pF 40 - 65 k 30:70 50:50 70:30 % Equivalent series resistance Duty cycle Table 3.2: Sleep Clock Specification The frequency of the slow clock is periodically calibrated against the system clock. As a result the rate of change of the frequency is more important than the maximum deviation. To meet the accuracy requirements the frequency should not drift due to temperature or other effects by more than 80ppm in any 5 minute period. (b) CSR1012 QFN can correct for 1% by using the fast clock to calibrate the slow clock. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 CSR1012 QFN Data Sheet (a) Page 19 of 48 CS-238833-DSP5 www.csr.com 4 Operating Modes CSR1012 QFN has 5 operating modes. 3 of these are sleep modes: Running Idle Sleep modes: Deep Sleep Hibernate Dormant For current consumption rates in the operating modes, see Section 10. 4.1 Run Mode In Run mode, all functions are on. RX and/or TX are active. 4.2 Idle Mode In Idle mode, the VDD_PADS and VDD_BAT domains are powered, the reference clock and the sleep clock are powered, the RAM is powered and the digital circuits are powered. The MCU is idle. 4.3 Deep Sleep Mode In Deep Sleep mode, the VDD_PADS and VDD_BAT domains are powered, the sleep clock is on but the reference clock is off, the RAM is on, the digital circuits are on and the SMPS is on (low-power mode). There is a configurable wake-up time. CSR1012 QFN is woken from Deep Sleep mode by any PIO configured to wake the IC. 4.4 Hibernate Mode In Hibernate mode, the VDD_PADS and VDD_BAT domains are powered and the sleep clock is on. The reference clock is off. CSR1012 QFN is woken from Hibernate mode by a selected level on the WAKE pin or by the watchdog timer. 4.5 Dormant Mode In Dormant mode, all functions are off. CSR1012 QFN is woken from Dormant mode by a selected level on the WAKE pin. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 20 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet There is a <1s wake-up time. 5 Microcontroller, Memory and Baseband Logic ADCs Bluetooth and Auxiliary Analogue Control DACs Bluetooth low energy Modem and LC Wake-ups RAM Interface (Buffers, LUTs, Tables and State) AES-CCS and AES Encryption RAM Arbiter I/O RAM UART I2C / Serial Flash Serial Flash I2C / Serial Flash Memory Protection DMA PIO and LED PWM AUX / CLK / PSU Control Interrupt MCU Debug Debug PIOs Data I/O Control Logic Timer Figure 5.1: Baseband Digits Block Diagram 5.1 System RAM 64KB of integrated RAM supports the RISC MCU and is shared between the ring buffers used to hold data for each active connection, general-purpose memory required by the Bluetooth stack and the user application. 5.2 Internal ROM CSR1012 QFN has 64KB of internal ROM. This memory is provided for system firmware implementation. If the internal ROM holds valid program code, on boot-up, this is copied into the program RAM. Code then executes from ROM and RAM. 5.3 Microcontroller The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and external interfaces. A 16-bit RISC microcontroller is used for low power consumption and efficient use of memory. 5.4 Programmable I/O Ports, PIO and AIO 12 lines of programmable bidirectional I/O are provided. They are all powered from VDD_PADS. PIO lines are software-configurable as weak pull-up, weak pull-down, strong pull-up or strong pull-down. Note: At reset all PIO lines are inputs with weak pull-downs. Any of the PIO lines can be configured as interrupt request lines or to wake the IC from deep sleep mode. Table 5.1 lists the options for waking the IC from the sleep modes. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 21 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Code G-TW-0005354.3.2 I2C EEPROM Sleep Mode Wake-up Options Dormant Can only be woken by the WAKE pin. Hibernate Can be woken by the WAKE pin or by the watchdog timer. Deep Sleep Can be woken by any PIO configured to wake the IC. Table 5.1: Wake Options for Sleep Modes The CSR1012 QFN supports alternative functions on the PIO lines, for example: SPI interface, see Section 1.2 and Section 6.4 UART, see Section 1.2 and Section 6.1.1 LED flasher / PWM module, see Section 5.5 Table 5.2 shows the alternative functions on the PIO lines. Function PIO SPI Flash UART PIO[8] DEBUG_MISO - - PIO[7] DEBUG_MOSI - - PIO[6] DEBUG_CS# - - PIO[5] DEBUG_CLK - - PIO[4] - SF_CS# - PIO[3] - SF_DIN - PIO[2] - - - PIO[1] - - UART_RX PIO[0] - - UART_TX CSR1012 QFN Data Sheet Debug SPI Table 5.2: Alternative PIO Functions Note: CSR cannot guarantee that the PIO assignments remain as described. Implementation of the PIO lines is firmware build-specific, for more information see the relevant software release note. CSR1012 QFN has 3 general-purpose analogue interface pins, AIO[2:0]. 5.5 LED Flasher / PWM Module CSR1012 QFN contains an LED flasher / PWM module. Note: The LED flasher functions in Deep Sleep and Active modes only. The PWM functions in all modes except Hibernate and Dormant. These functions are controlled by the on-chip firmware. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 22 of 48 CS-238833-DSP5 www.csr.com Figure 5.2 shows a typical PWM signal on a PIO. For more information, see CSR Energy Pulse Width Modulation Application Note. PWM output governed by the timings setup for the brightest part of the pulse sequence T off Ton (bright ) (bright ) T off T on (bright ) (bright ) A mp litud e T hold (bright ) - Duration for which the PWM output is held in the brightest part of the pulse sequence Hold Time (Bright ) PWM output while ramping from brightest to dullest Highest Varying Duty Duty Cycle Cycle (Bright to Dull) Ramp T ramp - Duration of the ramping and the number of pulses and their widths during ramping is proportional to the ramping rate Lowest Varying Duty Duty Cycle Cycle ( Dull to Bright ) Time PWM output governed by the timings setup for the dullest part of the pulse sequence Toff (dull ) (d ull ) T on PWM output while ramping from dullest to brightest T off (dull ) (dull ) T hold (dull ) - Duration for which the PWM output is held in the dullest part of the pulse sequence Tramp - Duration of the ramping, the number of pulses and their widths during ramping is proportional to the ramping rate G-TW-0013938.1.3 To n Figure 5.2: Typical PWM Signal on a PIO Figure 5.2 lists PWM the operating range. Parameter Min Max Unit Off Time (Toff) 30.5 7782 s On Time (Ton) 30.5 7782 s Hold Time (Thold) 16 4080 ms Duty Cycle = On Time (Ton) + Off Time (Toff) 61 15564 s Frequency = 1 / Duty Cycle 64.3 16320 Hz Table 5.3: PWM Operating Range 5.6 Temperature Sensor CSR1012 QFN contains a temperature sensor that measures the temperature of the die to an accuracy of 1 C. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 23 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Hold Time (Dull) 5.7 Battery Monitor CSR1012 QFN contains an internal battery monitor that reports the battery voltage to the software. CSR1012 QFN Data Sheet Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 24 of 48 CS-238833-DSP5 www.csr.com 6 Serial Interfaces 6.1 Application Interface 6.1.1 UART Interface The CSR1012 QFN UART interface provides a simple mechanism for communicating with other serial devices using the RS232 protocol. 2 signals implement the UART function, UART_TX and UART_RX. When CSR1012 QFN is connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. UART configuration parameters, e.g. baud rate and data format, are set using CSR1012 QFN firmware. When selected in firmware PIO[0] is assigned to a UART_TX output and PIO[1] is assigned to a UART_RX input, see Section 1.2. Note: To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated serial port adapter card. Parameter Baud rate Possible Values Minimum Maximum Parity 2400 baud (2%Error) 9600 baud (2%Error) 3.69Mbaud (0.1%Error) None, Odd or Even Number of stop bits 1 or 2 Bits per byte 8 Table 6.1: Possible UART Settings 6.1.1.1 UART Configuration While in Deep Sleep The maximum baud rate is 2400 baud during deep sleep. 6.2 IC Interface The IC interface communicates to EEPROM, external peripherals or sensors. An external EEPROM connection can hold the program code externally to the CSR1012 QFN. Figure 6.1 shows an example of an EEPROM connected to the IC interface where I2C_SCL, I2C_SDA and PIO[2] are connected to the external EEPROM. The PIO[2] pin supplies the power to the EEPROM supply pin, e.g. VDD. At bootup, if there is no valid ROM image in the CSR1012 QFN ROM area the CSR1012 QFN tries to boot from the IC interface, see Figure 6.5. This involves reading the code from the external EEPROM and loading it into the internal CSR1012 QFN RAM. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 25 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Table 6.1 shows the possible UART settings for the CSR1012 QFN. PIO[2] I2C_SCL I2C_SDA 1 2 3 4 G-TW-0005553.1.1 24AA512 8 A0 VDD 7 A1 WP 6 A2 SCL 5 VSS SDA Figure 6.1: Example of an IC Interface EEPROM Connection Standard Mode 100 kHz Figure 6.2 shows IC standard mode 100 kHz timing diagram. 1 / f SCL tf tr 70 % 70% 30% 30% 30 % tf SCL tr 70 % 70% 30% SDA 30% Time G-TW-0013940.1.2 Amplitude t SU;DAT Figure 6.2: IC Standard Mode 100 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) Table 6.2 lists IC standard mode 100 kHz timing definition. Parameter Symbol Min Max Unit Clock Rate fSCL - 100 kHz SCL: Rise-time (30% to 70%) tr - 50.3 ns SCL: Fall-time (70% to 30%) tf - 0.9 ns SDA: Rise-time (30% to 70%) tr - 55.3 ns SDA: Fall-time (70% to 30%) tf - 0.7 ns Data set-up time tSU;DAT 2511 - ns Data valid time tVD;DAT - 2.5 s Table 6.2: IC Standard Mode 100 kHz Timing Definition Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 26 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet tVD ;DAT Fast Mode 400 kHz Figure 6.3 shows IC fast mode 400 kHz timing diagram. 1 / f SCL t SU;DAT tf tr 70 % 70% 30 % 30% SCL 30% tf tr 70% 70% 30 % SDA 30 % Time G-TW-0013941.1.2 Amplitude tVD ;DAT Table 6.3 lists IC fast mode 400 kHz timing definition. Parameter Symbol Min Max Unit Clock Rate fSCL - 400 kHz SCL: Rise-time (30% to 70%) tr 41.4 50.6 ns SCL: Fall-time (70% to 30%) tf 0.7 0.9 ns SDA: Rise-time (30% to 70%) tr 46.0 55.9 ns SDA: Fall-time (70% to 30%) tf 0.5 0.7 ns Data set-up time tSU;DAT 573 - ns Data valid time tVD;DAT - 0.56 s Table 6.3: IC Fast Mode 400 kHz Timing Definition 6.3 SPI Master Interface The SPI master memory interface in the CSR1012 QFN is overlaid on the IC interface and uses a further 3 PIOs for the extra pins, see Table 6.4. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 27 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Figure 6.3: IC Fast Mode 400 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) SPI Flash Interface Pin Flash_VDD PIO[2] SF_DIN PIO[3] SF_CS# PIO[4] SF_CLK I2C_SCL SF_DOUT I2C_SDA Table 6.4: SPI Master Serial Flash Memory Interface Note: If an application using CSR1012 QFN is designed to boot from SPI serial flash, it is possible for the firmware to map the IC interface to alternative PIOs. Figure 6.4 shows simple SPI timing diagram. SF_DOUT MSB LSB SF_DIN MSB LSB G-TW-0012787.1.1 SF_CLK Figure 6.4: SPI Timing Diagram The boot-up sequence for CSR1012 QFN is controlled by hardware and firmware. Figure 6.5 shows the sequence of loading RAM with content from RAM, EEPROM and SPI serial flash. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 28 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet SF_CS# Device Starts Hardware Copies Content of ROM to RAM Hardware Checks I 2C Interface (Default Pins) Presence of EEPROM Device Presence of SPI Serial Flash Device Yes Copy Content of SPI Serial Flash to RAM Yes Copy Content of EEPROM to RAM Start MCU Executing from RAM No G-TW-0005552.3.2 No Figure 6.5: Memory Boot-up Sequence 6.4 Programming and Debug Interface Important Note: The CSR1012 QFN debug SPI interface is available in SPI slave mode to enable an external MCU to program and control the CSR1012 QFN, generally via libraries or tools supplied by CSR. The protocol of this interface is proprietary. The 4 SPI debug lines directly support this function. The SPI programs, configures and debugs the CSR1012 QFN. It is required in production. Ensure the 4 SPI signals are brought out to either test points or a header. Take SPI_PIO#_SEL high to enable the SPI debug feature on PIO[8:5]. CSR1012 QFN uses a 16-bit data and 16-bit address programming and debug interface. Transactions occur when the internal processor is running or is stopped. Data is written or read one word at a time. Alternatively, the auto-increment feature is available for block access. 6.4.1 Instruction Cycle The CSR1012 QFN is the slave and receives commands on DEBUG_MOSI and outputs data on DEBUG_MISO. Table 6.5 shows the instruction cycle for a SPI transaction. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 29 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Hardware Checks SPI Interface (Default Pins) 1 Reset the SPI interface Hold DEBUG_CS# high for 2 DEBUG_CLK cycles 2 Write the command word Take DEBUG_CS# low and clock in the 8-bit command 3 Write the address Clock in the 16-bit address word 4 Write or read data words Clock in or out 16-bit data word(s) 5 Termination Take DEBUG_CS# high Table 6.5: Instruction Cycle for a SPI Transaction With the exception of reset, DEBUG_CS# must be held low during the transaction. Data on DEBUG_MOSI is clocked into the CSR1012 QFN on the rising edge of the clock line DEBUG_CLK. When reading, CSR1012 QFN replies to the master on DEBUG_MISO with the data changing on the falling edge of the DEBUG_CLK. The master provides the clock on DEBUG_CLK. The transaction is terminated by taking DEBUG_CS# high. 6.4.2 Multi-slave Operation Do not connect the CSR1012 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines. When CSR1012 QFN is deselected (DEBUG_CS# = 1), the DEBUG_MISO line does not float. Instead, CSR1012 QFN outputs 0 if the processor is running or 1 if it is stopped. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 30 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet The auto increment operation on the CSR1012 QFN cuts down on the overhead of sending a command word and the address of a register for each read or write, especially when large amounts of data are to be transferred. The auto increment offers increased data transfer efficiency on the CSR1012 QFN. To invoke auto increment, DEBUG_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word written or read. 7 Power Control and Regulation CSR1012 QFN contains 2 regulators: 1 switch-mode regulator, which generates the main supply rail from the battery 1 low-voltage linear regulator Figure 7.1 shows the configuration for the power control and regulation with the CSR1012 QFN. SMPS_LX VDD_REG_IN Switch VDD _CORE Low-voltage VDD_CORE Linear Regulator Digits 0.65 /1.20 V Figure 7.1: Voltage Regulator Configuration 7.1 Switch-mode Regulator The switch-mode regulator generates the main rail from the battery supply, VDD_BAT_SMPS. The main rail supplies the lower regulated voltage to a further digital linear regulator and also to the analogue sections of the CSR1012 QFN. The switch-mode regulator generates typically 1.35V. 7.2 Low-voltage VDD_CORE Linear Regulator The integrated low-voltage VDD_CORE linear regulator powers the CSR1012 QFN digital circuits. The input voltage range is 0.65V to 1.35V. It can supply programmable voltages of 0.65V to 1.20V to the digital area of the CSR1012 QFN. The maximum output current for this regulator is 30mA. Connect a minimum 470nF low ESR capacitor, e.g. MLC, to the VDD_CORE output pin. Software controls the output voltage. Important Note: This regulator is only for CSR internal use. Section 8 shows CSR's recommended circuit connection. 7.3 Reset CSR1012 QFN is reset by: 7.3.1 Power-on reset Software-configured watchdog timer Digital Pin States on Reset Table 7.1 shows the pin states of CSR1012 QFN on reset. PU and PD default to weak values unless specified otherwise. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 31 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet VDD_RADIO 1.35 V VDD_ANA 1.35 V VDD_AUX 1.35 V Switch-mode Regulator G-TW-0005367.5.2 VDD _BAT _SMPS Pin Name / Group On Reset I2C_SDA Strong PU I2C_SCL Strong PU PIO[11:0] Weak PD AIO[2:0] Weak PU Table 7.1: Pin States on Reset 7.3.2 Power-on Reset Table 7.2 shows how the power-on reset occurs. Typ Reset release on VDD_CORE rising 1.05 Reset assert on VDD_CORE falling 1.00 Reset assert on VDD_CORE falling (Sleep mode) 0.60 Hysteresis 50 Unit V mV Table 7.2: Power-on Reset Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 32 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Power-on Reset Example Application Schematic C2032 BATTERY HOLDER C2 C3 C4 470n 4u7 470n 0R0 C5 150n U1 GND WAKE VDD_CORE 4 30 U2 I2C_SDA I2C_SCL PIO[2] 1 2 3 4 A0 A1 A2 GND VCC WP SCL SDA 8 7 6 5 C6 1u0 SO-8 GND AT24C512C-SSHM GND 29 28 27 VDD_BAT C11 0p5 ANT1 SPI_PIO# RF Note: Place C11 Close to RF (Pin 7) CSR1012 QFN GND PIO[5] / DEBUG_CLK PIO[6] / DEBUG_CS# PIO[7] / DEBUG_MOSI PIO[8] / DEBUG_MISO PIO[0] / UART_TX PIO[1] / UART_RX X1 XTAL_32K_IN XTAL_32K_OUT 16MHz AIO[2] AIO[1] AIO[0] X2 Production Information (c) Cambridge Silicon Radio Limited 2013-2015 C8 6p8 SB2 PIO9 16 17 24 25 11 12 13 C9 27p 1 2 3 4 5 6 7 8 9 10 11 12 VCHG SPI_MOSI SPI_CLK SPI_CSB SPI_MISO SERSER+ GND CASE CASE CASE CASE MINI SMT CONNECTOR 8PIN AIO[2] AIO[1] AIO[0] SW1 R1 820R R2 820R D1 D2 R3 0R0 1 2 + SP1 32.768kHz C7 15p SB3 3 2 10 XTAL_16M_IN XTAL_16M_OUT 9 VSS PIO[3] / SF_DIN PIO[4] / SF_CS# PIO[10] PIO[11] 23 CON1 SB1 18 19 20 22 14 15 GREEN C16 470n 0 8 VDD_XTAL PIO[9] Pull to VDD_PADS to enable debug SPI GREEN 7 26 C10 27p G-TW-0014618.1.2 4u7 R7 Page 33 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet VDD_BAT 1 GND Note: Place C2 Close to VDD_REG_IN (Pin 6) 5 C14 33p L1 VDD_CORE L2 GND 6 GND GND C12 4u7 VDD_REG_IN GND C13 47n C18 47n 31 C1 47u SMPS_LX BAT1 J1 21 PWR VDD_PADS 2 VDD_BAT 3 MMZ1005Y152C - 2 1 32 + 1 VDD_BAT_SMPS 8 9 Electrical Characteristics 9.1 Absolute Maximum Ratings Rating Min Max Unit Storage temperature -40 85 C Battery (VDD_BAT) operation 1.8 4.4 V I/O supply voltage -0.4 4.4 V VSS - 0.4 VDD + 0.4 V Other terminal voltages(a) (a) 9.2 VDD = Terminal Supply Domain Recommended Operating Conditions Min Typ Max Unit Operating temperature range -30 - 85 C Battery (VDD_BAT) operation(a) (b) 1.8 - 3.6 V I/O supply voltage (VDD_PADS)(c) 1.2 - 3.6 V (a) CSR1012 QFN is reliable and qualifiable to 4.3V (idle, active and deep sleep modes) and 3.8V (all modes), but there are minor deviations in performance relative to published performance values for 1.8V to 3.6V. For layout guidelines for 4.3V operation, see CSR1012 Hardware Design Review Template. (b) For hibernate and dormant mode, see Customer Advisory: Use of CSR101x at Operating Voltages Above 3.6V. (c) Safe to 4.3V if VDD_BAT = 4.3V. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 34 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Operating Condition 9.3 Input/Output Terminal Characteristics 9.3.1 Switch-mode Regulator Switch-mode Regulator Min Typ Max Unit Input voltage(a) 1.8 - 3.6 V - 1.35 - V -200 - 200 ppm/C Output noise, frequency range 100Hz to 100kHz - - 0.4 mV rms Settling time, settling to within 10% of final value - - 30 s Output current (Imax) - - 50 mA Quiescent current (excluding load, Iload < 1mA) - - 20 A Output current (Imax) - - 100 A Quiescent current - - 1 A Output voltage(b) Temperature coefficient Normal Operation (a) CSR1012 QFN is reliable and qualifiable to 4.3V (idle, active and deep sleep modes) and 3.8V (all modes), but there are minor deviations in performance relative to published performance values for 1.8V to 3.6V. For layout guidelines for 4.3V operation, see CSR1012 Hardware Design Review Template. (b) During Run mode, see Section 4.1. 9.3.2 Low-voltage Linear Regulator Normal Operation Min Typ Max Unit Input voltage 0.65 - 1.35 V Output voltage 0.65 - 1.20 V Important Note: This regulator is only for CSR internal use. Section 8 shows CSR's recommended circuit connection. 9.3.3 Digital Terminals Input Voltage Levels Min Typ Max Unit VIL input logic level low -0.4 - 0.3 x VDD_PADS V VIH input logic level high 0.7 x VDD_PADS - VDD_PADS + 0.4 V - - 25 ns Tr/Tf Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 35 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Ultra Low-power Mode Output Voltage Levels Typ Max Unit - - 0.4 V 0.75 x VDD_PADS - - V - - 5 ns Min Typ Max Unit IOL output current low, VOL max - 8 10 mA IOH output current high, VOH min - 8 10 mA With strong pull-up -150 -40 -10 A IC with strong pull-up -250 - - A With strong pull-down 10 40 150 A With weak pull-up -5.0 -1.0 -0.33 A With weak pull-down 0.33 1.0 5.0 A CI input capacitance 1.0 - 5.0 pF Min Typ Max Unit Input voltage 0 - VDD_AUX V Output voltage 0 - VDD_AUX V Output drive strength - 4 - mA VOL output logic level low, lOL = 4.0mA VOH output logic level high, lOH = -4.0mA Tr/Tf Input, Output and Tristate Currents(a) (a) Maximum current draw from VDD_PADS is less than 30mA depending on board design. 9.3.4 AIO Input/Output Voltage Levels 9.3.4.1 Auxiliary ADC Auxiliary ADC Min Typ Max Unit Resolution - - 10 Bits Input voltage range(a) 0 - VDD_AUX V INL -3 - 3 LSB DNL -3 - 3 LSB Accuracy Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 36 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Min Auxiliary ADC Min Typ Max Unit -1 - 1 LSB -0.8 - 0.8 % Input bandwidth - 100 - kHz Conversion time (measured at application) - 46 - s Sample rate(b) - - 21000 Samples/s ADC block conversion current - 410 - A Offset Gain error (a) LSB size = VDD_AUX/1023 (b) The auxiliary ADC is accessed through the firmware API. The sample rate given is achieved as part of this function. 9.3.4.2 Auxiliary DAC Min Typ Max Unit - - 10 Bits 1.30 1.35 1.40 V 0 - VDD_AUX V 1.30 1.35 1.40 V 0 1.32 2.64 mV -1.32 0 1.32 mV Integral non-linearity -3 0 3 LSB Settling time - - 250 ns Resolution Supply voltage, VDD_ANA Output voltage range Full-scale output voltage LSB size Offset Important Note: Access to the auxiliary DAC is firmware-dependent, for more information about its availability contact CSR. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 37 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Auxiliary DAC 9.4 Junction Temperature Table 9.1 lists the junction temperature when the device is operating within recommended operating conditions. Parameter Min Typ Max Unit - - 125 C Junction temperature Table 9.1: Junction Temperature within Recommended Operating Conditions 9.5 ESD Protection Apply ESD static handling precautions during manufacturing. Table 9.2 shows the ESD handling maximum ratings. Condition Class Max Rating 2 2000V (all pins) Charged Device Model Contact Discharge per JEDEC EIA/JESD22-C101 III 500V (all pins) Table 9.2: ESD Handling Ratings Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 38 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Human Body Model Contact Discharge per JEDEC EIA/JESD22-A114 10 Current Consumption Table 10.1 shows CSR1012 QFN total typical current consumption measured at the battery. Mode Description Total Typical Current at 3.0V Dormant All functions are shut down. To wake them up, toggle <900nA the WAKE pin. Hibernate VDD_PADS = OFF, REFCLK = OFF, SLEEPCLK = ON, VDD_BAT = ON Deep sleep VDD_PADS = ON, REFCLK = OFF, SLEEPCLK = ON, VDD_BAT = ON, RAM = ON, digital circuits = ON, <5A SMPS = ON (low-power mode), 2.2ms wake-up time Idle VDD_PADS = ON, REFCLK = ON, SLEEPCLK = ON, VDD_BAT = ON, RAM = ON, digital circuits = ON, ~1mA MCU = IDLE, <1s wake-up time RX active - ~20mA @ 3.0V peak current TX active - ~18mA @ 3.0V peak current <1.9A Note: Current consumption measurements were made: At 20C and with 3.0V VBAT. For the whole chip: including radio, microcontroller and necessary peripherals. Using SDK 2.4.3. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 39 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Table 10.1: Current Consumption 11 CSR Green Semiconductor Products and RoHS Compliance CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements: CSR has defined the "CSR Green" standard based on current regulatory and customer requirements including free from bromine, chlorine and antimony trioxide. Products and shipment packaging are marked and labelled with applicable environmental marking symbols in accordance with relevant regulatory requirements. This identifies the main environmental compliance regulatory restrictions CSR specify. For more information on the full "CSR Green" standard, contact product.compliance@csr.com. 1 Including applicable amendments to EU law which are published in the EU Official Journal, or SVHC Candidate List updates published by the European Chemicals Agency (ECHA). Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 40 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Restriction of Hazardous Substances directive guidelines in the EU RoHS Directive 2011/65/EU1. EU REACH, Regulation (EC) No 1907/20061: List of substances subject to authorisation (Annex XIV) Restrictions on the manufacture, placing on the market and use of certain dangerous substances, preparations and articles (Annex XVII). This Annex now includes requirements that were contained within EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not limited to, the control of use of Perfluorooctane sulfonates (PFOS). When requested by customers, notification of substances identified on the Candidate List as Substances of Very High Concern (SVHC)1. POP regulation (EC) No 850/20041 EU Packaging and Packaging Waste, Directive 94/62/EC1 Montreal Protocol on substances that deplete the ozone layer. Conflict minerals, Section 1502, Dodd-Frank Wall Street Reform and Consumer Protection act, which affects columbite-tantalite (coltan / tantalum), cassiterite (tin), gold, wolframite (tungsten) or their derivatives. CSR is a fabless semiconductor company: all manufacturing is performed by key suppliers. CSR have mandated that the suppliers shall not use materials that are sourced from "conflict zone mines" but understand that this requires accurate data from the EICC programme. CSR shall provide a complete EICC / GeSI template upon request. 12 CSR1012 QFN Software Stack CSR1012 QFN is supplied with Bluetooth v4.1 specification compliant stack firmware. Figure 12.1 shows that the CSR1012 QFN software architecture enables the Bluetooth processing and the application program to run on the internal RISC MCU. Application Peripherals and Power Control Generic Attribute Profile (GATT) Attribute Profile (ATT) Security Manager (SM) L2CAP Physical Layer G-TW-0005570.2.2 Radio Control Figure 12.1: Software Architecture Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 41 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Link Layer Control 13 Tape and Reel Information For tape and reel packing and labelling see IC Packing and Labelling Specification. 13.1 Tape Orientation Figure 13.1 shows the CSR1012 QFN packing tape orientation. G-TW-0013430.1.2 User Direction of Feed Figure 13.1: Tape Orientation Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 42 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet Pin A1 Marker 13.2 Tape Dimensions Figure 13.2 shows the dimensions of the tape for the CSR1012 QFN. P2 2.00.1 See Note 1 0.250.05 D0 O1.550.05 P0 4.00.1 See Note 2 E1 1.750.1 Y 'A' D1 O1.5MIN 5.500.1 See Note 3 12.000.3 B0 X Y K0 X REF 0.8 A0 8.000.1 SECTION X-X DETAIL 'A' REF R0.3 REF 0.8 REF 0.2 G-TW-0011237.1.2 REF 0.2 Figure 13.2: Tape Dimensions A0 B0 K0 Unit Notes 1. 4.25 0.1 4.25 0.1 0.75 0.1 mm 2. 3. 4. 5. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Measured from centreline of sprocket hole to centreline of pocket. 10 sprocket hole pitch cumulative tolerance 0.2 Measured from centreline of sprocket hole to centreline of pocket. Other material available. Typical SR of form tape Max 109 ohm/sq. Page 43 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet SECTION Y-Y 13.3 Reel Information a(rim height) ATTENTION Electrostatic Sensitive Devices Safe Handling Required 330.0 2.0 102.0 2.0 Detail "A" 20.2 88 REF MIN 13.0 +0.5 -0.2 "A" "b" REF 6 PS PS (MEASURED AT HUB) W1 (MEASURED AT HUB) W2 G-TW-0002797.5.2 Detail "B" Figure 13.3: Reel Dimensions Package Type Nominal Hub Width (Tape Width) a b W1 W2 Max Units 4 x 4 x 0.65mm QFN 12 1.5 (+0.0/-1.5) 96.5 (+3.5/-0.0) 12.4 (+2.0/-0.0) 18.4 mm 13.4 Moisture Sensitivity Level CSR1012 QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020. Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 44 of 48 CS-238833-DSP5 www.csr.com CSR1012 QFN Data Sheet 6 2.0 0.5 14 Document References Document Reference, Date Core Specification of the Bluetooth System. Bluetooth Specification Version 4.1, 03 December 2013 CSR1012 Hardware Design Review Template. CS-305810-DD CSR1012 QFN Performance Specification. CS-300888-SP CSR1012 QFN 4.3V Operation Performance Specification. CS-305809-SP Customer Advisory: Use of CSR101x at Operating Voltages Above 3.6V CS-306155-AN Electrostatic Discharge (ESD) Sensitivity Testing Human JESD22-A114 Body Model (HBM). CB-001036-ST IC Packing and Labelling Specification. CS-112584-SP Moisture / Reflow Sensitivity Classification for Nonhermitic Solid State Surface Mount Devices. IPC / JEDEC J-STD-020 Typical Solder Reflow Profile for Lead-free Devices. CS-116434-AN Production Information (c) Cambridge Silicon Radio Limited 2013-2015 CSR1012 QFN Data Sheet Environmental Compliance Statement for CSR Green Semiconductor Products. Page 45 of 48 CS-238833-DSP5 www.csr.com Terms and Definitions Definition AC Alternating Current ADC Analogue to Digital Converter AGC Automatic Gain Control AIO Analogue Input/Output ATT ATTribute protocol balun balanced/unbalanced interface or device that changes a balanced output to an unbalanced input or vice versa Bluetooth(R) Set of technologies providing audio and data transfer over short-range radio connections CSR Cambridge Silicon Radio dBm Decibels relative to 1 mW DC Direct Current DNL Differential Non Linearity (ADC accuracy parameter) e.g. exempli gratia, for example EDR Enhanced Data Rate EEPROM Electrically Erasable Programmable Read Only Memory EIA Electronic Industries Alliance ESD Electrostatic Discharge ESR Equivalent Series Resistance GAP Generic Access Profile GATT Generic ATTribute protocol GSM Global System for Mobile communications HID Human Interface Device IC Inter-Integrated Circuit Interface I/O Input/Output IC Integrated Circuit IF Intermediate Frequency INL Integral Non-Linearity (ADC accuracy parameter) IPC See www.ipc.org IQ In-Phase and Quadrature JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association) KB Kilobyte L2CAP Logical Link Control and Adaptation Protocol Production Information (c) Cambridge Silicon Radio Limited 2013-2015 CSR1012 QFN Data Sheet Term Page 46 of 48 CS-238833-DSP5 www.csr.com Definition LC An inductor (L) and capacitor (C) network LED Light-Emitting Diode LNA Low Noise Amplifier LSB Least Significant Bit (or Byte) MAC Medium Access Control MCU MicroController Unit MISO Master In Slave Out MLC MultiLayer Ceramic MOSI Master Out Slave In NSMD Non-Solder Mask Defined PA Power Amplifier PC Personal Computer PCB Printed Circuit Board PD Pull-Down PIO Parallel Input/Output PIO Programmable Input/Output, also known as general purpose I/O plc public limited company ppm parts per million PU Pull-Up PWM Pulse Width Modulation QFN Quad-Flat No-lead RAM Random Access Memory RF Radio Frequency RISC Reduced Instruction Set Computer RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/ EC) ROM Read Only Memory RSSI Received Signal Strength Indication RX Receive or Receiver SIG (Bluetooth) Special Interest Group SMP Security Manager Protocol SMPS Switch-Mode Power Supply Production Information (c) Cambridge Silicon Radio Limited 2013-2015 CSR1012 QFN Data Sheet Term Page 47 of 48 CS-238833-DSP5 www.csr.com Term Definition SPI Serial Peripheral Interface TCXO Temperature Compensated crystal Oscillator TX Transmit or Transmitter UART Universal Asynchronous Receiver Transmitter VCO Voltage Controlled Oscillator W-CDMA Wideband Code Division Multiple Access CSR1012 QFN Data Sheet Production Information (c) Cambridge Silicon Radio Limited 2013-2015 Page 48 of 48 CS-238833-DSP5 www.csr.com