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Features CSR µEnergy
®
CSR1012 QFN
Bluetooth
®
v4.1 specification compliant
Bluetooth Smart
128KB memory: 64KB RAM and 64KB ROM
Support for Bluetooth v4.1 specification host stack
including ATT, GATT, SMP, L2CAP, GAP
RSSI monitoring for proximity applications
<900nA current consumption in dormant mode
32kHz and 16MHz crystal or system clock
Switch-mode power supply
Programmable general purpose PIO controller
10-bit ADC
12 digital PIOs
3 analogue AIOs
UART
I²C / SPI for EEPROM / flash memory ICs and
peripherals
Debug SPI
4 PWM modules
Wake-up interrupt and watchdog timer
QFN 32-lead, 4 x 4 x 0.65mm, 0.4mm pitch
Bluetooth Smart IC
Production Information
CSR1012A05
Issue 5
General Description
CSR1012 QFN is a CSR µEnergy platform device.
CSR µEnergy are CSR's single-mode Bluetooth low
energy products for the Bluetooth Smart market.
CSR1012 QFN is a small footprint variant of CSR1010
QFN.
CSR μEnergy enables ultra low-power connectivity and
basic data transfer for applications previously limited by
the power consumption, size constraints and complexity
of other wireless standards. CSR1012 QFN provides
everything required to create a Bluetooth low energy
product with RF, baseband, MCU, qualified Bluetooth
v4.1 specification stack and customer application
running on a single IC.
Clock
Generation I
2
C / SPI
Bluetooth LE
Radio and Modem
MCU
I/O
LED PWM
PIO
AIO
UART
DebugRAM
ROM
16MHz
32kHz
Applications
Building an ecosystem using Bluetooth low energy
CSR is the industry leader for Bluetooth low energy, also
known as Bluetooth Smart. Bluetooth Smart enables
connectivity and data transfer to leading smartphone,
tablet and personal computing devices including Apple
iPhone, iPad, iPod and Mac products and leading
Android devices.
Bluetooth low energy takes less time to make a
connection than conventional Bluetooth wireless
technology and can consume approximately 1/20
th
of
the power of Bluetooth Basic Rate. CSR1012 QFN
supports profiles for health and fitness sensors,
watches, keyboards, mice and remote controls.
Typical Bluetooth Smart applications:
HID: keyboards, mice, touchpads, remote controls
Sports and fitness sensors: heart rate, runner
speed and cadence, cycle speed and cadence
Health sensors: blood pressure, thermometer and
glucose meters
Mobile accessories: watches, proximity tags, alert
tags and camera controls
Smart home: heating control and lighting control
Production Information
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CSR1012 QFN
Data Sheet
Ordering Information
Device
Package
Order Number
Type Size Shipment
Method
CSR1012 QFN QFN‑32-lead
(Pb free)
4 x 4 x 0.65mm
0.4mm pitch Tape and reel CSR1012A05-IQQP-R
Note:
The minimum order quantity is 4kpcs taped and reeled.
Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local
sales account manager or representative.
Contacts
General information
Information on this product
Customer support for this product
Details of compliance and standards
Help with this document
www.csr.com
sales@csr.com
www.csrsupport.com
product.compliance@csr.com
comments@csr.com
Production Information
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CSR1012 QFN
Data Sheet
Device Details
Bluetooth Radio
On-chip balun (50Ω impedance in TX and RX modes)
No external trimming is required in production
Bluetooth v4.1 specification compliant
Bluetooth Transmitter
9dBm RF transmit power with level control from
integrated 6-bit DAC over a dynamic range >25dB
No external power amplifier or TX/RX switch required
Bluetooth Receiver
-94dBm sensitivity
Integrated channel filters
Digital demodulator for improved sensitivity and co-
channel rejection
Fast AGC for enhanced dynamic range
Bluetooth Stack
CSR's protocol stack runs on the integrated MCU:
Support for Bluetooth v4.1 specification features:
Master and slave operation
Including encryption
Software stack in firmware includes:
GAP
L2CAP
Security manager
Attribute protocol
Attribute profile
Bluetooth low energy profile support
Synthesiser
Fully integrated synthesiser requires no external
VCO varactor diode, resonator or loop filter
Baseband and Software
Hardware MAC for all packet types enables packet
handling without the need to involve the MCU
Physical Interfaces
SPI master interface
SPI programming and debug interface
I²C
12 digital PIOs
3 analogue AIOs
UART
Auxiliary Features
Battery monitor
Power management features include software
shutdown and hardware wake-up
CSR1012 QFN can run in low power modes from an
external 32.768kHz clock signal
Integrated switch-mode power supply
Linear regulator (internal use only)
Power-on-reset cell detects low supply voltage
Package
32-lead 4 x 4 x 0.65mm, 0.4mm pitch QFN
Production Information
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CSR1012 QFN
Data Sheet
Functional Block Diagram
G-TW-0005362.9.2
I
2
C EEPROM
RF
UART
AUX / CLK /
PSU Control
PIO and LED
PWM
I/O
Clock Generation
SMPULDO
Bluetooth LE Modem
and LC
Bluetooth Radio
RAM 64KB
RAM Arbiter
Memory
Protection
MCU
Interrupt
Debug
Timer
AES-CCS and
AES Encryption
I
2
C / SPI Serial Flash
DMA
I
2
C / SPI
Serial
Flash
Control State Machine
ROM
DataCode
Debug
Wake-up
XTAL_16M XTAL_32K
PIO
VDD_PADS
VDDREG_IN VDD_BAT
SPI Serial Flash
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CSR1012 QFN Data Sheet
Document History
Revision Date Change Reason
118 APR 13 Original publication of this document.
221 DEC 13 Updates include:
Pre-production Information added.
Status Information.
4.4V operation added.
Absolute maximum ratings value for battery operation.
Package Information.
UART hardware flow control removed.
PIO definitions clarified.
Sleep clock maximum load capacitance.
Non-confidential information.
VDD_DIG corrected to VDD_CORE.
Hibernate current.
Correction to Performance Specification document number in Document
References.
Bluetooth 4.1 specification added.
Example Application Schematic.
Dev kit details removed.
303 FEB 14 Updates include:
Production Information added.
RF parameters.
Minimum order quantity.
4.3V Performance Specification document reference added.
Copyright years.
Minimum operating temperature in Recommended Operating Conditions.
Machine Model removed from ESD as it is not required by CSR or the latest
JEDEC standards .
403 FEB 14 Confidentiality Status added to Status Information.
506 JAN 15 Updates include:
Section 3 Clock Generation
Section 4 Operating Modes.
Section 5 Microcontroller, Memory and Baseband Logic.
Section 6 Serial Interfaces.
Section 7 Power Control and Regulation.
Section 8 Example Application Schematic.
Section 9 Electrical Characteristics.
Section 10 Current Consumption.
Section 14 Document References.
Other minor updates.
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CSR1012 QFN
Data Sheet
Status Information
The status of this Data Sheet is Production Information. CSR Product Data Sheets progress according to the following format:
Advance Information:
Information for designers concerning CSR product in development. All values specified are the target values of the design.
Minimum and maximum values specified are only given as guidance to the final specification limits and must not be
considered as the final values.
Engineering Sample:
Information about initial devices. Devices are untested or partially tested prototypes, their status is described in an
Engineering Sample Release Note. All values specified are the target values of the design. Minimum and maximum values
specified are only given as guidance to the final specification limits and must not be considered as the final values.
All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.
Pre-production Information:
Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design. Minimum
and maximum values specified are only given as guidance to the final specification limits and must not be considered as
the final values.
All electrical specifications may be changed by CSR without notice.
Production Information:
Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.
Production Data Sheets supersede all previous document versions.
Device Implementation
Important Note:
As the feature-set of the CSR1012 QFN is firmware build-specific, see the relevant software release note for the exact
implementation of features on the CSR1012 QFN.
Life Support Policy and Use in Safety-critical Applications
CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole
discretion of the customer. CSR will not warrant the use of its devices in such applications.
CSR Green Semiconductor Products and RoHS Compliance
CSR1012 QFN devices meet the requirements of Directive 2011/65/EU of the European Parliament and of the Council on the
Restriction of Hazardous Substance (RoHS). CSR1012 QFN devices are free from halogenated or antimony trioxide-based flame
retardants and other hazardous chemicals. For more information, see CSR's
Environmental Compliance Statement for CSR Green
Semiconductor Products
.
Confidentiality Status
This document is non-confidential. The right to use, copy and disclose this document may be subject to license restrictions in
accordance with the terms of the agreement entered into by CSR plc and the party that CSR plc delivered this document to.
Trademarks, Patents and Licences
Unless otherwise stated, words and logos marked with
or
®
are trademarks registered or owned by CSR plc or its affiliates.
Bluetooth
®
and the Bluetooth
®
logos are trademarks owned by Bluetooth
®
SIG, Inc. and licensed to CSR. Other products, services
and names used in this document may have been trademarked by their respective owners.
The publication of this information does not imply that any license is granted under any patent or other rights owned by CSR plc
and/or its affiliates.
CSR reserves the right to make technical changes to its products as part of its development programme.
While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept responsibility for any
errors.
Refer to www.csrsupport.com for compliance and conformance to standards information.
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CSR1012 QFN
Data Sheet
Contents
Ordering Information ........................................................................................................................................... 2
Contacts ..................................................................................................................................................... 2
Device Details ..................................................................................................................................................... 3
Functional Block Diagram .................................................................................................................................. 4
1 Package Information ......................................................................................................................................... 10
1.1 Pinout Diagram ........................................................................................................................................ 10
1.2 Device Terminal Functions ....................................................................................................................... 11
1.3 Package Dimensions ............................................................................................................................... 14
1.4 PCB Design and Assembly Considerations ............................................................................................. 15
1.5 Typical Solder Reflow Profile ................................................................................................................... 15
2 Bluetooth Modem .............................................................................................................................................. 16
2.1 RF Ports ................................................................................................................................................... 16
2.2 RF Receiver ............................................................................................................................................. 16
2.2.1 Low Noise Amplifier .................................................................................................................... 16
2.2.2 RSSI Analogue to Digital Converter ........................................................................................... 16
2.3 RF Transmitter ......................................................................................................................................... 16
2.3.1 IQ Modulator ............................................................................................................................... 16
2.3.2 Power Amplifier .......................................................................................................................... 16
2.4 Bluetooth Radio Synthesiser .................................................................................................................... 16
2.5 Baseband ................................................................................................................................................. 16
2.5.1 Physical Layer Hardware Engine ............................................................................................... 16
3 Clock Generation ............................................................................................................................................... 17
3.1 Clock Architecture .................................................................................................................................... 17
3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT .......................................................................... 17
3.2.1 Crystal Specification ................................................................................................................... 17
3.2.2 Frequency Trim .......................................................................................................................... 18
3.3 Sleep Clock .............................................................................................................................................. 18
3.3.1 Crystal Specification ................................................................................................................... 18
4 Operating Modes ............................................................................................................................................... 20
4.1 Run Mode ................................................................................................................................................. 20
4.2 Idle Mode ................................................................................................................................................. 20
4.3 Deep Sleep Mode .................................................................................................................................... 20
4.4 Hibernate Mode ........................................................................................................................................ 20
4.5 Dormant Mode ......................................................................................................................................... 20
5 Microcontroller, Memory and Baseband Logic .................................................................................................. 21
5.1 System RAM ............................................................................................................................................ 21
5.2 Internal ROM ........................................................................................................................................... 21
5.3 Microcontroller .......................................................................................................................................... 21
5.4 Programmable I/O Ports, PIO and AIO .................................................................................................... 21
5.5 LED Flasher / PWM Module ..................................................................................................................... 22
5.6 Temperature Sensor ................................................................................................................................ 23
5.7 Battery Monitor ......................................................................................................................................... 24
6 Serial Interfaces ................................................................................................................................................ 25
6.1 Application Interface ................................................................................................................................. 25
6.1.1 UART Interface ........................................................................................................................... 25
6.2 I²C Interface ............................................................................................................................................. 25
6.3 SPI Master Interface ................................................................................................................................ 27
6.4 Programming and Debug Interface .......................................................................................................... 29
6.4.1 Instruction Cycle ......................................................................................................................... 29
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Data Sheet
6.4.2 Multi-slave Operation .................................................................................................................. 30
7 Power Control and Regulation .......................................................................................................................... 31
7.1 Switch-mode Regulator ............................................................................................................................ 31
7.2 Low-voltage VDD_CORE Linear Regulator ............................................................................................. 31
7.3 Reset ........................................................................................................................................................ 31
7.3.1 Digital Pin States on Reset ......................................................................................................... 31
7.3.2 Power-on Reset .......................................................................................................................... 32
8 Example Application Schematic ........................................................................................................................ 33
9 Electrical Characteristics ................................................................................................................................... 34
9.1 Absolute Maximum Ratings ..................................................................................................................... 34
9.2 Recommended Operating Conditions ...................................................................................................... 34
9.3 Input/Output Terminal Characteristics ...................................................................................................... 35
9.3.1 Switch-mode Regulator .............................................................................................................. 35
9.3.2 Low-voltage Linear Regulator ..................................................................................................... 35
9.3.3 Digital Terminals ......................................................................................................................... 35
9.3.4 AIO ............................................................................................................................................. 36
9.4 Junction Temperature .............................................................................................................................. 38
9.5 ESD Protection ......................................................................................................................................... 38
10 Current Consumption ........................................................................................................................................ 39
11 CSR Green Semiconductor Products and RoHS Compliance .......................................................................... 40
12 CSR1012 QFN Software Stack ......................................................................................................................... 41
13 Tape and Reel Information ................................................................................................................................ 42
13.1 Tape Orientation ...................................................................................................................................... 42
13.2 Tape Dimensions ..................................................................................................................................... 43
13.3 Reel Information ....................................................................................................................................... 44
13.4 Moisture Sensitivity Level ......................................................................................................................... 44
14 Document References ....................................................................................................................................... 45
Terms and Definitions ................................................................................................................................................ 46
List of Figures
Figure 1.1 Pinout Diagram .................................................................................................................................... 10
Figure 3.1 Clock Architecture ................................................................................................................................ 17
Figure 3.2 Crystal Driver Circuit ............................................................................................................................ 17
Figure 3.3 Sleep Clock Crystal Driver Circuit ........................................................................................................ 18
Figure 5.1 Baseband Digits Block Diagram .......................................................................................................... 21
Figure 5.2 Typical PWM Signal on a PIO ............................................................................................................. 23
Figure 6.1 Example of an I²C Interface EEPROM Connection ............................................................................. 26
Figure 6.2 I²C Standard Mode 100 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) ............................. 26
Figure 6.3 I²C Fast Mode 400 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA) .................................... 27
Figure 6.4 SPI Timing Diagram ............................................................................................................................. 28
Figure 6.5 Memory Boot-up Sequence ................................................................................................................. 29
Figure 7.1 Voltage Regulator Configuration .......................................................................................................... 31
Figure 12.1 Software Architecture .......................................................................................................................... 41
Figure 13.1 Tape Orientation .................................................................................................................................. 42
Figure 13.2 Tape Dimensions ................................................................................................................................. 43
Figure 13.3 Reel Dimensions .................................................................................................................................. 44
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CSR1012 QFN
Data Sheet
List of Tables
Table 3.1 Crystal Specification ............................................................................................................................. 18
Table 3.2 Sleep Clock Specification ..................................................................................................................... 19
Table 5.1 Wake Options for Sleep Modes ............................................................................................................ 22
Table 5.2 Alternative PIO Functions ..................................................................................................................... 22
Table 5.3 PWM Operating Range ......................................................................................................................... 23
Table 6.1 Possible UART Settings ....................................................................................................................... 25
Table 6.2 I²C Standard Mode 100 kHz Timing Definition ..................................................................................... 26
Table 6.3 I²C Fast Mode 400 kHz Timing Definition ............................................................................................. 27
Table 6.4 SPI Master Serial Flash Memory Interface ........................................................................................... 28
Table 6.5 Instruction Cycle for a SPI Transaction ................................................................................................ 30
Table 7.1 Pin States on Reset .............................................................................................................................. 32
Table 7.2 Power-on Reset .................................................................................................................................... 32
Table 9.1 Junction Temperature within Recommended Operating Conditions .................................................... 38
Table 9.2 ESD Handling Ratings .......................................................................................................................... 38
Table 10.1 Current Consumption ............................................................................................................................ 39
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Data Sheet
1 Package Information
1.1 Pinout Diagram
G-TW-0005350.6.1
Orientation from Top of Device
13
1
2
3
4
5
6
7
8
9 101112 141516
17
18
19
20
21
22
23
24
2526272829303132
Figure 1.1: Pinout Diagram
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CSR1012 QFN
Data Sheet
1.2 Device Terminal Functions
Radio Lead Pad Type Supply Domain Description
RF 7RF VDD_RADIO
(a)
Bluetooth transmitter / receiver.
(a)
The VDD_RADIO domain is generated from VDD_REG_IN, see Figure 7.1.
Synthesiser and
Oscillator Lead Pad Type Supply Domain Description
XTAL_32K_OUT 2Analogue VDD_BAT Drive for sleep clock crystal.
XTAL_32K_IN 3Analogue VDD_BAT 32.768kHz sleep clock input.
XTAL_16M_OUT 9Analogue VDD_ANA
(b)
Drive for crystal.
XTAL_16M_IN 10 Analogue VDD_ANA Reference clock input.
(b)
The VDD_ANA domain is generated from VDD_REG_IN, see Figure 7.1.
I²C Interface Lead Pad Type Supply Domain Description
I2C_SDA 29
Bidirectional, tristate,
with weak internal
pull-up
VDD_PADS
I²C data input / output or SPI serial
flash data output (SF_DOUT). If
connecting to SPI serial flash,
connect this pin to SO on the serial
flash. See Section 6.3.
I2C_SCL 28 Input with weak
internal pull-up VDD_PADS I²C clock or SPI serial flash clock
output (SF_CLK), see Section 6.3.
PIO Port Lead Pad Type Supply Domain Description
PIO[11] 25 Bidirectional with
programmable
strength internal pull-
up/down
VDD_PADS Programmable I/O line.PIO[10] 24
PIO[9] 23
PIO[8] /
DEBUG_MISO 22
Bidirectional with
programmable
strength internal pull-
up/down
VDD_PADS
Programmable I/O line or debug SPI
MISO selected by SPI_PIO#.
PIO[7] /
DEBUG_MOSI 20 Programmable I/O line or debug SPI
MOSI selected by SPI_PIO#.
PIO[6] /
DEBUG_CS# 19
Programmable I/O line or debug SPI
chip select (CS#) selected by
SPI_PIO#.
PIO[5] /
DEBUG_CLK 18 Programmable I/O line or debug SPI
CLK selected by SPI_PIO#.
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CSR1012 QFN
Data Sheet
PIO Port Lead Pad Type Supply Domain Description
PIO[4] /
SF_CS# 17
Bidirectional with
programmable
strength internal pull-
up/down
VDD_PADS
Programmable I/O line or SPI serial
flash chip select (SF_CS#), see
Section 6.3.
PIO[3] /
SF_DIN 16
Programmable I/O line or SPI serial
flash data (SF_DIN) input. If
connecting to SPI serial flash, this pin
connects to SI on the serial flash. See
Section 6.3.
PIO[2] 27
Bidirectional with
programmable
strength internal pull-
up/down
VDD_PADS Programmable I/O line or I²C power.
PIO[1] /
UART_RX 15 Bidirectional with
programmable
strength internal pull-
up/down
VDD_PADS
Programmable I/O line or UART RX.
PIO[0] /
UART_TX 14 Programmable I/O line or UART TX.
AIO[2] 11
Bidirectional
analogue VDD_AUX
(c)
Analogue programmable I/O line.AIO[1] 12
AIO[0] 13
(c)
The VDD_AUX domain is generated from VDD_REG_IN, see Figure 7.1.
Test and Debug Lead Pad Type Supply Domain Description
SPI_PIO# 26 Input with strong
internal pull-down VDD_PADS Selects SPI debug on PIO[8:5].
Wake-up Lead Pad Type Supply Domain Description
WAKE 4
Input has no internal
pull-up or pull-down,
use external pull-
down.
VDD_BAT Input to wake CSR1012 QFN from
hibernate or dormant.
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CSR1012 QFN
Data Sheet
Power Supplies and
Control Lead Description
VDD_BAT 1Battery input and regulator enable (active high).
VDD_BAT_SMPS 32 Input to high-voltage switch-mode regulator.
SMPS_LX 31 High-voltage switch-mode regulator output.
VDD_CORE 5, 30 Positive supply for digital domain.
VDD_PADS 21 Positive supply for all digital I/O ports PIO[11:0].
VDD_REG_IN 6Positive supply for Bluetooth radio and digital linear regulator.
VDD_XTAL 8Decouple with 470nF capacitor to ground.
VSS Exposed pad Ground connections.
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CSR1012 QFN
Data Sheet
1.3 Package Dimensions
G-TW-0012803.3.3
Bottom View
Top View
J
BC
Caaa
Cbbb
Cccc
eee
e1
25
24
17
32 x L
d1 16
32 x b
9
CAB
M
ddd
1
8
P
32
Pin 1 ID
1
A
32
DBCC
M
MM
A
A2
A1
(A3)
Seating Plane
E
Pin 1 Corner
e/2
e
Exposed Die
Attach Pad
A
BCeee A
Dimension Min Typ Max Dimension Min Typ Max
A0.55 0.6 0.65 J2.24 2.34 2.44
A1 00.035 0.05 K2.24 2.34 2.44
A2 -0.4 - L 0.25 0.30 0.35
A3 -0.203 -aaa -0.1 -
b0.15 0.20 0.25 bbb -0.1 -
D - 4.0 -ccc -0.08 -
E - 4.0 -ddd -0.1 -
e - 0.4 -eee -0.1 -
d1/e1 -0.118 - P 0.43 - -
Notes
1.
Coplanarity applies to leads, corner leads and die attach pad.
Description 32-lead Quad-flat No-lead Package
Size 4 x 4 x 0.65mm JEDEC MO-220
Pitch 0.4 Units mm
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CSR1012 QFN
Data Sheet
1.4 PCB Design and Assembly Considerations
This section lists recommendations to achieve maximum board-level reliability of the 4 x 4 x 0.65mm QFN 32-lead
package:
NSMD lands (lands smaller than the solder mask aperture) are preferred, because of the greater accuracy of
the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap
of the solder mask on the land creates a step in the solder at the land interface, which can cause stress
concentration and act as a point for crack initiation.
CSR recommends that the PCB land pattern is in accordance with IPC standard IPC-7351.
Solder paste must be used during the assembly process.
1.5 Typical Solder Reflow Profile
For information, see
Typical Solder Reflow Profile for Lead-free Devices Information Note
.
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Data Sheet
2 Bluetooth Modem
2.1 RF Ports
CSR1012 QFN contains an integrated balun which provides a single-ended RF TX / RX port pin. No matching
components are needed as the receive mode impedance is 50Ω and the transmitter has been optimised to deliver
power in to a 50Ω load.
2.2 RF Receiver
The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient
out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and
W‑CDMA cellular phone transmitters without being significantly desensitised.
An ADC digitises the IF received signal.
2.2.1 Low Noise Amplifier
The LNA operates in differential mode and takes its input from the balanced port of the integrated balun.
2.2.2 RSSI Analogue to Digital Converter
The ADC samples the RSSI voltage on a packet-by-packet basis and implements a fast AGC. The front-end LNA gain
is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This
improves the dynamic range of the receiver, improving performance in interference-limited environments.
2.3 RF Transmitter
2.3.1 IQ Modulator
The transmitter features a direct IQ modulator to minimise frequency drift during a transmit packet, which results in a
controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
2.3.2 Power Amplifier
The internal PA has a maximum 9dBm output power without needing an external RF PA.
2.4 Bluetooth Radio Synthesiser
The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening can,
varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time across the
guaranteed temperature range to meet the Bluetooth v4.1 specification.
2.5 Baseband
2.5.1 Physical Layer Hardware Engine
Dedicated logic performs:
Cyclic redundancy check
Encryption
Data whitening
Access code correlation
The hardware supports all optional and mandatory features of Bluetooth v4.1 specification.
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CSR1012 QFN
Data Sheet
3 Clock Generation
The Bluetooth reference clock for the system is generated from an external 16MHz clock source, see Figure 3.1. All
the CSR1012 QFN internal digital clocks are generated using a phase locked loop, which is locked to the frequency of
either the external reference clock source or a sleep clock frequency of 32.768kHz, see Figure 3.1.
3.1 Clock Architecture
G-TW-0005266.2.2
Fast XTAL Clock
for System
Slow XTAL Clock
for Sleep
Bluetooth PLL
16MHz
32kHz
Core Digits
(16MHz)
Embedded Digits
(32kHz)
Bluetooth LO
(~4.8GHz)
Figure 3.1: Clock Architecture
3.2 Crystal Oscillator: XTAL_16M_IN and XTAL_16M_OUT
CSR1012 QFN contains crystal driver circuits. This operates with an external crystal and capacitors to form a Pierce
oscillator. Figure 3.2 shows the external crystal is connected to pins XTAL_16M_IN and XTAL_16M_OUT.
G-TW-0005348.1.1
-
C
LOAD1
C
LOAD2
XTAL_16M_IN
XTAL_16M_OUT
C
TRIM
Figure 3.2: Crystal Driver Circuit
Note:
C
TRIM
is the internal trimmable capacitance in Table 3.1.
C
LOAD1
and C
LOAD2
in combination with C
TRIM
and any parasitic capacitance provide the load capacitance required
by the crystal.
3.2.1 Crystal Specification
Table 3.1 shows the specification for an external crystal.
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CSR1012 QFN
Data Sheet
Parameter Min Typ Max Unit
Frequency -16 -MHz
Frequency tolerance (without trimming)
(a)
- - ±25 ppm
Frequency trim range
(b)
-±50 -ppm
Drive level -0.4 - V
Equivalent series resistance - - 60 Ω
Load capacitance - 9 - pF
Pullability 10 - - ppm/pF
Table 3.1: Crystal Specification
(a)
Use integrated load capacitors to trim initial frequency tolerance in production or to trim frequency over temperature, increasing the allowable
frequency tolerance.
(b)
Frequency trim range is dependent on crystal load capacitor values and crystal pullability.
3.2.2 Frequency Trim
CSR1012 QFN contains variable integrated capacitors to allow for fine-tuning of the crystal resonant frequency. This
firmware-programmable feature allows accurate trimming of crystals on a per-device basis on the production line. The
resulting trim value is stored in non-volatile memory.
3.3 Sleep Clock
The sleep clock is an externally provided 32.768kHz clock that is used during deep sleep and in other low-power modes.
Figure 3.3 shows the sleep clock crystal driver circuit.
G-TW-0005349.2.2
-
C
LOAD1
C
LOAD2
XTAL_32K_IN
XTAL_32K_OUT
Figure 3.3: Sleep Clock Crystal Driver Circuit
Note:
C
LOAD1
and C
LOAD2
in combination with any parasitic capacitance provide the load capacitance required by the
crystal.
3.3.1 Crystal Specification
Table 3.2 shows the requirements for the sleep clock.
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CSR1012 QFN
Data Sheet
Sleep Clock Min Typ Max Units
Frequency 30 32.768 35 kHz
Frequency tolerance
(a)
(b)
- - 250 ±ppm
Frequency trim range -50 -±ppm
Drive level -0.4 - V
Load capacitance - - 10 pF
Equivalent series resistance 40 -65
Duty cycle 30:70 50:50 70:30 %
Table 3.2: Sleep Clock Specification
(a)
The frequency of the slow clock is periodically calibrated against the system clock. As a result the rate of change of the frequency is more
important than the maximum deviation. To meet the accuracy requirements the frequency should not drift due to temperature or other effects
by more than 80ppm in any 5 minute period.
(b)
CSR1012 QFN can correct for ±1% by using the fast clock to calibrate the slow clock.
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CSR1012 QFN
Data Sheet
4 Operating Modes
CSR1012 QFN has 5 operating modes. 3 of these are sleep modes:
Running
Idle
Sleep modes:
Deep Sleep
Hibernate
Dormant
For current consumption rates in the operating modes, see Section 10.
4.1 Run Mode
In Run mode, all functions are on. RX and/or TX are active.
4.2 Idle Mode
In Idle mode, the VDD_PADS and VDD_BAT domains are powered, the reference clock and the sleep clock are
powered, the RAM is powered and the digital circuits are powered. The MCU is idle.
There is a <1μs wake-up time.
4.3 Deep Sleep Mode
In Deep Sleep mode, the VDD_PADS and VDD_BAT domains are powered, the sleep clock is on but the reference
clock is off, the RAM is on, the digital circuits are on and the SMPS is on (low-power mode). There is a configurable
wake-up time.
CSR1012 QFN is woken from Deep Sleep mode by any PIO configured to wake the IC.
4.4 Hibernate Mode
In Hibernate mode, the VDD_PADS and VDD_BAT domains are powered and the sleep clock is on. The reference
clock is off.
CSR1012 QFN is woken from Hibernate mode by a selected level on the WAKE pin or by the watchdog timer.
4.5 Dormant Mode
In Dormant mode, all functions are off. CSR1012 QFN is woken from Dormant mode by a selected level on the WAKE
pin.
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CSR1012 QFN
Data Sheet
5 Microcontroller, Memory and Baseband Logic
G-TW-0005354.3.2
I
2
C / Serial Flash
Bluetooth low energy Modem
and LC
RAM Arbiter
RAM
MCU
I
2
C /
Serial
Flash
I/O
UART
PIO and
LED PWM
AES-CCS and
AES
Encryption
AUX / CLK /
PSU Control
Interrupt
DMA
ADCs DACs
I/O
Control Logic
Memory Protection
Wake-ups
RAM Interface
(Buffers, LUTs, Tables and State)
Bluetooth and
Auxiliary Analogue
Control
PIOs
Debug
I
2
C EEPROM
Debug Timer
Code Data
Serial Flash
Figure 5.1: Baseband Digits Block Diagram
5.1 System RAM
64KB of integrated RAM supports the RISC MCU and is shared between the ring buffers used to hold data for each
active connection, general-purpose memory required by the Bluetooth stack and the user application.
5.2 Internal ROM
CSR1012 QFN has 64KB of internal ROM. This memory is provided for system firmware implementation. If the internal
ROM holds valid program code, on boot-up, this is copied into the program RAM. Code then executes from ROM and
RAM.
5.3 Microcontroller
The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and
external interfaces. A 16-bit RISC microcontroller is used for low power consumption and efficient use of memory.
5.4 Programmable I/O Ports, PIO and AIO
12 lines of programmable bidirectional I/O are provided. They are all powered from VDD_PADS.
PIO lines are software-configurable as weak pull-up, weak pull-down, strong pull-up or strong pull-down.
Note:
At reset all PIO lines are inputs with weak pull-downs.
Any of the PIO lines can be configured as interrupt request lines or to wake the IC from deep sleep mode. Table 5.1
lists the options for waking the IC from the sleep modes.
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CSR1012 QFN
Data Sheet
Sleep Mode Wake-up Options
Dormant Can only be woken by the WAKE pin.
Hibernate Can be woken by the WAKE pin or by the watchdog timer.
Deep Sleep Can be woken by any PIO configured to wake the IC.
Table 5.1: Wake Options for Sleep Modes
The CSR1012 QFN supports alternative functions on the PIO lines, for example:
SPI interface, see Section 1.2 and Section 6.4
UART, see Section 1.2 and Section 6.1.1
LED flasher / PWM module, see Section 5.5
Table 5.2 shows the alternative functions on the PIO lines.
PIO
Function
Debug SPI SPI Flash UART
PIO[8] DEBUG_MISO - -
PIO[7] DEBUG_MOSI - -
PIO[6] DEBUG_CS# - -
PIO[5] DEBUG_CLK - -
PIO[4] -SF_CS# -
PIO[3] -SF_DIN -
PIO[2] ---
PIO[1] --UART_RX
PIO[0] --UART_TX
Table 5.2: Alternative PIO Functions
Note:
CSR cannot guarantee that the PIO assignments remain as described. Implementation of the PIO lines is firmware
build-specific, for more information see the relevant software release note.
CSR1012 QFN has 3 general-purpose analogue interface pins, AIO[2:0].
5.5 LED Flasher / PWM Module
CSR1012 QFN contains an LED flasher / PWM module.
Note:
The LED flasher functions in Deep Sleep and Active modes only.
The PWM functions in all modes except Hibernate and Dormant.
These functions are controlled by the on-chip firmware.
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Data Sheet
Figure 5.2 shows a typical PWM signal on a PIO. For more information, see
CSR µEnergy Pulse Width Modulation
Application Note
.
G-TW-0013938.1.3
Hold
Time
(Bright )
Hold
Time
(Dull)
Highest
Duty
Cycle
Ramp
Time
Amplitude
T
hold (dull )
Duration for which the PWM output is held in the dullest part of
the pulse sequence
T
on
(dull)
T
off (dull )
T
on
(dull )
T
of f ( dull )
PWM output governed by the timings setup for
the dullest part of the pulse sequence
Varying
Duty
Cycle
(Bright
to Dull)
Lowest
Duty
Cycle
Varying
Duty
Cycle
(Dull to
Bright )
T
ramp
- Duration of the ramping, the number of
pulses and their widths during ramping is
proportional to the ramping rate
PWM output while ramping from dullest to brightest
T
ramp
- Duration of the ramping and the number
of pulses and their widths during ramping
is proportional to the ramping rate
PWM output while ramping from brightest to dullest
T
hold (bright )
Duration for which the PWM output is
held in the brightest part of the pulse sequence
T
on (bright )
T
off
(bright )
T
on (bright )
T
off
(bright )
PWM output governed by the timings setup for the
brightest part of the pulse sequence
Figure 5.2: Typical PWM Signal on a PIO
Figure 5.2 lists PWM the operating range.
Parameter Min Max Unit
Off Time (T
off
)30.5 7782 µs
On Time (T
on
)30.5 7782 µs
Hold Time (T
hold
)16 4080 ms
Duty Cycle = On Time (T
on
) + Off Time (T
off
)61 15564 µs
Frequency = 1 / Duty Cycle 64.3 16320 Hz
Table 5.3: PWM Operating Range
5.6 Temperature Sensor
CSR1012 QFN contains a temperature sensor that measures the temperature of the die to an accuracy of ±1 °C.
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CSR1012 QFN
Data Sheet
5.7 Battery Monitor
CSR1012 QFN contains an internal battery monitor that reports the battery voltage to the software.
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CSR1012 QFN
Data Sheet
6 Serial Interfaces
6.1 Application Interface
6.1.1 UART Interface
The CSR1012 QFN UART interface provides a simple mechanism for communicating with other serial devices using
the RS232 protocol.
2 signals implement the UART function, UART_TX and UART_RX. When CSR1012 QFN is connected to another digital
device, UART_RX and UART_TX transfer data between the 2 devices.
UART configuration parameters, e.g. baud rate and data format, are set using CSR1012 QFN firmware.
When selected in firmware PIO[0] is assigned to a UART_TX output and PIO[1] is assigned to a UART_RX input, see
Section 1.2.
Note:
To communicate with the UART at its maximum data rate using a standard PC, the PC requires an accelerated
serial port adapter card.
Table 6.1 shows the possible UART settings for the CSR1012 QFN.
Parameter Possible Values
Baud rate Minimum
2400 baud (≤2%Error)
9600 baud (≤2%Error)
Maximum 3.69Mbaud (≤0.1%Error)
Parity None, Odd or Even
Number of stop bits 1 or 2
Bits per byte 8
Table 6.1: Possible UART Settings
6.1.1.1 UART Configuration While in Deep Sleep
The maximum baud rate is 2400 baud during deep sleep.
6.2 I²C Interface
The I²C interface communicates to EEPROM, external peripherals or sensors. An external EEPROM connection can
hold the program code externally to the CSR1012 QFN.
Figure 6.1 shows an example of an EEPROM connected to the I²C interface where I2C_SCL, I2C_SDA and PIO[2] are
connected to the external EEPROM. The PIO[2] pin supplies the power to the EEPROM supply pin, e.g. VDD. At boot-
up, if there is no valid ROM image in the CSR1012 QFN ROM area the CSR1012 QFN tries to boot from the I²C interface,
see Figure 6.5. This involves reading the code from the external EEPROM and loading it into the internal CSR1012 QFN
RAM.
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CSR1012 QFN
Data Sheet
G-TW-0005553.1.1
VDD
WP
SCL
SDA
A0
A1
A2
VSS
I2C_SCL
I2C_SDA
PIO[2]
1
2
3
45
6
7
8
24AA512
Figure 6.1: Example of an I²C Interface EEPROM Connection
Standard Mode 100 kHz
Figure 6.2 shows I²C standard mode 100 kHz timing diagram.
G-TW-0013940.1.2
Time
Amplitude
SDA
SCL
70%
30%
t
f
70%
t
f
30%
t
VD ;DAT
70%
30%
t
r
70%
t
r
30%
t
SU;DAT
1 / f
SCL
30%
Figure 6.2: I²C Standard Mode 100 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA)
Table 6.2 lists I²C standard mode 100 kHz timing definition.
Parameter Symbol Min Max Unit
Clock Rate f
SCL
-100 kHz
SCL: Rise-time (30% to 70%) t
r
-50.3 ns
SCL: Fall-time (70% to 30%) t
f
-0.9 ns
SDA: Rise-time (30% to 70%) t
r
-55.3 ns
SDA: Fall-time (70% to 30%) t
f
-0.7 ns
Data set-up time t
SU;DAT
2511 -ns
Data valid time t
VD;DAT
-2.5 µs
Table 6.2: I²C Standard Mode 100 kHz Timing Definition
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Data Sheet
Fast Mode 400 kHz
Figure 6.3 shows I²C fast mode 400 kHz timing diagram.
G-TW-0013941.1.2
Time
Amplitude
SDA
SCL
70%
30%
t
f
70%
t
f
30%
t
VD;DAT
70%
30%
t
r
70%
t
r
30%
t
SU;DAT
1 / f
SCL
30%
Figure 6.3: I²C Fast Mode 400 kHz Timing Diagram (Top Line: SCL, Bottom Line: SDA)
Table 6.3 lists I²C fast mode 400 kHz timing definition.
Parameter Symbol Min Max Unit
Clock Rate f
SCL
-400 kHz
SCL: Rise-time (30% to 70%) t
r
41.4 50.6 ns
SCL: Fall-time (70% to 30%) t
f
0.7 0.9 ns
SDA: Rise-time (30% to 70%) t
r
46.0 55.9 ns
SDA: Fall-time (70% to 30%) t
f
0.5 0.7 ns
Data set-up time t
SU;DAT
573 -ns
Data valid time t
VD;DAT
-0.56 µs
Table 6.3: I²C Fast Mode 400 kHz Timing Definition
6.3 SPI Master Interface
The SPI master memory interface in the CSR1012 QFN is overlaid on the I²C interface and uses a further 3 PIOs for
the extra pins, see Table 6.4.
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CSR1012 QFN
Data Sheet
SPI Flash Interface Pin
Flash_VDD PIO[2]
SF_DIN PIO[3]
SF_CS# PIO[4]
SF_CLK I2C_SCL
SF_DOUT I2C_SDA
Table 6.4: SPI Master Serial Flash Memory Interface
Note:
If an application using CSR1012 QFN is designed to boot from SPI serial flash, it is possible for the firmware to
map the I²C interface to alternative PIOs.
Figure 6.4 shows simple SPI timing diagram.
G-TW-0012787.1.1
SF_CS#
MSB LSB
MSB LSB
SF_CLK
SF_DOUT
SF_DIN
Figure 6.4: SPI Timing Diagram
The boot-up sequence for CSR1012 QFN is controlled by hardware and firmware. Figure 6.5 shows the sequence of
loading RAM with content from RAM, EEPROM and SPI serial flash.
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CSR1012 QFN
Data Sheet
G-TW-0005552.3.2
Device Starts
Hardware Copies
Content of ROM
to RAM
Hardware Checks
I
2
C Interface
(Default Pins)
Presence of
EEPROM
Device
Hardware Checks
SPI Interface
(Default Pins)
Presence of
SPI Serial Flash
Device
Start MCU
Executing from RAM
Copy Content of SPI
Serial Flash to RAM
Copy Content of
EEPROM to RAM
YesNo
Yes
No
Figure 6.5: Memory Boot-up Sequence
6.4 Programming and Debug Interface
Important Note:
The CSR1012 QFN debug SPI interface is available in SPI slave mode to enable an external MCU to program and
control the CSR1012 QFN, generally via libraries or tools supplied by CSR. The protocol of this interface is
proprietary. The 4 SPI debug lines directly support this function.
The SPI programs, configures and debugs the CSR1012 QFN. It is required in production. Ensure the 4 SPI signals
are brought out to either test points or a header.
Take SPI_PIO#_SEL high to enable the SPI debug feature on PIO[8:5].
CSR1012 QFN uses a 16-bit data and 16-bit address programming and debug interface. Transactions occur when the
internal processor is running or is stopped.
Data is written or read one word at a time. Alternatively, the auto-increment feature is available for block access.
6.4.1 Instruction Cycle
The CSR1012 QFN is the slave and receives commands on DEBUG_MOSI and outputs data on DEBUG_MISO. Table
6.5 shows the instruction cycle for a SPI transaction.
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Data Sheet
1Reset the SPI interface Hold DEBUG_CS# high for 2 DEBUG_CLK cycles
2Write the command word Take DEBUG_CS# low and clock in the 8-bit command
3Write the address Clock in the 16-bit address word
4Write or read data words Clock in or out 16-bit data word(s)
5Termination Take DEBUG_CS# high
Table 6.5: Instruction Cycle for a SPI Transaction
With the exception of reset, DEBUG_CS# must be held low during the transaction. Data on DEBUG_MOSI is clocked
into the CSR1012 QFN on the rising edge of the clock line DEBUG_CLK. When reading, CSR1012 QFN replies to the
master on DEBUG_MISO with the data changing on the falling edge of the DEBUG_CLK. The master provides the
clock on DEBUG_CLK. The transaction is terminated by taking DEBUG_CS# high.
The auto increment operation on the CSR1012 QFN cuts down on the overhead of sending a command word and the
address of a register for each read or write, especially when large amounts of data are to be transferred. The auto
increment offers increased data transfer efficiency on the CSR1012 QFN. To invoke auto increment, DEBUG_CS# is
kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word written or
read.
6.4.2 Multi-slave Operation
Do not connect the CSR1012 QFN in a multi-slave arrangement by simple parallel connection of slave MISO lines.
When CSR1012 QFN is deselected (DEBUG_CS# = 1), the DEBUG_MISO line does not float. Instead, CSR1012 QFN
outputs
0
if the processor is running or
1
if it is stopped.
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CSR1012 QFN
Data Sheet
7 Power Control and Regulation
CSR1012 QFN contains 2 regulators:
1 switch-mode regulator, which generates the main supply rail from the battery
1 low-voltage linear regulator
Figure 7.1 shows the configuration for the power control and regulation with the CSR1012 QFN.
G-TW-0005367.5.2
Switch-mode
Regulator
Switch
SMPS_LX
VDD _BAT _SMPS
Low-voltage
VDD_CORE
Linear Regulator
VDD_AUX 1.35 V
VDD_RADIO 1.35 V
VDD_ANA 1.35V
Digits 0.65 /1.20 V
VDD _CORE
VDD_REG_IN
Figure 7.1: Voltage Regulator Configuration
7.1 Switch-mode Regulator
The switch-mode regulator generates the main rail from the battery supply, VDD_BAT_SMPS. The main rail supplies
the lower regulated voltage to a further digital linear regulator and also to the analogue sections of the CSR1012 QFN.
The switch-mode regulator generates typically 1.35V.
7.2 Low-voltage VDD_CORE Linear Regulator
The integrated low-voltage VDD_CORE linear regulator powers the CSR1012 QFN digital circuits. The input voltage
range is 0.65V to 1.35V. It can supply programmable voltages of 0.65V to 1.20V to the digital area of the CSR1012 QFN.
The maximum output current for this regulator is 30mA.
Connect a minimum 470nF low ESR capacitor, e.g. MLC, to the VDD_CORE output pin. Software controls the output
voltage.
Important Note:
This regulator is only for CSR internal use. Section 8 shows CSR's recommended circuit connection.
7.3 Reset
CSR1012 QFN is reset by:
Power-on reset
Software-configured watchdog timer
7.3.1 Digital Pin States on Reset
Table 7.1 shows the pin states of CSR1012 QFN on reset. PU and PD default to weak values unless specified otherwise.
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CSR1012 QFN
Data Sheet
Pin Name / Group On Reset
I2C_SDA Strong PU
I2C_SCL Strong PU
PIO[11:0] Weak PD
AIO[2:0] Weak PU
Table 7.1: Pin States on Reset
7.3.2 Power-on Reset
Table 7.2 shows how the power-on reset occurs.
Power-on Reset Typ Unit
Reset release on VDD_CORE rising 1.05
V
Reset assert on VDD_CORE falling 1.00
Reset assert on VDD_CORE falling (Sleep mode) 0.60
Hysteresis 50 mV
Table 7.2: Power-on Reset
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CSR1012 QFN
Data Sheet
8 Example Application Schematic
G-TW-0014618.1.2
GREEN
D1
GREEN
D2
Pull to VDD_PADS to enable debug SPI
C2032 BATTERY HOLDER
+1
-2
BAT1
VDD_BAT
470n
C3
470n
C4
820R
R1
820R
R2
32.768kHz
X2
SO-8
AT24C512C-SSHM
VCC 8
GND
4A2
3SCL 6
A1
2A0
1
WP 7
SDA 5
U1
GND GND
VCHG
1
SPI_MOSI
2
SPI_CLK
3
SPI_CSB
4
SPI_MISO
5
SER-
6
SER+
7
GND
8
CASE
9
CASE
10
CASE
11
CASE
12
CON1
MINI SMT CONNECTOR 8PIN
RF
7
VDD_REG_IN 6
VDD_CORE 5
WAKE 4
XTAL_32K_OUT
2
XTAL_32K_IN
3
VDD_BAT 1
VDD_BAT_SMPS 32
SMPS_LX 31
I2C_SDA 29
I2C_SCL 28
PIO[0] / UART_TX 14
PIO[1] / UART_RX 15
PIO[2] 27
PIO[3] / SF_DIN 16
PIO[4] / SF_CS# 17
PIO[5] / DEBUG_CLK 18
PIO[6] / DEBUG_CS# 19
PIO[7] / DEBUG_MOSI 20
PIO[8 / DEBUG_MISO]22
PIO[9] 23
PIO[10] 24
PIO[11] 25
SPI_PIO# 26
XTAL_16M_OUT
9
XTAL_16M_IN
10
AIO[0] 13
AIO[1] 12
VSS
0
VDD_CORE 30
VDD_PADS 21
AIO[2] 11
VDD_XTAL
8
U2
SB1
VDD_BAT
SB3
SB2
PIO9
AIO[2]
AIO[1]
AIO[0]
1
3
2
PWR J1
SW1
4u7
L1
47n
C13
GND GNDGND
GND
27p
C9
1u0
C6
4u7
C2 0R0
R7
+
1
-
2
SP1
GND
47u
C1
GND
0p5
C11
16MHz
X1
15p
C7
6p8
C8
27p
C10
470n
C16
ANT1
0R0
R3
4u7
C12
33p
C14
150n
C5
47n
C18
GND
MMZ1005Y152C
L2
Note: Place C2 Close to
VDD_REG_IN (Pin 6)
Note: Place C11 Close to
RF (Pin 7)
CSR1012 QFN
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CSR1012 QFN
Data Sheet
9 Electrical Characteristics
9.1 Absolute Maximum Ratings
Rating Min Max Unit
Storage temperature -40 85 °C
Battery (VDD_BAT) operation 1.8 4.4 V
I/O supply voltage -0.4 4.4 V
Other terminal voltages
(a)
VSS - 0.4 VDD + 0.4 V
(a)
VDD = Terminal Supply Domain
9.2 Recommended Operating Conditions
Operating Condition Min Typ Max Unit
Operating temperature range -30 -85 °C
Battery (VDD_BAT) operation
(a)
(b)
1.8 -3.6 V
I/O supply voltage (VDD_PADS)
(c)
1.2 -3.6 V
(a)
CSR1012 QFN is reliable and qualifiable to 4.3V (idle, active and deep sleep modes) and 3.8V (all modes), but there are minor deviations in
performance relative to published performance values for 1.8V to 3.6V. For layout guidelines for 4.3V operation, see
CSR1012 Hardware Design
Review Template
.
(b)
For hibernate and dormant mode, see
Customer Advisory: Use of CSR101x at Operating Voltages Above 3.6V
.
(c)
Safe to 4.3V if VDD_BAT = 4.3V.
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9.3 Input/Output Terminal Characteristics
9.3.1 Switch-mode Regulator
Switch-mode Regulator Min Typ Max Unit
Input voltage
(a)
1.8 -3.6 V
Output voltage
(b)
-1.35 - V
Temperature coefficient -200 -200 ppm/°C
Normal Operation
Output noise, frequency range 100Hz to 100kHz - - 0.4 mV rms
Settling time, settling to within 10% of final value - - 30 μs
Output current (I
max
)- - 50 mA
Quiescent current (excluding load, I
load
< 1mA) - - 20 µA
Ultra Low-power Mode
Output current (I
max
)- - 100 µA
Quiescent current - - 1 µA
(a)
CSR1012 QFN is reliable and qualifiable to 4.3V (idle, active and deep sleep modes) and 3.8V (all modes), but there are minor deviations in
performance relative to published performance values for 1.8V to 3.6V. For layout guidelines for 4.3V operation, see
CSR1012 Hardware Design
Review Template
.
(b)
During Run mode, see Section 4.1.
9.3.2 Low-voltage Linear Regulator
Normal Operation Min Typ Max Unit
Input voltage 0.65 -1.35 V
Output voltage 0.65 -1.20 V
Important Note:
This regulator is only for CSR internal use. Section 8 shows CSR's recommended circuit connection.
9.3.3 Digital Terminals
Input Voltage Levels Min Typ Max Unit
V
IL
input logic level low -0.4 -0.3 x
VDD_PADS V
V
IH
input logic level high 0.7 x
VDD_PADS -VDD_PADS +
0.4 V
T
r
/T
f
- - 25 ns
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Output Voltage Levels Min Typ Max Unit
V
OL
output logic level low, l
OL
= 4.0mA - - 0.4 V
V
OH
output logic level high, l
OH
= -4.0mA 0.75 x
VDD_PADS - - V
T
r
/T
f
- - 5 ns
Input, Output and Tristate Currents
(a)
Min Typ Max Unit
I
OL
output current low, V
OL
max - 8 10 mA
I
OH
output current high, V
OH
min - 8 10 mA
With strong pull-up -150 -40 -10 μA
I²C with strong pull-up -250 - - μA
With strong pull-down 10 40 150 μA
With weak pull-up -5.0 -1.0 -0.33 μA
With weak pull-down 0.33 1.0 5.0 μA
C
I
input capacitance 1.0 -5.0 pF
(a)
Maximum current draw from VDD_PADS is less than 30mA depending on board design.
9.3.4 AIO
Input/Output Voltage Levels Min Typ Max Unit
Input voltage 0 - VDD_AUX V
Output voltage 0 - VDD_AUX V
Output drive strength - 4 - mA
9.3.4.1 Auxiliary ADC
Auxiliary ADC Min Typ Max Unit
Resolution - - 10 Bits
Input voltage range
(a)
0 - VDD_AUX V
Accuracy
INL -3 - 3 LSB
DNL -3 - 3 LSB
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Auxiliary ADC Min Typ Max Unit
Offset -1 - 1 LSB
Gain error -0.8 -0.8 %
Input bandwidth -100 -kHz
Conversion time (measured at application) -46 -µs
Sample rate
(b)
- - 21000 Samples/s
ADC block conversion current -410 -µA
(a)
LSB size = VDD_AUX/1023
(b)
The auxiliary ADC is accessed through the firmware API. The sample rate given is achieved as part of this function.
9.3.4.2 Auxiliary DAC
Auxiliary DAC Min Typ Max Unit
Resolution - - 10 Bits
Supply voltage, VDD_ANA 1.30 1.35 1.40 V
Output voltage range 0 - VDD_AUX V
Full-scale output voltage 1.30 1.35 1.40 V
LSB size 01.32 2.64 mV
Offset -1.32 01.32 mV
Integral non-linearity -3 0 3 LSB
Settling time - - 250 ns
Important Note:
Access to the auxiliary DAC is firmware-dependent, for more information about its availability contact CSR.
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9.4 Junction Temperature
Table 9.1 lists the junction temperature when the device is operating within recommended operating conditions.
Parameter Min Typ Max Unit
Junction temperature - - 125 °C
Table 9.1: Junction Temperature within Recommended Operating Conditions
9.5 ESD Protection
Apply ESD static handling precautions during manufacturing.
Table 9.2 shows the ESD handling maximum ratings.
Condition Class Max Rating
Human Body Model Contact Discharge per JEDEC EIA/JESD22-A114 22000V (all pins)
Charged Device Model Contact Discharge per JEDEC EIA/JESD22-C101III 500V (all pins)
Table 9.2: ESD Handling Ratings
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10 Current Consumption
Table 10.1 shows CSR1012 QFN total typical current consumption measured at the battery.
Mode Description Total Typical Current at 3.0V
Dormant All functions are shut down. To wake them up, toggle
the WAKE pin. <900nA
Hibernate VDD_PADS = OFF, REFCLK = OFF, SLEEPCLK =
ON, VDD_BAT = ON <1.9µA
Deep sleep
VDD_PADS = ON, REFCLK = OFF, SLEEPCLK =
ON, VDD_BAT = ON, RAM = ON, digital circuits = ON,
SMPS = ON (low-power mode), 2.2ms wake-up time
<5μA
Idle
VDD_PADS = ON, REFCLK = ON, SLEEPCLK = ON,
VDD_BAT = ON, RAM = ON, digital circuits = ON,
MCU = IDLE, <1μs wake-up time
~1mA
RX active -~20mA @ 3.0V peak current
TX active -~18mA @ 3.0V peak current
Table 10.1: Current Consumption
Note:
Current consumption measurements were made:
At 20°C and with 3.0V VBAT.
For the whole chip: including radio, microcontroller and necessary peripherals.
Using SDK 2.4.3.
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11 CSR Green Semiconductor Products and RoHS Compliance
CSR confirms that CSR Green semiconductor products comply with the following regulatory requirements:
Restriction of Hazardous Substances directive guidelines in the EU RoHS Directive 2011/65/EU
1
.
EU REACH, Regulation (EC) No 1907/2006
1
:
List of substances subject to authorisation (Annex XIV)
Restrictions on the manufacture, placing on the market and use of certain dangerous substances,
preparations and articles (Annex XVII). This Annex now includes requirements that were contained within
EU Directive, 76/769/EEC. There are many substance restrictions within this Annex, including, but not
limited to, the control of use of Perfluorooctane sulfonates (PFOS).
When requested by customers, notification of substances identified on the Candidate List as Substances
of Very High Concern (SVHC)
1
.
POP regulation (EC) No 850/2004
1
EU Packaging and Packaging Waste, Directive 94/62/EC
1
Montreal Protocol on substances that deplete the ozone layer.
Conflict minerals, Section 1502, Dodd-Frank Wall Street Reform and Consumer Protection act, which affects
columbite-tantalite (coltan / tantalum), cassiterite (tin), gold, wolframite (tungsten) or their derivatives. CSR is
a fabless semiconductor company: all manufacturing is performed by key suppliers. CSR have mandated that
the suppliers shall not use materials that are sourced from "conflict zone mines" but understand that this
requires accurate data from the EICC programme. CSR shall provide a complete EICC / GeSI template upon
request.
CSR has defined the "CSR Green" standard based on current regulatory and customer requirements including free
from bromine, chlorine and antimony trioxide.
Products and shipment packaging are marked and labelled with applicable environmental marking symbols in
accordance with relevant regulatory requirements.
This identifies the main environmental compliance regulatory restrictions CSR specify. For more information on the full
"CSR Green" standard, contact product.compliance@csr.com.
1
Including applicable amendments to EU law which are published in the EU Official Journal, or SVHC
Candidate List updates published by the European Chemicals Agency (ECHA).
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12 CSR1012 QFN Software Stack
CSR1012 QFN is supplied with Bluetooth v4.1 specification compliant stack firmware. Figure 12.1 shows that the
CSR1012 QFN software architecture enables the Bluetooth processing and the application program to run on the
internal RISC MCU.
G-TW-0005570.2.2
Peripherals and
Power Control
Generic Attribute
Profile (GATT)
Application
Security
Manager (SM)
Attribute Profile
(ATT)
L2CAP
Link Layer Control
Radio Control
Physical Layer
Figure 12.1: Software Architecture
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13 Tape and Reel Information
For tape and reel packing and labelling see
IC Packing and Labelling Specification
.
13.1 Tape Orientation
Figure 13.1 shows the CSR1012 QFN packing tape orientation.
G-TW-0013430.1.2
User Direction of Feed
Pin A1 Marker
Figure 13.1: Tape Orientation
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13.2 Tape Dimensions
Figure 13.2 shows the dimensions of the tape for the CSR1012 QFN.
G-TW-0011237.1.2
0.25±0.05
P
2
2.0±0.1
See Note 1
P
0
4.0±0.1
See Note 2
E
1
1.75±0.1
D
0
Ø1.55±0.05
B
0
K
0
D
1
Ø1.5MIN
SECTION Y-Y
SECTION X-X DETAIL 'A'
Y
YA
0
XX
'A' 5.50±0.1
See Note 3
8.00±0.1
12.00±0.3
REF 0.2
REF 0.8
REF 0.8
REF 0.2
REF
R0.3
Figure 13.2: Tape Dimensions
A
0
B
0
K
0
Unit Notes
4.25 ±0.1 4.25 ±0.1 0.75 ±0.1 mm
1. Measured from centreline of sprocket hole to
centreline of pocket.
2. 10 sprocket hole pitch cumulative tolerance ±0.2
3. Measured from centreline of sprocket hole to
centreline of pocket.
4. Other material available.
5. Typical SR of form tape Max 10
9
ohm/sq.
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13.3 Reel Information
G-TW-0002797.5.2
102.0
2.0
330.0
2.0
W1
(MEASURED AT HUB)
(MEASURED AT HUB)
"A"
ATTENTION
Electrostatic Sensitive Devices
Safe Handling Required
W2
20.2
MIN
2.0 0.5
13.0
+0.5
-0.2
Detail "A"
Detail "B"
6
PS
PS
6
a
(rim height)
88 REF
"b" REF
Figure 13.3: Reel Dimensions
Package Type Nominal Hub Width
(Tape Width) a b W1 W2 Max Units
4 x 4 x 0.65mm
QFN 12 1.5
(+0.0/-1.5)
96.5
(+3.5/-0.0)
12.4
(+2.0/-0.0) 18.4 mm
13.4 Moisture Sensitivity Level
CSR1012 QFN is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.
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14 Document References
Document Reference, Date
Core Specification of the Bluetooth System.
Bluetooth Specification Version 4.1, 03 December 2013
CSR1012 Hardware Design Review Template.
CS-305810-DD
CSR1012 QFN Performance Specification.
CS-300888-SP
CSR1012 QFN 4.3V Operation Performance
Specification.
CS-305809-SP
Customer Advisory: Use of CSR101x at Operating
Voltages Above 3.6V
CS-306155-AN
Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
JESD22-A114
Environmental Compliance Statement for CSR Green
Semiconductor Products.
CB-001036-ST
IC Packing and Labelling Specification.
CS-112584-SP
Moisture / Reflow Sensitivity Classification for
Nonhermitic Solid State Surface Mount Devices.
IPC / JEDEC J-STD-020
Typical Solder Reflow Profile for Lead-free Devices.
CS-116434-AN
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Terms and Definitions
Term Definition
AC Alternating Current
ADC Analogue to Digital Converter
AGC Automatic Gain Control
AIO Analogue Input/Output
ATT ATTribute protocol
balun balanced/unbalanced interface or device that changes a balanced output to an unbalanced input
or vice versa
Bluetooth
®
Set of technologies providing audio and data transfer over short-range radio connections
CSR Cambridge Silicon Radio
dBm Decibels relative to 1 mW
DC Direct Current
DNL Differential Non Linearity (ADC accuracy parameter)
e.g.
exempli gratia
, for example
EDR Enhanced Data Rate
EEPROM Electrically Erasable Programmable Read Only Memory
EIA Electronic Industries Alliance
ESD Electrostatic Discharge
ESR Equivalent Series Resistance
GAP Generic Access Profile
GATT Generic ATTribute protocol
GSM Global System for Mobile communications
HID Human Interface Device
I²C Inter-Integrated Circuit Interface
I/O Input/Output
IC Integrated Circuit
IF Intermediate Frequency
INL Integral Non-Linearity (ADC accuracy parameter)
IPC See www.ipc.org
IQ In-Phase and Quadrature
JEDEC Joint Electron Device Engineering Council (now the JEDEC Solid State Technology Association)
KB Kilobyte
L2CAP Logical Link Control and Adaptation Protocol
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Term Definition
LC An inductor (L) and capacitor (C) network
LED Light-Emitting Diode
LNA Low Noise Amplifier
LSB Least Significant Bit (or Byte)
MAC Medium Access Control
MCU MicroController Unit
MISO Master In Slave Out
MLC MultiLayer Ceramic
MOSI Master Out Slave In
NSMD Non-Solder Mask Defined
PA Power Amplifier
PC Personal Computer
PCB Printed Circuit Board
PD Pull-Down
PIO Parallel Input/Output
PIO Programmable Input/Output, also known as general purpose I/O
plc public limited company
ppm parts per million
PU Pull-Up
PWM Pulse Width Modulation
QFN Quad-Flat No-lead
RAM Random Access Memory
RF Radio Frequency
RISC Reduced Instruction Set Computer
RoHS Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive (2002/95/
EC)
ROM Read Only Memory
RSSI Received Signal Strength Indication
RX Receive or Receiver
SIG (Bluetooth) Special Interest Group
SMP Security Manager Protocol
SMPS Switch-Mode Power Supply
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Term Definition
SPI Serial Peripheral Interface
TCXO Temperature Compensated crystal Oscillator
TX Transmit or Transmitter
UART Universal Asynchronous Receiver Transmitter
VCO Voltage Controlled Oscillator
W-CDMA Wideband Code Division Multiple Access
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