TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 Dual-Output or Two-Phase Synchronous Buck Controller with PMBus Check for Samples: TPS40422 FEATURES APPLICATIONS * * * * * * * 1 * * * * * * * * * * * * * * Single Supply Operation: 4.5 V to 20 V Output Voltage from 0.6 V to 5.6 V Dual or Two-Phase Synchronous Buck Controller PMBus Capability - Margining Up/Down with 2-mV Step - Programmable Fault Limit and Response - Output Voltage, Output Current Monitoring - External Temperature Monitoring with 2N3904 - Programmable UVLO ON/OFF Thresholds - Programmable Soft Start Time and Turn On/Off Delay On-Chip Non-volatile Memory (NVM) to Store Custom Configurations 180 Out-of-Phase to Reduce Input Ripple 600-mV Reference Voltage with 0.5% Accuracy from 0C to 85C Inductor DCR Current Sensing Programmable Switching Frequency from 200 kHz to 1 MHz Voltage Mode Control with Input Feed Forward Current Sharing for Multiphase Operation Supports Pre-biased Output Differential Remote Sensing External SYNC BPEXT Pin Boosts Efficiency by Supporting External Bias Power OC/OV/UV/OT Fault Protection 40-Pin, 6 mm x 6 mm, QFN Package Multiple Rail Systems Telecom Base Station Switcher/Router Networking Server and Storage System DESCRIPTION The TPS40422 is a dual-output PMBus synchronous buck controller. It can be configured also for a single, two-phase output. Its wide input range can support 5-V and 12-V intermediate buses. The accurate reference voltage satisfies the need of precision voltage to the modern ASICs and potentially reduces the output capacitance. Voltage mode control is implemented to reduce noise sensitivity and also ensures low duty ratio conversion. Using the PMBus protocol, the TPS40422 margining function, reference voltage, fault limit, UVLO threshold, soft start time and turn on/off delay can be programmed. In addition, an accurate measurement system is implemented to monitor the output voltages, currents and temperatures for each channel. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011-2012, Texas Instruments Incorporated TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com SIMPLIFIED APPLICATION VIN 31 CLK DATA SMBALRT SYNC PG1 CNTL1 VDD 12 CLK BP3 32 11 DATA ADDR1 13 SMBALRT ADDR0 10 40 SYNC RT 33 PG1 4 9 1 PG2 PG2 19 CNTL1 CNTL2 CNTL2 5 29 HDRV1 HDRV2 21 30 BOOT1 BOOT2 20 VOUT1 28 SW1 SW2 22 27 LDRV1 VOUT2 LDRV2 23 TPS40422 26 PGND 34 CS1P CS2P 18 35 CS1N CS2N 17 37 VSNS1 VSNS2 15 38 GSNS1 39 DIFFO1 2 3 FB2 8 COMP2 7 FB1 COMP1 GSNS2 14 TSNS1 AGND BPEXT 36 6 24 BP6 TSNS2 25 16 UDG-11278 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) (1) (2) 2 TEMPERATUREE RANGE PACKAGE PINS -40C to 125C QFN 40 OUTPUT SUPPLY MINIMUM QUANTITY ORDERABLE DEVICE NUMBER Tape and Reel 3000 TPS40422RHAR Tube 250 TPS40422RHAT For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) over operating free-air temperature range (unless otherwise noted) Input voltage range (2) Output voltage range (3) Electrostatic discharge MIN MAX VDD -0.3 20 BOOT1 , BOOT2, HDRV1, HDRV2 -0.3 30 BOOT1 - SW1, BOOT2 - SW2 -0.3 7 CLK, DATA, CNTL1, CNTL2, SYNC -0.3 3.6 FB1, FB2, VSNS1, VSNS2, BPEXT -0.3 7 LDRV1, LDRV2, BP6 -0.3 7 -1 30 COMP1, COMP2, DIFFO1, SMBALRT, PG1, PG2, TSNS1, TSNS2 -0.3 7 ADDR0, ADDR1, BP3, RT -0.3 3.6 Human body model (HBM) 2 SW1, SW2 Charged device model (CDM) UNITS V V kV 1.5 Storage junction temperature, TJ -40 150 C Operating junction temperature, Tstg -55 155 C (1) (2) (3) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to the network ground terminal unless otherwise noted. Voltage values are with respect to the SW terminal. RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT VDD Input operating voltage 4.5 20 V TJ Operating junction temperature -40 125 C Electrostatic discharge (ESD) ratings Human Body Model (HBM) 2000 Charge Device Model (CDM) 1500 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 V 3 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS (1) TJ = -40C to 125C, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT INPUT SUPPLY VVDD Input supply voltage range IVDD Input operating current 4.5 20 Switching, no driver load 18 25 Not switching 15 20 V mA UVLO VIN(on) Input turn on voltage (2) Default settings 4.25 VIN(off) Input turn off voltage (2) Default settings 4 VINON(rng) Programmable range for turn on voltage 4.25 16 V VINOFF(rng) Programmable range for turn off voltage 4 15.75 V -5% 5% VINONOFF(acc) Turn on and turn off voltage accuracy (1) 4.5 V VVDD 20 V, all VIN_ON and VIN_OFF settings V V ERROR AMPLIFIER 0C TJ 85C 597 600 603 -40C TJ 125C 594 600 606 VFB Feedback pin voltage AOL Open-loop gain (3) GBWP Gain bandwidth product (3) IFB FB pin bias current (out of pin) VFB = 0.6 V Sourcing VFB = 0 V 1 3 Sinking VFB = 1 V 3 9 6.2 6.5 6.8 V 70 120 mV ICOMP 80 mV dB 24 MHz 50 nA mA BP6 REGULATOR Output voltage IBP6 = 10 mA Dropout voltage VVIN - VBP6, VVDD = 4.5 V, IBP6 = 25 mA IBP6 Output current VVDD = 12 V VBP6UV Regulator UVLO voltage (3) 3.3 3.55 3.8 V VBP6UV(hyst) Regulator UVLO voltage hysteresis (3) 230 255 270 mV 4.6 200 mV 100 mV 0.7 1.0 V 3.3 3.5 V VBP6 120 mA BPEXT VBPEXT(swover) BPEXT switch-over voltage 4.5 Vhys(swover) BPEXT switch-over hysteresis 100 VBPEXT(do) BPEXT dropout voltage VBPEXT-VBP6, VBPEXT = 4.8 V, IBP6 = 25 mA Bootstrap voltage drop IBOOT = 5 mA V BOOTSTRAP VBOOT(drop) BP3 REGULATOR VBP3 Output voltage VVDD = 4.5 V, IBP3 5 mA 3.1 OSCILLATOR Adjustment range fSW Switching frequency VRMP Ramp peak-to-peak (3) VVLY Valley voltage (3) (1) (2) (3) 4 100 RRT = 40 k 450 500 1000 kHz 550 kHz VVDD/8.2 0.7 0.8 V 1.0 V Thresholds selected by entering high side parameters for PGOOD_ON and PGOOD_OFF. Cannot select same threshold for PGOOD_ON & PGOOD_OFF. By design, hysteresis of at least 150 mV is specified. Specified by design. Not production tested. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS(1) (continued) TJ = -40C to 125C, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYNCHRONIZATION VSYNCH SYNC high level threshold VSYNCL SYNC low level threshold 2.0 0.8 V V tSYNC Minimum SYNC pulse width 100 ns fSYNC(max) Maximum SYNC frequency (4) fSYNC(min) Minimum SYNC frequency (4) 2000 kHz 200 SYNC frequency range (increase from nominal oscillator frequency) -20% 20% PWM tOFF(min) Minimum off time tON(min) Minimum pulse (5) tDEAD Output driver dead time 90 100 ns 90 130 HDRV off to LDRV on 15 25 30 LDRV off to HDRV on 25 35 45 2.4 2.7 ns ns SOFT START Soft-start time Factory default settings Accuracy over range (5) 600 s tSS 9 ms tON(delay) Turn-on delay time (6) Factory default settings 0 ms tOFF(delay) Turn-off delay time Factory default settings 0 ms tSS -15% 3.0 ms 15% REMOTE SENSE AMPLIFIER VDIFFO(err) Error voltage from DIFFO1 to (VSNS1- GSNS1) BW Closed-loop bandwidth (5) VDIFFO(max) Maximum DIFFOx output voltage IDIFFO (VSNS1- GSNS1) = 0.6 V -5 (VSNS1- GSNS1) = 1.2 V -8 5 8 (VSNS1- GSNS1) = 3.0 V -17 17 2 MHz VBP6-0.2 Sourcing 1 Sinking 1 mV V mA DRIVERS RHS(up) High-side driver pull-up resistance (VBOOT-VSW) = 6.5 V, IHS = -40 mA 0.8 1.5 2.5 RHS(dn) High-side driver pull-down resistance (VBOOT-VSW) = 6.5 V, IHS = 40 mA 0.5 1.0 1.5 RLS(up) Low-side driver pull-up resistance ILS = -40 mA 0.8 1.5 2.5 RLS(dn) Low-side driver pull-down resistance ILS = 40 mA 0.35 0.70 1.40 (5) tHS(rise) High-side driver rise time CLOAD = 5 nF 15 tHS(fall) High-side driver fall time (5) CLOAD = 5 nF 12 tLS(rise) Low-side driver rise time (5) CLOAD = 5 nF 15 tLS(fall) Low-side driver fall time CLOAD = 5 nF 10 (5) ns CURRENT SENSING AMPLIFIER VCS(rng) Differential input voltage range VCS(cmr) Input common-mode range VCS(os) Input offset voltage ACS Current sensing gain VCS(out) Amplfier output fC0 Closed-loop bandwidth (5) VCS(chch) (4) (5) (6) VCSxP-VCSxN VCSxP = VCSxN = 0 V -60 60 0 VBP6-0.2 -3 3 15.00 (VCSxP-VCSxN) = 20 mV Amplifier output difference between CH1, CH2 270 300 3 5 mV V mV V/V 330 mV MHz (VCS1P- VCS1N) = (VCS2P-VCS2N) = 20 mV, TJ = 25C -5.00% 5.00% (VCS1P- VCS1N) = (VCS2P-VCS2N) = 20 mV, TJ = 85C -6.67% 6.67% When using SYNC, the switching frequency is set to one-half the SYNC frequency. Specified by design. Not production tested. The minimum turn-on delay is 50 s, when TON_DELAY is set to a factor of zero. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 5 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com ELECTRICAL CHARACTERISTICS(1) (continued) TJ = -40C to 125C, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CURRENT LIMIT tOFF(oc) Off-time between restart attempts DCR Inductor DCR current sensing calibration value IOC(flt) Output current overcurrent fault threshold IOC(warn) Output current overcurrent warning threshold IOC(tc) Output current fault/warning temperature coefficient (7) IOC(acc) Hiccup mode 7xtSS Factory default settings 0.488 Programmable range 0.240 Factory default settings Programmable range 15.500 30 3 Factory default settings Programmable range ms 50 27 2 3900 49 4000 -15% 4100 m A A ppm/C Output warning and fault accuracy (VCSxP-VCSxN) = 30 mV 15% VFBPGH FB PGOOD high threshold Factory default settings 675 mV VFBPGL FB PGOOD low threshold Factory default settings 525 mV VPG(acc) PGOOD accuracy over range 4.5 V VVDD 20 V, 468 mV VPGOOD 675 mV Vpg(hyst) FB PGOOD hysteresis voltage RPGOOD PGOOD pulldown resistance VFB = 0, IPGOOD = 5 mA IPGOOD(lk) PGOOD pin leakage current No fault, VPGOOD = 5 V (8) PGOOD -4% 4% 25 40 40 70 mV 20 A OUTPUT OVERVOLTAGE/UNDERVOLTAGE VFBOV FB pin over voltage threshold Factory default settings 700 VFBUV FB pin under voltage threshold Factory default settings 500 VUVOV(acc) FB UV/OV accuracy over range 4.5 V VVDD 20 V -4% mV mV 4% OUTPUT VOLTAGE TRIMMING AND MARGINING VFBTM(step) Resolution of FB steps with trim and margin tFBTM(step) Transition time per trim or margin step VFBTM(max) 2 After soft-start time mV 30 s Maximum FB voltage with trim and/or margin 660 mV Minimum FB voltage with trim or margin only 480 VFBTM(min) Minimum FB voltage range with trim and margin combined 420 VFBMH Margin high FB pin voltage Factory default settings 660 mV VFBML Margin low FB pin voltage Factory default settings 540 mV mV TEMPERATURE SENSE AND THERMAL SHUTDOWN TSD Junction shutdown temperature (7) 135 145 155 C THYST Thermal shutdown hysteresis (7) 15 20 25 C ITSNS(ratio) Ratio of bias current flowing out of TSNS pin, state 2 to state 1 9.7 10.0 10.3 (7) State 1 current out of TSNSx pin 10 ITSNS (7) State 2 current out of TSNSx pin 100 VTSNS Voltage range on TSNSx pin (7) TSNS(acc) External temperature sense accuracy (9) 0C TJ 125C TOT(flt) Overtemperature fault limit (7) Factory default settings ITSNS OT fault limit range (7) TOT(warn) Overtemperature warning limit (7) TOT(step) OT fault/warning step TOT(hys) OT fault/warning hysteresis (7) (7) (8) (9) 6 A 0 1.00 V -5 5 C 145 120 Factory default settings OT warning limit range (7) A C 165 125 100 C 140 5 15 20 C C C 25 C Specified by design. Not production tested. Thresholds selected by entering high side parameters for PGOOD_ON and PGOOD_OFF. Cannot select same threshold for PGOOD_ON & PGOOD_OFF. Specified by design. Not production tested. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 ELECTRICAL CHARACTERISTICS(1) (continued) TJ = -40C to 125C, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MEASUREMENT SYSTEM MVOUT(rng) Output voltage measurement range (10) MVOUT(acc) Output voltage measurement accuracy MIOUT(rng) MIOUT(acc) 0.5 5.8 -2.0% 2.0% VCSxP-VCSxN, 0.2440 m IOUT_CAL_GAIN 0.5795 m 0 36 VCSxP-VCSxN, 0.5796 m IOUT_CAL_GAIN 1.1285 m 0 60 VCSxP-VCSxN, 1.1286 m IOUT_CAL_GAIN 15.5 m 0 90 -1.0 1.0 A 11.76 A VOUT = 1.0 V Output current measurement signal range (10) IOUT 20 A, DCR = 0.5 m Output current measurement accuracy V mV PMBus ADDRESSING IADD Address pin bias current 9.24 10.50 PMBus INTERFACE VIH Input high voltage, CLK, DATA, CNTLx VIL Input low voltage, CLK, DATA, CNTLx 2.1 IIH Input high level current, CLK, DATA -10 IIL Input low level current, CLK, DATA -10 ICTNL CNTL pin pull-up current VOL Output low level voltage, DATA, IOH Output high level open drain leakage current, DATA, SMBALRT V 0.8 V 10 A 10 mA 6 (10) 4.5 V VVDD 20 V, IOUT = 4 mA A 0.8 V A VOUT = 5.5 V 0 10 1 pF Slave mode 10 400 kHz (10) COUT Pin capacitance, CLK, DATA FPMB PMBus operating frequency range (10) tBUF Bus free time between START and STOP (10) 4.7 s tHD:STA Hold time after repeated START (10) 4.0 s tSU:STA Repeated START setup time (10) 4.7 s tSU:STO STOP setup time (10) 4.0 s tHD:DAT Data hold time (10) tSU:DAT Data setup time (10) tTIMEOUT Error signal/detect (10) tLOW:MEXT tLOW:SEXT tLOW Clock low time (10) Receive mode 0 Transmit mode 300 ns 250 25 ns 35 s Cumulative clock low master extend time (10) 50 s Cumulative clock low slave extend time (10) 25 s 4.7 (10) s tHIGH Clock high time tFALL CLK/DATA fall time (10) 4.0 300 s s tRISE CLK/DATA rise time (10) 1000 s (10) Specified by design. Not production tested. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 7 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com SYNC DIFFO1 GSNS1 VSNS1 TSNS1 CS1N CS1P PG1 BP3 VDD DEVICE INFORMATION 40 39 38 37 36 35 34 33 32 31 RT 1 30 BOOT1 FB1 2 29 HDRV1 COMP1 3 28 SW1 CNTL1 4 27 LDRV1 26 PGND CNTL2 5 TPS40422 12 13 14 15 16 17 18 19 20 BOOT2 HDRV2 11 PG2 SW2 21 CS2P 22 ADDR0 10 CS2N LDRV2 TSNS2 23 ADDR1 9 VSNS2 BPEXT GSNS2 24 FB2 8 SMBALRT BP6 CLK 25 DATA AGND 6 COMP2 7 PIN DESCRIPTIONS PIN NO. I/O DESCRIPTION ADDR0 10 I Low-order address pin for PMBus address configuration. One of eight resistor values must be connected from this pin to AGND to select the low-order octal digit in the PMBus address. ADDR1 9 I High-order address pin for PMBus address configuration. One of eight resistor values must be connected from this pin to AGND to select the low-order octal digit in the PMBus address. AGND 6 -- Low-noise ground connection to the controller. Connections should be arranged so that power level currents do not flow through the AGND path. BOOT1 30 I Bootstrapped supply for the high-side FET driver for channel 1 (CH1). Connect a capacitor (100 nF typical) from BOOT1 to SW1 pin. BOOT2 20 I Bootstrapped supply for the high-side FET driver for channel 2 (CH2). Connect a capacitor (100 nF typical) from BOOT2 to SW2 pin. BP3 32 O Output bypass for the internal 3.3-V regulator. Connect a 100 nF or larger capacitor from this pin to AGND. BP6 25 O Output bypass for the internal 6.5-V regulator. Connect a low ESR, 1 F or larger ceramic capacitor from this pin to PGND. BPEXT 24 I External voltage input for BP6 switchover function. If the BPEXT function is not used, connect this pin directly to PGND. Otherwise connect a 100-nF or larger capacitor from this pin to PGND. CLK 12 I Clock input for the PMBus interface. Pull up to 3.3 V with a resistor. CNTL1 4 I Logic level input which controls startup and shutdown of CH1, determined by PMBus options. CNTL2 5 I Logic level input which controls startup and shutdown of CH2, determined by PMBus options. COMP1 3 O Output of the error amplifier for CH1 and connection node for loop feedback components. COMP2 7 O Output of the error amplifier for CH2 and connection node for loop feedback components. For two-phase operation, use COMP1 for loop feedback and connect COMP1 to COMP2. CS1N 35 I Negative terminal of current sense amplifier for CH1. CS2N 17 I Negative terminal of current sense amplifier for CH2. CS1P 34 I Positive terminal of current sense amplifier for CH1. CS2P 18 I Positive terminal of current sense amplifier for CH2. DATA 11 I/O Data input/output for the PMBus interface. Pull up to 3.3 V with a resistor. DIFFO1 39 O Output of the differential remote sense amplifier for CH1. 8 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 PIN DESCRIPTIONS (continued) PIN NO. I/O DESCRIPTION FB1 2 I Inverting input of the error amplifier for CH1. Connect a voltage divider to FB1 between DIFFO1 and AGND to program the output voltage for CH1. FB2 8 I Inverting input of the error amplifier for CH2. Connect a voltage divider to FB2 between VSNS2 and GSNS2 to program the output voltage for CH2. For two-phase operation, use FB1 to program the output voltage and connect FB2 to BP6 before applying voltage to VDD. GSNS1 38 I Negative terminal of the differential remote sense amplifier for CH1. GSNS2 14 I Negative terminal of the differential remote sense amplifier for CH2. HDRV1 29 O Bootstrapped gate drive output for the high-side N-channel MOSFET for CH1. HDRV2 21 O Bootstrapped gate drive output for the high-side N-channel MOSFET for CH2. LDRV1 27 O Gate drive output for the low side synchronous rectifier N-channel MOSFET for CH1. LDRV2 23 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET for CH2. PGND 26 -- Power GND. PG1 33 O Open drain power good indicator for CH1 output voltage. PG2 19 O Open drain power good indicator for CH2 output voltage. RT 1 I Frequency programming pin. Connect a resistor from this pin to AGND to set the oscillator frequency. SMBALRT 13 O Alert output for the PMBus interface. Pull up to 3.3 V with a resistor. SW1 28 I Return of the high-side gate driver for CH1. Connect to the switched node for CH1. SW2 22 I Return of the high-side gate driver for CH2. Connect to the switched node for CH2. SYNC 40 I Logic level input for external clock synchronization. When an external clock is applied to this pin, the oscillator frequency sychronizes to one half of its frequency. When an external clock is not used, tie this pin to AGND. TSNS1 36 I External temperature sense input for CH1. TSNS2 16 I External temperature sense input for CH2. VDD 31 I Power input to the controller. Connect a low ESR, 100 nF or larger ceramic capacitor from this pin to AGND. VSNS1 37 I Positive terminal of the differential remote sense amplifier for CH1. VSNS2 15 I Positive terminal of the differential remote sense amplifier for CH2. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 9 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com EN1 EN2 VDD BP Regulators ADDR0 ADDR1 SMBALRT DATA CLK CNTL2 BP3 CNTL1 FUNCTIONAL BLOCK DIAGRAM PMBus Interface Non-Volatile Logic Memory and Processing EN, SS and VREF VREF BOOT1 BP6 BOOT2 BPEXT Bypass SW and Logic RT SYNC Fault and Warning Limits Measurement System MUX and ADC TSNS2 TSNS1 DIFFO1 DIFFO2 VDD CS1P CS1N CS2P CS2N BOOT1 Oscillator RAMP1 RAMP2 HDRV1 BP6 CS1P LDRV1 CS1 + PGND CS1N VREF Anti-Cross Conduction and PWM Latch Logic RAMP1 + + FB1 - + Current Share COMP1 VREF + + RAMP2 COMP2 BOOT2 HDRV2 SW2 - FB2 CS2P SW1 + BP6 LDRV2 + CS2 EN1 EN2 PGND CS2N VSNS1 OC TSNS2 FB1 OV OC/UV/OV/OT Detection FB2 + DIFFO2 GSNS2 TSNS1 UV TSNS1 + GSNS1 VSNS2 OT Fault and Warning Limits DIFFO1 CS1 CS2 TSNS2 PG1 PG2 AGND UDG-11216 10 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 4.8 601.0 4.7 600.5 Reference Voltage (mV) BPEXT Voltage (V) TYPICAL CHARACTERISTICS 4.6 4.5 4.4 4.3 4.2 -40 -25 -10 95 599.5 599.0 598.0 -40 -25 -10 110 125 G000 Figure 1. BPEXT Voltage vs. Junction Temperature Low-Side Driver Resistance () High-Side Driver Resistance () 95 110 125 G001 1.6 1.60 1.40 1.20 1.00 0.80 RHDHI RHDLO 5 20 35 50 65 80 Junction Temperature (C) 95 1.4 1.2 1 0.8 0.6 RLDHI RLDLO 0.4 -40 -25 -10 110 125 G002 Figure 3. High-Side Driver Resistance vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (C) 95 110 125 G003 Figure 4. Low-Side Driver Resistance vs. Junction Temperature 16.0 540 15.5 Switching Frequency (kHz) Non-Switching Quiescent Current (mA) 5 20 35 50 65 80 Junction Temperature (C) Figure 2. Reference Voltage vs. Junction Temperature 1.80 0.60 -40 -25 -10 VDD = 12 V VDD = 20 V VDD = 4.5 V 598.5 Switch-Over Enabled Switch-Over Disabled 5 20 35 50 65 80 Junction Temperature (C) 600.0 15.0 14.5 14.0 13.5 13.0 VDD = 12 V VDD = 20 V VDD = 4.5 V 12.5 12.0 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 530 520 510 VDD = 12 V VDD = 20 V 110 125 500 -40 -25 -10 G004 Figure 5. Non-Switching Quiescent Current vs. Junction Temperature 5 20 35 50 65 80 Junction Temperature (C) RT = 40 k 95 110 125 G005 Figure 6. Switching Frequency vs. Junction Temperature Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 11 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) 116 40 HDRV Minimum Off-Time (ns) 38 Dead Time (ns) 36 34 32 30 28 26 24 HDRV off to LDRV on LDRV off to HDRV on 22 20 -40 -25 -10 5 20 35 50 65 80 Junction Temperature (C) 95 110 125 112 110 108 106 104 -40 -25 -10 G006 Figure 7. Dead Time vs. Junction Temperature 12 114 5 20 35 50 65 80 Junction Temperature (C) 95 110 125 G007 Figure 8. HDRV Minimum Off-Time vs. Junction Temperature Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 APPLICATION INFORMATION General Description/Control Architecture The TPS40422 is a flexible synchronous buck controller. It can be used as a dual-output controller, or as a twophase single-output controller. It operates with a wide input range from 4.5 V to 20 V and generates accurate regulated output as low as 600 mV. In dual output mode, voltage mode control with input feed-forward architecture is implemented. With this architecture, the benefits are less noise sensitivity, no control instability issues for small DCR applications, and a smaller minimum controllable on-time, often desired for high conversion ratio applications. In two-phase single-output mode, a current-sharing loop is implemented to ensure a balance of current between phases. Because the induced error current signal to the loop is much smaller when compared to the PWM ramp amplitude, the control loop is modeled as voltage mode with input feed-forward. DESIGN NOTE To operate the device in two-phase mode, tie the FB2 pin to the BP6 pin and tie the COMP1 pin to the COMP2 pin. These connections must be made before applying voltage to the VDD pin. PMBus General Description Timing and electrical characteristics of the PMBus can be found in the PMB Power Management Protocol Specification, Part 1, revision 1.1 available at http://pmbus.org. The TPS40422 supports both the 100 kHz and 400 kHz bus timing requirements. The TPS40422 does not stretch pulses on the PMBus when communicating with the master device. Communication over the TPS40422 device PMBus interface can either support the Packet Error Checking (PEC) scheme or not. If the master supplies CLK pulses for the PEC byte, it is used. If the CLK pulses are not present before a STOP, the PEC is not used. The TPS40422 supports a subset of the commands in the PMBus 1.1 specification. Most all of the controller parameters can be programmed using the PMBus and stored as defaults for later use. All commands that require data input or output use the literal format. The exponent of the data words is fixed at a reasonable value for the command and altering the exponent is not supported. Direct format data input or output is not supported by the TPS40422. See the SUPPORTED COMMANDS section for specific details. The TPS40422 also supports the SMBALERT response protocol. The SMBALERT response protocol is a mechanism by which a slave (the TPS40422) can alert the bus master that it wants to talk. The master processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the alert response address. Only the slave that caused the alert acknowledges this request. The host performs a modified receive byte operation to get the slave's address. At this point, the master can use the PMBus status commands to query the slave that caused the alert. For more information on the SMBus alert response protocol, see the System Management Bus (SMBus) specification. The TPS40422 contains non-volatile memory that is used to store configuration settings and scale factors. The settings programmed into the device are not automatically saved into this non-volatile memory though. The STORE_USER_ALL command must be used to commit the current settings to non-volatile memory as device defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed descriptions. Voltage Reference The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final regulation voltage. The 0.5-% tolerance on the reference voltage allows the user to design a very accurate power supply. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 13 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com Output Voltage The output voltage is set in a very similar to the way to a traditional analog controller using a voltage divider from the output to the feedback (FB) pin. The output voltage must be divided down to the nominal reference voltage of 600mV. Figure 9 shows the typical connections for the controller. The voltage at the load can be sensed using the unity gain differential voltage sense amplifier. This provides better load regulation for output voltages lower than 5V nominal (see electrical specifications for the maximum output voltage of the differential sense amplifier). For output voltages above this level, connect the output voltage directly to the junction of R1 and C1, leave DIFFO1 open and do not connect the VSNS1 pin to the output voltage. If desired the differential amplifier may also be used elsewhere in the overall system as a voltage buffer, provided the electrical specifications are not exceeded. VSNS1 DIFFO1 + To load supply connections X1 C1 R1 GSNS1 C3 R3 R4 C2 COMP1 FB1 R2 UDG-11245 Figure 9. Setting the Output Voltage The components in Figure 9 that determine the nominal output voltage are R1 and R2. R1 is normally chosen to make the feedback compensation values (R3, R4, C1, C2 andC3) come close to readily available standard values. R2 is then calculated in Equation 1. ae o R1 R2 = VFB c / c (VOUT - VFB ) / e o where * * * VFB is the feedback voltage VOUT is the desired output voltage R1 and R2 are in the same units (1) DESIGN NOTE There is no DIFFO2 pin. In dual-output mode, VSNS2 and GSNS2 are connected to the load for channel 2 and the DIFFO2 signal is used internally for voltage monitoring. Connect the output directly to the junction of R1 and C1 for channel 2 to set the output voltage and for feedback. The feedback voltage can be changed -30% to +10% from the nominal 600 mV using PMBus commands. This allows the output voltage to vary by the same percentage. See the PMBus Functionality section for further details. 14 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 Voltage Feed Forward The TPS40422 uses input voltage feed forward that maintains a constant power stage gain as input voltage varies and provides for very good response to input voltage transient disturbances. The simple constant power stage gain of the controller greatly simplifies feedback loop design because loop characteristics remains constant as the input voltage changes, unlike a buck converter without voltage feed forward. For modeling purposes, the gain from the COMP pin to the average voltage at the input of the L-C filter is 8.2 V/V. Current Sensing The TPS40422 uses a differential current sense scheme to sense the output current. The sense element can be either the series resistance of the power stage filter inductor or a separate current sense resistor. When using the inductor series resistance as in Figure 10, a filter must be used to remove the large AC component of voltage across the inductor and leave only the component of the voltage that appears across the resistance of the inductor. The values of R5 and C4 for the ideal case can be found by Equation 2. The time constant of the R-C filter should be equal to or greater than the time constant of the inductor itself. If the time constants are equal, the voltage appearing across C4 is be the current in the inductor multiplied the inductor resistance. The inductor ripple current is reflected in the voltage across C4 perfectly in this case and there is no reason to have a shorter R-C time constant. The time constant of the R-C filter can be made longer than the inductor time constant because this is a voltage mode controller and the current sensing is done for overcurrent detection and output current reporting only. Extending the R-C filter time constant beyond the inductor time constant lowers the AC ripple component of voltage present at the current sense pins of the TPS40422 but allows the correct DC current information to remain intact. This also delays slightly the response to an overcurrent event, but reduces noise in the system leading to cleaner overcurrent performance and current reporting data over the PMBus ae L o R5 C4 c / e RDCR o where (from Figure 10) * * * R5 and RESR are in C4 is in F (suggest 100 nF, 10-7F) L is in H (2) The maximum voltage that the TPS40422 is designed to accept across the curent sense pins is 60 mV. Because most all inductors have a copper conductor and because copper has a fairly large temperature coefficient of resistance, the resistance of the inductor and the current through the inductor should make a DC voltage less than 60 mV when the inductor is at the maximum temperature for the converter. This also applies for the external resistor in Figure 11. The full load output current multiplied by the sense resistor value, must be less that 60 mV at the maximum converter operating temperature. In all cases, C4 should be placed as close to the current sense pins as possible to help avoid problems with noise. VIN VIN L R DCR L R5 R ISNS C4 To load To load CSxP CSxP CSxN CSxN UDG-11246 Figure 10. Current Sensing Using Inductor Resistance UDG-11247 Figure 11. Current Sensing Using Sense Resistor Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 15 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com After choosing the current sensing method, set the current sense element resistance. This value allows the proper calculation of thresholds for the overcurrent fault and warning, as well as more accurate reporting of the actual output current. The IOUT_CAL_GAIN command is used to set the value of the sense element resistence of the device. IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT set the levels for the overcurrent warning and fault levels respectively. (See the PMBus Functionality section for more details.) Overcurrent Protection The TPS40422 has overcurrent fault and warning thresholds for each channel which can be independently set, when operating in dual-output mode. When operating in two-phase mode, both channels share the same overcurrent fault and warning thresholds. The overcurrent thresholds are set over PMBus using the IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands. (See the PMBus Functionality section for more details.) The TPS40422 generates an internal voltage corresponding to the desired overcurrent threshold, using the IOUT_OC_FAULT_LIMIT threshold and the IOUT_CAL_GAIN setting, and adjusting for temperature using the measured external temperature value. The sensed current signal is amplified by the current sense amplifier with a fixed gain of 15 and then compared with this internal voltage threshold. A similar structure is used to activate an overcurrent warning based on the IOUT_OC_WARN_LIMIT threshold. IOUT L1 L DCR VOUTx SWx R1 C1 CSxP CSxN ACS=15 + + OC IOUT_OC_FAULT_LIMIT IOUT_CAL_GAIN OC Threshold Voltage TSNSx measured temperature UDG-11248 Figure 12. Overcurrent Protection The programmable range of the overcurrent fault and warning voltage thresholds places a functional limit on the input voltage of the current sense amplifier. The minimum overcurrent fault and warning thresholds correspond to a voltage from CSxP to CSxN of 6 mV and 4.7 mV, respectively. If the voltage across these pins does not exceed the minimum thresholds, then overcurrent fault and warning cannot be tripped, regardless of the setting of IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. There is also maximum overcurrent fault and warning thresholds corresponding to a voltage from CSxP to CSxN of 60 mV and 59 mV, respectively. If the voltage across these pins exceeds this maximum threshold, the overcurrent fault or warning will be tripped, regardless of the setting of IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. This means that for higher values of inductor DCR, a resistor across the current sensing capacitor may be required to create a voltage divider into the current sensing inputs. 16 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 The TPS40422 implements cycle-by-cycle current limit when the peak sensed current exceeds the set threshold. In a time constant matched current sensor network, the signal across the CSxP and CSxN pins has both dc and ac inductor current information, so overcurrent trips when the dc current plus half of the ripple current exceeds the set threshold. When the time constant is not well-matched, the dc current which trips the overcurrent changes accordingly. When the controller counts three consecutive clock cycles of an overcurrent condition, the high-side and low-side MOSFETs are turned off and the controller enters hiccup mode or latches the output off, depending on the IOUT_OC_FAULT_RESPONSE register. In continuous restart hiccup mode, after seven soft-start cycles, normal switching is attempted. If the overcurrent has cleared, normal operation resumes; otherwise, the sequence repeats. Two-Phase Mode and Current Sharing Loop The TPS40422 can be configured to operate in single-output two-phase mode for high-current applications. With proper selection of the external MOSFETs, this device can support up to 50-A of load current in a two-phase configuration. As shown in Figure 13, to configure TPS40422 as two-phase mode, FB2 is tied to BP6. In this mode, COMP1 must be connected to COMP2 to ensure current sharing between the two phases. For highcurrent applications, the remote sense amplifier is used to compensate for the parasitic offset to provide an accurate output voltage. DIFFO1, which is the output of the remote sensing amplifier, is connected to the resistor divider of the feedback network. Power Stage RPARASITIC L O A D COMP2 COMP1 FB2 RPARASITIC BP6 R GSNS VSNS1 R + VSNS GSNS1 R R DIFFO1 + VREF FB1 COMP1 UDG-11249 Figure 13. Two-Phase Mode Configuration Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 17 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com When the device operates in two-phase mode, a current sharing loop as shown in Figure 13 is designed to maintain the current balance between phases. Both phases share the same comparator voltage (COMP1). The sensed current in each phase is compared first in a current share block, then an error current and fed into COMP. The resulted error voltage is compared with the voltage ramp to generate the PWM pulse. IO1 L1 DCR L SW1 VOUT R1 C1 CS1P CS1N ISNS2 ISNS1 ISHARE Block + FB1 + VREF - + PWM1 COMP1 PWM2 + - + ISNS2 ISHARE Block ISNS1 CS2P CS2N C2 R2 IO2 L DCR SW2 L2 VOUT UDG-11250 Figure 14. Two-Phase Mode Current Share Loop 18 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 Linear Regulators The TPS40422 has two on-board linear regulators primarily intended to provide suitable power for the internal circuitry of the device. These pins, BP3 and BP6 must be properly bypassed to function properly. BP3 needs a minimum of 100 nF connected to AGND and BP6 should have approximately 1 F of capacitance connected to PGND. It is permissible to use the external regulator to power other circuits if desired, but care must be taken to ensure that the loads placed on the regulators do not adversely affect operation of the controller. The main consideration is to avoid loads with heavy transient currents that can affect the regulator outputs. Transient voltages on these outputs could result in noisy or erratic operation of the TPS40422. Current limits must also be observed. Shorting the BP3 pin to GND damages the BP3 regulator. The BP3 regulator input comes from the BP6 regulator output. The BP6 regulator can supply 120 mA so the total current drawn from both regulators must be less than that. This total current includes the device operating current IVDD plus the gate drive current required to drive the power FETs. The total available current from two regulators is described in Equation 3 and Equation 4: IL(in ) = IBP6 - (IVDD + IGATE ) ( IGATE = fSW QgHIGH + QgLOW (3) ) where * * * * * * * IL(in) is the total current that can be drawn from BP3 and BP6 in aggregate IBP6 is the current limit of the BP6 regulator (120-mA minimum) IVDD is the quiescent current of the TPS40422 (15-mA maximum) IGATE is the gate drive current required by the power FETs fSW is the switching frequency QgHIGH is the total gate charge required by the high-side FETs QgLOW is the total gate charge required by the low-side FETs (4) BP Crossover If the voltage on the BPEXT pin is lower than the switch-over voltage, VBPEXT(swover), then the internal BP6 regulator is used. If the voltage on the BPEXT pin exceeds this switch-over voltage, then the internal BP6 regulator is bypassed and the BP6 pin follows BPEXT, until the voltage on the BPEXT pin falls by the BPEXT switch-over hysteresis amount, VHYS(swover). If the BPEXT function is not used, it is recommended to connect the BPEXT pin to GND. Depending on board layout, there may be noise injected into the BPEXT pin. If the voltage on the BPEXT pin changes dynamically in the application, crossing above and below the switch-over voltage, then an external 10 k resistor can be connected from BPEXT to GND to increase noise immunity. Switching Frequency Setting The switching frequency is set by the value of the resistor connected from the RT pin to AGND. The RT resistor value is calculated in Equation 5. RRT = 20 109 fSW where * * RRT is the the resistor from RT pin to AGND, in fSW is the desired switching frequency, in Hz (5) The TPS40422 device can also synchronize to an external clock that is 20% of the master clock frequency which is two times the free running frequency. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 19 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com PMBus Functionality PMBus Address The PMBus specification requires that each device connected to the PMBus have a unique address on the bus. The TPS40422 has 64 possible addresses (0 through 63 in decimal) that can be assigned by connecting resistors from the ADDR0 and ADDR1 pins to AGND. The address is set in the form of two octal (0-7) digits, one digit for each pin. ADDR1 is the high-order digit and ADDR0 is the low-order digit. The E48 series resistors suggested for each digit value are shown in Table 1. Table 1. E48 Series Resistors DIGIT RESISTANCE (k) 0 11 1 18.7 2 27.4 3 38.3 4 53.6 5 82.5 6 127 7 187 The TPS40422 also detects values that are out of range on the ADDR0 and ADDR1 pins. If either pin is detected as having an out of range resistance connected to it, the device continues to respond to PMBus commands, but at address 127, which is outside of the possible programmed addresses. It is possible but not recommended to use the device in this condition, especially if other TPS40422 devices are present on the bus or if another device could possibly occupy the 127 address. PMBus Connections The TPS40422 supports both the 100-kHz and 400-kHz bus speeds. Connection for the PMBus interface should follow the High Power DC specifications given in section 3.1.3 on the System Management Bus (SMBus) Specification V2.0 for the 400-kHz bus speed or the Low Power DC specifications in section 3.1.2. The complete SMBus specification is available from the SMBus web site, smbus.org. PMBus Data Format There are three data formats supported in PMBus form commands that require representation of a literal number as their argument (commands that set thresholds, voltages or report such). A compatible device needs to only support one of these formats. The TPS40422 supports the Linear data format only for these commands. In this format, the data argument consists of two parts, a mantissa and an exponent. The number represented by this argument can be expressed as shown in Equation 6. Value = Mantissa 2exp onent (6) PMBus Output Voltage Adjustment The nominal output voltage of the converter can be adjusted using the VREF_TRIM command. See the VREF_TRIM command description for the format of this command as used in the TPS40422. The adjustment range is between -20% and +10% from the nominal output voltage. The VREF_TRIM command is typically used to trim the final output voltage of the converter without relying on high precision resistors being used in Figure 9. The resolution of the adjustment is 7 bits, with a resulting minimum step size of approximately 0.4%. Note that the output margining is accomplished using this same 7 bit structure so the total combined deviation from the nominal output for margining and VREF_TRIM is remains limited to between -20% and +10%. Exceeding this range is not supported. The TPS40422 operates in three states that the are determine the actual output voltage: * No output margin * Margin high * Margin low 20 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 These output states are set using the OPERATION command. The FB pin reference voltage is calculated as follows in each of these states. No margin voltage: VFB = VREF _ TRIM + 0.6 (7) Margin high voltage state: VFB = STEP _ VREF _ MARGIN _ HIGH + VREF _ TRIM + 0.6 (8) Margin low state: VFB = STEP _ VREF _ MARGIN _ LOW + VREF _ TRIM + 0.6 where * * * * VFB is the FB pin voltage VREF_TRIM is the offset voltage in volts to be applied to the output voltage VREF_MARGIN_HIGH is the requested margin high voltage VREF_MARGIN_LOW is the requested margin low voltage (9) For these conditions, the output voltage is shown in Equation 10. ae (R2 + R1) o VOUT = VFB c / c / R2 e o where * * * VFB is the pin voltage calculated in Equation 7, Equation 8 or Equation 9 depending on the output state R2 and R1 are in consistent units from Figure 9 VOUT is the output voltage (10) NOTE The sum of the margin and trim voltages cannot be more tha between -20% and +10% of the nominal output voltage. The FB pin voltage can deviate no more that this from the nominal 600 mV. Reading the Output Current The average output current for the converter is readable using the READ_IOUT command. The results of this command support only positive or current sourced from the converter. If the converter is sinking current the result of this command is a reading of 0 A. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 21 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com Soft-Start Time The TPS40422 supports several soft-start times from 600 s to 9 ms selected by the TON_RISE PMBus command. See the command description for full details on the levels and implementation. When selecting the soft-start time, care must be taken to ensure that the charging current for the output capacitors is considered. In some applications (e.g., those with large amounts of output capacitance) this current can lead to problems with nuisance tripping of the overcurrent protection circuitry. To ensure that this does not happen, the output capacitor charging current should be included when considering where to set the overcurrent threshold. The output capacitor charging current can be found using Equation 11: ae (VOUT COUT ) o ICAP = c / c / tSS e o where * * * * ICAP is the startup charging current of the output capacitance in A VOUT is the output voltage of the converter in V COUT is the total output capacitance in F tSS is the selected soft-start time in seconds (11) With the charging current calculated, the overcurrent threshold can then be calibrated to the sum of the maximum load current and the output capacitor charging current plus some margin. The amount of margin required depends on the individual application, but 25% is a suggested starting point. More or less may be required. Turn-On/Turn-Off Delay and Sequencing The TPS40422 provides many sequencing options. Using the ON_OFF_CONFIG command, each rail can be configured to startup whenever the input is not in undervoltage lockout or to additionally require a signal on the CNTLx pin and/or receive an update to the OPERATION command over PMBus. When the gating signal as specified by ON_OFF_CONFIG is reached for that rail, a programmable turn-on delay can be set with TON_DELAY. The rise time can be programmed with TON_RISE. When the specified signal(s) are set to turn the output off, a programmable turn-off delay set by TOFF_DELAY is used before switching is inhibited. More information can be found in the PMBus command descriptions. When the output voltage is within the PGOOD window after the start-up period, the PGOOD pin is asserted. This can be connected to the CNTL pin of another rail in dual-output mode or on another device to control turn-on and turn-off sequencing. Pre-Biased Output Start-Up The TPS40422 contains a circuit that prevents current from being pulled from the output during the start-up sequence in a pre-biased output condition. There are no PWM pulses until the internal soft-start voltage rises above the error amplifier input (FBx pin), if the output is pre-biased. Once the soft-start voltage exceeds the error amplifier input, the device slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a prebiased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and controlled. DESIGN NOTE During the soft-start sequence, when the PWM pulse width is shorter than the minimum controllable on-time, which is generally caused by the PWM comparator and gate driver delays, pulse skipping may occur and the output might show larger ripple voltage. Undervoltage Lockout The TPS40422 provides flexible user adjustment of the undervoltage lockout threshold and the hysteresis. Two PMBus commands VIN_ON and VIN_OFF allow the user to set these input voltage turn on and turn off thresholds independently, with a minimum of 4-V turn off to a maximum 16-V turn on. See the command descriptions for more details. 22 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 Overvoltage and Undervoltage Fault Protection The TPS40422 has output overvoltage protection and undervoltage protection capability. The comparators that regulate the overvoltage and undervoltage conditions use the FBx pin as the output sensing point so the filtering effect of the compensation network connected from COMPx to FBx has an effect on the speed of detection. As the output voltage rises or falls below the nominal value, the error amplifier attempts to force FBx to match its reference voltage. When the error amplifier is no longer able to do this, the FB pin begins to drift and trip the overvoltage threshold (VOVP) or the undervoltage threshold (VUVP) . When an undervoltage fault is detected, the device enters hiccup mode and resumes normal operation when the fault is cleared. When an overvoltage fault is detected, the device turns off the high-side MOSFET and latches on the low-side MOSFET to discharge the output current to the regulation level (within the power good window) When operating in dual-channel mode, both channels have identical but independent protection schemes which means one channel would not be affected when the other channel is in fault mode. When operating in two-phase mode, only the FB1 pin is detected for overvoltage and undervoltage fault. Therefore both channels take action together during a fault. Power Good The TPS40422 has user selectable power good thresholds. These thresholds determine at what voltage the PGOOD pin is allowed to go high and the associated PMBus flags are cleared. There are three possible settings that can be had. See the POWER_GOOD_ON and POWER_GOOD_OFF command descriptions for complete details. Note that these commands establish symmetrical values above and below the nominal voltage. Values entered for each threshold should be the voltages corresponding to the threshold below the nominal output voltage. For instance, if the nominal output voltage is 3.3 V, and the desired power good on thresholds are 5%, the POWER_GOOD_ON command is issued with 2.85 V as the desired threshold. The POWER_GOOD_OFF command must be set to a lower value (higher percentage) than the POWER_GOOD_ON command as well. The VOUT_SCALE_LOOP command must be set to approximately 0.1818 for these examples to work correctly. The FB pin is used to sense the output voltage for the purposes of power good detection. Because of this there is the inherent filtering action provided by the compensation network connected from COMP to FB. As the output voltage rises or falls below the nominal value, the error amplifier attempts to force FB to match its reference voltage. When the error amplifier is no longer able to do this, the FB pin begins to drift and trip the power good threshold. For this reason the network from COMP to FB should have no purely resistive path. Power good de-asserts during all startups, after any fault condition is detected or whenever the device is turned off or in a disabled state (OPERATION command or CNTLx pins put the device into a disabled or off state). The PGOOD pin acts like a diode to GND when the device has no power applied to the VDD pin. Overtemperature Fault Protection The TPS40422 provides programmable overtemperature fault and warning thresholds using measurements from the external temperature sensors connected on the TSNSx pins for each rail. More information can be found in the OT_FAULT_LIMIT (4Fh) and OT_WARN_LIMIT (51h) command descriptions. Thermal Shutdown If the junction temperature of the device reaches the thermal shutdown limit of 150C, the PWMs and the oscillators are turned off and HDRVs and LDRVs are driven low. When the junction cools to the required level (130C typical), the PWM initiates soft start as during a normal power-up cycle. Programmable Fault Responses The overcurrent and output undervoltage response can IOUT_OC_FAULT_RESPONSE command. More information IOUT_OC_FAULT_RESPONSE (47h) command description. Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 be can programmed using be found in the the Submit Documentation Feedback 23 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com User Data and Adjustable Anti-Cross Conduction Delay The TPS40422 provides a command, MFR_SPECIFIC_00, which can be used as a scratchpad to store 14 bits of arbitrary data. These bits can represent anything that the user desires and can be stored in EEPROM for nonvolatility. Bit 0 of this command is used to select between two dead time settings for the controller. The particular setting required for a given application depends upon several things, including total FET gate charge, FET gate resistance, PCB layout quality, temperature, etc. It is not possible to give a hard and fast rule as to when to use which setting, but generally, for FETs above 25 nC gate charge, the longer dead time setting should be looked at. The shorter dead time setting allows higher efficiency in applications where the FETs are generally small and switch very quickly, while may lead to minimum amounts of cross conduction in applications with larger, slower switching FETs. Conversely, using the longer dead time setting with smaller, faster switching FETs leads to excessive body diode conduction in the low-side FET, leading to a drop in converter efficiency. CAUTION Bit 1 of this command permanently locks certain parameters from being changed when set to 1. For more detail, see the MFR_SPECIFIC_00 command description. 24 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 SUPPORTED COMMANDS The TPS40422 supports the following commands from the PMBus 1.1 specification. PAGE (00h) The PAGE command provides the ability to configure, control, and monitor through only one physical address both channels (outputs) of the TPS40422. Command PAGE Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r/w r r r r r r r/w Function PA X X X X X X P0 0 X X X X X X 0 Default Value Table 2. PAGE Command Truth Table PA P0 LOGIC RESULTS 0 0 All commands address the first channel 0 1 All commands address the second channel 1 0 Illegal input. Ignore this write, take no action 1 1 All commands address both channels If PAGE=11, then any read commands affect the first channel. Any value written to read-only registers is ignored. OPERATION (01h) OPERATION is a paged register. The OPERATION command is used to turn the device output on or off in conjunction with input from the CNTLx pins. It is also used to set the output voltage to the upper or lower MARGIN voltages. The unit stays in the commanded operating mode until a subsequent OPERATION command or a change in the state of the CNTLx pins instructs the device to change to another mode. Command OPERATION Format Bit Position Unsigned binary 7 6 5 4 3 2 1 Access r/w r r/w r/w r/w r/w r r Function ON X X X 0 0 X X Default Value Margin 0 0 0 0 0 On This bit is an enable command to the converter. * 0: output switching is disabled. Both drivers placed in an off or low state. * 1: output switching is enabled. The device is allowed to begin power conversion assuming no fault conditions exist. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 25 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com Margin If Margin Low is enabled, load the value from the VOUT_MARGIN_LOW command. If Margin High is enabled, load the value from the VOUT_MARGIN_HIGH command. (See PMBus specification for more information) * 00XX: Margin Off * 0101: Margin Low (Act on Fault) * 0110: Margin Low (Act on Fault) * 1001: Margin High (Act on Fault) * 1010: Margin High (Act on Fault) ON_OFF_CONFIG (02h) ON_OFF_CONFIG is a paged register. The ON_OFF_CONFIG command configures the combination of CNTLx pins input and serial bus commands needed to turn the unit on and off. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. Command ON_OFF_CONFIG Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r/w r/w r/w r/w r Function X X X pu cmd cpr pol cpa Default Value X X X 1 0 1 1 0 pu The pu bit sets the default to either operate any time power is present or for the on/off to be controlled by CNTLx pins and PMBus OPERATION command. This bit is used in conjunction with the 'cp', 'cmd', and 'on' bits to determine start up. Bit Value ACTION 0 Channel powers up any time power is present regardless of state of the CNTLx pins. 1 Channel does not power up until commanded by the CNTLx pins and OPERATION command as programmed in bits [2:0] of the ON_OFF_CONFIG register. cmd The cmd bit controls how the device responds to the OPERATION command. Bit Value ACTION 0 Channel ignores the "on" bit in the OPERATION command. 1 Channel responds to the "on" bit in the OPERATION command. cpr The cpr bit sets the CNTLx pins response. This bit is used in conjunction with the 'cmd', 'pu', and 'on' bits to determine start up. Bit Value ACTION 0 Channel ignores the CNTLx pins. On/off is controlled only by the OPERATION command. 1 Channel requires the CNTLx pins to be asserted to start the unit. pol The pol bit controls the polarity of the CNTLx pins. For a change to become effective, the contents of the ON_OFF_CONFIG register must be stored to non-volatile memory using the STORE_USER_ALL command and the device power cycled. Simply writing a new value to this bit does not change the polarity of the CNTLx pins. 26 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 Bit Value ACTION 0 CNTLx pins is active low. 1 CNTLx pins is active high. cpa The cpa bit sets the CNTLx pins action when turning the controller off. This bit is read internally and cannot be modified by the user. Bit Value 0 ACTION Turn off the output using the programmed delay. CLEAR_FAULTS (03h) The CLEAR_FAULTS command is used to clear any fault bits that have been set. This command clears all bits in all status registers in the selected page simultaneously. At the same time, the device negates (clears, releases) its SMBALERT signal output if the device is asserting the SMBALERT signal. The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. If the fault is still present when the bit is cleared, the fault bit is immediately reset and the host notified by the usual means. WRITE_PROTECT (10h) The WRITE_PROTECT command is used to control writing to the PMBus device. The intent of this command is to provide protection against accidental changes. This command is not intended to provide protection against deliberate or malicious changes to the device configuration or operation. All supported command parameters may have their parameters read, regardless of the WRITE_PROTECT settings. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. Command WRITE_PROTECT Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r/w r/w r/w X X X X X Function bit7 bit6 bit5 X X X X X 0 0 0 X X X X X Default Value bit5 Bit Value ACTION 0 Enable all writes as permitted in bit6 or bit7 1 Disable all writes except the WRITE_PROTECT, PAGE, OPERATION and ON_OFF_CONFIG. (bit6 and bit7 must be 0 to be valid data) bit6 Bit Value ACTION 0 Enable all writes as permitted in bit5 or bit7 1 Disable all writes except for the WRITE_PROTECT, PAGE and OPERATION commands. (bit5 and bit7 must be 0 to be valid data) bit7 Bit Value ACTION 0 Enable all writes as permitted in bit5 or bit6 1 Disable all writes except for the WRITE_PROTECT command. (bit5 and bit6 must be 0 to be valid data) Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 27 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com In any case, only one of the three bits may be set at any one time. Attempting to set more than one bit results in an alert being generated and the cml bit is STATUS_WORD being set. STORE_USER_ALL (15h) The STORE_USER_ALL command stores all of the current storable register settings in the EEPROM memory as the new defaults on power up. It is permissible to use this command while the device is switching. Note however that the device continues to switch but ignores all fault conditions until the internal store process has completed. EEPROM programming faults cause the device to NACK and set the 'cml' bit in the STATUS_BYTE and the 'oth' bit in the STATUS_CML registers. RESTORE_USER_ALL (16h) The RESTORE_USER_ALL command restores all of the storable register settings from EEPROM memory. This command should not be used while the device is actively switching. If this is done, the device stops switching the output drivers and the output voltage drops. Depending on loading conditions, the output voltage could reach an undervoltage level and trigger an undervoltage fault response if programmed to do so. The command can be used while the device is switching, but it is not recommended as it results in a restart that could disrupt power sequencing requirements in more complex systems. It is strongly recommended that the device be stopped before issuing this command. CAPABILITY (19h) The CAPABILTY command provides a way for a host system to determine some key capabilities of this PMBus device. Command CAPABILITY Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r 0 0 Function PEC Default Value 1 SPD 0 ALRT 1 1 Reserved 0 0 The default values indicate that the TPS40422 supports Packet Error Checking (PEC), a maximum bus speed of 400 kHz (SPD) and the SMBus Alert Response Protocol using a SMBALERT pin (ALRT). VOUT_MODE (20h) The PMBus specification dictates that the data word for the VOUT_MODE command is one byte that consists of a 3-bit mode and 5-bit exponent parameter, as shown below. The 3-bit mode sets whether the device uses the Linear or Direct modes for output voltage related commands. The 5-bit parameter sets the exponent value for the linear data mode. The mode and exponent parameters are set and do not permit the user to change the values. Command VOUT_MODE Bit Position 7 Access r Function Default Value 6 5 4 3 r r r r Mode 0 0 2 1 0 r r r 1 1 Exponent 0 1 1 1 Mode: Value fixed at 000, linear mode. Exponent Value fixed at 10111, Exponent for Linear mode values is -9. 28 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 VIN_ON (35h) The VIN_ON command sets the value of the input voltage at which the unit should start operation assuming all other required startup conditions are met. Values are mapped to the nearest supported increment. Values outside the supported range are treated as invalid data and cause the device set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers. The value of VIN_ON remains unchanged on an out-of-range write attempt. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The supported VIN_ON values are: 4.25 (default) 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 8 8.25 8.5 8.75 9 9.25 9.5 10 10.5 11 11.5 12 12.5 13 14 15 16 VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON results in the new value being rejected, SMBALERT being asserted along with the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. The data word that accompanies this command is divided into a fixed 5-bit exponent and an 11-bit mantissa. The four most significant bits of the mantissa are fixed, while the lower 7 bits may be altered. Command VIN_ON Format Linear, two's complement binary Bit Position 7 6 Access r r Function Default Value 5 4 3 2 1 0 7 6 r r r r r r r r/w Exponent 1 1 1 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w 1 0 0 0 1 Mantissa 1 0 0 0 0 0 0 0 Exponent -2 (dec), fixed. Mantissa The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 9 (dec). This corresponds to a default of 4.25 V. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 29 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com VIN_OFF (36h) The VIN_OFF command sets the value of the input voltage at which the unit should stop operation. Values are mapped to the nearest supported increment. Values outside the supported range is treated as invalid data and causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers. The value of VIN_OFF remains unchanged during an out-of-range write attempt. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The supported VIN_OFF values are: 4 (default) 4.25 4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.5 6.75 7 7.25 7.5 8 8.25 8.5 8.75 9 9.25 9.75 10.25 10.75 11.25 11.75 12 13.75 14.75 15.75 VIN_ON must be set higher than VIN_OFF. Attempting to write either VIN_ON lower than VIN_OFF or VIN_OFF higher than VIN_ON resultx in the new value being rejected, SMBALERT being asserted along with the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. The data word that accompanies this command is divided into a fixed 5 bit exponent and an 11 bit mantissa. The 4 most significant bits of the mantissa are fixed, while the lower 7 bits may be altered. Command VIN_OFF Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w 1 1 1 0 0 0 0 0 0 0 1 0 0 0 Function Default Value Exponent 1 Mantissa 0 Exponent -2 (dec), fixed. Mantissa The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 8 (dec). This corresponds to a default value of 4.0 V. IOUT_CAL_GAIN (38h) IOUT_CAL_GAIN is a paged register. The IOUT_CAL_GAIN is the ratio of the voltage at the current sense element to the sensed current. The units are Ohms (). The effective current sense element can be the DC resistance of the inductor or a separate current sense resistor. The default setting is 0.488 m, and the resolution is 30.5 . The range is 0.244 m to 15.5 m. The contents of this register can be stored to nonvolatile memory using the STORE_USER_ALL or STORE_DEFAULT_CODE commands. Command IOUT_CAL_GAIN Format Linear, two's complement binary Bit Position 7 6 Access r r Function Default Value 30 5 4 3 2 1 0 7 6 r r r r r r/w r/w r/w Exponent 1 0 0 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w 1 0 0 0 0 Mantissa 0 1 0 0 0 0 Submit Documentation Feedback 0 0 Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 Exponent -15 (dec), fixed. Mantissa The upper two bits are fixed at 0. The lower nine bits are programmable with a default value of 16 (dec). Depending on the value of IOUT_CAL_GAIN, the current sense amplifier used for current monitoring (but not overcurrent or current sharing) changes, as shown in Table 3. Table 3. Current Sense Amplifier Settings IOUT_CAL_GAIN (m) RANGE MIN MAX CSA GAIN (V/V) 0.244 0.5795 25 0.5796 1.1285 15 1.1286 15.5 10 IOUT_CAL_OFFSET (39h) IOUT_CAL_OFFSET is a paged register. The IOUT_CAL_OFFSET is used to compensate for offset errors in the READ_IOUT results and the IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT thresholds. The units are amperes. The default setting is 0 A. The resolution of the argument for this command is 62.5 mA and the range is +3937.5 mA to -4000 mA. Values written outside of this range alias into the supported range. For example, 1110 0100 0000 0001 has an expected value of -63.9375 A, but results in 1110 0111 1111 0001 which is -3.9375 A. This occurs because the read-only bits are fixed. The exponent is always -4 and the 5 msb bits of the Mantissa are always equal to the sign bit. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. Command IOUT_CAL_OFFSET Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r/w r r r r r/w r/w r/w r/w r/w r/w 0 0 0 0 0 Function Default Value Exponent 1 1 1 Mantissa 0 0 0 0 0 0 0 0 Exponent -4 (dec), fixed. Mantissa MSB is programmable with sign, next 4 bits are sign extend only. Lower six bits are programmable with a default value of 0 (dec). Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 31 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com IOUT_OC_FAULT_LIMIT (46h) IOUT_OC_FAULT_LIMIT is a paged register. The IOUT_OC_FAULT_LIMIT command sets the value of the output current, in amperes, that causes the overcurrent detector to indicate an overcurrent fault condition. The IOUT_OC_FAULT_LIMIT should be set equal to or greater than the IOUT_OC_WARN_LIMIT. Writing a value to IOUT_OC_FAULT_LIMIT less than IOUT_OC_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALRT signal. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The IOUT_OC_FAULT_LIMIT takes a two-byte data word formatted as shown below: Command IOUT_OC_FAULT_LIMIT Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r/w r/w r/w r/w r/w r/w r/w 1 1 1 1 0 0 0 0 0 1 1 1 0 0 Function Exponent Default Value 1 Mantissa 1 Exponent -1 (dec), fixed. Mantissa The upper four bits are fixed at 0. The lower seven bits are programmable with a default value of 60 (dec). The actual output current for a given mantissa and exponent is shown in Equation 12. Mantissa IOUT(oc) = Mantissa 2Exponent = 2 (12) The default output fault current setting is 30 A. Values of IOUT(oc) can range between 3 A and 50 A in 500-mA increments. IOUT_OC_FAULT_RESPONSE (47h) IOUT_OC_FAULT_RESPONSE is a paged register. The IOUT_OC_FAULT_RESPONSE command instructs the device on what action to take in response to an IOUT_OC_FAULT_LIMIT or a VOUT undervoltage (UV) fault. The device also: * Sets the IOUT_OC bit in the STATUS_BYTE * Sets the IOUT/POUT bit in the STATUS_WORD * Sets the IOUT OC Fault bit in the STATUS_IOUT register * Notifies the host by asserting SMBALERT The contents of this register can be stored to non-volatile memory using the STORE_USER command. Command IOUT_OC_FAULT_RESPONSE Format 32 Unsigned binary Bit Position 7 6 5 4 3 2 1 Access r r r/w r/w r/w r r r Function X X RS[2] RS[1] RS[0] X X X Default Value 0 0 1 1 1 1 0 0 Submit Documentation Feedback 0 Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 RS[2:0] 000: A zero value for the Retry Setting means that the unit does not attempt to restart. The output remains disabled until the fault is cleared (See section 10.7 of the PMBus spec.) 111: A one value for the Retry Setting means that the unit goes through a normal startup (Soft start) continuously, without limitation, until it is commanded off or bias power is removed or another fault condition causes the unit to shutdown. Any value other than 000 or 111 is not accepted. Attempting to write any other value is rejected, causing the TPS404022 to assert SMBALERT along with the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. IOUT_OC_WARN_LIMIT (4Ah) IOUT_OC_WARN_LIMIT is a paged register. The IOUT_OC_WARN_LIMIT command sets the value of the output current, in amperes, that causes the over-current detector to indicate an over-current warning. When this current level is exceeded the device: * Sets the OTHER bit in the STATUS_BYTE * Sets the IOUT/POUT bit in the STATUS_WORD * Sets the IOUT overcurrent Warning (OCW) bit in the STATUS_IOUT register, and * Notifies the host by asserting SMBALRT The IOUT_OC_WARN_LIMIT threshold should always be set to less than or equal to the IOUT_OC_FAULT_LIMIT. Writing a value to IOUT_OC_WARN_LIMIT greater than IOUT_OC_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALRT signal. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The IOUT_OC_WARN_LIMIT takes a two byte data word formatted as shown below: Command IOUT_OC_WARN_LIMIT Format Linear, two's complement binary Bit Position 7 6 Access r r Function Default Value 5 4 3 2 1 0 7 6 r r r r r r r r/w Exponent 1 1 1 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w 1 0 1 1 0 Mantissa 1 1 0 0 0 0 0 1 Exponent -1 (dec), fixed. Mantissa The upper four bits are fixed at 0. Lower seven bits are programmable with a default value of 54 (dec). The actual output warning current level for a given mantissa and exponent is: Mantissa IOUT(OCW ) = Mantissa 2Exponent 2 (13) The default output warning current setting is 27 A. Values of IOUT(OCW) can range from 2 A to 49 A in 500-mA increments. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 33 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com OT_FAULT_LIMIT (4Fh) OT_FAULT_LIMIT is a paged register. The OT_FAULT_LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-temperature fault condition, when the sensed temperature from the external sensor exceeds this limit. Upon triggering the over-temperature fault, the following actions are taken: * Sets the TEMPERATURE bit in the STATUS_BYTE * Sets the OT Fault bit in the STATUS_TEMPERATURE * Notifies the host by asserting SMBALERT Once the over-temperature fault is tripped, the output is latched off until the external sensed temperature falls 20C from the OT_FAULT_LIMIT, at which point the output goes through a normal startup (soft-start). The OT_FAULT_LIMIT must always be greater than the OT_WARN_LIMIT. Writing a value to OT_FAULT_LIMIT less than or equal to OT_WARN_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as asserts the SMBALERT signal. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The OT_FAULT_LIMIT takes a two byte data word formatted as shown below. Command OT_FAULT_LIMIT Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 1 0 0 1 0 0 Function Default Value Exponent 0 Mantissa 1 Exponent 0 (dec), fixed. Mantissa The upper three bits are fixed at 0. Lower eight bits are programmable with a default value of 145 (dec). The default over-temperature fault setting is 145C. Values can range from 120C to 165C in 1C increments. OT_WARN_LIMIT (51h) OT_WARN_LIMIT is a paged register. The OT_ WARN _LIMIT command sets the value of the temperature, in degrees Celsius, that causes an over-temperature warning condition, when the sensed temperature from the external sensor exceeds this limit. Upon triggering the over-temperature warning, the following actions are taken: * Sets the TEMPERATURE bit in the STATUS_BYTE * Sets the OT Warning bit in the STATUS_TEMPERATURE * Notifies the host by asserting SMBALERT Once the over-temperature warning is tripped, warning is latched until the external sensed temperature falls 20C from the OT_WARN_LIMIT. The OT_WARN_LIMIT must always be less than the OT_FAULT_LIMIT. Writing a value to OT_WARN_LIMIT greater than or equal to OT_FAULT_LIMIT causes the device to set the CML bit in the STATUS_BYTE and the invalid data (ivd) bit in the STATUS_CML registers as well as assert the SMBALERT signal. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. 34 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 The OT_WARN_LIMIT takes a two byte data word formatted as shown below: Command OT_WARN_LIMIT Format Unsigned binary Bit Position 7 6 Access r r Function 5 4 3 2 1 0 7 6 r r r r r r r/w r/w Exponent Default Value 0 0 0 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w 1 1 1 0 1 Mantissa 0 0 0 0 0 0 1 1 Exponent 0 (dec), fixed. Mantissa The upper three bits are fixed at 0. Lower eight bits are programmable with a default value of 125 (dec). The default over-temperature fault setting is 125C. Values can range from 100C to 140C in 1C increments. TON_RISE (61h) TON_RISE is a paged register. The TON_RISE command sets the time in ms, from when the output starts to rise until the voltage has entered the regulation band. It also determines the rate of the transition of the reference voltage (either due to VREF_TRIM or STEP_VREF_MARGIN_x commands) when this transition is executed during the soft-start period. There are several discrete settings that this command supports. Commanding a value other than one of these values results in the nearest supported value being selected. The supported TON_RISE times over PMBus are: * 600 s * 900 s * 1.2 ms * 1.8 ms * 2.7 ms (default value) * 4.2 ms * 6.0 ms * 9.0 ms A value of 0 ms instructs the unit to bring its output voltage to the programmed regulation value as quickly as possible. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The TON_RISE command is formatted as a linear mode two's complement binary integer. Command TON_RISE Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r/w r/w r/w r/w r/w r/w r/w r/w 0 1 0 1 1 Function Default Value Exponent 1 1 1 Mantissa 0 0 0 0 0 0 0 1 Exponent -4 (dec), fixed. Mantissa The upper two bits are fixed at 0. The lower eight bits are programmable with a default value of 43 (dec). Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 35 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com STATUS_BYTE (78h) STATUS_BYTE is a paged register. The STATUS_BYTE command returns one byte of information with a summary of the most critical device faults. Three fault bits are flagged in this particular command: output overvoltage, output overcurrent, and over-temperature. The STATUS_BYTE reports communication faults in the CML bit. Other communication faults set the NONE OF THE ABOVE bit. Command STATUS_BYTE Format Unsigned binary Bit Position 7 6 5 4 3 2 1 Access r r r r r r r 0 r Function X OFF VOUT_OV IOUT_OC VIN_UV TEMPERATURE CML NONE OF THE ABOVE Default Value 0 0 0 0 0 0 0 0 A "1" in any of these bit positions indicates that: OFF: The device is not providing power to the output, regardless of the reason. In TPS40422, this flag means that the converter is not enabled. VOUT_OV: An output overvoltage fault has occurred. IOUT_OC: An output over current fault has occurred. VIN_UV: An input undervoltage fault has occurred. TEMPERATURE: A temperature fault or warning has occurred. CML: A Communications, Memory or Logic fault has occurred. NONE OF THE ABOVE: A fault or warning not listed in bit1 through bits 1-7 has occurred, for example an undervoltage condition or an over current warning condition STATUS_WORD (79h) STATUS_WORD is a paged register. The STATUS_WORD command returns two bytes of information with a summary of the device's fault/warning conditions. The low byte is identical to the STATUS_BYTE above. The additional byte reports the warning conditions for output overvoltage and overcurrent, as well as the power good status of the converter. Command STATUS_WORD (low byte) Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r Function X OFF VOUT_OV IOUT_OC VIN_UV TEMPERATURE CML NONE OF THE ABOVE Default Value 0 x 0 0 0 0 0 0 36 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 A "1" in any of the low byte (STATUS_BYTE) bit positions indicates that: OFF: The device is not providing power to the output, regardless of the reason. In TPS40422, this flag means that the converter is not enabled. VOUT_OV: An output overvoltage fault has occurred. IOUT_OC: An output over current fault has occurred. VIN_UV: An input undervoltage fault has occurred. TEMPERATURE: A temperature fault or warning has occurred. CML: A Communications, Memory or Logic fault has occurred. NONE OF THE ABOVE: A fault or warning not listed in bits 1-7 has occurred Command STATUS_WORD (high byte) Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r VOUT IOUT/POUT X MFR POWER_GOOD X X X 0 0 0 0 0 0 0 0 Function Default Value A "1" in any of the high byte bit positions indicates that: VOUT: An output voltage fault or warning has occurred IOUT/POUT: An output current warning or fault has occurred. The PMBus specification states that this also applies to output power. TPS40422 does not support output power warnings or faults. MFR: An internal thermal shutdown (TSD) fault has occurred in the device. POWER_GOOD: The power good signal has not transitioned from high-to-low. This is not implemented in 2-phase operation. STATUS_VOUT (7Ah) STATUS_VOUT is a paged register. The STATUS_VOUT command returns one byte of information relating to the status of the converter's output voltage related faults. The only bits of this register supported are: * VOUT_OV Fault * VOUT_UV Fault Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 37 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com Command STATUS_VOUT Format Unsigned binary Bit Position 7 6 5 4 3 2 1 Access r r r r r r r r VOUT OV Fault X X VOUT UV Fault X X X X 0 0 0 0 0 0 0 0 Function Default Value 0 A "1" in any of these bit positions indicates that: VOUT OV Fault: The device has seen the output voltage rise above the output overvoltage threshold. VOUT UV Fault: The device has seen the output voltage fall below the output undervoltage threshold. STATUS_IOUT (7Bh) STATUS_IOUT is a paged register. The STATUS_IOUT command returns one byte of information relating to the status of the converter's output current related faults. The only bits of this register supported are . * IOUT_OC Fault * IOUT_OC Warning Command STATUS_IOUT Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r IOUT_OV Fault X IOUT OC Warning X X X X X 0 0 0 0 0 0 0 0 Function Default Value A "1" in any of these bit positions indicates that: IOUT_OV Fault: The device has seen the output current rise above the level set by IOUT_OC_FAULT_LIMIT. VOUT_UV Fault: The device has seen the output current rise relating to the level set by IOUT_OC_WARN_LIMIT. STATUS_TEMPERATURE (7Dh) STATUS_TEMPERATURE is a paged register. The STATUS_TEMPERATURE command returns one byte of information relating to the status of the external temperature related faults. The only bits of this register supported are: * OT Fault * OT Warning Command STATUS_TEMPERATURE Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r OT Fault OT Warning X X X X X X 0 0 0 0 0 0 0 0 Function Default Value 38 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 A "1" in any of these bit positions indicates that: OT Fault: The measured external temperature has exceeded the level set by OT_FAULT_LIMIT. OT Warning: The measured external temperature has exceeded the level set by OT_WARN_LIMIT. STATUS_CML (7Eh) The STATUS_CML command returns one byte of information relating to the status of the converter's communication related faults. The bits of this register supported by the TPS40422 are: * nvalid/Unsuppported Command * Invalid/Unsupported Data * Packet Error Check Failed * Memory Fault Detected * Other Communication Fault. I Command STATUS_CML Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r Invalid/ Unsuppported Command Invalid/ Unsupported Data Packet Error Check Failed Memory Fault Detected X X Other Communication Fault X 0 0 0 0 0 0 0 0 Function Default Value A "1" in any of these bit positions indicates that: Invalid/Unsupported Command: An invalid or unsupported command has been received. Invalild/Unsupported Data Invalid or unsupported data has been received Packet Error Check Failed A packet has failed the CRC error check. Memory Fault Detected A fault has been detected with the internal memory. Other Communication Fault Some other communication fault or error has occurred Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 39 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com STATUS_MFR_SPECIFIC (80h) The STATUS_MFR_SPECIFIC command returns one byte of information relating to the status of manufacturerspecific faults or warnings. Command STATUS_MFR_SPECIFIC Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r OTFI X X IVADDR X X X TWOPH_EN 0 0 0 0 0 0 0 0 Function Default Value A "1" in any of these bit positions indicates that: OTFI: The internal temperature is above the thermal shutdown (TSD) fault threshold IVADDR: The PMBus address detection circuit is not resolving to a valid address. In this event, the device responds to the address 127 (dec). TWOPH_EN: The part has detected that it is in two-phase mode (by pulling FB2 high). This bit does not trigger SMBALERT. READ_VOUT (8Bh) READ_VOUT is a paged register. The READ_VOUT commands returns two bytes of data in the linear data format that represent the output voltage of the controller. The output voltage is sensed at the remote sense amplifier output pin so voltage drop to the load is not accounted for. The data format is as shown below: Command READ_VOUT Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r r r r r r r 0 0 0 0 0 0 0 Function Default Value Mantissa 0 0 0 0 0 0 0 0 0 The setting of the VOUT_MODE affects the results of this command as well. In the TPS40422, VOUT_MODE is set to linear mode with an exponent of -9 and cannot be altered. The output voltage calculation is shown in Equation 14. 40 VOUT = Mantissa 2Exponent (14) Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 READ_IOUT (8Ch) READ_IOUT is a paged register. The READ_IOUT commands returns two bytes of data in the linear data format that represent the output current of the controller. The output current is sensed across the CSxP and CSxN pins. The data format is as shown below: Command READ_IOUT Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r r r r r r r 0 0 0 0 0 Function Default Value Exponent 1 1 1 Mantissa 0 0 0 0 0 0 0 0 The output current is scaled before it reaches the internal analog to digital converter so that resolution of the output current read is 62.5 mA, though resolution may be less depending on the setting of IOUT_CAL_GAIN. The maximum value that can be reported is 64 A. It is mandatory that the IOUT_CAL_GAIN and IOUT_CAL_OFFSET parameters are set correctly in order to obtain accurate results. The output current can be found by using Equation 15. IOUT = Mantissa 2Exponent (15) Exponent Fixed at -4.. Mantissa The lower 10 bits are the result of the ADC conversion of the input voltage. The 11th bit is fixed at 0 because only positive numbers are considered valid. Any computed negative current is reported as 0 A.. READ_TEMPERATURE_2 (8Eh) READ_TEMPERATURE_2 is a paged register. The READ_TEMPERATURE_2 command returns the external temperature in degrees Celsius of the current channel. Command READ_TEMPERATURE_2 Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r r r r r r r 1 1 0 0 1 Function Default Value Exponent 0 0 0 Mantissa 0 0 0 0 0 0 0 0 Exponent 0 (dec), fixed. Mantissa The lower 11 bits are the result of the ADC conversion of the external temperature. The default reading is 25 (dec) corresponding to a temperature of 25C. Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 41 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com PMBUS_REVISION (98h) The PMBUS_REVISION command returns a single, unsigned binary byte that indicates that the TPS40422 is compatible with the 1.1 revision of the PMBus specification. Command PMBUS_REVISION Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r r Default Value 0 0 0 1 0 0 0 1 MFR_SPECIFIC_00 (D0h) The MFR_SPECIFIC_00 register is dedicated as a user scratch pad. Command MFR_SPECIFIC_00 Format Unsigned binary Bit Position Access 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Function Default Value User scratch pad 0 0 The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. VREF_TRIM (MFR_SPECIFIC_04) (D4h) VREF_TRIM is a paged register. The VREF_TRIM command is used to apply a fixed offset voltage to the reference voltage. It is most typically used by the end user to trim the output voltage at the time the PMBus device is assembled into the end user system. The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the VOUT_MODE is fixed to Linear with an exponent of -9 (decimal). VREF(offset ) = VREF _ TRIM 2-9 (16) The maximum trim range is -20% to +10% of the nominal reference voltage (600 mV) in 2 mV steps. Permissible values range from -120 mV to +60 mV. If a value outside this range is given with this command, the TPS40422 sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible reference voltage adjustment range is -180 mV to +60 mV (-30% to +10%). If a value outside this range is given with this command, the TPS40422 sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. 42 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is executed during soft-start. Any transition in the reference voltage after soft-start is complete occurs at the rate determined by the highest programmable TON_RISE. Command VREF_TRIM Format Bit Position Access Linear, two's complement binary 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 r/w r r r r r r r r r r/w r/w r/w r/w r/w r/w 0 0 0 Function Default Value High Byte 0 0 0 0 Low Byte 0 0 0 0 0 0 0 0 0 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h) STEP_VREF_MARGIN_HIGH is a paged register. The STEP_VREF_MARGIN_HIGH command sets the target voltage which the reference voltage changes to when the OPERATION command is set to "Margin High". The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the VOUT_MODE is fixed to Linear with an exponent of -9 (decimal). The actual reference voltage commanded by a margin high command can be found by: VREF(MH) = (STEP _ VREF _ MARGIN _ HIGH + VREF _ TRIM) 2-9 (17) The margin high range is 0% to 10% of the nominal reference voltage (600 mV) in 2-mV steps. Permissible values range from 0 mV to 60 mV. If a value outside this range is given with this command, the TPS40422 sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible reference voltage adjustment range is -180 mV to 60 mV (-30% to 10%). If a value outside this range is given with this command, the TPS40422 sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is executed during soft-start. Any transition in the reference voltage after soft-start is complete occurs at the rate determined by the highest programmable TON_RISE. Command STEP_VREF_MARGIN_HIGH Format Linear, two's complement binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r r r/w r/w r/w r/w r/w 1 1 0 Function Default Value High Byte 0 0 0 0 0 Low Byte 0 0 0 0 0 0 1 1 The default value of STEP_VREF_MARGIN_HIGH is 30 (dec). This corresponds to a default margin high voltage of 60 mV (10%) . STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h) STEP_VREF_MARGIN_LOW is a paged register. The STEP_VREF_MARGIN_LOW command sets the target voltage which the reference voltage changes to when the OPERATION command is set to "Margin Low". The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. The effect of this command is determined by the settings of the VOUT_MODE command. In this device, the VOUT_MODE is fixed to Linear with an exponent of -9 (decimal). The actual output voltage commanded by a margin high command is shown in Equation 18. VREF(ML ) = (STEP _ VREF _ MARGIN _ LOW + VREF _ TRIM) 2-9 (18) Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 43 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com The margin low range is -20% to 0% of the nominal reference voltage (600 mV) in 2-mV steps. Permissible values range from -120 mV to 0 mV. If a value outside this range is given with this command, the TPS40422 sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. Including settings from both VREF_TRIM and STEP_VREF_MARGIN_x commands, the net permissible reference voltage adjustment range is -180 mV to 60 mV (-30% to +10%). If a value outside this range is given with this command, the TPS40422 sets the reference voltage to the upper or lower limit depending on the direction of the setting, asserts SMBALERT and sets the CML bit in STATUS_BYTE and the invalid data bit in STATUS_CML. The reference voltage transition occurs at the rate determined by the TON_RISE command if the transition is executed during soft-start. Any transition in the reference voltage after soft-start is complete occurs at the rate determined by the highest programmable TON_RISE. Command STEP_VREF_MARGIN_LOW Format Linear, two's complement binary Bit Position Access 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 r/w r r r r r r r r r r/w r/w r/w r/w r/w r/w 1 1 1 1 1 1 1 1 1 0 1 0 Function Default Value High Byte 1 1 Low Byte 0 0 The default value of STEP_VREF_MARGIN_LOW is -30 (dec). This corresponds to a default margin low voltage of -60 mV (10%). 44 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h) PCT_VOUT_FAULT_PG_LIMIT is a paged register. The PCT_VOUT_FAULT_PG_LIMIT command is used to set the PGOOD, VOUT_UNDER_VOLTAGE (UV) and VOUT_OVER_VOLTAGE (OV) limits as a percentage of nominal. In two-phase mode, the user can write to PAGE 0 (channel 1) only. Any writes to PAGE 1 are not acknowledged. The PCT_VOUT_FAULT_PG_LIMIT takes a one byte data word formatted as shown below: Command PCT_VOUT_FAULT_PG_LIMIT Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 Access r r r r r r r/w r/w Function X X X X X X PCT_MSB PCT_LSB Default Value 0 0 0 0 0 0 0 0 The PGOOD, VOUT_UNDER_VOLTAGE (UV) and VOUT_OVER_VOLTAGE (OV) settings are shown in Table 4, as a percentage of nominal reference voltage on the FBx pins. Table 4. Protection Settings PCT_MSB PCT_LSB UV PGL LOW PGL HIGH PGH HIGH PGH LOW OV 0 0 -16.67% -12.5% -8.33% 12.50% 8.33% 16.67% 0 1 -12.50% -8.33% -4.17% 8.33% 4.17% 12.50% 1 0 -29.17% -20.83% -16.67% 8.33% 4.17% 12.50% 1 1 -41.67% -37.50% -33.33% 8.33% 4.17% 12.50% The PGOOD pin can be tripped if the output voltage is too high (using PGH high) or too low (using PGL low). Additionally, the PGOOD pin has hysteresis. When the output trips PGOOD going low (at PGL low), the output must rise past PGL high before PGOOD is reset. Likewise, when the output trips PGOOD going high (at PGH high), the output must lower past PGH low before PGOOD is reset. Additionally, when output overvoltage (OV) is tripped, the output must lower below the PGH low threshold, before PGOOD and OV are reset. Likewise, when output undervoltage (UV) is tripped, the output must rise above the PGOOD high threshold, before PGOOD and UV are reset. SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h) SEQUENCE_TON_TOFF_DELAY is a paged register. The SEQUENCE_TON_TOFF_DELAY command is used to set the delay for turning on the device and turning off the device as a ratio of TON_RISE. In two-phase mode, the user can only write to PAGE 0 (channel 1). Any writes to PAGE 1 is not acknowledged. The SEQUENCE_TON_TOFF_DELAY takes a one byte data word formatted as shown below: Command SEQUENCE_TON_TOFF_DELAY Format Unsigned binary Bit Position Access 7 6 5 4 3 2 1 r/w r/w r/w r r/w r/w r/w Function TON_DELAY Default Value 0 0 X 0 0 TOFF_DELAY 0 0 0 r X 0 0 TON_DELAY: This parameter selects the delay from when the output is enabled until soft-start beings, as a multiple of the TON_RISE time. The default value is 0. Values can range from 0 to 7 in increments of 1. TOFF_DELAY: Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 45 TPS40422 SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 www.ti.com This parameter selects the delay from when the output is disabled until the output stops switching, as a multiple of the TON_RISE time. The default value is 0. Values can range from 0 to 7 in increments of 1. OPTIONS (MFR_SPECIFIC_21) (E5h) The OPTIONS register can be used for setting user selectable options, as shown below. Command OPTIONS Format Unsigned binary Bit Position 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Access r r r r r r r r r r r r r r/w r/w r/w Function X X X X X X X X X X X X X EN_ADC_CNTL CH2_DTC CH1_DTC Default Value 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 The contents of this register can be stored to non-volatile memory using the STORE_USER_ALL command. A "1" in any of these bit positions indicates that: EN_ADC_CNTL: Enables ADC operation used for voltage, current and temperature monitoring. CH2_DTC: Increases the non-overlap dead time for gate drivers on channel 2. CH1_DTC: Increases the non-overlap dead time for gate drivers on channel 1. DEVICE_CODE (MFR_SPECIFIC_44) (FCh) The DEVICE_CODE command returns a two byte unsigned binary 12-bit device identifier code and 4-bit revision code in the following format. Command MFR_SPECIFIC_44 Format Linear, two's complement binary Bit Position 7 6 5 4 3 Access r r r r r Function Default Value 2 1 0 7 6 5 4 3 r r r r r r r r Identifier Code 0 0 0 0 0 0 0 0 2 1 0 r r r Revision Code 0 1 1 1 0 1 0 0 This command is oriented toward providing similar information to the DEVICE_ID command but for devices that do not support block read and write functions. Identifier Code Fixed at 7 (dec). Revision Code Fixed at 4 (dec). 46 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 TPS40422 www.ti.com SLUSAQ4C - OCTOBER 2011 - REVISED AUGUST 2012 REVISION HISTORY Changes from Original (OCTOBER) to Revision A * Page Added Application Information section ............................................................................................................................... 13 Changes from Revision A (DECEMBER 2011) to Revision B Page * Added updated SYNC pin description in PIN DESCRIPTIONS table .................................................................................. 9 * Added clarity to BP Crossover section ............................................................................................................................... 19 Changes from Revision B (JUNE 2012) to Revision C Page * Changed "The full load output current multiplied by the sense resistor value, must be less that 100 mV at the maximum converter operating temperature' to "The full load output current multiplied by the sense resistor value, must be less that 60 mV at the maximum converter operating temperature" .................................................................... 15 * Added clarity to Overcurrent Protection section ................................................................................................................. 16 Submit Documentation Feedback Copyright (c) 2011-2012, Texas Instruments Incorporated Product Folder Links :TPS40422 47 PACKAGE OPTION ADDENDUM www.ti.com 31-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPS40422RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPS40422RHAT ACTIVE VQFN RHA 40 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS40422RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 TPS40422RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.5 12.0 16.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 31-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS40422RHAR VQFN RHA 40 2500 367.0 367.0 38.0 TPS40422RHAT VQFN RHA 40 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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