TPS40422
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SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
Dual-Output or Two-Phase Synchronous Buck Controller with PMBus
Check for Samples: TPS40422
1FEATURES APPLICATIONS
• Single Supply Operation: 4.5 V to 20 V • Multiple Rail Systems
• Output Voltage from 0.6 V to 5.6 V • Telecom Base Station
• Dual or Two-Phase Synchronous Buck • Switcher/Router Networking
Controller • Server and Storage System
• PMBus Capability DESCRIPTION
– Margining Up/Down with 2-mV Step The TPS40422 is a dual-output PMBus synchronous
– Programmable Fault Limit and Response buck controller. It can be configured also for a single,
– Output Voltage, Output Current Monitoring two-phase output.
– External Temperature Monitoring with Its wide input range can support 5-V and 12-V
2N3904 intermediate buses. The accurate reference voltage
– Programmable UVLO ON/OFF Thresholds satisfies the need of precision voltage to the modern
ASICs and potentially reduces the output
– Programmable Soft Start Time and Turn capacitance. Voltage mode control is implemented to
On/Off Delay reduce noise sensitivity and also ensures low duty
• On-Chip Non-volatile Memory (NVM) to Store ratio conversion.
Custom Configurations Using the PMBus protocol, the TPS40422 margining
• 180° Out-of-Phase to Reduce Input Ripple function, reference voltage, fault limit, UVLO
• 600-mV Reference Voltage with ±0.5% threshold, soft start time and turn on/off delay can be
Accuracy from 0°C to 85°C programmed.
• Inductor DCR Current Sensing In addition, an accurate measurement system is
• Programmable Switching Frequency from implemented to monitor the output voltages, currents
200 kHz to 1 MHz and temperatures for each channel.
• Voltage Mode Control with Input Feed Forward
• Current Sharing for Multiphase Operation
• Supports Pre-biased Output
• Differential Remote Sensing
• External SYNC
• BPEXT Pin Boosts Efficiency by Supporting
External Bias Power
• OC/OV/UV/OT Fault Protection
• 40-Pin, 6 mm × 6 mm, QFN Package
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS40422
SMBALRT
BP6BPEXT
VDD
AGND
24 256
HDRV1
BOOT1
SW1
LDRV1
PGND
CS1P
CS1N
GSNS1
DIFFO1
FB1
COMP1
TSNS1
VSNS1
29
30
28
27
26
34
35
37
38
39
2
3
36
VOUT1
HDRV2
BOOT2
SW2
LDRV2
CS2P
CS2N
GSNS2
FB2
COMP2
TSNS2
VSNS2
21
20
22
23
18
17
15
14
8
7
16
VOUT2
32
9
BP3
ADDR1
ADDR0
CNTL2
PG2
RT
10
1
19
5
12
11
CLK
DATA
CNTL1
PG1
SYNC
13
40
33
4
31
VIN
SMBALRT
CLK
DATA
CNTL1
PG1
SYNC
CNTL2
PG2
UDG-11278
TPS40422
SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
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SIMPLIFIED APPLICATION
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION(1)(2)
TEMPERATUREE OUTPUT ORDERABLE DEVICE
PACKAGE PINS MINIMUM QUANTITY
RANGE SUPPLY NUMBER
Tape and Reel 3000 TPS40422RHAR
–40°C to 125°C QFN 40 Tube 250 TPS40422RHAT
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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ABSOLUTE MAXIMUM RATINGS(1)(2)(3)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNITS
VDD –0.3 20
BOOT1 , BOOT2, HDRV1, HDRV2 –0.3 30
Input voltage range(2) BOOT1 - SW1, BOOT2 - SW2 –0.3 7 V
CLK, DATA, CNTL1, CNTL2, SYNC –0.3 3.6
FB1, FB2, VSNS1, VSNS2, BPEXT –0.3 7
LDRV1, LDRV2, BP6 –0.3 7
SW1, SW2 –1 30
Output voltage V
range(3) COMP1, COMP2, DIFFO1, SMBALRT, PG1, PG2, TSNS1, TSNS2 –0.3 7
ADDR0, ADDR1, BP3, RT –0.3 3.6
Human body model (HBM) 2
Electrostatic kV
discharge Charged device model (CDM) 1.5
Storage junction temperature, TJ–40 150 °C
Operating junction temperature, Tstg –55 155 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.
RECOMMENDED OPERATING CONDITIONS MIN MAX UNIT
VDD Input operating voltage 4.5 20 V
TJOperating junction temperature –40 125 °C
Human Body Model (HBM) 2000
Electrostatic discharge V
(ESD) ratings Charge Device Model (CDM) 1500
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ELECTRICAL CHARACTERISTICS(1)
TJ= –40ºC to 125ºC, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VVDD Input supply voltage range 4.5 20 V
Switching, no driver load 18 25
IVDD Input operating current mA
Not switching 15 20
UVLO
VIN(on) Input turn on voltage(2) Default settings 4.25 V
VIN(off) Input turn off voltage(2) Default settings 4 V
VINON(rng) Programmable range for turn on voltage 4.25 16 V
VINOFF(rng) Programmable range for turn off voltage 4 15.75 V
4.5 V ≤VVDD ≤20 V, all VIN_ON and
VINONOFF(acc) Turn on and turn off voltage accuracy(1) –5% 5%
VIN_OFF settings
ERROR AMPLIFIER
0°C ≤TJ≤85°C 597 600 603
VFB Feedback pin voltage mV
–40°C ≤TJ≤125°C 594 600 606
AOL Open-loop gain(3) 80 dB
GBWP Gain bandwidth product(3) 24 MHz
IFB FB pin bias current (out of pin) VFB = 0.6 V 50 nA
Sourcing VFB = 0 V 1 3
ICOMP mA
Sinking VFB = 1 V 3 9
BP6 REGULATOR
Output voltage IBP6 = 10 mA 6.2 6.5 6.8 V
VBP6 Dropout voltage VVIN – VBP6, VVDD = 4.5 V, IBP6 = 25 mA 70 120 mV
IBP6 Output current VVDD = 12 V 120 mA
VBP6UV Regulator UVLO voltage(3) 3.3 3.55 3.8 V
VBP6UV(hyst) Regulator UVLO voltage hysteresis(3) 230 255 270 mV
BPEXT
VBPEXT(swover) BPEXT switch-over voltage 4.5 4.6 V
Vhys(swover) BPEXT switch-over hysteresis 100 200 mV
VBPEXT(do) BPEXT dropout voltage VBPEXT–VBP6, VBPEXT = 4.8 V, IBP6 = 25 mA 100 mV
BOOTSTRAP
VBOOT(drop) Bootstrap voltage drop IBOOT = 5 mA 0.7 1.0 V
BP3 REGULATOR
VBP3 Output voltage VVDD = 4.5 V, IBP3 ≤5 mA 3.1 3.3 3.5 V
OSCILLATOR
Adjustment range 100 1000 kHz
fSW Switching frequency RRT = 40 kΩ450 500 550 kHz
VRMP Ramp peak-to-peak(3) VVDD/8.2 V
VVLY Valley voltage(3) 0.7 0.8 1.0 V
(1) Thresholds selected by entering high side parameters for PGOOD_ON and PGOOD_OFF. Cannot select same threshold for
PGOOD_ON & PGOOD_OFF.
(2) By design, hysteresis of at least 150 mV is specified.
(3) Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS(1) (continued)
TJ= –40ºC to 125ºC, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SYNCHRONIZATION
VSYNCH SYNC high level threshold 2.0 V
VSYNCL SYNC low level threshold 0.8 V
tSYNC Minimum SYNC pulse width 100 ns
fSYNC(max) Maximum SYNC frequency(4) 2000 kHz
fSYNC(min) Minimum SYNC frequency(4) 200
SYNC frequency range (increase from nominal –20% 20%
oscillator frequency)
PWM
tOFF(min) Minimum off time 90 100 ns
tON(min) Minimum pulse(5) 90 130 ns
HDRV off to LDRV on 15 25 30
tDEAD Output driver dead time ns
LDRV off to HDRV on 25 35 45
SOFT START
Soft-start time Factory default settings 2.4 2.7 3.0 ms
tSS Accuracy over range(5) 600 µs ≤tSS ≤9 ms –15% 15%
tON(delay) Turn-on delay time(6) Factory default settings 0 ms
tOFF(delay) Turn-off delay time Factory default settings 0 ms
REMOTE SENSE AMPLIFIER
(VSNS1– GSNS1) = 0.6 V –5 5
VDIFFO(err) Error voltage from DIFFO1 to (VSNS1– GSNS1) (VSNS1– GSNS1) = 1.2 V –8 8 mV
(VSNS1– GSNS1) = 3.0 V –17 17
BW Closed-loop bandwidth(5) 2 MHz
VDIFFO(max) Maximum DIFFOx output voltage VBP6-0.2 V
Sourcing 1
IDIFFO mA
Sinking 1
DRIVERS
RHS(up) High-side driver pull-up resistance (VBOOT–VSW) = 6.5 V, IHS = -40 mA 0.8 1.5 2.5
RHS(dn) High-side driver pull-down resistance (VBOOT–VSW) = 6.5 V, IHS = 40 mA 0.5 1.0 1.5 Ω
RLS(up) Low-side driver pull-up resistance ILS = -40 mA 0.8 1.5 2.5
RLS(dn) Low-side driver pull-down resistance ILS = 40 mA 0.35 0.70 1.40
tHS(rise) High-side driver rise time (5) CLOAD = 5 nF 15
tHS(fall) High-side driver fall time (5) CLOAD = 5 nF 12 ns
tLS(rise) Low-side driver rise time (5) CLOAD = 5 nF 15
tLS(fall) Low-side driver fall time (5) CLOAD = 5 nF 10
CURRENT SENSING AMPLIFIER
VCS(rng) Differential input voltage range VCSxP-VCSxN -60 60 mV
VCS(cmr) Input common-mode range 0 VBP6–0.2 V
VCS(os) Input offset voltage VCSxP = VCSxN = 0 V -3 3 mV
ACS Current sensing gain 15.00 V/V
VCS(out) Amplfier output (VCSxP-VCSxN) = 20 mV 270 300 330 mV
fC0 Closed-loop bandwidth(5) 3 5 MHz
(VCS1P– VCS1N) = (VCS2P–VCS2N) = 20 mV, -5.00% 5.00%
TJ= 25°C
VCS(chch) Amplifier output difference between CH1, CH2 (VCS1P– VCS1N) = (VCS2P–VCS2N) = 20 mV, -6.67% 6.67%
TJ= 85°C
(4) When using SYNC, the switching frequency is set to one-half the SYNC frequency.
(5) Specified by design. Not production tested.
(6) The minimum turn-on delay is 50 µs, when TON_DELAY is set to a factor of zero.
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ELECTRICAL CHARACTERISTICS(1) (continued)
TJ= –40ºC to 125ºC, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT
tOFF(oc) Off-time between restart attempts Hiccup mode 7×tSS ms
Factory default settings 0.488
DCR Inductor DCR current sensing calibration value mΩ
Programmable range 0.240 15.500
Factory default settings 30
IOC(flt) Output current overcurrent fault threshold A
Programmable range 3 50
Factory default settings 27
IOC(warn) Output current overcurrent warning threshold A
Programmable range 2 49
Output current fault/warning temperature
IOC(tc) 3900 4000 4100 ppm/°C
coefficient(7)
IOC(acc) Output warning and fault accuracy (VCSxP-VCSxN) = 30 mV –15% 15%
PGOOD (8)
VFBPGH FB PGOOD high threshold Factory default settings 675 mV
VFBPGL FB PGOOD low threshold Factory default settings 525 mV
4.5 V ≤VVDD ≤20 V,
VPG(acc) PGOOD accuracy over range –4% 4%
468 mV ≤VPGOOD ≤675 mV
Vpg(hyst) FB PGOOD hysteresis voltage 25 40 mV
RPGOOD PGOOD pulldown resistance VFB = 0, IPGOOD = 5 mA 40 70 Ω
IPGOOD(lk) PGOOD pin leakage current No fault, VPGOOD = 5 V 20 µA
OUTPUT OVERVOLTAGE/UNDERVOLTAGE
VFBOV FB pin over voltage threshold Factory default settings 700 mV
VFBUV FB pin under voltage threshold Factory default settings 500 mV
VUVOV(acc) FB UV/OV accuracy over range 4.5 V ≤VVDD ≤20 V –4% 4%
OUTPUT VOLTAGE TRIMMING AND MARGINING
VFBTM(step) Resolution of FB steps with trim and margin 2 mV
tFBTM(step) Transition time per trim or margin step After soft-start time 30 µs
VFBTM(max) Maximum FB voltage with trim and/or margin 660 mV
Minimum FB voltage with trim or margin only 480
VFBTM(min) mV
Minimum FB voltage range with trim and margin 420
combined
VFBMH Margin high FB pin voltage Factory default settings 660 mV
VFBML Margin low FB pin voltage Factory default settings 540 mV
TEMPERATURE SENSE AND THERMAL SHUTDOWN
TSD Junction shutdown temperature(7) 135 145 155 °C
THYST Thermal shutdown hysteresis(7) 15 20 25 °C
Ratio of bias current flowing out of TSNS pin,
ITSNS(ratio) 9.7 10.0 10.3
state 2 to state 1
ITSNS(7) State 1 current out of TSNSx pin 10 µA
ITSNS(7) State 2 current out of TSNSx pin 100 µA
VTSNS Voltage range on TSNSx pin(7) 0 1.00 V
TSNS(acc) External temperature sense accuracy(9) 0°C ≤TJ≤125°C –5 5 °C
TOT(flt) Overtemperature fault limit(7) Factory default settings 145 °C
OT fault limit range(7) 120 165 °C
TOT(warn) Overtemperature warning limit(7) Factory default settings 125 °C
OT warning limit range(7) 100 140 °C
TOT(step) OT fault/warning step 5 °C
TOT(hys) OT fault/warning hysteresis(7) 15 20 25 °C
(7) Specified by design. Not production tested.
(8) Thresholds selected by entering high side parameters for PGOOD_ON and PGOOD_OFF. Cannot select same threshold for
PGOOD_ON & PGOOD_OFF.
(9) Specified by design. Not production tested.
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ELECTRICAL CHARACTERISTICS(1) (continued)
TJ= –40ºC to 125ºC, VIN = VDD = 12 V, RT set for 500 kHz, all parameters at zero power dissipation (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
MEASUREMENT SYSTEM
MVOUT(rng) Output voltage measurement range(10) 0.5 5.8 V
MVOUT(acc) Output voltage measurement accuracy VOUT = 1.0 V –2.0% 2.0%
VCSxP–VCSxN, 0.2440 mΩ ≤ IOUT_CAL_GAIN 0 36
≤0.5795 mΩ
VCSxP–VCSxN, 0.5796 mΩ ≤ IOUT_CAL_GAIN
MIOUT(rng) Output current measurement signal range(10) 0 60 mV
≤1.1285 mΩ
VCSxP–VCSxN, 1.1286 mΩ ≤ IOUT_CAL_GAIN 0 90
≤15.5 mΩ
MIOUT(acc) Output current measurement accuracy IOUT ≥20 A, DCR = 0.5 mΩ–1.0 1.0 A
PMBus ADDRESSING
IADD Address pin bias current 9.24 10.50 11.76 µA
PMBus INTERFACE
VIH Input high voltage, CLK, DATA, CNTLx 2.1 V
VIL Input low voltage, CLK, DATA, CNTLx 0.8 V
IIH Input high level current, CLK, DATA –10 10 µA
IIL Input low level current, CLK, DATA –10 10 mA
ICTNL CNTL pin pull-up current 6 µA
VOL Output low level voltage, DATA, (10) 4.5 V ≤VVDD ≤20 V, IOUT = 4 mA 0.8 V
Output high level open drain leakage current,
IOH VOUT = 5.5 V 0 10 µA
DATA, SMBALRT
COUT Pin capacitance, CLK, DATA(10) 1 pF
FPMB PMBus operating frequency range(10) Slave mode 10 400 kHz
tBUF Bus free time between START and STOP(10) 4.7 µs
tHD:STA Hold time after repeated START(10) 4.0 µs
tSU:STA Repeated START setup time(10) 4.7 µs
tSU:STO STOP setup time(10) 4.0 µs
Receive mode 0
tHD:DAT Data hold time(10) ns
Transmit mode 300
tSU:DAT Data setup time(10) 250 ns
tTIMEOUT Error signal/detect(10) 25 35 µs
tLOW:MEXT Cumulative clock low master extend time(10) 50 µs
tLOW:SEXT Cumulative clock low slave extend time(10) 25 µs
tLOW Clock low time(10) 4.7 µs
tHIGH Clock high time(10) 4.0 µs
tFALL CLK/DATA fall time(10) 300 µs
tRISE CLK/DATA rise time(10) 1000 µs
(10) Specified by design. Not production tested.
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1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
30
29
28
27
26
25
24
23
22
21
40 39 38 37 36 35 34 33 32 31
DATA
CLK
SMBALRT
GSNS2
VSNS2
TSNS2
CS2N
CS2P
PG2
BOOT2
SYNC
DIFFO1
GSNS1
VSNS1
TSNS1
CS1N
CS1P
PG1
BP3
VDD
RT
FB1
COMP1
CNTL1
CNTL2
AGND
COMP2
FB2
ADDR1
ADDR0
TPS40422
BOOT1
HDRV1
SW1
LDRV1
PGND
BP6
BPEXT
LDRV2
SW2
HDRV2
TPS40422
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DEVICE INFORMATION
PIN DESCRIPTIONS
PIN NO. I/O DESCRIPTION
Low-order address pin for PMBus address configuration. One of eight resistor values must be connected
ADDR0 10 I from this pin to AGND to select the low-order octal digit in the PMBus address.
High-order address pin for PMBus address configuration. One of eight resistor values must be
ADDR1 9 I connected from this pin to AGND to select the low-order octal digit in the PMBus address.
Low-noise ground connection to the controller. Connections should be arranged so that power level
AGND 6 — currents do not flow through the AGND path.
Bootstrapped supply for the high-side FET driver for channel 1 (CH1). Connect a capacitor (100 nF
BOOT1 30 I typical) from BOOT1 to SW1 pin.
Bootstrapped supply for the high-side FET driver for channel 2 (CH2). Connect a capacitor (100 nF
BOOT2 20 I typical) from BOOT2 to SW2 pin.
Output bypass for the internal 3.3-V regulator. Connect a 100 nF or larger capacitor from this pin to
BP3 32 O AGND.
Output bypass for the internal 6.5-V regulator. Connect a low ESR, 1 µF or larger ceramic capacitor from
BP6 25 O this pin to PGND.
External voltage input for BP6 switchover function. If the BPEXT function is not used, connect this pin
BPEXT 24 I directly to PGND. Otherwise connect a 100-nF or larger capacitor from this pin to PGND.
CLK 12 I Clock input for the PMBus interface. Pull up to 3.3 V with a resistor.
CNTL1 4 I Logic level input which controls startup and shutdown of CH1, determined by PMBus options.
CNTL2 5 I Logic level input which controls startup and shutdown of CH2, determined by PMBus options.
COMP1 3 O Output of the error amplifier for CH1 and connection node for loop feedback components.
Output of the error amplifier for CH2 and connection node for loop feedback components. For two-phase
COMP2 7 O operation, use COMP1 for loop feedback and connect COMP1 to COMP2.
CS1N 35 I Negative terminal of current sense amplifier for CH1.
CS2N 17 I Negative terminal of current sense amplifier for CH2.
CS1P 34 I Positive terminal of current sense amplifier for CH1.
CS2P 18 I Positive terminal of current sense amplifier for CH2.
DATA 11 I/O Data input/output for the PMBus interface. Pull up to 3.3 V with a resistor.
DIFFO1 39 O Output of the differential remote sense amplifier for CH1.
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PIN DESCRIPTIONS (continued)
PIN NO. I/O DESCRIPTION
Inverting input of the error amplifier for CH1. Connect a voltage divider to FB1 between DIFFO1 and
FB1 2 I AGND to program the output voltage for CH1.
Inverting input of the error amplifier for CH2. Connect a voltage divider to FB2 between VSNS2 and
FB2 8 I GSNS2 to program the output voltage for CH2. For two-phase operation, use FB1 to program the output
voltage and connect FB2 to BP6 before applying voltage to VDD.
GSNS1 38 I Negative terminal of the differential remote sense amplifier for CH1.
GSNS2 14 I Negative terminal of the differential remote sense amplifier for CH2.
HDRV1 29 O Bootstrapped gate drive output for the high-side N-channel MOSFET for CH1.
HDRV2 21 O Bootstrapped gate drive output for the high-side N-channel MOSFET for CH2.
LDRV1 27 O Gate drive output for the low side synchronous rectifier N-channel MOSFET for CH1.
LDRV2 23 O Gate drive output for the low-side synchronous rectifier N-channel MOSFET for CH2.
PGND 26 — Power GND.
PG1 33 O Open drain power good indicator for CH1 output voltage.
PG2 19 O Open drain power good indicator for CH2 output voltage.
RT 1 I Frequency programming pin. Connect a resistor from this pin to AGND to set the oscillator frequency.
SMBALRT 13 O Alert output for the PMBus interface. Pull up to 3.3 V with a resistor.
SW1 28 I Return of the high-side gate driver for CH1. Connect to the switched node for CH1.
SW2 22 I Return of the high-side gate driver for CH2. Connect to the switched node for CH2.
Logic level input for external clock synchronization. When an external clock is applied to this pin, the
SYNC 40 I oscillator frequency sychronizes to one half of its frequency. When an external clock is not used, tie this
pin to AGND.
TSNS1 36 I External temperature sense input for CH1.
TSNS2 16 I External temperature sense input for CH2.
Power input to the controller. Connect a low ESR, 100 nF or larger ceramic capacitor from this pin to
VDD 31 I AGND.
VSNS1 37 I Positive terminal of the differential remote sense amplifier for CH1.
VSNS2 15 I Positive terminal of the differential remote sense amplifier for CH2.
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VSNS2
Oscillator
PMBus Interface
Logic
and Processing
ADDR0
ADDR1
DATA
CLK
CNTL2
SMBALRT
Non-Volatile
Memory
BP3
CNTL1
+
GSNS2
DIFFO2
VSNS1 +
GSNS1
DIFFO1
CS2P +
CS2N
CS2
Current
Share
FB2
VREF
FB1
VREF
COMP1
COMP2 RAMP2
+
–
RAMP1
+ –
CS1P +
CS1N
CS1
RT
SYNC RAMP1
RAMP2
VDD
EN, SS
and VREF
Bypass SW
and Logic
BPEXT
BP
Regulators
VDD
BP6
EN1
EN2
VREF
Measurement
System
MUX
and
ADC
CS1P
CS1N
CS2P
CS2N
TSNS2
TSNS1
DIFFO1
DIFFO2
Fault and
Warning Limits
HDRV1
BOOT1
SW1
LDRV1
PGND
Anti-Cross
Conduction
and
PWM Latch
Logic
BP6
HDRV2
BOOT2
SW2
LDRV2
PGND
BP6
TSNS1
TSNS2
PG1
PG2
AGND
OC/UV/OV/OT
Detection
OT
OC
UV
OV
TSNS1
TSNS2
FB1
FB2
CS1
CS2
Fault and
Warning Limits
UDG-11216
BOOT1
BOOT2
EN1 EN2
+
+
+
+
TPS40422
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FUNCTIONAL BLOCK DIAGRAM
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12.0
12.5
13.0
13.5
14.0
14.5
15.0
15.5
16.0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Non−Switching Quiescent Current (mA)
VDD = 12 V
VDD = 20 V
VDD = 4.5 V
G004
500
510
520
530
540
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Switching Frequency (kHz)
VDD = 12 V
VDD = 20 V RT = 40 kΩ
G005
0.60
0.80
1.00
1.20
1.40
1.60
1.80
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
High−Side Driver Resistance (Ω)
RHDHI
RHDLO
G002
0.4
0.6
0.8
1
1.2
1.4
1.6
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Low−Side Driver Resistance (Ω)
RLDHI
RLDLO
G003
4.2
4.3
4.4
4.5
4.6
4.7
4.8
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
BPEXT Voltage (V)
Switch−Over Enabled
Switch−Over Disabled
G000
598.0
598.5
599.0
599.5
600.0
600.5
601.0
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Reference Voltage (mV)
VDD = 12 V
VDD = 20 V
VDD = 4.5 V
G001
TPS40422
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SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
TYPICAL CHARACTERISTICS
Figure 1. BPEXT Voltage vs. Junction Temperature Figure 2. Reference Voltage vs. Junction Temperature
Figure 3. High-Side Driver Resistance vs. Junction Figure 4. Low-Side Driver Resistance vs. Junction
Temperature Temperature
Figure 5. Non-Switching Quiescent Current vs. Junction Figure 6. Switching Frequency vs. Junction Temperature
Temperature
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20
22
24
26
28
30
32
34
36
38
40
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
Dead Time (ns)
HDRV off to LDRV on
LDRV off to HDRV on
G006
104
106
108
110
112
114
116
−40 −25 −10 5 20 35 50 65 80 95 110 125
Junction Temperature (°C)
HDRV Minimum Off−Time (ns)
G007
TPS40422
SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
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TYPICAL CHARACTERISTICS (continued)
Figure 7. Dead Time vs. Junction Temperature Figure 8. HDRV Minimum Off-Time vs. Junction
Temperature
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TPS40422
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SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
APPLICATION INFORMATION
General Description/Control Architecture
The TPS40422 is a flexible synchronous buck controller. It can be used as a dual-output controller, or as a two-
phase single-output controller. It operates with a wide input range from 4.5 V to 20 V and generates accurate
regulated output as low as 600 mV.
In dual output mode, voltage mode control with input feed-forward architecture is implemented. With this
architecture, the benefits are less noise sensitivity, no control instability issues for small DCR applications, and a
smaller minimum controllable on-time, often desired for high conversion ratio applications.
In two-phase single-output mode, a current-sharing loop is implemented to ensure a balance of current between
phases. Because the induced error current signal to the loop is much smaller when compared to the PWM ramp
amplitude, the control loop is modeled as voltage mode with input feed-forward.
DESIGN NOTE
To operate the device in two-phase mode, tie the FB2 pin to the BP6 pin and tie the
COMP1 pin to the COMP2 pin. These connections must be made before applying voltage
to the VDD pin.
PMBus General Description
Timing and electrical characteristics of the PMBus can be found in the PMB Power Management Protocol
Specification, Part 1, revision 1.1 available at http://pmbus.org. The TPS40422 supports both the 100 kHz and
400 kHz bus timing requirements. The TPS40422 does not stretch pulses on the PMBus when communicating
with the master device.
Communication over the TPS40422 device PMBus interface can either support the Packet Error Checking (PEC)
scheme or not. If the master supplies CLK pulses for the PEC byte, it is used. If the CLK pulses are not present
before a STOP, the PEC is not used.
The TPS40422 supports a subset of the commands in the PMBus 1.1 specification. Most all of the controller
parameters can be programmed using the PMBus and stored as defaults for later use. All commands that require
data input or output use the literal format. The exponent of the data words is fixed at a reasonable value for the
command and altering the exponent is not supported. Direct format data input or output is not supported by the
TPS40422. See the SUPPORTED COMMANDS section for specific details.
The TPS40422 also supports the SMBALERT response protocol. The SMBALERT response protocol is a
mechanism by which a slave (the TPS40422) can alert the bus master that it wants to talk. The master
processes this event and simultaneously accesses all slaves on the bus (that support the protocol) through the
alert response address. Only the slave that caused the alert acknowledges this request. The host performs a
modified receive byte operation to get the slave’s address. At this point, the master can use the PMBus status
commands to query the slave that caused the alert. For more information on the SMBus alert response protocol,
see the System Management Bus (SMBus) specification.
The TPS40422 contains non-volatile memory that is used to store configuration settings and scale factors. The
settings programmed into the device are not automatically saved into this non-volatile memory though. The
STORE_USER_ALL command must be used to commit the current settings to non-volatile memory as device
defaults. The settings that are capable of being stored in non-volatile memory are noted in their detailed
descriptions.
Voltage Reference
The 600-mV bandgap cell is internally connected to the non-inverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 0.5-% tolerance on the reference voltage allows the user to design a very accurate power
supply.
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( )
FB
OUT FB
R1
R2 V
V V
æ ö
= ´ ç ÷
ç ÷
-
è ø
COMP1
FB1
R1
R2
C1
C2R4
C3
R3
DIFFO1 +
X1
VSNS1
GSNS1
To load supply
connections
UDG-11245
TPS40422
SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
www.ti.com
Output Voltage
The output voltage is set in a very similar to the way to a traditional analog controller using a voltage divider from
the output to the feedback (FB) pin. The output voltage must be divided down to the nominal reference voltage of
600mV. Figure 9 shows the typical connections for the controller. The voltage at the load can be sensed using
the unity gain differential voltage sense amplifier. This provides better load regulation for output voltages lower
than 5V nominal (see electrical specifications for the maximum output voltage of the differential sense amplifier).
For output voltages above this level, connect the output voltage directly to the junction of R1 and C1, leave
DIFFO1 open and do not connect the VSNS1 pin to the output voltage. If desired the differential amplifier may
also be used elsewhere in the overall system as a voltage buffer, provided the electrical specifications are not
exceeded.
Figure 9. Setting the Output Voltage
The components in Figure 9 that determine the nominal output voltage are R1 and R2. R1 is normally chosen to
make the feedback compensation values (R3, R4, C1, C2 andC3) come close to readily available standard
values. R2 is then calculated in Equation 1.
where
• VFB is the feedback voltage
• VOUT is the desired output voltage
• R1 and R2 are in the same units (1)
DESIGN NOTE
There is no DIFFO2 pin. In dual-output mode, VSNS2 and GSNS2 are connected to the
load for channel 2 and the DIFFO2 signal is used internally for voltage monitoring.
Connect the output directly to the junction of R1 and C1 for channel 2 to set the output
voltage and for feedback.
The feedback voltage can be changed –30% to +10% from the nominal 600 mV using PMBus commands. This
allows the output voltage to vary by the same percentage. See the PMBus Functionality section for further
details.
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L
R5
To load
CSxP
CSxN
C4
UDG-11246
RDCR
VIN
L
To load
UDG-11247
RISNS
CSxP
CSxN
VIN
DCR
L
R5 C4
R
æ ö
´ ³ ç ÷
è ø
TPS40422
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SLUSAQ4C –OCTOBER 2011–REVISED AUGUST 2012
Voltage Feed Forward
The TPS40422 uses input voltage feed forward that maintains a constant power stage gain as input voltage
varies and provides for very good response to input voltage transient disturbances. The simple constant power
stage gain of the controller greatly simplifies feedback loop design because loop characteristics remains constant
as the input voltage changes, unlike a buck converter without voltage feed forward. For modeling purposes, the
gain from the COMP pin to the average voltage at the input of the L-C filter is 8.2 V/V.
Current Sensing
The TPS40422 uses a differential current sense scheme to sense the output current. The sense element can be
either the series resistance of the power stage filter inductor or a separate current sense resistor. When using
the inductor series resistance as in Figure 10, a filter must be used to remove the large AC component of voltage
across the inductor and leave only the component of the voltage that appears across the resistance of the
inductor. The values of R5 and C4 for the ideal case can be found by Equation 2. The time constant of the R-C
filter should be equal to or greater than the time constant of the inductor itself. If the time constants are equal, the
voltage appearing across C4 is be the current in the inductor multiplied the inductor resistance. The inductor
ripple current is reflected in the voltage across C4 perfectly in this case and there is no reason to have a shorter
R-C time constant.
The time constant of the R-C filter can be made longer than the inductor time constant because this is a voltage
mode controller and the current sensing is done for overcurrent detection and output current reporting only.
Extending the R-C filter time constant beyond the inductor time constant lowers the AC ripple component of
voltage present at the current sense pins of the TPS40422 but allows the correct DC current information to
remain intact. This also delays slightly the response to an overcurrent event, but reduces noise in the system
leading to cleaner overcurrent performance and current reporting data over the PMBus
where (from Figure 10)
• R5 and RESR are in Ω
• C4 is in F (suggest 100 nF, 10-7F)
• L is in H (2)
The maximum voltage that the TPS40422 is designed to accept across the curent sense pins is 60 mV. Because
most all inductors have a copper conductor and because copper has a fairly large temperature coefficient of
resistance, the resistance of the inductor and the current through the inductor should make a DC voltage less
than 60 mV when the inductor is at the maximum temperature for the converter. This also applies for the external
resistor in Figure 11. The full load output current multiplied by the sense resistor value, must be less that 60 mV
at the maximum converter operating temperature.
In all cases, C4 should be placed as close to the current sense pins as possible to help avoid problems with
noise.
Figure 10. Current Sensing Using Inductor Figure 11. Current Sensing Using Sense Resistor
Resistance
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After choosing the current sensing method, set the current sense element resistance. This value allows the
proper calculation of thresholds for the overcurrent fault and warning, as well as more accurate reporting of the
actual output current. The IOUT_CAL_GAIN command is used to set the value of the sense element resistence
of the device. IOUT_OC_WARN_LIMIT and IOUT_OC_FAULT_LIMIT set the levels for the overcurrent warning
and fault levels respectively. (See the PMBus Functionality section for more details.)
Overcurrent Protection
The TPS40422 has overcurrent fault and warning thresholds for each channel which can be independently set,
when operating in dual-output mode. When operating in two-phase mode, both channels share the same
overcurrent fault and warning thresholds. The overcurrent thresholds are set over PMBus using the
IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT commands. (See the PMBus Functionality section for
more details.)
The TPS40422 generates an internal voltage corresponding to the desired overcurrent threshold, using the
IOUT_OC_FAULT_LIMIT threshold and the IOUT_CAL_GAIN setting, and adjusting for temperature using the
measured external temperature value. The sensed current signal is amplified by the current sense amplifier with
a fixed gain of 15 and then compared with this internal voltage threshold. A similar structure is used to activate
an overcurrent warning based on the IOUT_OC_WARN_LIMIT threshold.
Figure 12. Overcurrent Protection
The programmable range of the overcurrent fault and warning voltage thresholds places a functional limit on the
input voltage of the current sense amplifier. The minimum overcurrent fault and warning thresholds correspond to
a voltage from CSxP to CSxN of 6 mV and 4.7 mV, respectively. If the voltage across these pins does not
exceed the minimum thresholds, then overcurrent fault and warning cannot be tripped, regardless of the setting
of IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. There is also maximum overcurrent fault and warning
thresholds corresponding to a voltage from CSxP to CSxN of 60 mV and 59 mV, respectively. If the voltage
across these pins exceeds this maximum threshold, the overcurrent fault or warning will be tripped, regardless of
the setting of IOUT_OC_FAULT_LIMIT and IOUT_OC_WARN_LIMIT. This means that for higher values of
inductor DCR, a resistor across the current sensing capacitor may be required to create a voltage divider into the
current sensing inputs.
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